WO2014136761A1 - 電力変換器制御装置 - Google Patents
電力変換器制御装置 Download PDFInfo
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- WO2014136761A1 WO2014136761A1 PCT/JP2014/055438 JP2014055438W WO2014136761A1 WO 2014136761 A1 WO2014136761 A1 WO 2014136761A1 JP 2014055438 W JP2014055438 W JP 2014055438W WO 2014136761 A1 WO2014136761 A1 WO 2014136761A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/12—Stator flux based control involving the use of rotor position or rotor speed sensors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
- H02P21/24—Vector control not involving the use of rotor position or rotor speed sensors
- H02P21/28—Stator flux based control
- H02P21/30—Direct torque control [DTC] or field acceleration method [FAM]
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
- H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
- H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
- H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
- H02P27/12—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation pulsing by guiding the flux vector, current vector or voltage vector on a circle or a closed curve, e.g. for direct torque control
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
- G01R31/42—AC power supplies
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
- H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
- H02M7/53876—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times
Definitions
- the present invention relates to a technique for controlling a power converter, and more particularly to a technique for detecting a current flowing in a power converter that converts three-phase alternating current to direct current.
- DC link current a current flowing therethrough
- DC Ringing occurs because the DC link current commutates the current path inside the inverter by switching the inverter. There is also a turn-on time of a switching device that performs inverter switching. Furthermore, in order to handle the value of the DC link current as data, time for A / D conversion is also required.
- the time that one switching pattern should last in order to associate the DC link current as a line current of a phase is longer than at least the total time of the ringing of the DC link current, the A / D conversion time, and the turn-on of the switching device. There must be. Alternatively, other factors such as switching dead time may have to be considered.
- this value is referred to as a minimum time limit.
- the switching pattern of the inverter can be determined by adopting a so-called circular locus method (or circle approximation method).
- the circular locus method is well known, for example, from Patent Document 1 and Non-Patent Documents 1 to 3.
- the magnetic flux in the load is controlled every predetermined control period.
- Patent Documents 2 to 5 are also cited as prior art documents in order to explain problems to be described later.
- Japanese Patent No. 3289281 Japanese Patent Laid-Open No. 11-4594 Japanese Patent No. 3664040 Japanese Patent No. 4643404 JP 2011-234428 A
- Patent Document 1 and Non-Patent Documents 1 to 3 do not have a viewpoint on the above-mentioned minimum time limit. Therefore, when the circular locus method is used, the line current is maintained while maintaining the magnetic flux in the entire control cycle. There is no consideration of maintaining the switching pattern for detection beyond the minimum time limit.
- Patent Documents 2 to 5 when a so-called voltage vector is used, a technique for setting a switching pattern for detecting a line current to be longer than the minimum time limit while maintaining the output voltage of the inverter in the entire control cycle. It is disclosed. However, these documents also do not have a viewpoint on control using time integration of voltage vectors, and therefore a technique that can be directly applied to the circular locus method is not disclosed or suggested.
- the present application provides a technique for maintaining a switching pattern for detecting a phase current or a line current for a minimum limit time or more while maintaining a magnetic flux in the entire control cycle in control using the circular locus method. For the purpose.
- the first aspect of the power converter control device supplies a three-phase current (Iu, Iv, Iw) by applying a three-phase voltage (Vu, Vv, Vw) to the inductive load (5). It is a power converter control apparatus (6) which controls a power converter (3) for every predetermined period (T0).
- the power converter has three current paths. Each of the current paths is connected in series between the connection point (Pu, Pv, Pw) and a pair of DC buses (LL, LH) capable of detecting current at any one of the current paths.
- a pair of switches (4up, 4un) (4vp, 4vn) (4wp, 4wn), and the three-phase current is output from the three connection points according to the conduction / non-conduction state of the three pairs of switches. .
- the conduction / non-conduction state is based on a plurality of switching patterns.
- the voltage vectors (V0 to V7) corresponding to the switching pattern are classified into a pair of zero voltage vectors (V0, V7) and six non-zero voltage vectors (V1 to V6) other than the zero voltage vector.
- the first zero voltage vector (V0) corresponds to the first switching pattern in which the inductive load is connected only to the first DC bus (LL), and the second zero voltage vector (V7).
- the non-zero voltage vector is represented on the complex plane by being arranged at every angle ⁇ / 3 starting from the zero voltage vector.
- the switching pattern is common in one current path and is different in the other two current paths.
- the switching pattern corresponding to one of the pair of non-zero voltage vectors and the switching pattern corresponding to the other of the pair of non-zero voltage vectors arranged at an angle ⁇ on the complex plane Is different in the three current paths.
- the power converter control device includes a difference command generation unit (62), a vector command generation unit (63, 64, 65), a switching signal generation unit (67), and a phase current calculation unit (61).
- the difference command generation unit (62) outputs a difference command ( ⁇ ( ⁇ )) equivalent to time integration of the three-phase voltage applied to the inductive load in one predetermined period on the complex plane. Generate.
- the vector command generation unit outputs a plurality of vector commands ([ ⁇ V] *), each of which is a time integration of the voltage vector, and synthesizes the difference command.
- the switching signal generator generates a switching signal (Gup, Gvp, Gwp, Gun, Gvn, Gwn) for controlling the conduction / non-conduction state of the three pairs of switches based on the vector command.
- the phase current calculation unit detects a current (Id) flowing through the DC bus, and obtains an estimated value of the three-phase current based on the current and the vector command.
- the time integral of different non-zero voltage vectors is at least two magnitudes that are required to maintain the switching pattern at a minimum in order for the phase current calculation unit to detect the current. Is equal to or greater than a predetermined value (Tmin) corresponding to.
- a second mode of the power converter control device is the first mode, wherein the vector command generation unit includes an original vector generation unit (63), a correction vector generation unit (64), and compensation.
- a vector generation unit (65) and a vector integration unit (66) are included.
- the original vector generation unit includes original vectors ( ⁇ 0 ⁇ V0, ⁇ 7 ⁇ V7, ⁇ 4 ⁇ V4, ⁇ 6 ⁇ V6) including a pair of original non-zero vectors ( ⁇ 4 ⁇ V4, ⁇ 6 ⁇ V6) for each predetermined period (T0). ) Is generated.
- the correction vector output unit outputs a pair of correction vectors ( ⁇ 4 ′ ⁇ V4, ⁇ 6 ′ ⁇ V6) ( ⁇ 4′a ⁇ V4, ⁇ 6′a ⁇ V6) ( ⁇ 4′b ⁇ V4) every predetermined period (T0).
- ⁇ 2′b ⁇ V2) ( ⁇ 6′b ⁇ V6, ⁇ 5′b ⁇ V5) is output.
- the compensation vector output unit outputs a pair of compensation vectors ( ⁇ 4 ′′ ⁇ V4, ⁇ 6 ′′ ⁇ V6) ( ⁇ 3 ′′ a ⁇ V3, ⁇ 1 ′′ a ⁇ V1) ( ⁇ 5 ′) for each predetermined period (T0).
- 'b ⁇ V5, ⁇ 1 ′′ b ⁇ V1) ( ⁇ 2 ′′ b ⁇ V2, ⁇ 3 ′′ b ⁇ V3) is output.
- the vector integration unit integrates the pair of correction vectors, the pair of compensation vectors, and at least one valueless vector ( ⁇ 0 ⁇ V0) ( ⁇ 7 ⁇ V7), and outputs the vector command. .
- Each of the pair of original non-zero vectors is a time integration of the non-zero voltage vector, and forms an angle ⁇ / 3 with each other on the complex plane, and half of the difference command ( ⁇ ( ⁇ )). Synthesize.
- Each of the pair of correction vectors is a time integration of the non-zero voltage vector, the magnitude of which is greater than or equal to the predetermined value (Tmin), and corresponds to the different non-zero voltage vectors.
- One correction vector ( ⁇ 4 ′ ⁇ V4) ( ⁇ 6 ′ ⁇ V6) ( ⁇ 4′a ⁇ V4) ( ⁇ 6′a ⁇ V6) ( ⁇ 4′b ⁇ V4) ( ⁇ 6′b ⁇ V6) corresponds
- the non-zero voltage vector corresponding to the original non-zero vector ( ⁇ 4 ⁇ V4) ( ⁇ 6 ⁇ V6) corresponds to the non-zero voltage vector.
- Each of the pair of compensation vectors is a time integration of the non-zero voltage vector, corresponds to the different non-zero voltage vectors, and combines the difference command together with the pair of correction vectors.
- Each of the non-value vectors is a time integration of the zero voltage vector (V0) (V7) and has no magnitude.
- a third aspect of the power converter control device is the second aspect, wherein in the vector command, at the start time (ts) and / or the end time (te) of the predetermined period.
- the valueless vector is adopted.
- the number of the switches that conduct between the connection point and one of the DC buses in the switching pattern corresponding to the voltage vector (V0) (V7) to which the valueless vector corresponds
- the difference from the number is 1.
- a fourth aspect of the power converter control device is the third aspect, wherein each of the non-zero voltage vectors (V4, V6) to which the pair of correction vectors correspond is the pair. Of the original non-zero vectors coincide with each of the corresponding non-zero voltage vectors (V4, V6).
- the pair of compensation vectors ( ⁇ 4 ′′ ⁇ V4, ⁇ 6 ′′ ⁇ V6) ( ⁇ 6 ′′ ⁇ V6, ⁇ 2 ′′ ⁇ V2) ( ⁇ 2 ′′ ⁇ V2, ⁇ 3 ′′ ⁇ V3) ( ⁇ 3 ′′ ⁇ V3, ⁇ 1 ′′ ⁇ V1) ( ⁇ 1 ′′ ⁇ V1, ⁇ 5 ′′ ⁇ V5) ( ⁇ 5 ′′ ⁇ V5, ⁇ 4 ′′ ⁇ V4) form an angle ⁇ / 3 with each other on the complex plane.
- the first compensation vector ( ⁇ 6 ′′ ⁇ V6) ( ⁇ 3 ′′ ⁇ V3) ( ⁇ 5 ′′ ⁇ V5) is the second compensation vector ( ⁇ 4 ′′ ⁇ V4) ( ⁇ 2 ′′ ⁇ V2) ( ⁇ 1 ′′ ⁇ V1) is adopted before.
- the first number is conductive between the connection point and the one of the DC buses in a switching pattern corresponding to the voltage vector (V6) (V3) (V5) to which the first compensation vector corresponds. This is the number of the switches to be operated.
- the second number is conductive between the connection point and the one of the DC buses in a switching pattern corresponding to the voltage vector (V4) (V2) (V1) to which the second compensation vector corresponds. This is the number of the switches to be operated.
- the third number is the vector command ( ⁇ 7 ′′ ⁇ V7) ( ⁇ 7a ′′ ⁇ V7) ( ⁇ 0a ′′ ⁇ V0) ( ⁇ 6 ′ ⁇ V6) (just before the first compensation vector) ( In the switching pattern corresponding to the voltage vectors (V7), (V6), and (V4) corresponding to ( ⁇ 4 ′ ⁇ V4) ( ⁇ 6′a ⁇ V6) ( ⁇ 4′a ⁇ V4), the connection point and the DC bus This is the number of the switches that are electrically connected to the one side.
- a fifth aspect of the power converter control device is the third aspect, in which the sum of the magnitudes ( ⁇ 4 + ⁇ 6) of the pair of original non-zero vectors is half the predetermined value (Tmin / 2) The following holds when the following is true.
- a pair of the correction vectors ( ⁇ 4′b ⁇ V4, ⁇ 2′b ⁇ V2) ( ⁇ 6′b ⁇ V6, ⁇ 5′b ⁇ V5) is a pair of the non-sets that form an angle 2 ⁇ / 3 on the complex plane. Corresponds to the zero voltage vector.
- a pair of the compensation vectors ( ⁇ 5 ′′ b ⁇ V5, ⁇ 1 ′′ b ⁇ V1) ( ⁇ 2 ′′ b ⁇ V2, ⁇ 3 ′′ b ⁇ V3) form an angle ⁇ / 3 with each other on the complex plane. It corresponds to a pair of the non-zero voltage vectors.
- each of the pair of the correction vectors has a magnitude equal to the predetermined value (Tmin).
- Tmin the predetermined value
- ( ⁇ 1 ′′ b ⁇ V1) ( ⁇ 3 ′′ b ⁇ V3) employed later is twice the sum of the magnitudes ( ⁇ 4 + ⁇ 6) of the pair of original non-zero vectors. It has a magnitude (Tmin ⁇ 2 ( ⁇ 4 + ⁇ 6)) subtracted from the predetermined value (Tmin).
- the non-value vector is not interposed between the pair of compensation vectors and the pair of correction vectors.
- the original non-zero vector having a magnitude equal to or larger than the predetermined value (Tmin) is adopted as the correction vector.
- the original vector is adopted at the start time point (ts) and the end time point (te) of the predetermined period, and is equal to each other.
- the valueless vector ( ⁇ 0 ⁇ V0) ( ⁇ 7 ⁇ V7) is further included.
- the vector command at least at the start time (ts) of the predetermined period, the one pair of valueless vectors included in the original vector is employed.
- the current for each phase flowing from the power converter to the inductive load is impaired in the overall magnetic flux trajectory. And can be estimated from the current flowing in the DC bus.
- At least two magnitudes of vector commands corresponding to different non-zero voltage vectors can be set to a predetermined value or more.
- the number of times of switching can be reduced.
- the number of times of switching can be further reduced.
- the magnetic flux deviation can be reduced as compared with the aspect in which the number of times of switching is minimized.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combination compensation vector in 1st Embodiment The vector diagram which shows a synthetic
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- combines this in 1st Embodiment.
- the vector figure which shows the original vector which 2nd Embodiment can apply.
- FIG. 1 is a block diagram illustrating a power converter control device according to the following embodiment.
- the inverter 3 serving as a power converter includes three current paths connected in parallel between the pair of DC buses LH and LL.
- a DC voltage E is applied between the DC buses LH and LL, and the potential of the DC bus LH is higher than the potential of the DC bus LL.
- the three current paths have connection points Pu, Pv, and Pw, respectively.
- the current path having the connection point Pu has a pair of switches 4up and 4un connected in series between the DC buses LH and LL via the connection point Pu.
- the current path having the connection point Pv has a pair of switches 4vp and 4vn connected in series between the DC buses LH and LL via the connection point Pv.
- the current path having the connection point Pw has a pair of switches 4wp and 4wn connected in series between the DC buses LH and LL via the connection point Pw. Switches 4up, 4vp, and 4wp are arranged closer to DC bus LH than switches 4un, 4vn, and 4wn, respectively.
- the inverter 3 applies voltages Vu, Vv, Vw from the connection points Pu, Pv, Pw to the inductive load 5 by opening / closing (conductive / non-conductive state) of the switches 4up, 4vp, 4wp, 4un, 4vn, 4wn, respectively.
- Currents Iu, Iv, and Iw are supplied.
- the currents Iu, Iv, and Iw are three-phase line currents, and the voltages Vu, Vv, and Vw are three-phase phase voltages.
- the inductive load 5 is a three-phase load, for example, an electric motor. In the electric motor, a rotating magnetic flux corresponding to a magnetic flux vector described later is formed (for example, see Non-Patent Document 3).
- the inductive load 5 will be described below by taking as an example a case where it has a so-called Y-connected three-phase coil. Therefore, the phase current and the line current have the same meaning.
- the inductive load 5 has a three-phase coil that is ⁇ -connected, it is easy to estimate the phase current from the line current, and the description in that case is omitted here.
- the DC link current Id flowing through the DC bus LL is DC and flows away from the inverter 3.
- a method for detecting the DC link current Id it is known to measure a voltage drop in a resistance element or adopt a current transformer.
- the DC link current Id also flows in the DC bus LH, and its direction is a direction approaching the inverter 3.
- the means for detecting the DC link current Id may be arranged on any of the DC buses LL and LH.
- the inverter control device 6 as a power converter control device receives switching signals Gup, Gvp, Gwp, Gun, Gvn, Gwn for controlling the opening and closing of the switches 4up, 4vp, 4wp, 4un, 4vn, 4wn, respectively, to control the inverter 3. Output. That is, the switching pattern in the inverter 3 is directly determined by the switching signals Gup, Gvp, Gwp, Gun, Gvn, Gwn.
- the inverter control device 6 includes a phase current calculation unit 61, a difference command generation unit 62, an original vector generation unit 63, a correction vector generation unit 64, a compensation vector generation unit 65, and a vector integration unit. 66 and a switching signal generator 67.
- the phase current calculation unit 61 detects the DC link current Id, calculates based on the DC link current Id and the vector command [ ⁇ V] *, and obtains estimated values of the three-phase currents Iu, Iv, and Iw.
- the symbol [] indicates that the enclosing symbols make sense as a whole, and is adopted as an expression to clarify that it is not the product of ⁇ and V (the same applies hereinafter).
- the vector command [ ⁇ V] * has information about the switching pattern in the inverter 3 and the time when the switching pattern is adopted, as will be described later. Since the method of calculating the phase current from these information and the DC link current Id is known, the details thereof are omitted here.
- the switching signal generation unit 67 determines the switching signal Gup based on the switching pattern of the vector command [ ⁇ V] * and the time when the switching pattern is employed. , Gvp, Gwp, Gun, Gvn, Gwn. Since such a generation method is also known, its details are omitted here.
- the difference command generation unit 62 is based on the currents Iu, Iv, Iw (which are strictly estimated values, but in the following, for simplicity, they are mixed with actual values) and the current commands I * as these command values.
- the difference command ⁇ ( ⁇ ) is generated.
- a speed command may be employed instead of the input of the currents Iu, Iv, Iw and the current command I *.
- the output of the speed control is adopted as the difference command ⁇ ( ⁇ ).
- the currents Iu, Iv, and Iw are used as information for sensorless vector control, for example.
- the difference command ⁇ ( ⁇ ) coincides with the command value corresponding to the change of the magnetic flux vector in the period in which the inverter control device 6 controls the inverter 3.
- FIG. 2 is a vector diagram showing the basic concept and voltage vectors employed in the respective embodiments.
- voltage vectors are represented in the complex plane. Since the inverter 3 operates corresponding to the three phases of the U phase, the V phase, and the W phase, the voltage E or the voltage 0 is ideally applied between the DC bus LL and the connection points Pu, Pv, and Pw.
- the As for the three-digit numerical value that determines the voltage vector 1/0 of the third digit is 2 according to the voltage E / 0 applied to the connection point Pu, and 1/0 of the third digit is 2 according to the voltage E / 0 applied to the connection point Pv.
- the 1/0 of the first digit is adopted according to the voltage E / 0 applied to the connection point Pw. Then, the three-digit value is grasped as a binary number, and a value obtained by converting the value into a decimal number is adopted as the voltage vector number.
- the voltage vector V0 to which the voltage 0 is applied to all of the connection points Pu, Pv, and Pw and the voltage vector V7 to which the voltage E is applied to any of the connection points Pu, Pv, and Pw have a magnitude in FIG. I don't have it.
- These voltage vectors V0 and V7 are commonly referred to as zero voltage vectors.
- Zero voltage vector V0 corresponds to inductive load 5 connected only to DC bus LL
- zero voltage vector V7 corresponds to inductive load 5 connected only to DC bus LH.
- the voltage vectors V1 to V6 other than the zero voltage vector are referred to as non-zero voltage vectors.
- the non-zero voltage vectors V1 to V6 are represented on the complex plane by the following relationship.
- Non-zero voltage vectors are represented on the complex plane arranged at an angle of ⁇ / 3 starting from the zero voltage vector: (ii) For any of a pair of non-zero voltage vectors arranged at an angle of 2 ⁇ / 3 on the complex plane, a switching pattern corresponding to one of the pair of non-zero voltage vectors, and a switching pattern corresponding to the other Are common in one current path and different in the other two current paths: (iii) For any of a pair of non-zero voltage vectors arranged at an angle ⁇ on the complex plane, a switching pattern corresponding to one of the pair of non-zero voltage vectors and a switching pattern corresponding to the other The three current paths are different.
- the relationship (i) will be described with an example.
- the voltage vector V5 is arranged at an angle ⁇ / 3 with the voltage vectors V1 and V4 expressed adjacent to the voltage vector V5.
- the relationship (ii) will be described with an example.
- the voltage vectors V4 and V2 are arranged at an angle of 2 ⁇ / 3, and switching patterns corresponding to these are common to the W-phase current path (voltage vector).
- the first digit of the three-digit value that determines the value is common to 0), and is different in the V-phase current path (one of the above three-digit values is different from 0 and 1), and also in the U-phase current path There is a difference (the first digit of the above three digits is different from 1, 0).
- the relationship (iii) will be described with an example.
- the voltage vectors V4 and V3 are arranged at an angle ⁇ , and all three-digit numerical values for determining the voltage vector are different.
- the zero voltage vector V0 and the non-zero voltage vectors V1, V2, and V4 have a common switching pattern in two current paths (two digits are common among three digits that determine the voltage vector), The switching pattern is different in one current path.
- the zero voltage vector V7 and the non-zero voltage vectors V3, V5, V6 have the same switching pattern in the two current paths (two digits of the three digits that determine the voltage vector are common to one), and one The switching pattern is different in the current path.
- the voltage vector When the voltage vector is switched, it is desirable to employ a voltage vector having a common switching pattern in the two current paths before and after switching in order to reduce switching loss.
- a voltage vector having a common switching pattern For example, after the voltage vector V4 is employed, it is desirable to employ any one of the voltage vectors V0, V5, and V6 from the viewpoint of reducing the switching loss. This is to reduce the number of switching times.
- the magnitude of the non-zero voltage vector is ⁇ (2/3) ⁇ E.
- the fluctuation amount of the magnetic flux vector representing the rotating magnetic flux interlinking with the coil is expressed as a time integral of the non-zero voltage vector.
- the magnitude of the non-zero voltage vector is assumed to be 1 in order to associate the time integration with the magnitude of the non-zero voltage vector.
- E ⁇ (3/2).
- FIG. 3 is a vector diagram showing a magnetic flux vector ⁇ ( ⁇ ) representing a rotating magnetic flux and a locus drawn by the end point on a complex plane. From the viewpoint of making the rotating magnetic flux sinusoidal, it is ideally desirable that the locus draws a circle. However, since the actual control of the inverter 3 is based on the above-described voltage vector, the magnetic flux vector ⁇ ( ⁇ ) exhibits a polygon.
- the voltage vector numbers are indicated by circled numbers added to each side of the polygon.
- the time integration of the voltage vector indicated by this number is represented by this side.
- the complex plane is divided into regions of every ⁇ / 3 according to the magnitude of the angle ⁇ .
- the angle ⁇ is defined as the angle formed by the magnetic flux vector ⁇ ( ⁇ ) in the clockwise direction with respect to the combined vector of the voltage vectors V1 and V5 (0 ⁇ ⁇ ⁇ 2 ⁇ ).
- the non-zero voltage vectors adopted in each region are limited as follows. This is because it is desirable that the locus drawn by the end point of the magnetic flux vector ⁇ ( ⁇ ) draws a circle on the complex plane as described above.
- FIG. 4 is a vector diagram showing the difference command ⁇ ( ⁇ (te)).
- Such a vector is equivalent to the time integration of the three-phase voltages Vu, Vv, and Vw in one predetermined cycle on the complex plane, and the difference command ⁇ ( ⁇ (te)) itself is a pair of end points of the above-described magnetic flux vector. Asking for itself is not mandatory.
- FIG. 4 illustrates element vectors (hereinafter also referred to as “original vectors”) that have been employed in the normal circular locus method.
- the element vector is expressed as a time integral of the voltage vector, and the magnitude of the non-zero voltage vector is set to 1 in order to simplify the explanation as described above. Therefore, the size (length) of the element vector corresponding to each voltage vector represents the time during which the voltage vector is continuously maintained.
- the direction of the element vector corresponding to each voltage vector matches the direction of the voltage vector.
- element vectors (hereinafter also referred to as non-value vectors) corresponding to zero voltage vectors V0 and V7 (specifically, time integration of zero voltage vectors) are represented by zero voltage vectors V0 and V7 as shown in FIG. Since it has no magnitude, the valueless vector also has no magnitude.
- the original vector sequentially maintains a zero voltage vector V0 at time ⁇ 0, a nonzero voltage vector V4 is maintained at time ⁇ 4, and a nonzero voltage vector V6 is maintained at time ⁇ 6.
- a case is shown where the zero voltage vector V7 is maintained at ⁇ 7, the nonzero voltage vector V6 is maintained at time ⁇ 6, the nonzero voltage vector V4 is maintained at time ⁇ 4, and the zero voltage vector V0 is maintained at time ⁇ 0. .
- the element vector is expressed as a time integral of the voltage vector, for example, the element vector obtained by maintaining the non-zero voltage vector V4 at time ⁇ 4 is the non-zero voltage vector V4 and the time ⁇ 4. It is represented by the product ⁇ 4 ⁇ V4. Other element vectors are similarly described. Further, since the magnitude of the non-zero voltage vector is 1, the length (magnitude) of the element vector, which is the time integration of the non-zero voltage vector, represents the time for maintaining the corresponding non-zero voltage vector. Become.
- the following equation is satisfied.
- the voltage control rate Ks is introduced.
- the voltage control rate Ks is defined by the following equation by introducing the effective value Vi of the line voltage applied to the three-phase coil Y-connected in the inductive load 5.
- the original vector generation unit 63 generates an original vector [ ⁇ V].
- the original vector [ ⁇ V] is composed of element vectors ⁇ 0 ⁇ V0, ⁇ 4 ⁇ V4, ⁇ 6 ⁇ V6, ⁇ 7 ⁇ V7, ⁇ 6 ⁇ V6, ⁇ 4 ⁇ V4, ⁇ 0 ⁇ V0.
- a pair of element vectors ⁇ 4 ⁇ V4, ⁇ 6 ⁇ V6 corresponding to the first non-zero voltage vectors V4 and V6 appear as a difference command. Synthesize half of ⁇ ( ⁇ (te)).
- the element vectors corresponding to the zero voltage vectors V0 and V7 do not directly contribute to the synthesis of the difference command ⁇ ( ⁇ ).
- the time ⁇ 0, ⁇ 7 for maintaining the zero voltage vectors V0, V7 is an element vector corresponding to the nonzero voltage vector (hereinafter also referred to as a nonzero element vector: It can be determined depending on the time ⁇ 4, ⁇ 6 for maintaining the original vector and the non-zero element vector.
- non-zero element vector corresponds to the non-zero voltage vector
- the magnitude is zero when the period for maintaining the non-zero voltage vector is zero.
- the valueless vector is always zero in magnitude regardless of the time for which the zero voltage vector is maintained.
- the correction vector generation unit 64 outputs a pair of correction vectors [ ⁇ V] ′ every predetermined cycle T0, and the compensation vector generation unit 65 outputs a pair of compensation vectors [ ⁇ V] ′′ every predetermined cycle T0.
- the correction vector [ ⁇ V] ′ and the compensation vector [ ⁇ V] ′′ will be described with reference to FIGS. 5 and 6.
- FIG. 5 and 6 both show an original vector (original non-zero vector is indicated by a broken line arrow) adopted in a predetermined period T0 and an element vector (non-zero element vector is adopted by a solid line arrow) adopted in this basic concept.
- FIG. 5 shows a case where the time ⁇ 4 represented by the magnitude of the original non-zero vector ⁇ 4 ⁇ V4 is shorter than a predetermined minimum limit time Tmin.
- FIG. 6 shows a case where both of the times ⁇ 4 and ⁇ 6 represented by the magnitudes of the original non-zero vectors ⁇ 4 ⁇ V4, ⁇ 6 ⁇ V6 are shorter than the minimum limit time Tmin.
- the symbol Tmin is also used for the length indicating the minimum time limit Tmin in FIGS.
- the length of the element vector ⁇ 4 ⁇ V4 (corresponding to the time ⁇ 4) is shorter than the length Tmin, and in FIG. 6, the length of the element vector ⁇ 6 ⁇ V6 (corresponding to the time ⁇ 6) is also shorter than the length Tmin. Therefore, in any case, the currents Iu, Iv, and Iw cannot be estimated with the original vector.
- Tmin ⁇ ⁇ 4 ′, Tmin ⁇ ⁇ 6 ′ ⁇ 6 is adopted. That is, the original non-zero vector ⁇ 6 ⁇ V6 is adopted as the correction vector ⁇ 6 ′ ⁇ V6.
- the DC link current Id can be accurately measured, and thus the currents Iu, Iv, and Iw can be estimated for each predetermined period T0.
- a pair of correction vectors correspond to different non-zero voltage vectors V4 and V6, and these non-zero voltage vectors V4 and V6 correspond to original non-zero vectors.
- such a relationship is not essential in the present embodiment, as long as the size is equal to or greater than the length Tmin and corresponds to different non-zero voltage vectors.
- the zero voltage vector V0 when the zero voltage vector V0 is employed, it is desirable that the non-zero voltage vector employed immediately before / after that is any one of the voltage vectors V1, V2, and V4 from the viewpoint of reducing the switching loss.
- the zero voltage vector V0 it is not desirable to use the voltage vectors V1 and V2 (since the region of 0 ⁇ ⁇ ⁇ ⁇ / 3 is considered here). Therefore, when the zero voltage vector V0 is employed, it is desirable that the non-zero voltage vector employed immediately before / after that is the voltage vector V4.
- the zero voltage vector V7 when the zero voltage vector V7 is adopted, it is desirable that the non-zero voltage vector adopted immediately before / after that is the voltage vector V6 (first matter: referred later).
- the voltage vectors V0, V4, V6, V7, V6, V4, and V0 are employed in this order based on the original vectors. This is desirable from the viewpoint of reducing the above-described switching loss. Therefore, the element vectors ⁇ 4 ′ ⁇ V4, ⁇ 6 ′ ⁇ V6 are adopted in this order after the voltage vector V0 is adopted at the start of the predetermined period T0. However, the time ⁇ 0 ′′, ⁇ 7 ′′ for maintaining the voltage vectors V0, V7 has a high degree of freedom as will be described later.
- the compensation vector is an element vector that combines the difference command ⁇ ( ⁇ ) with a pair of correction vectors.
- the compensation vector is also a non-zero element vector corresponding to a pair of different voltage vectors.
- the compensation vectors ⁇ ′′ 6 ⁇ V6, ⁇ 4 ′′ ⁇ V4 are used. Since the correction vector has already been adopted in the predetermined period T0, it is not necessary to accurately measure the DC link current Id. Therefore, the magnitude relationship between the time ⁇ ′′ 4, ⁇ ′′ 6 and the minimum limit time Tmin is not questioned. Therefore, in the special case described above, any of the times ⁇ ′′ 4 and ⁇ ′′ 6 may be zero.
- the valueless vector ⁇ 0 ⁇ V0 employed in the original vector may be employed as the valueless vector ⁇ 0 ′′ ⁇ V0 employed at the start of the predetermined period T0. In that case, the following formula (6) needs to be satisfied.
- the original vector generation unit 63 only needs to output a pair of original non-zero vectors among the original vectors [ ⁇ V].
- the compensation vector is set so as to combine the difference command ⁇ ( ⁇ ) with the pair of correction vectors. Therefore, the compensation vector generator 65 receives the correction vector [ ⁇ V] ′ and the difference command ⁇ ( ⁇ ).
- the correction vector generation unit 64 it is sufficient to input only a pair of original non-zero vectors to the correction vector generation unit 64, and it is not necessary to input the difference command ⁇ ( ⁇ ). If the magnitude of one of the input pair of original non-zero vectors is greater than or equal to the length Tmin, it is sufficient to output this as it is as one of the correction vectors [ ⁇ V] ′. If at least one of the magnitudes is less than the length Tmin, the correction vector [ ⁇ V] ′ is generated based on the non-zero voltage vector selected independently of the corresponding non-zero voltage vector. can do.
- the non-zero voltage vector to which the original vector corresponds and the non-zero voltage vector to which the correction vector corresponds are obtained. It is desirable to match.
- the order in which the correction vector [ ⁇ V] ′ is adopted matches the order in which the original vector [ ⁇ V] is adopted from the viewpoint of reducing the switching frequency and switching loss.
- the vector integration unit 66 receives the correction vector [ ⁇ V] ′ and the compensation vector [ ⁇ V] ′′, sets at least one valueless vector, integrates them, and outputs a vector command [ ⁇ V] *. 5 and FIG. 6, a null vector ⁇ 7 ′′ ⁇ v7, ⁇ ′′ 0 ⁇ V0 is set, and ⁇ ′′ 0 ⁇ V0, ⁇ 4 ′ ⁇ V4 is set as a vector command [ ⁇ V] *. , ⁇ 6 ′ ⁇ V6, ⁇ 7 ′′ ⁇ v7, ⁇ 6 ′′ ⁇ V6, ⁇ 4 ′′ ⁇ V6, ⁇ ′′ 0 ⁇ V0 and the order thereof are output.
- the vector command [ ⁇ V] * uniquely determines the order of voltage vectors employed in the predetermined period T0 and the period for maintaining them.
- time for maintaining the zero voltage vectors V0 and V7 since there is a degree of freedom regarding the time for maintaining the zero voltage vectors V0 and V7, the time for maintaining the zero voltage vector V0 employed at the start of the predetermined period T0 and the period of the predetermined period T0. It is not necessary to set the time ⁇ 0 ′′ equal to the time for maintaining the zero voltage vector V0 adopted in FIG. For example, either time can be set to zero, or both can be set to zero (second matter: referred later). However, in the latter case, the degree of freedom with respect to time ⁇ 7 ′′ is lost.
- the vector command [ ⁇ V] * includes the correction vector [ ⁇ V] ′, at least two magnitudes corresponding to the different nonzero voltage vectors (time integration of the nonzero voltage vectors) are equal to or longer than the length Tmin. . Then, the difference command ⁇ ( ⁇ ) is obtained within the predetermined period T0 by combining the vector command [ ⁇ V] *.
- the inverter 3 when the inverter 3 is controlled based on the locus of the magnetic flux vector ⁇ ( ⁇ ), the currents Iu, Iv, Iw flowing from the inverter 3 to the inductive load 5 are grasped in a time equal to or longer than a predetermined period T0. It is possible to estimate for each phase from the DC link current Id flowing in the DC bus LL without impairing the trajectory of the overall magnetic flux vector ⁇ ( ⁇ ).
- the original vector generation unit 63, the correction vector generation unit 64, the compensation vector generation unit 65, and the vector integration unit 66 can be grasped as a vector command generation unit that generates a vector command [ ⁇ V] *.
- the vector command generation unit includes a microcomputer and a storage device.
- the microcomputer executes each processing step (in other words, a procedure) described in the program.
- the storage device is composed of one or more of various storage devices such as a ROM (Read Only Memory), a RAM (Random Access Memory), a rewritable nonvolatile memory (EPROM (Erasable Programmable ROM), etc.), and a hard disk device, for example. Is possible.
- the storage device stores various information, data, and the like, stores a program executed by the microcomputer, and provides a work area for executing the program.
- microcomputer functions as various means corresponding to each processing step described in the program, or can realize that various functions corresponding to each processing step are realized.
- the microcomputer functions as various means corresponding to the original vector generation unit 63, the correction vector generation unit 64, the compensation vector generation unit 65, and the vector integration unit 66, respectively.
- the vector command generation unit may implement part or all of the original vector generation unit 63, the correction vector generation unit 64, the compensation vector generation unit 65, and the vector integration unit 66 in hardware.
- First embodiment In the first embodiment, a technique for reducing the number of times of switching is introduced in order to reduce the switching loss.
- the compensation vectors ⁇ ′′ 6 ⁇ V6, ⁇ 4 ′′ ⁇ V4 are employed as the compensation vector [ ⁇ V] ′′.
- the non-zero voltage vector to which the compensation vector [ ⁇ V] ′′ corresponds and the non-zero voltage vector to which the original non-zero vector corresponds to the original vector [ ⁇ V] do not necessarily match. If the difference command ⁇ ( ⁇ ) is obtained by combining the correction vector [ ⁇ V] ′ and the compensation vector [ ⁇ V] ′′, the trajectory of the overall magnetic flux vector ⁇ ( ⁇ ) grasped in a time longer than the predetermined period T0. It is because it does not spoil.
- a vector obtained by synthesizing a pair of compensation vectors [ ⁇ V] ′′ is treated as a synthesized compensation vector Vp.
- the null vector ⁇ 0 ⁇ V0 is adopted at both the start time and the end time of the predetermined period T0 in the original vector [ ⁇ V], and the vector command [ ⁇ V] * Of these, a case where it is assumed that the null vector ⁇ 0 ′′ ⁇ V0 is adopted at both the start time and the end time of the predetermined period T0 is illustrated. Such a limitation does not affect the technique for reducing the number of times of switching.
- the difference command ⁇ ( ⁇ ) is synthesized only with the correction vector [ ⁇ V] ′ and the compensation vector [ ⁇ V] ′′; either one of the original non-zero vectors If the magnitude is less than the length Tmin, the sum of the time for adopting only the correction vector [ ⁇ V] ′ and the compensation vector [ ⁇ V] ′′ is usually shorter than the predetermined period T0, so that the vector command [ ⁇ V] * Always contains a valueless vector.
- the vector command [ ⁇ V] * adopts the null vector ⁇ 7 ′′ ⁇ V7 between the correction vector [ ⁇ V] ′ and the compensation vector [ ⁇ V] ′′. There remains a degree of freedom.
- the non-zero voltage vector to which the correction vector [ ⁇ V] ′ corresponds matches the non-zero voltage vector to which the original non-zero vector corresponds, including the order of adoption.
- the description is limited to the case of 0 ⁇ ⁇ ⁇ ⁇ / 3, and therefore correction vectors ⁇ ′4 ⁇ corresponding to the non-zero voltage vectors V4 and V6 in order from the start time of the predetermined period T0.
- V4 ′, ⁇ 6 ′ ⁇ V6 is employed will be described.
- FIG. 7 is a vector diagram showing an original vector (indicated by a broken line), a correction vector, and a combined compensation vector in a predetermined period T0.
- a case where the combined compensation vector Vp falls within the triangular region formed by the line segments connecting the voltage vectors V4 and V6 and the respective end points in FIG. 2 is illustrated. In such a case, the relationship of Expression (7) is established.
- 8 to 10 are vector diagrams showing the combined compensation vector Vp and a pair of compensation vectors for combining them.
- FIG. 8 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 6 ′′, V6, ⁇ 4 ′′, and V4 corresponding to the two non-zero voltage vectors V6 and V4, respectively.
- FIG. 9 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 5 ′′, V5, ⁇ 6 ′′, and V6 corresponding to the two non-zero voltage vectors V5 and V6, respectively.
- FIG. 10 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 4 ′′, V4, ⁇ 2 ′′, and V2 corresponding to the two non-zero voltage vectors V4 and V2, respectively.
- the compensation vector [ ⁇ V] ′′ is the compensation vector ⁇ 6 ′′ ⁇ V6. It can be seen that it is desirable to adopt ⁇ 4 ′′ ⁇ V4.
- the compensation vector [ ⁇ V] '' is adopted.
- the vector command [ ⁇ V] * adopts the non-value vector ⁇ 7 ′′ ⁇ V7
- this is adopted immediately after the correction vector ⁇ 6 ′ ⁇ V6, so that the first one of the compensation vector [ ⁇ V] ′′ is adopted.
- the non-zero voltage vector corresponding to the compensation vector [ ⁇ V] ′′ employed first is the non-zero voltage vector V1. , V2, V4, and preferably non-zero voltage vectors V3, V5, V6.
- the non-zero voltage vector corresponding to the compensation vector [ ⁇ V] ′′ employed first is the correction vector ⁇ 6 ′ employed later among the correction vectors [ ⁇ V] ′.
- the same non-zero voltage vector V6 is most desirable for the non-zero voltage vector V6 corresponding to V6.
- the mode in which one of the compensation vectors [ ⁇ V] ′′ corresponds to the non-zero voltage vector V6 is shown in FIGS.
- the number of times of switching in the transition between the compensation vectors [ ⁇ V] ′′ is smaller in the aspect shown in FIG. Therefore, even when the non-value vector ⁇ 7 ′′ ⁇ V7 is not adopted in the vector command [ ⁇ V] *, the compensation vectors ⁇ 6 ′′ ⁇ V6, ⁇ 4 ′′ ⁇ V4 are adopted in this order, as in the case where it is adopted. It is desirable.
- the fact that the compensation vector ⁇ 4 ′′ ⁇ V4 is adopted after the compensation vector ⁇ 6 ′′ ⁇ V6 means that the null vector ⁇ 0 ′′ ⁇ V0 is adopted immediately after the compensation vector ⁇ 4 ′′ ⁇ V4 is adopted. It is desirable from the viewpoint.
- the non-zero voltage corresponding to the compensation vector ⁇ 6 ′′ ⁇ V6 This is because the switching between conduction / non-conduction is less than the transition between the voltage vector V6 and the zero voltage vector V0 corresponding to the non-value vector ⁇ 0 ′′ ⁇ V0.
- the time ⁇ 6 ′′ and ⁇ 4 ′′ can be determined by the equation (8).
- FIG. 11 is a vector diagram showing an original vector (indicated by a broken line), a correction vector, and a combined compensation vector in a predetermined period T0.
- a case where the combined compensation vector Vp falls within a triangular region formed by line segments connecting the voltage vectors V6 and V2 and the respective end points in FIG. 2 is illustrated. In such a case, the relationship of Formula (9) is established.
- 12 to 14 are vector diagrams showing the combined compensation vector Vp and a pair of compensation vectors for combining the combined compensation vector Vp.
- FIG. 12 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 3 ′′ ⁇ V3, ⁇ 6 ′′ ⁇ V6.
- FIG. 13 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 6 ′′ ⁇ V6, ⁇ 2 ′′ ⁇ V2.
- FIG. 14 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 4 ′′ ⁇ V4, ⁇ 2 ′′ ⁇ V2.
- FIG. 13 shows that the compensation vectors ⁇ 6 ′′ ⁇ V6, ⁇ 2 ′′ ⁇ V2 are preferably employed in this order.
- the non-zero voltage vectors V6 and V2 form an angle ⁇ / 3 on the complex plane shown in FIG.
- the switching between conduction / non-conduction is less than the transition between the non-zero voltage vector V6 and the zero voltage vector V0. is there.
- the time ⁇ 6 ′′ and ⁇ 2 ′′ can be determined by the equation (10).
- FIG. 15 is a vector diagram showing an original vector (indicated by a broken line), a correction vector, and a combined compensation vector in a predetermined period T0.
- the combined compensation vector Vp falls within the triangular region formed by the line segments connecting the voltage vectors V2 and V3 and the respective end points in FIG. In such a case, the relationship of Formula (11) is established.
- FIGS. 16 to 18 are vector diagrams showing the combined compensation vector Vp and a pair of compensation vectors for combining them.
- FIG. 16 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 6 ′′ ⁇ V6, ⁇ 3 ′′ ⁇ V3.
- FIG. 17 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 1 ′′ ⁇ V1, ⁇ 2 ′′ ⁇ V2.
- FIG. 18 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 3 ′′ ⁇ V3, ⁇ 2 ′′ ⁇ V2.
- the transition between the zero voltage vector V 7 and the non-zero voltage vector V 3 switches between conduction / non-conduction for the switches 4 un and 4 up. Switching is required once, and switching between the non-zero voltage vector V2 and the zero voltage vector V0 switches between conduction / non-conduction for the switches 4vn and 4vp, and one switching is required.
- the switch 4un, 4up, 4wn, 4wp is turned on / off at the transition between the zero voltage vector V7 and the non-zero voltage vector V2. Will need to be switched twice. In the transition between the non-zero voltage vector V3 and the zero voltage vector V0, the switches 4vn, 4vp, 4wn, and 4wp are switched between conduction / non-conduction and two switching operations are required.
- the compensation vectors ⁇ 3 ′′ ⁇ V3, ⁇ 2 ′′ ⁇ V2 are obtained from the viewpoint of reducing the switching frequency and reducing the switching loss. It is desirable to employ them in this order.
- the switch 4un, 4up, 4wn, 4wp is turned on / off at the transition between the nonzero voltage vector V6 and the nonzero voltage vector V3.
- the conduction is switched and two switching operations are required.
- the conduction / non-conduction is switched for the switches 4vn and 4vp, and one switching is required.
- the switch between the non-zero voltage vector V6 and the non-zero voltage vector V2 switches between conduction / non-conduction for the switches 4un and 4up. Switching once. In the transition between the non-zero voltage vector V3 and the zero voltage vector V0, the switches 4vn, 4vp, 4wn, and 4wp are switched between conduction / non-conduction and two switching operations are required.
- the compensation vectors ⁇ 3 ′′, V3, ⁇ 2 ′′, and V2 are employed in this order from the viewpoint of reducing the number of times of switching regardless of whether or not the non-value vector ⁇ 7 ′′ and V7 are adopted in the vector command [ ⁇ V] *. It is desirable.
- FIG. 19 is a vector diagram showing an original vector (shown by a broken line), a correction vector, and a combined compensation vector in a predetermined period T0.
- the case where the combined compensation vector Vp falls within the triangular region formed by the line segments connecting the voltage vectors V3 and V1 and the respective end points in FIG. 2 is illustrated. In such a case, the relationship of Formula (13) is established.
- 20 to 22 are vector diagrams showing the combined compensation vector Vp and a pair of compensation vectors for combining them.
- FIG. 20 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 3 ′′ ⁇ V3, ⁇ 1 ′′ ⁇ V1.
- FIG. 21 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 2 ′′ ⁇ V2, ⁇ 1 ′′ ⁇ V1.
- FIG. 22 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 5 ′′ ⁇ V5, ⁇ 3 ′′ ⁇ V3.
- the switches 4un, 4up, 4vn, and 4vp are turned on / off at the transition between the zero voltage vector V7 and the non-zero voltage vector V1. Will need to be switched twice. In the transition between the non-zero voltage vector V3 and the zero voltage vector V0, the switches 4vn, 4vp, 4wn, and 4wp are switched between conduction / non-conduction and two switching operations are required.
- the compensation vectors ⁇ 3 ′′ ⁇ V3, ⁇ 1 ′′ ⁇ V1 are obtained from the viewpoint of reducing the switching frequency and the switching loss. It is desirable to employ them in this order.
- the switch 4un, 4up, 4wn, 4wp is turned on / off at the transition between the nonzero voltage vector V6 and the nonzero voltage vector V3.
- the conduction is switched and two switching operations are required.
- the conduction / non-conduction is switched for the switches 4wn and 4wp, and one switching is required.
- the compensation vectors ⁇ 3 ′′, V3, ⁇ 1 ′′, and V1 are adopted in this order from the viewpoint of reducing the number of switching regardless of whether or not the non-value vector ⁇ 7 ′′ and V7 are adopted in the vector command [ ⁇ V] *. Is desirable.
- FIG. 23 is a vector diagram showing an original vector (indicated by a broken line), a correction vector, and a combined compensation vector in a predetermined period T0.
- a case where the combined compensation vector Vp falls within the triangular region formed by the line segments connecting the voltage vectors V1 and V5 and the respective end points in FIG. 2 is illustrated. In such a case, the relationship of Formula (15) is established.
- 24 to 26 are vector diagrams showing the combined compensation vector Vp and a pair of compensation vectors for combining the combined compensation vector Vp.
- FIG. 24 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 1 ′′ ⁇ V1, ⁇ 4 ′′ ⁇ V4.
- FIG. 25 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 5 ′′ ⁇ V5, ⁇ 1 ′′ ⁇ V1.
- FIG. 26 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 3 ′′ ⁇ V3, ⁇ 5 ′′ ⁇ V5.
- the mode in which the number of times of switching can be reduced most depends on whether or not the non-value vector ⁇ 7 ′′ ⁇ V7 is adopted in the vector command [ ⁇ V] *.
- the compensation vectors ⁇ 5 ′′ ⁇ V5, ⁇ 1 ′′ ⁇ V1 are preferably employed in this order.
- FIG. 27 is a vector diagram showing an original vector (indicated by a broken line) correction vector and a combined compensation vector in a predetermined period T0.
- a case where the combined compensation vector Vp falls within the triangular region formed by the line segments connecting the voltage vectors V5 and V4 and the respective end points in FIG. 2 is illustrated. In such a case, the relationship of Expression (17) is established.
- 28 to 30 are vector diagrams showing the combined compensation vector Vp and a pair of compensation vectors for combining the combined compensation vector Vp.
- FIG. 28 shows a case where the synthesized compensation vector Vp is synthesized with the compensation vectors ⁇ 1 ′′ ⁇ V1, ⁇ 4 ′′ ⁇ V4.
- FIG. 29 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 5 ′′ ⁇ V5, ⁇ 6 ′′ ⁇ V6.
- FIG. 30 shows a case where the combined compensation vector Vp is combined with the compensation vectors ⁇ 5 ′′ ⁇ V5, ⁇ 4 ′′ ⁇ V4.
- the mode in which the number of times of switching can be reduced most depends on whether or not the non-value vector ⁇ 7 ′′ ⁇ V 7 is adopted in the vector command [ ⁇ V] *. It is desirable that the compensation vectors ⁇ 5 ′′ ⁇ V5, ⁇ 4 ′′ ⁇ V4 are employed in this order.
- connection points Pu, Pv, Pw and the DC bus LL (or DC bus LH) in the switching pattern corresponding to the zero voltage vector corresponding to the non-value vector in the vector command [ ⁇ V] *.
- connection points Pu, Pv, Pw and the DC bus LL (or DC bus LH) in the switching pattern corresponding to the voltage vector corresponding to the vector command [ ⁇ V] * adopted immediately after the valueless vector.
- the difference from the number of switches that conduct between them is one.
- the number of switches that are electrically connected between the connection points Pu, Pv, Pw and the DC bus LL is three.
- the number of switches that conduct with the bus LH is zero.
- the correction vector [ ⁇ V] ′ adopted immediately after the non-value vector ⁇ 0 ′′ ⁇ V0 is the correction vector ⁇ 4 ′ ⁇ V4 in any of the above six situations.
- the number of switches that are electrically connected between the connection points Pu, Pv, Pw and the DC bus LL is two. The number of switches that conduct between them is one.
- the one that is adopted first is the first compensation vector, and the one that is adopted later is the second compensation vector;
- the number of switches that conduct between the connection points Pu, Pv, Pw and the DC bus LL (or DC bus LH) is the first number;
- the second number is the number of switches that conduct between the connection points Pu, Pv, Pw and the DC bus LL (or DC bus LH);
- the switch conducting between the connection points Pu, Pv, Pw and the DC bus LL (or DC bus LH) If the number is the third number; (d-1) when the third number is 3, the first number is greater than the second number; (d-2) If the third number is 0, the first number is smaller than the second number; (d-3) When the third number is 1 or 2, the
- the vector command [ ⁇ V] * adopts the valueless vector ⁇ 7 ′′ ⁇ V7
- the vector command adopted immediately before the first compensation vector is the valueless vector ⁇ 7 ′′ ⁇ V7. Therefore, the third number is 0 for the DC bus LL and 3 for the DC bus LH, and corresponds to the cases (d-2) and (d-1).
- the vector command [ ⁇ V] * does not adopt the non-value vector ⁇ 7 ′′ ⁇ V7
- the vector command adopted immediately before the first compensation vector is the correction vector ⁇ 6 ′ ⁇ V6. Therefore, the third number is 1 for the DC bus LL and 2 for the DC bus LH, both of which correspond to the case classification (d-3) above.
- the first compensation vector and the second compensation vector are the compensation vectors ⁇ 6 ′′ ⁇ V6, ⁇ 4 ′′ ⁇ V4, respectively. Therefore, the first number is one for the DC bus LL and two for the DC bus LH, and the second number is two for the DC bus LL and one for the DC bus LH.
- the first number is 2 and the second number is 1, which satisfies the condition (d-1).
- the first number is 1 and the second number is 2, which satisfies the condition (d-2).
- the desirable mode when the expression (7) is satisfied satisfies the condition (d).
- the first number is one for the DC bus LL and two for the DC bus LH
- the second number is DC Two for the bus LL and one for the DC bus LH. Therefore, the same first number and second number are obtained as in the case where equation (7) is satisfied. Satisfies the condition (d).
- the above conditions (b), (c), ( d) is valid.
- the voltage vectors corresponding to the vectors adopted in the vector command [ ⁇ V] * are V7, V6, V4, V0, V4, V6, V7 in order from the start time of the predetermined period T0.
- the valueless vector ⁇ 7 ′′ ⁇ V7 in the vector command [ ⁇ V] * described so far there is a degree of freedom whether or not a valueless vector corresponding to the zero voltage vector V0 is adopted.
- the switch conducting between the connection points Pu, Pv, Pw and the DC bus LL.
- the number of switches is zero, and the number of switches that conduct with the DC bus LH is three.
- the correction vector [ ⁇ V] ′ adopted immediately after the non-value vector ⁇ 7 ′′ ⁇ V7 becomes the correction vector ⁇ 6 ′ ⁇ V6 in any of the above six situations (the first concept shown in “Basic Concept”). (See 1 item).
- the number of switches that conduct between the connection points Pu, Pv, Pw and the DC bus LL is one, The number of switches that conduct between them is two.
- condition (c) holds.
- condition (d) can be explained as follows.
- the vector command [ ⁇ V] * adopts the valueless vector ⁇ 0 ′′ ⁇ V0
- the vector command adopted immediately before the first compensation vector is the valueless vector ⁇ 0 ′′ ⁇ V0. Therefore, the third number is 3 for the DC bus LL and 0 for the DC bus LH, and corresponds to the cases (d-1) and (d-2).
- the vector command [ ⁇ V] * does not adopt the non-value vector ⁇ 0 ′′ ⁇ V0
- the vector command adopted immediately before the first compensation vector is the correction vector ⁇ 4 ′ ⁇ V4. Therefore, the third number is 2 for the DC bus LL and 1 for the DC bus LH, both of which correspond to the case classification (d-3) above.
- the first compensation vector and the second compensation vector are the compensation vectors ⁇ 4 ′′ ⁇ V4, ⁇ 6 ′′ ⁇ V6, respectively. Accordingly, the first number is two for the DC bus LL and one for the DC bus LH, and the second number is one for the DC bus LL and two for the DC bus LH.
- the first number is 2 and the second number is 1, which satisfies the condition (d-1).
- the first number is 1 and the second number is 2, which satisfies the above condition (d-2).
- the desirable mode when the expression (7) is satisfied satisfies the condition (d).
- the first number is one for the DC bus LH and two for the DC bus LL
- the second number is DC Two for the bus LH and one for the DC bus LL. Therefore, the same first number and second number are obtained as in the case where equation (7) is satisfied. Satisfies the condition (d).
- the magnitudes of the correction vectors ⁇ 4 ′, V4, ⁇ 6 ′, and V6 (these are the times ⁇ 4 ′ and ⁇ 6 ′ at which the non-zero voltage vectors V4 and V6 are employed, respectively).
- Any of the formulas (9), (11), (13), (15), and (17) can be established by adopting a large value.
- the times ⁇ 4 ′ and ⁇ 6 ′ are preferably as small as possible.
- Non-Patent Document 2 describes that the magnetic noise increases as the deviation of the magnetic flux increases. Therefore, in the second embodiment, selection of a compensation vector [ ⁇ V] ′′ that is desirable from the viewpoint of reducing a magnetic flux deviation (difference between a command value and an actual value) will be described.
- FIG. 31 is a vector diagram showing original vectors to which the second embodiment can be applied.
- the sum of the magnitudes of a pair of original non-zero vectors corresponding to different non-zero voltage vectors in the predetermined period T0 is half the minimum limit time Tmin (Tmin / 2). )
- Tmin Tmin / 2
- the original non-zero vectors ⁇ 4 ⁇ V4, ⁇ 6 ⁇ V6 are adopted, and it is necessary to satisfy the following equation (19).
- a correction vector whose magnitude is equal to or longer than the length Tmin is employed to obtain the estimated values of the currents Iu, Iv, and Iw.
- the minimum value of the magnitude of the correction vector for obtaining the estimated values of the currents Iu, Iv, and Iw is the length Tmin. Therefore, the trajectory of the vector command has the length of one side and the length of one diagonal line with the starting point of the difference command ⁇ ( ⁇ ) (the position indicated as the null vector ⁇ 0 ⁇ V0 in FIG. 31) as one vertex. All of these fall within the parallelogram of length Tmin. In FIG. 31, the parallelogram and the regular triangle are shown by thin lines.
- the times ⁇ 4 ′ and ⁇ 6 ′ are preferably as small as possible. Therefore, in the present embodiment for reducing the deviation of the magnetic flux, it is sufficient to consider only the case where Expression (20) holds.
- FIG. 32 is a vector diagram showing the vector command adopted in the present embodiment together with the original vector and the vector command adopted in the first embodiment.
- the original vector is indicated by a thin line arrow
- the vector command adopted in the first embodiment is indicated by a broken line
- the vector command adopted in the present embodiment is indicated by a thick line.
- Vector commands ⁇ 0 ′′ a ⁇ V0, ⁇ 4′a ⁇ V4, ⁇ 6′a ⁇ V6, ⁇ 7 ′′ a ⁇ V7, ⁇ 3 ′′ a ⁇ V3, ⁇ 1 ′′ a ⁇ V1, ⁇ 0 ′′ shown in FIG. 'a ⁇ V0 is ⁇ 0 ′′ ⁇ V0, ⁇ 4 ′ ⁇ V4, ⁇ 6 ′ ⁇ V6, ⁇ 7 ′′ ⁇ V7, ⁇ 3 ′′ ⁇ V3, ⁇ 1 ′′ ⁇ V1 respectively employed in the first embodiment. , ⁇ 0 ′′ ⁇ V0 (see FIGS. 19 and 20).
- the time integration of the magnetic flux deviation more specifically, the magnetic flux deviation in the predetermined period T0, compared to the vector command adopted in the first embodiment. (Hereinafter referred to as “magnetic flux deviation integration”) can be reduced.
- FIG. 33 shows a vector diagram of the original vector and the locus ⁇ ( ⁇ ) ⁇ of the ideal magnetic flux vector ⁇ ( ⁇ ) at the predetermined period T0.
- the trajectory ⁇ ( ⁇ ) ⁇ is an arc, and the vector from its start point to its end point coincides with the difference command ⁇ ( ⁇ ) (see FIG. 4).
- Region d1 a region in which the zero voltage vector employed at the beginning of the predetermined period T0 is maintained;
- Region d2 a region next to the region d1 in which the non-zero voltage vector is maintained;
- Area d3 an area that is next to area d2 and maintains a non-zero voltage vector different from area d2;
- Area d4 an area that is next to area d3 and maintains a zero voltage vector different from area d1;
- Area d5 An area that is next to the area d4 and is different from the areas d1 to d4.
- Region d1 a region in which the zero voltage vector V0 employed at the beginning of the predetermined period T0 is maintained at time ⁇ 0 ′′ a;
- Region d2 a region that follows the region d1 and maintains the non-zero voltage vector V4 at time ⁇ 4′a;
- Region d3 a region next to region d2 in which the non-zero voltage vector V6 is maintained at time ⁇ 6′a;
- Region d4 a region next to the region d3 and in which the zero voltage vector V7 is maintained at time ⁇ 7 ⁇ ;
- Area d5 Next to area d4, zero voltage vector V7, non-zero voltage vectors V3, V1 and zero voltage vector V0 are adopted in this order, and time ( ⁇ 7 ′′ a ⁇ 7 ⁇ + ⁇ 3 ′′ a + ⁇ 1 ′′ a + ⁇ 0 '''Area corresponding to a).
- Region d1 a region in which the zero voltage vector V0 employed at the start of the predetermined period T0 is maintained at time ⁇ 0 ′′ b;
- Region d2 a region next to region d1, in which the non-zero voltage vector V4 is maintained at time ⁇ 4′b;
- Region d3 a region next to the region d2 in which the non-zero voltage vector V2 is maintained at time ⁇ 2′b;
- Region d4 a region next to the region d3 and in which the zero voltage vector V7 is maintained at time ⁇ 7 ⁇ ;
- Area d5 Next to area d4, zero voltage vector V7, non-zero voltage vectors V5, V1 and zero voltage vector V0 are adopted in this order, and time ( ⁇ 7 ′′ b ⁇ 7 ⁇ + ⁇ 5 ′′ b + ⁇ 1 ′′ b + ⁇ 0) The area corresponding to '''b).
- the period during which the voltage vector is maintained in these regions does not necessarily match between the first embodiment and the second embodiment.
- the region d1 matches in both. That is, it is desirable that the following expression (23) is established.
- the magnetic flux deviation integration for the region d1 is the same as the case where the vector command of the first embodiment is adopted and the second implementation. This is the same as when the vector command of the form is adopted.
- Equation (21) is established, and the region d2 matches the vector command of the first embodiment and the vector command of the second embodiment. Further, the correction vectors ⁇ 4′a ⁇ V4 and ⁇ 4′b ⁇ V4 have the same corresponding non-zero voltage vector V4. Therefore, the magnetic flux deviation integration for the region d2 is the same when the vector command of the first embodiment is adopted and when the vector command of the second embodiment is adopted.
- FIG. 34 is a vector diagram showing correction vectors ⁇ 4′a ⁇ V4, ⁇ 4′b ⁇ V4, ⁇ 6′a ⁇ V6, ⁇ 2′b ⁇ V2 when the end point of the magnetic flux vector ⁇ ( ⁇ ) is in the region d3. . Since Expression (21) is established, the vector command of the first embodiment matches the vector command of the second embodiment in the first half of the region d3.
- the correction vector ⁇ 6 is used to compare the vector command of the first embodiment and the vector command of the second embodiment with respect to the magnetic flux deviation integral. What is necessary is just to compare the distance of the point on 'a * V6, (tau) 2'b * V2, and the point on area
- the size (length) of the element vector corresponding to each voltage vector represents the time during which the voltage vector is continuously maintained. Therefore, the point (x ⁇ , y ⁇ ) at a certain time point tp during the period when the end point of the magnetic flux vector ⁇ ( ⁇ ) is on the region d3 and the point (x6, y6) on the element vector ⁇ 6′a ⁇ V6 at the time point tp. ) M6 is expressed by the following equation (24). Similarly, the distance m2 between the point (x ⁇ , y ⁇ ) and the point (x2, y2) on the element vector ⁇ 2′b ⁇ V2 at the time tp is expressed by the following equation (25). However, the x-axis was adopted in parallel with the voltage vector V4, and the y-axis was adopted in a direction perpendicular to the x-axis.
- m6 [(x ⁇ x6) 2 + (y ⁇ y6) 2 ] 1/2
- m2 [(x ⁇ x2) 2 + (y ⁇ y2) 2 ] 1/2
- the distances m6 and m2 represent the absolute value of the deviation of the magnetic flux at the time point tp during the period in which the non-zero voltage vectors V6 and V2 are employed, respectively.
- the zero voltage vector V7 is maintained at the same time ⁇ 7 ⁇ regardless of whether the vector command of the first embodiment or the vector command of the second embodiment is adopted.
- the point indicated by the non-value vector ⁇ 7 ′′ b ⁇ V7 is clearly the end point of the magnetic flux vector ⁇ ( ⁇ ) (in FIG. 32, the non-value vector ⁇ 7 ′′ a ⁇ V7). It is close to the value vector ⁇ 7 ′ ′′ 0 ⁇ V0, ⁇ 0 ′ ′′ b ⁇ V0, ⁇ 0 ⁇ V0). Therefore, in the region d4, the magnetic flux deviation integration is smaller when the vector command of the second embodiment is adopted than when the vector command of the first embodiment is adopted.
- the position of the vector command of the second embodiment is at the apex of the right regular triangle shown in FIG. Therefore, also in this case, the larger the time ⁇ 7 ⁇ , the larger the magnetic flux deviation integral. Therefore, in both the vector command of the first embodiment and the vector command of the second embodiment, it is desirable that the time ⁇ 7 ⁇ is 0 and the region d4 does not substantially exist.
- FIG. 35 shows vectors indicating compensation vectors ⁇ 3 ′′ a ⁇ V3, ⁇ 1 ′′ a ⁇ V1, ⁇ 5 ′′ b ⁇ V5, ⁇ 1 ′′ b ⁇ V1 when the end point of the magnetic flux vector ⁇ ( ⁇ ) is in the region d5.
- FIG. 35 shows vectors indicating compensation vectors ⁇ 3 ′′ a ⁇ V3, ⁇ 1 ′′ a ⁇ V1, ⁇ 5 ′′ b ⁇ V5, ⁇ 1 ′′ b ⁇ V1 when the end point of the magnetic flux vector ⁇ ( ⁇ ) is in the region d5.
- the magnetic flux deviation integral can be made zero by setting the time ⁇ 7 ⁇ to 0 when the vector command of the second embodiment is adopted. Similarly, if the time ⁇ 7 ′′ b is set to 0 when the vector command of the second embodiment is adopted, the time ⁇ 7 ′′ a is set when the vector command of the first embodiment is adopted.
- the vector integration unit 66 calculates the compensation vector ⁇ 4′b ⁇ V4, ⁇ 2′b ⁇ V2 and the correction vector ⁇ 5 ′′ b ⁇ V5, ⁇ 1 ′′ b ⁇ V1. It is desirable to obtain a vector command by integrating these without interposing a non-value vector.
- 36 to 38 are timing charts illustrating examples of lengths in which voltage vectors are adopted when a vector command is adopted in the region d5 based on the first embodiment and the second embodiment.
- graphs in which conduction / non-conduction of the switches 4up, 4vp, and 4wp are H / L are shown in the U column, the V column, and the W column, respectively, along with the voltage vector.
- the periods in which the voltage vectors V7, V3, V1, and V0 are employed are time ⁇ 7 ′ ′′ a, ⁇ 3 ′′ a, and ⁇ 1 ′′ a, respectively. , ⁇ 0 ′ ′′ a.
- the periods in which the voltage vectors V7, V5, V1, and V0 are employed are the times ⁇ 7 ′ ′′ b, ⁇ 5 ′′ b, and ⁇ 1 ′′, respectively. b, ⁇ 0 ′ ′′ b (refer to the second item of “Basic Concept”).
- FIG. 36 shows a case where the zero voltage vectors V0 and V7 are equally distributed, that is, the following equation (32) is established.
- FIG. 37 shows a case where the zero voltage vector V0 is not employed, that is, the following equation (33) is established.
- FIG. 38 shows a case where the zero voltage vector V7 is not adopted, that is, the following equation (34) is established.
- the boundary between the compensation vectors ⁇ 3 ′′ a ⁇ V3 and ⁇ 1 ′′ a ⁇ V1 when the vector command of the first embodiment is adopted that is, transition from the nonzero voltage vector V3 to the nonzero voltage vector V1.
- the magnetic flux deviation at the time point tq is expressed by the distance m3.
- the boundary between the non-value vector ⁇ 7 ′′ b ⁇ V7 and the compensation vector ⁇ 5 ′′ b ⁇ V5 when the vector command of the second embodiment is adopted that is, from the zero voltage vector V7 to the nonzero voltage vector V5.
- the deviation of the magnetic flux at the time tr when transitioning to is represented by the distance m5.
- one of the two positions indicating the valueless vector ⁇ 0 ⁇ V0 is located at the apex of one of the two equilateral triangles (the left side in FIG. 31) constituting the parallelogram.
- the other is inside the equilateral triangle. Therefore, Formula (35) is materialized.
- Time tr is before time tq. This is because the formula (31) is established, and it is valid in any of the cases shown in FIGS.
- the magnetic flux deviation during the period in which the non-zero voltage vector V3 is maintained in accordance with the compensation vector ⁇ 3 ′′ a ⁇ V3 of the first embodiment is not less than the distance m3. Therefore, the magnetic flux deviation integration for this period is smaller or equal when the vector command of the second embodiment is employed as compared to the case of employing the vector command of the first embodiment.
- the magnetic flux deviation during the period in which the non-zero voltage vector V3 is maintained in accordance with the compensation vector ⁇ 3 ′′ a ⁇ V3 of the first embodiment is the vector command of the second embodiment during that period. Is larger than the deviation of the magnetic flux in the case of adopting (see Equation (35)).
- the compensation vector ⁇ 1 ′′ a ⁇ V1 is employed in the first embodiment.
- the vector command of the second embodiment is adopted rather than the case where the vector command of the first embodiment is adopted. In this case, the magnetic flux deviation integral is smaller.
- the compensation vector ⁇ 1 ′′ a ⁇ V1 is employed in the first embodiment.
- the magnetic flux deviation when the vector command of the second embodiment is adopted is equal to the magnetic flux deviation when the vector command of the first embodiment is adopted.
- both of the times ⁇ 0 ′ ′′ a and ⁇ 0 ′ ′′ b are zero. Therefore, even when the time points tq and tr coincide with each other, the subsequent magnetic flux deviation integration is performed when the vector command of the second embodiment is employed rather than when the vector command of the first embodiment is employed. Is smaller.
- the times ⁇ 0 ′ ′′ a and ⁇ 0 ′ ′′ b are non-zero (as illustrated in FIGS. 36 and 38).
- the compensation vector ⁇ 0 ′ ′′ b ⁇ V0 is employed in the second embodiment. Therefore, during this period, the magnetic flux deviation integration is smaller when the vector command of the second embodiment is adopted than when the vector command of the first embodiment is adopted.
- the magnetic flux deviation integration is greater when the vector command of the second embodiment is adopted than when the vector command of the first embodiment is adopted. Become smaller or equal to each other. Therefore, considering the entire predetermined period T0, the magnetic flux deviation integral is smaller when the vector command of the second embodiment is adopted than when the vector command of the first embodiment is adopted.
- FIG. 39 is a vector diagram showing the vector command in such a case with a broken line for the vector command of the first embodiment and a solid line for the vector command of the second embodiment ("basic concept"). 1).
- the vector command of the second embodiment for reducing the magnetic flux deviation integral is less than the vector command of the first embodiment for reducing the number of times of switching. It can be grasped that (I), (II) and (III) are satisfied.
- a pair of correction vectors corresponds to a pair of non-zero voltage vectors that form an angle 2 ⁇ / 3 with each other on a complex plane;
- a pair of compensation vectors correspond to a pair of non-zero voltage vectors that form an angle ⁇ / 3 with each other on the complex plane,
- the non-zero voltage vector to which the later adopted one of the pair of correction vectors corresponds to the non-zero voltage vector to which the earlier adopted one of the pair of compensation vectors is an angle on the complex plane. Make ⁇ .
- correction vectors ⁇ 4′b ⁇ V4 and ⁇ 2′b ⁇ V2 are employed, which correspond to the non-zero voltage vectors V4 and V2, respectively.
- non-zero voltage vectors V4 and V2 form an angle 2 ⁇ / 3 on the complex plane.
- correction vectors ⁇ 6′b ⁇ V6, ⁇ 5′b ⁇ V5 are employed, which correspond to non-zero voltage vectors V6 and V5, respectively.
- non-zero voltage vectors V6 and V5 form an angle 2 ⁇ / 3 on the complex plane.
- the compensation vectors ⁇ 5 ′′ b ⁇ V5, ⁇ 1 ′′ b ⁇ V1 are employed, which correspond to the non-zero voltage vectors V5 and V1, respectively.
- non-zero voltage vectors V5 and V1 form an angle ⁇ / 3 on the complex plane.
- the compensation vectors ⁇ 2 ′′ b ⁇ V2 and ⁇ 3 ′′ b ⁇ V3 are employed, which correspond to the non-zero voltage vectors V2 and V3, respectively.
- non-zero voltage vectors V2 and V3 form an angle ⁇ / 3 on the complex plane.
- the correction vector employed later is the correction vector ⁇ 2′b ⁇ V2
- the compensation vector employed earlier is the compensation vector ⁇ 5 ′′ b ⁇ V5.
- non-zero voltage vectors V2 and V5 form an angle ⁇ on the complex plane.
- the correction vector employed later is the correction vector ⁇ 5′b ⁇ V5
- the compensation vector employed earlier is the compensation vector ⁇ 2 ′′ b ⁇ V2. These correspond to the non-zero voltage vectors V5 and V2, respectively, which form an angle ⁇ on the complex plane.
- Each of the pair of correction vectors has a size corresponding to the minimum limit time Tmin.
- the later adopted one is the sum of the sizes of the pair of original non-zero vectors. 2 times the minimum limit time Tmin.
- the first implementation is performed when the vector command of the second embodiment is adopted in consideration of the entire predetermined period T0.
- the magnetic flux deviation integral is smaller than when the vector command of the form is adopted.
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Abstract
Description
詳細な実施の形態を説明する前に、それらの実施の形態についての基本的概念を説明する。もちろん、この基本的概念も本発明の一つの実施の形態として把握することもできる。
(ii)複素平面上において角度2π/3をなして配置される一対の非零電圧ベクトルのいずれについても、一対の非零電圧ベクトルの一方に対応するスイッチングパターンと、他方に対応するスイッチングパターンとは、一つの電流経路において共通し、他の二つの電流経路において相違する:
(iii)複素平面上において角度πをなして配置される一対の非零電圧ベクトルのいずれについても、当該一対の非零電圧ベクトルの一方に対応するスイッチングパターンと、他方に対応するスイッチングパターンとは、三つの電流経路において相違する。
π/3≦θ≦2π/3:非零電圧ベクトルV6,V2;
2π/3≦θ≦π:非零電圧ベクトルV2,V3;
π≦θ≦4π/3:非零電圧ベクトルV3,V1;
4π/3≦θ≦5π/3:非零電圧ベクトルV1,V5;
5π/3≦θ≦2π:非零電圧ベクトルV5,V4
これらの領域における磁束の制御は、角度θについてπ/3毎に同様であるので、以下では各実施の形態をも含め、0≦θ≦π/3の場合のみを例にとって説明する。この場合の説明は、単に角度θの基準をπ/3だけずらせることで他の領域にも妥当するからである。
τ6=Ks・sin(θ)・T0/2;
2・τ0+τ7=T0-2・τ4-2・τ6…(1)
例えば下式が満足される。
τ7=τ0×2…(2)
但し式(1)においては電圧制御率Ksを導入した。電圧制御率Ksは、誘導性負荷5中でY結線された三相コイルに印加される線間電圧の実効値Viを導入して次式で定義される。
図1に戻って説明を続ける。原ベクトル生成部63は原ベクトル[τV]を生成する。上記図4に即して言えば、原ベクトル[τV]は要素ベクトルτ0・V0,τ4・V4,τ6・V6,τ7・V7,τ6・V6,τ4・V4,τ0・V0で構成される。図4及び式(1)から明確なように、原ベクトル[τV]のうち、最初に登場する非零電圧ベクトルV4,V6に対応する一対の要素ベクトルτ4・V4,τ6・V6が、差分指令ΔΨ(θ(te))の半分を合成する。このように、差分指令ΔΨ(θ)の半分を合成し、それぞれが異なる非零電圧ベクトル(これらは複素平面上で角度π/3をなす)に対応する一対の原ベクトルを、原非零ベクトルと称することにする。図4では原非零ベクトルτ4・V4,τ6・V6が例示されている。
図5においてはTmin≦τ6であるので、τ6'=τ6が採用されている。つまり補正ベクトルτ6'・V6として原非零ベクトルτ6・V6が採用されている。
=2・τ0''+τ7''+τ4'+τ6'+τ4''+τ6''…(5)
例えば簡単のため、所定周期T0の開始時点において採用する無値ベクトルτ0''・V0として、原ベクトルにおいて採用された無値ベクトルτ0・V0を採用することもできる。その場合には、下式(6)が成立する必要がある。
差分指令ΔΨ(θ)の合成に係わるのは非零要素ベクトルであって、無値ベクトルではない。よって、時間の和(2・τ0''+τ7'')あるいは(τ0''+τ7'')についてそれぞれ式(5)あるいは式(6)を満足させるのであれば、時間τ0'',τ7''は自由に設定することができる。
第1の実施の形態では、スイッチングロスを低減すべく、スイッチング回数を低減する技術を紹介する。
図8乃至図10はいずれも、合成補償ベクトルVpとこれを合成する一対の補償ベクトルとを示すベクトル図である。
図11は、所定周期T0における原ベクトル(破線で示す)と補正ベクトルと合成補償ベクトルとを示すベクトル図である。ここでは合成補償ベクトルVpが、図2において電圧ベクトルV6,V2及びそれぞれの終点を結ぶ線分が形成する三角形の領域内に収まる場合を例示する。このような場合は、式(9)の関係が成立している。
|2・τ4-τ4'|≦|2・τ6-τ6'|…(9)
図12乃至図14はいずれも、合成補償ベクトルVpとこれを合成する一対の補償ベクトルとを示すベクトル図である。
図15は、所定周期T0における原ベクトル(破線で示す)と補正ベクトルと合成補償ベクトルとを示すベクトル図である。ここでは合成補償ベクトルVpが、図2において電圧ベクトルV2,V3及びそれぞれの終点を結ぶ線分が形成する三角形の領域内に収まる場合を例示する。このような場合は、式(11)の関係が成立している。
|2・τ4-τ4'|>|2・τ6-τ6'|…(11)
図16乃至図18はいずれも、合成補償ベクトルVpとこれを合成する一対の補償ベクトルとを示すベクトル図である。
図19は、所定周期T0における原ベクトル(破線で示す)と補正ベクトルと合成補償ベクトルとを示すベクトル図である。ここでは合成補償ベクトルVpが、図2において電圧ベクトルV3,V1及びそれぞれの終点を結ぶ線分が形成する三角形の領域内に収まる場合を例示する。このような場合は、式(13)の関係が成立している。
図20乃至図22はいずれも、合成補償ベクトルVpとこれを合成する一対の補償ベクトルとを示すベクトル図である。
図23は、所定周期T0における原ベクトル(破線で示す)と補正ベクトルと合成補償ベクトルとを示すベクトル図である。ここでは合成補償ベクトルVpが、図2において電圧ベクトルV1,V5及びそれぞれの終点を結ぶ線分が形成する三角形の領域内に収まる場合を例示する。このような場合は、式(15)の関係が成立している。
|2・τ4-τ4'|≦|2・τ6-τ6'|…(15)
図24乃至図26はいずれも、合成補償ベクトルVpとこれを合成する一対の補償ベクトルとを示すベクトル図である。
図27は、所定周期T0における原ベクトル(破線で示す))補正ベクトルと合成補償ベクトルとを示すベクトル図である。ここでは合成補償ベクトルVpが、図2において電圧ベクトルV5,V4及びそれぞれの終点を結ぶ線分が形成する三角形の領域内に収まる場合を例示する。このような場合は、式(17)の関係が成立している。
|2・τ4-τ4'|>|2・τ6-τ6'|…(17)
図28乃至図30はいずれも、合成補償ベクトルVpとこれを合成する一対の補償ベクトルとを示すベクトル図である。
上記の合成補償ベクトルVpについて、それぞれ式(7)(9)(11)(13)(15)(17)に対応する6つの状況において採用されることが望ましい補正ベクトル[τV]'、補償ベクトル[τV]''については以下のように纏めることができる。
第1の補償ベクトルが対応する電圧ベクトルに対応するスイッチングパターンにおいて、接続点Pu,Pv,Pwと直流母線LL(あるいは直流母線LH)との間で導通するスイッチの個数を第1数とし;
第2の前記補償ベクトルが対応する電圧ベクトルに対応するスイッチングパターンにおいて、接続点Pu,Pv,Pwと直流母線LL(あるいは直流母線LH)との間で導通するスイッチの個数を第2数とし;
第1の補償ベクトルの直前に採用されるベクトル指令が対応する電圧ベクトルに対応するスイッチングパターンにおいて、接続点Pu,Pv,Pwと直流母線LL(あるいは直流母線LH)との間で導通するスイッチの個数を第3数とすると;
(d-1)第3数が3の場合には第1数は第2数よりも大きく;
(d-2)第3数が0の場合には第1数は第2数よりも小さく;
(d-3)第3数が1もしくは2の場合は第1数は第3数と等しい。
非特許文献2では磁束の偏差が大きいほど磁気騒音が大きいことが説明されている。そこで第2の実施の形態では、磁束の偏差(指令値と実際の値との差)を低減する観点で望ましい、補償ベクトル[τV]''の選定について説明する。
原ベクトルでは原非零ベクトルτ4・V4,τ6・V6が二回採用されるので、結局、差分指令ΔΨ(θ)(不図示)が、一辺の長さTminの正三角形内に収まる場合において、第2の実施の形態が適用できることになる。
式(19),(20)から本実施の形態が採用されるのは式(13)が成立する場合(図19参照)であることが判る。
第1実施の形態とは異なり、所定周期T0で零電圧ベクトルV0を維持する期間は、所定周期T0の始期と、所定周期T0の終期とでは一般に異なっていることとする。即ち、式(22)が成立するとは限らない。
以下、本実施の形態のベクトル指令を採用することにより、第1の実施の形態で採用されたベクトル指令に比べて、磁束の偏差、より具体的には所定周期T0における磁束の偏差の時間積分(以下、「磁束偏差積分」と称す)を低減できることを説明する。
領域d2:領域d1の次にあって、非零電圧ベクトルが維持される領域;
領域d3:領域d2の次にあって、領域d2とは異なる非零電圧ベクトルが維持される領域;
領域d4:領域d3の次にあって、領域d1とは異なる零電圧ベクトルが維持される領域;
領域d5:領域d4の次にあって、領域d1~d4とは異なる領域。
領域d2:領域d1の次にあって、非零電圧ベクトルV4が時間τ4'aで維持される領域;
領域d3:領域d2の次にあって、非零電圧ベクトルV6が時間τ6'aで維持される領域;
領域d4:領域d3の次にあって、零電圧ベクトルV7が時間τ7^で維持される領域;
領域d5:領域d4の次にあって、零電圧ベクトルV7、非零電圧ベクトルV3,V1及び零電圧ベクトルV0がこの順に採用され、時間(τ7''a-τ7^+τ3''a+τ1''a+τ0'''a)に相当する領域。
領域d2:領域d1の次にあって、非零電圧ベクトルV4が時間τ4'bで維持される領域;
領域d3:領域d2の次にあって、非零電圧ベクトルV2が時間τ2'bで維持される領域;
領域d4:領域d3の次にあって、零電圧ベクトルV7が時間τ7^で維持される領域;
領域d5:領域d4の次にあって、零電圧ベクトルV7、非零電圧ベクトルV5,V1及び零電圧ベクトルV0がこの順に採用され、時間(τ7''b-τ7^+τ5''b+τ1''b+τ0'''b)に相当する領域。
この場合、領域d1のみならず、領域d1において採用されるベクトル指令も一致するので、領域d1についての磁束偏差積分は、第1の実施の形態のベクトル指令を採用した場合と、第2の実施の形態のベクトル指令を採用した場合とで、一致する。
m2=[(xθ-x2)2+(yθ-y2)2]1/2…(25)
距離m6,m2は、それぞれ非零電圧ベクトルV6,V2が採用される期間の時点tpにおける磁束の偏差の絶対値を表している。
よって磁束ベクトルΨ(θ)の終点が領域d3に載る場合において、常に次式(27)が成立する。
これにより、領域d3についての磁束偏差積分は、第1の実施の形態のベクトル指令よりも、第2の実施の形態のベクトル指令の方が小さいことが判る。
τ1''b=Tmin-2・τ6-2・τ4…(29)
τ1''a=Tmin-2・τ6…(30)
τ1''a=τ5''b+τ1''b…(31)
上述のように領域d4については第2の実施の形態のベクトル指令を採用した場合に時間τ7^を0とすることで磁束偏差積分を零にすることができる。同様に考えて、第2の実施の形態のベクトル指令を採用した場合に時間τ7''bを0とすれば、第1の実施の形態のベクトル指令を採用した場合に時間τ7''aを0とした場合であってもなお、領域d5における磁束偏差積分は前者が後者以下となる。式(31)が成立する上に、第1の実施の形態のベクトル指令では、ベクトル指令τ3''a・V3の分だけ磁束偏差が多いからである。この観点から、第2の実施の形態においては、ベクトル統合部66が、補償ベクトルτ4'b・V4,τ2'b・V2と補正ベクトルτ5''b・V5,τ1''b・V1との間に、無値ベクトルを介在させずに、これらを統合してベクトル指令を得ることが望ましい。
図37は、零電圧ベクトルV0が採用されない場合、即ち次式(33)が成立している場合である。
図38は、零電圧ベクトルV7が採用されない場合、即ち次式(34)が成立している場合である。
次に、第1の実施の形態において補償ベクトルτ3''a・V3に従って時間τ3''aで非零電圧ベクトルV3が維持されている期間の磁束の偏差について考察する。
時点trは時点tq以前である。これは式(31)が成立するからであり、図36乃至図38のいずれの場合にも妥当する。
(II)一対の補償ベクトルは、相互に前記複素平面上で角度π/3をなす一対の非零電圧ベクトルに対応し、
(III)一対の補正ベクトルのうち後に採用されるものが対応する非零電圧ベクトルと、一対の補償ベクトルのうち先に採用されるものが対応する前記非零電圧ベクトルとは複素平面上で角度πをなす。
(V)一対の補償ベクトルのうち後に採用されるものは、一対の原非零ベクトルの大きさの和の二倍を最小制限時間Tminから減じた大きさを有する。
以上のように、条件(I)(II)(III)を満足することによって、所定周期T0全体で考えて、第2の実施の形態のベクトル指令を採用した場合の方が、第1の実施の形態のベクトル指令を採用した場合よりも、磁束偏差積分が小さくなる。
Claims (9)
- 誘導性負荷(5)へ三相電圧(Vu,Vv,Vw)を印加して三相電流(Iu,Iv,Iw)を供給する電力変換器(3)を、所定周期(T0)毎に制御する電力変換器制御装置(6)であって、
前記電力変換器は三つの電流経路を備え、その各々は、
接続点(Pu,Pv,Pw)と、
一対の直流母線(LL,LH)の間で前記接続点を介して直列に接続される一対のスイッチ(4up,4un)(4vp、4vn)(4wp、4wn)と
を有し、
前記三相電流は3対の前記スイッチの導通/非導通状態によって3つの前記接続点から出力され、前記導通/非導通状態は複数のスイッチングパターンに基づき、
前記スイッチングパターンに対応する電圧ベクトル(V0~V7)は、一対の零電圧ベクトル(V0,V7)と、前記零電圧ベクトル以外の6つの非零電圧ベクトル(V1~V6)とに分類され、第1の前記零電圧ベクトル(V0)は、前記誘導性負荷が第1の前記直流母線(LL)のみに接続される第1の前記スイッチングパターンに対応し、第2の前記零電圧ベクトル(V7)は、前記誘導性負荷が第2の前記直流母線(LL)のみに接続される第2の前記スイッチングパターンに対応し、
前記非零電圧ベクトルは複素平面上において前記零電圧ベクトルを始点として角度π/3毎に配置されて表され、
前記複素平面上において角度2π/3をなして配置される一対の前記非零電圧ベクトルのいずれについても、当該一対の前記非零電圧ベクトルの一方に対応する前記スイッチングパターンと、他方に対応する前記スイッチングパターンとは、一つの前記電流経路において共通し、他の二つの前記電流経路において相違し、
前記複素平面上において角度πをなして配置される一対の前記非零電圧ベクトルのいずれについても、当該一対の前記非零電圧ベクトルの一方に対応する前記スイッチングパターンと、他方に対応する前記スイッチングパターンとは、三つの前記電流経路において相違し、
前記電力変換器制御装置は、
前記誘導性負荷に印加される前記三相電圧の、前記複素平面上における一の前記所定周期での時間積分と等価の差分指令(ΔΨ(θ))を生成する差分指令生成部(62)と、
各々が前記電圧ベクトルの時間積分であって、前記差分指令を合成する複数のベクトル指令([τV]*)を出力するベクトル指令生成部(63,64,65)と、
前記ベクトル指令に基づいて、前記3対のスイッチの前記導通/非導通状態を制御するスイッチング信号(Gup,Gvp,Gwp,Gun,Gvn,Gwn)を生成するスイッチング信号生成部(67)と、
前記直流母線に流れる電流(Id)を検出し、前記電流及び前記ベクトル指令に基づいて、前記三相電流の推定値を得る相電流演算部(61)と、
を備え、
前記ベクトル指令のうち異なる前記非零電圧ベクトルの時間積分であるものの少なくとも二つの大きさが、前記電流を前記相電流演算部が検出するために前記スイッチングパターンを最低限維持することが必要な時間に対応する所定値(Tmin)以上である、電力変換器制御装置。 - 前記ベクトル指令生成部は、
前記所定周期(T0)毎に一対の原非零ベクトル(τ4・V4,τ6・V6)を含む原ベクトル(τ0・V0,τ7・V7,τ4・V4,τ6・V6)を生成する原ベクトル生成部(63)と、
前記所定周期(T0)毎に一対の補正ベクトル(τ4'・V4,τ6'・V6)(τ4'a・V4,τ6'a・V6)(τ4'b・V4,τ2'b・V2)(τ6'b・V6,τ5'b・V5)を出力する補正ベクトル生成部(64)と、
前記所定周期(T0)毎に一対の補償ベクトル(τ4''・V4,τ6''・V6)(τ3''a・V3,τ1''a・V1)(τ5''b・V5,τ1''b・V1)(τ2''b・V2,τ3''b・V3)を出力する補償ベクトル生成部(65)と、
前記一対の前記補正ベクトルと、前記一対の前記補償ベクトルと、少なくとも一つの無値ベクトル(τ0・V0)(τ7・V7)とを統合して、前記ベクトル指令を出力するベクトル統合部(66)と
を有し、
前記一対の前記原非零ベクトルは、いずれも前記非零電圧ベクトルの時間積分であって、前記複素平面上で相互に角度π/3をなし、前記差分指令(ΔΨ(θ))の半分を合成し、
前記一対の前記補正ベクトルは、いずれも前記非零電圧ベクトルの時間積分であってその大きさが前記所定値(Tmin)以上であり、互いに異なる前記非零電圧ベクトルに対応し、一の前記一対の前記補正ベクトル(τ4'・V4)(τ6'・V6)(τ4'a・V4)(τ6'a・V6)(τ4'b・V4)(τ6'b・V6)が対応する前記非零電圧ベクトルと、一の前記原非零ベクトル(τ4・V4)(τ6・V6)が対応する前記非零電圧ベクトルとは一致し、
前記一対の前記補償ベクトルは、いずれも前記非零電圧ベクトルの時間積分であって、互いに異なる前記非零電圧ベクトルに対応し、前記一対の前記補正ベクトルと相まって前記差分指令を合成し、
前記無値ベクトルの各々は前記零電圧ベクトル(V0)(V7)の時間積分であって、かつ大きさを有しない請求項1記載の電力変換器制御装置。 - 前記ベクトル指令において、前記所定周期の開始時点(ts)及び/又は前記所定周期の終了時点(te)において前記無値ベクトルが採用され、
前記ベクトル指令において、前記無値ベクトルが対応する前記電圧ベクトル(V0)(V7)に対応する前記スイッチングパターンにおいて前記接続点と前記直流母線の一方との間で導通する前記スイッチの個数と、前記無値ベクトルの直後に採用される前記ベクトル指令が対応する前記電圧ベクトル(V4)(V6)に対応する前記スイッチングパターンにおいて前記接続点と前記直流母線の前記一方との間で導通する前記スイッチの個数との差が1である、請求項2記載の電力変換器制御装置。 - 前記一対の前記補正ベクトルが対応する前記非零電圧ベクトル(V4,V6)の各々は、前記一対の前記原非零ベクトルが対応する前記非零電圧ベクトル(V4,V6)の各々と一致し、
前記一対の前記補償ベクトル(τ4''・V4,τ6''・V6)(τ6''・V6,τ2''・V2)(τ2''・V2,τ3''・V3)(τ3''・V3,τ1''・V1)(τ1''・V1,τ5''・V5)(τ5''・V5,τ4''・V4)は、相互に前記複素平面上で角度π/3をなし、
前記一対の前記補償ベクトルのうち、第1の前記補償ベクトル(τ6''・V6)(τ3''・V3)(τ5''・V5)が第2の前記補償ベクトル(τ4''・V4)(τ2''・V2)(τ1''・V1)よりも先に採用され、
前記第1の前記補償ベクトルが対応する前記電圧ベクトル(V6)(V3)(V5)に対応するスイッチングパターンにおいて、前記接続点と前記直流母線の前記一方との間で導通する前記スイッチの個数を第1数とし、
前記第2の前記補償ベクトルが対応する前記電圧ベクトル(V4)(V2)(V1)に対応するスイッチングパターンにおいて、前記接続点と前記直流母線の前記一方との間で導通する前記スイッチの個数を第2数とし、
前記第1の前記補償ベクトルの直前に採用される前記ベクトル指令(τ7''・V7)(τ7a''・V7)(τ0a''・V0)(τ6'・V6)(τ4'・V4)(τ6'a・V6)(τ4'a・V4)が対応する前記電圧ベクトル(V7)(V6)(V4)に対応する前記スイッチングパターンにおいて、前記接続点と前記直流母線の前記一方との間で導通する前記スイッチの個数を第3数とすると、
前記第3数が3の場合には前記第1数は前記第2数よりも大きく、
前記第3数が0の場合には前記第1数は前記第2数よりも小さく、
前記第3数が1もしくは2の場合は前記第1数は前記第3数と等しい、請求項3記載の電力変換器制御装置。 - 前記一対の前記原非零ベクトルの大きさ(τ4+τ6)の和が前記所定値の半分(Tmin/2)以下である場合に、
一対の前記補正ベクトル(τ4'b・V4,τ2'b・V2)(τ6'b・V6,τ5'b・V5)は、相互に前記複素平面上で角度2π/3をなす一対の前記非零電圧ベクトルに対応し、
一対の前記補償ベクトル(τ5''b・V5,τ1''b・V1)(τ2''b・V2,τ3''b・V3)は、相互に前記複素平面上で角度π/3をなす一対の前記非零電圧ベクトルに対応し、
前記一対の補正ベクトルのうち後に採用されるもの(τ2'b・V2)(τ5'b・V5)が対応する前記非零電圧ベクトル(V2)(V5)と、前記一対の補償ベクトルのうち先に採用されるもの(τ5''b・V5)(τ2''b・V2)が対応する前記非零電圧ベクトル(V5)(V2)とは前記複素平面上で角度πをなす、請求項3記載の電力変換器制御装置。 - 前記一対の前記補正ベクトルは、いずれも前記所定値(Tmin)に等しい大きさを有し、
前記一対の前記補償ベクトルのうち後に採用されるもの(τ1''b・V1)(τ3''b・V3)は、前記一対の前記原非零ベクトルの大きさ(τ4+τ6)の和の二倍を前記所定値(Tmin)から減じた大きさ(Tmin-2(τ4+τ6))を有する、請求項5記載の電力変換器制御装置。 - 一の前記所定周期中の前記ベクトル指令において、前記一対の前記補償ベクトルと前記一対の前記補正ベクトルの間には前記無値ベクトルが介在しない、請求項6記載の電力変換器制御装置。
- 前記所定値(Tmin)以上の大きさを有する前記原非零ベクトルを、前記補正ベクトルとして採用する、請求項2乃至請求項7のいずれか一つに記載の電力変換器制御装置。
- 前記原ベクトルは、前記所定周期の前記開始時点(ts)及び前記終了時点(te)において採用され、互いに等しい一対の前記無値ベクトル(τ0・V0)(τ7・V7)を更に含み、
前記ベクトル指令において少なくとも前記所定周期の前記開始時点(ts)には、前記原ベクトルに含まれる一の前記一対の前記無値ベクトルが採用される、請求項3乃至請求項7のいずれか一つに記載の電力変換器制御装置。
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