WO2014106879A1 - 放熱部材を備えた半導体装置 - Google Patents

放熱部材を備えた半導体装置 Download PDF

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Publication number
WO2014106879A1
WO2014106879A1 PCT/JP2013/007536 JP2013007536W WO2014106879A1 WO 2014106879 A1 WO2014106879 A1 WO 2014106879A1 JP 2013007536 W JP2013007536 W JP 2013007536W WO 2014106879 A1 WO2014106879 A1 WO 2014106879A1
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Prior art keywords
semiconductor device
base
sealing material
block
semiconductor element
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PCT/JP2013/007536
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English (en)
French (fr)
Inventor
越智　岳雄
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パナソニック株式会社
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Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to JP2014555397A priority Critical patent/JP6237647B2/ja
Publication of WO2014106879A1 publication Critical patent/WO2014106879A1/ja
Priority to US14/788,853 priority patent/US9437517B2/en

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Definitions

  • the present disclosure relates to a semiconductor device including a heat dissipation member and a method for manufacturing the same.
  • the heat dissipation characteristic of the semiconductor device is improved by attaching a heat sink on the main surface of the semiconductor device.
  • a conventional semiconductor device includes a semiconductor element, a substrate, a connection member, a sealing resin, and a heat sink.
  • the semiconductor element is fixed on the substrate with a die bond paste, and the electrode of the semiconductor element and the internal terminal of the substrate are connected by a connecting member.
  • the semiconductor element, the connection member, and the internal terminals of the substrate are covered with a sealing resin, and a heat sink is attached on the sealing resin with an adhesive (see, for example, Patent Documents 1 and 2).
  • the semiconductor device includes a semiconductor element 101, a substrate 102, wires 103, a heat sink 104, and a sealing resin 105.
  • the semiconductor element 101 is fixed on the substrate 102 by a die bond paste 106.
  • An electrode provided on the semiconductor element 101 and an internal terminal provided on the substrate 102 are connected by a wire 103.
  • a heat sink 104 is disposed above the semiconductor element 101 with a sealing resin 105 interposed therebetween.
  • the semiconductor element 101, the substrate 102, the wire 103, and the heat sink 104 are integrally sealed with a sealing resin 105.
  • the heat sink 104 is designed to reduce the thickness of the semiconductor device by forming a recess at a position where it interferes with the wire 103.
  • a piece-like heat sink 104 is prepared for each semiconductor device in advance, and a method of embedding in the upper part of the sealing resin 105 at the time of molding is adopted. According to this method, since the outer shape of the heat sink 104 is slightly smaller than the outer shape of the semiconductor device, the heat sink 104 is exposed only from the upper surface of the semiconductor device and not from the side surface.
  • the thickness of the semiconductor device can be reduced by forming a recess that avoids the wire 103 in the heat sink 104, the remaining thickness of the recess remains, and the thickness of the semiconductor device increases accordingly.
  • the problem of filling the sealing resin 105 and securing the flow path the gap between the heat sink 104 and the semiconductor element 101 and the gap between the heat sink 104 and the substrate 102 are reduced.
  • the exposed surface of the heat radiating plate 104 is limited to the upper surface of the semiconductor device, there is a problem that the heat radiating characteristic is lowered.
  • the semiconductor device includes a semiconductor element 201, a substrate 202, a heat sink 204, and a sealing resin 205.
  • the main surface of the semiconductor element 201 is arranged to face the main surface of the substrate 202, and the electrode on the main surface of the semiconductor element 201 and the internal terminal 208 of the substrate 202 are joined.
  • a flat heat radiation plate 204 is fixed to the back surface of the semiconductor element 201, and the gap between the substrate 202 and the heat radiation plate 204 is filled with a sealing resin 205 to be integrally sealed.
  • the main surface of the plurality of semiconductor elements 201 is changed to the main surface of a single substrate 202.
  • the heat sink 204 is fixed to the back surface of the plurality of semiconductor elements 201 with an adhesive.
  • the gap between the substrate 202 and the heat sink 204 is filled with the sealing resin 205 and molded integrally.
  • the semiconductor device is cut together with the heat radiating plate 204 to obtain a separated semiconductor device.
  • the heat sink 204 can be directly attached to the back surface of the semiconductor element 201 without avoiding the connecting member. Thereby, the improvement of the thermal radiation characteristic and thickness reduction in a semiconductor device can be made compatible.
  • the second conventional example to the wire bond method as in the first conventional example.
  • the main surface of the semiconductor element is die-bonded upward and the wires are wired, so that the wired wires interfere with the heat sink.
  • the main surface of the semiconductor element may be damaged when the heat sink is pressed against the sealing resin.
  • the flip chip method may not be applicable because the cost and reliability are inferior to those of the wire bond method.
  • This disclosure is intended to solve the above-described problems and to achieve high heat dissipation characteristics and thinning in a semiconductor device provided with a heat dissipation member manufactured by a wire bond method.
  • the present disclosure has a configuration in which a semiconductor device is provided with a space portion in a region facing a connection member in a heat sink provided above a base and a semiconductor element via a sealing material.
  • a semiconductor device includes a base in which an internal terminal is disposed on a main surface, and a first semiconductor that is held on the main surface of the base and an electrode is disposed on an upper surface.
  • a heat dissipating member A space is formed in the upper part of the connection member in the heat dissipation member, and a sealing material is disposed in the space, and the apex of the connection member is located inside the space as viewed from the side of the base. .
  • a semiconductor device includes a base on which an internal terminal is disposed on a main surface, a heat dissipating member disposed in a region excluding the internal terminal on the main surface of the base, and an upper surface of the heat dissipating member.
  • a first semiconductor element having an electrode disposed on the upper surface, a connection member connecting the internal terminal and the electrode, and covering the internal terminal, the first semiconductor element and the connection member on the main surface of the base And a sealing material arranged as described above.
  • the heat dissipation member is formed such that the upper surface of the region excluding the region where the connection member is arranged on the base is higher than the apex of the connection member.
  • the semiconductor device According to the semiconductor device according to the present invention, high heat dissipation characteristics, miniaturization and thickness reduction, and high mass productivity can be realized in a semiconductor device provided with a heat dissipation member.
  • FIG. 1A is a plan view schematically showing the configuration of the semiconductor device according to the first embodiment.
  • FIG. 1B is a front view schematically showing the configuration of the semiconductor device according to the first embodiment.
  • FIG. 1C is a right side view schematically showing the configuration of the semiconductor device according to the first embodiment.
  • FIG. 2A is a schematic diagram illustrating the configuration of the semiconductor device according to the first embodiment, and is a plan view when the sealing material is seen through in FIG. 1A.
  • 2B is a schematic diagram illustrating the configuration of the semiconductor device according to the first embodiment, and is a cross-sectional view taken along the line IIb-IIb in FIG. 2A.
  • FIG. 2C is a schematic diagram illustrating the configuration of the semiconductor device according to the first embodiment, and is a cross-sectional view taken along the line IIc-IIc in FIG. 2A.
  • FIG. 3 is a plan view schematically showing one step of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 4 is a plan view schematically showing one step of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIG. 5 is a plan view schematically showing one step of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 6 is a plan view schematically showing one step of the method for manufacturing the semiconductor device according to the first embodiment.
  • FIG. 7 is a plan view schematically showing one step of the method of manufacturing the semiconductor device according to the first embodiment.
  • FIGS. 9A to 9F are schematic views showing the semiconductor device manufacturing method according to the first embodiment in the order of steps, and are cross-sectional views taken along the line IIc-IIc in FIG. 2A.
  • FIGS. 10A to 10F are schematic views showing the method of manufacturing the semiconductor device according to the first embodiment in the order of steps, and are cross-sectional views taken along the line IIb-IIb in FIG. 2A.
  • FIG. 11A to FIG. 11E are schematic views showing another manufacturing method of the semiconductor device according to the first embodiment in order of steps, and are cross-sectional views taken along the line IIc-IIc in FIG. 2A.
  • FIG. 12A to 12E are schematic views showing another method of manufacturing the semiconductor device according to the first embodiment in the order of steps, and are cross-sectional views taken along the line IIb-IIb in FIG. 2A.
  • FIG. 13A is a plan view schematically showing the configuration of the heat dissipation member frame used in the manufacturing process of the semiconductor device according to the first embodiment.
  • FIG. 13B is a schematic view illustrating the configuration of the heat dissipation member frame used in the manufacturing process of the semiconductor device according to the first embodiment, and is a cross-sectional view taken along line XIIIb-XIIIb in FIG. 13A.
  • FIG. 13C is a schematic view illustrating the configuration of the heat dissipation member frame used in the manufacturing process of the semiconductor device according to the first embodiment, and is a cross-sectional view taken along line XIIIc-XIIIc in FIG. 13A.
  • FIG. 14A is a schematic view illustrating a configuration of a semiconductor device according to a first modification of the first embodiment, and is a plan view when a sealing material is seen through.
  • FIG. 14B is a schematic diagram illustrating the configuration of the semiconductor device according to the first modification example of the first embodiment, and is a cross-sectional view taken along line XIVb-XIVb in FIG. 14A.
  • FIG. 14C is a schematic diagram illustrating the configuration of the semiconductor device according to the first modification example of the first embodiment, and is a cross-sectional view taken along line XIVc-XIVc in FIG. 14A.
  • FIG. 15A is a plan view schematically showing a configuration of a base frame used in the manufacturing process of the semiconductor device according to the first modification example of the first embodiment.
  • FIG. 15B is a front view schematically showing the configuration of the base frame used in the manufacturing process of the semiconductor device according to the first modification example of the first embodiment.
  • FIG. 16A is a schematic diagram illustrating a configuration of a semiconductor device according to a second modification of the first embodiment, and is a plan view when a sealing material is seen through.
  • FIG. 16B is a schematic diagram illustrating the configuration of the semiconductor device according to the second modification example of the first embodiment, and is a cross-sectional view taken along line XVIb-XVIb in FIG. 16A.
  • FIG. 16C is a schematic diagram illustrating the configuration of the semiconductor device according to the second modification example of the first embodiment, and is a cross-sectional view taken along line XVIc-XVIc in FIG. 16A.
  • FIG. 17A is a plan view schematically illustrating a modification of the heat dissipation member included in the semiconductor device according to the first embodiment and the first modification.
  • FIG. 17B is a plan view schematically showing a modification of the heat dissipation member provided in the semiconductor device according to the first embodiment and the first modification.
  • FIG. 17C is a plan view schematically showing a modification of the heat dissipation member provided in the semiconductor device according to the second modification of the first embodiment.
  • FIG. 18A is a plan view schematically showing the configuration of the semiconductor device according to the second embodiment.
  • FIG. 18B is a front view schematically showing the configuration of the semiconductor device according to the second embodiment.
  • FIG. 18C is a right side view schematically showing the configuration of the semiconductor device according to the second embodiment.
  • FIG. 19A is a schematic view showing the semiconductor device according to the second embodiment, and is a plan view when the sealing material is seen through in FIG. 18A.
  • FIG. 19B is a schematic diagram illustrating the semiconductor device according to the second embodiment, and is a cross-sectional view taken along line XIXb-XIXb in FIG. 19A.
  • FIG. 19C is a schematic view illustrating the semiconductor device according to the second embodiment, and is a cross-sectional view taken along line XIXc-XIXc in FIG. 19A.
  • FIG. 20A is a plan view schematically showing the configuration of the heat dissipation member frame in one manufacturing process of the semiconductor device according to the second embodiment.
  • FIG. 20B is a schematic diagram illustrating the configuration of the heat dissipation member frame in one manufacturing process of the semiconductor device according to the second embodiment, and is a cross-sectional view taken along line XXb-XXb in FIG. 20A.
  • FIG. 21 is a cross-sectional view showing the configuration of the semiconductor device according to the first conventional example.
  • 22A to 22E are cross-sectional views showing a method of manufacturing a semiconductor device according
  • the semiconductor device includes a base 2 in which a plurality of internal terminals 8 are arranged on the main surface, and an adhesive layer on the main surface of the base 2. 6 and a semiconductor element 1 having a plurality of electrodes 7 arranged on the upper surface.
  • the base 2 is a wiring board in which a wiring layer is formed on a base material, for example, and the adhesive layer 6 is a die bond paste, for example.
  • the plurality of internal terminals 8 of the base 2 are connected to the plurality of electrodes 7 of the semiconductor element 1 by connection members 3, respectively.
  • the connection member 3 is a wire whose main material is, for example, copper (Cu), gold (Au), or the like.
  • a sealing material 5 is formed so as to integrally cover the plurality of internal terminals 8, the semiconductor element 1, and the plurality of connection members 3.
  • a plurality of external terminals 9 are disposed on the back surface opposite to the main surface of the base 2.
  • a plurality of electrodes 7 are provided on the upper surface, which is an element formation surface of the semiconductor element 1, along two opposite sides of the semiconductor element 1.
  • a heat radiating member 4 is disposed on the sealing material 5.
  • a metal material such as aluminum (Al) or copper (Cu) or an alloy material thereof can be used.
  • the heat radiating member 4 may be a plate having a flat exposed surface, for example. Notches 4a, which are spaces, are formed in the upper portions of the internal terminals 8, the connection members 3 and the electrodes 7 in the heat dissipation member 4, and the notches 4a are filled with the sealing material 5, respectively. Yes.
  • the heat dissipation member 4 includes a first block 11 having a shape along two other opposing sides where the electrode 7 in the semiconductor element 1 is not formed, and the first block 11. 2 has a planar H-shaped outer shape formed by a second block 12 and a third block 13 which is disposed above the semiconductor element 1 and connects the first block 11 and the second block 12 to each other. .
  • the electrode 7 of the semiconductor element 1, the internal terminal 8 of the base 2, and the connection member 3 are disposed below the notch 4 a of the heat dissipation member 4.
  • FIG. 2C seeing from the side surface of the base 2, the vertex of each connection member 3 is located inside the notch part 4a.
  • the heat dissipation member 4 does not interfere with the connection member 3 because the cutout portion 4a is provided directly above the arrangement region of the connection member 3. . For this reason, even in a semiconductor device in which the connection member 3 such as a wire is connected by the wire bonding method, the heat dissipation member 4 can be disposed close to the semiconductor element 1. Further, the third block 13 is overlaid on the entire region excluding the region where the connection member 3 is disposed on the semiconductor element 1.
  • the semiconductor device according to the present embodiment can significantly improve the thermal conductivity to the heat radiating member 4 while being thinner than the conventional semiconductor device.
  • the third block 13 positioned above the semiconductor element 1 in the heat dissipation member 4 is thinner than the first block 11 and the second block 12.
  • FIG. 2B between the upper surface of the semiconductor element 1 and the third block, and between the main surface of the base 2 and the first block 11 and the second block 12, Each of them can be fixed in close proximity, and the semiconductor device can be easily reduced in thickness.
  • the thickness of the third block 13 is made thinner than the first block 11 and the second block 12 by about the thickness of the semiconductor element 1, the semiconductor element 1 and the heat dissipation member 4 are brought closer to each other. Can be placed.
  • the thickness of the third block 13 is approximately the thickness of the sealing material 5, in other words, the height from the upper surface of the semiconductor element 1 to the upper surface of the sealing material 5 (thickness h0 shown in FIG. 2C). If the thickness is reduced, the semiconductor device including the heat radiating member 4 can be formed without changing the thickness of the semiconductor device from the state in which the heat radiating member 4 is not provided.
  • the configuration in which the sealing material 5 is filled in the gap between the first block 11 and the second block 12 and the base 2 and the gap between the third block 13 and the semiconductor element 1 has been described above.
  • the sealing material 5 may not be interposed in the gap, and the heat dissipation member 4 may be in direct contact with the base 2 and / or the semiconductor element 1.
  • the heat radiating member 4 is embedded in the sealing material 5 and built in the semiconductor device, and the upper surface and the side surface of the heat radiating member 4 coincide with the outer shape of the semiconductor device, respectively, It is desirable to make If it does in this way, since the thermal radiation member 4 will be exposed to an upper surface and a side surface, heat dissipation will improve, and the reliability of a semiconductor device will improve. In addition, it is possible to expect effects such as reduction in warpage and improvement in strength as a semiconductor device.
  • the thickness of the sealing material 5 is set to be several tens of ⁇ m or more thicker than the height of the top of the connecting member 3, that is, the height of the wire loop. You may make it not expose from the surface of 5. By doing in this way, since the short circuit by the connection member 3 contacting with the structure outside a semiconductor device can be prevented, the reliability of a semiconductor device improves.
  • the shape of the heat radiating member 4 is not necessarily limited to a planar H-shape, and the same function can be obtained with other planar shapes as long as the notched portion 4a that does not interfere with the arrangement region of the connecting member 3 is provided. (Manufacturing method of the first embodiment).
  • FIGS. 3 to 8 show the plane corresponding to FIG. 1A in the order of the manufacturing process
  • FIGS. 9A to 9F show the cross sections corresponding to FIG. 2C in the order of the manufacturing process
  • FIG. FIG. 10F shows a cross section corresponding to FIG. 2B in the order of the manufacturing process.
  • the heat dissipation member frame 15 is attached to the base frame 18 in which the formation regions of the plurality of semiconductor devices are arranged in a matrix, These are collectively sealed with the sealing material 5 and then divided into individual pieces.
  • FIG. 9 (a) and FIG. 10 (a) a base frame 18 used in this manufacturing method is prepared.
  • the base frame 18 includes a plurality of bases 2 and a base frame part 17 that holds the plurality of bases 2.
  • Each base 2 has a plurality of internal terminals 8 formed on its main surface along two sides facing each other.
  • a plurality of external terminals 9 are formed on the back surface of each base 2.
  • the base 2 is provided with copper wiring on the main surface and the back surface, and the main surface and the back surface are connected by a through hole (not shown). Nickel (Ni) / gold (Au) plating is formed on each surface of the internal terminal 8 and the external terminal 9 to protect the surface.
  • the matrix-like arrangement form in the plurality of bases 2 can be arbitrarily determined according to the size of the product and the base size allowed by the production line.
  • the matrix-like arrangement form of the base frame 18 is four (2 rows ⁇ 2 columns).
  • the semiconductor element 1 is mounted in a predetermined region of each base 2.
  • the semiconductor element 1 provided with a plurality of electrodes 7 on its upper surface is fixed via an adhesive layer 6 with its back surface facing the main surface of the base 2.
  • the mounting direction of the semiconductor element 1 is a direction in which the two rows of electrodes 7 provided on the semiconductor element 1 face the two rows of internal terminals 8 on the base 2.
  • the semiconductor element 1 is made of, for example, silicon (Si), and the electrode 7 is made of, for example, aluminum (Al).
  • the adhesive layer 6 is a die bond paste using, for example, a glass epoxy resin, and includes a filler (not shown).
  • each electrode 7 of the semiconductor element 1 facing each other and the internal terminal 8 of the base 2 are connected by the connecting member 3.
  • the connection member 3 for example, a gold (Au) wire is used.
  • the sealing material 5 is filled into the gap between the semiconductor element 1 and the gap between the heat dissipation member frame 15 and the base frame 18. Thereafter, the filled sealing material 5 is cured, and the base frame 18, the plurality of semiconductor elements 1 including the connection member 3, and the heat dissipation member frame 15 are integrally formed.
  • a thermosetting glass epoxy material is used for the sealing material 5 for example.
  • the heat radiating member frame 15 includes a plurality of heat radiating members 4 and a heat radiating member frame portion 14 that holds the plurality of heat radiating members 4 at outer portions.
  • the sealing material 5 becomes difficult to flow during batch molding, and it may be difficult to inject the sealing material 5. That is, sealing molding may be difficult with a normal transfer mold method. This tendency becomes stronger as the size of the base 2 and the number of matrix arrangements increase.
  • a compression molding method is applied to the resin sealing process to seal the gap between the heat dissipation member 4 and the semiconductor element 1 and the gap between the heat dissipation member 4 and the base 2. It is also possible to adopt a method in which the stopper 5 can be filled easily and reliably.
  • 11A to 11E show the cross sections corresponding to FIG. 2C in the order of the manufacturing steps
  • FIGS. 12A to 12E show the cross sections corresponding to FIG. 2B in the order of the manufacturing steps. .
  • FIGS. 13A to 13C a configuration diagram of the heat dissipation member frame 15 used in the present embodiment is shown in FIGS. 13A to 13C.
  • the heat dissipating member frame 15 includes the plurality of heat dissipating members 4 and the heat dissipating member frame portions 14 that hold the heat dissipating members 4, and the matrix arrangement of the heat dissipating members 4 is the matrix arrangement of the plurality of bases 2. Arranged together.
  • the first blocks 11 and the second blocks 12 are respectively connected in the XIIIb-XIIIb line direction, and the first block 11 and the second block 12 are connected in the XIIIc-XIIIc line direction.
  • Two blocks 12 are connected and formed integrally.
  • the heat radiating members 4 are connected to each other, and the respective cutouts 4a when formed into individual pieces are also formed as a plurality of planar quadrangular openings.
  • the third block 13 in each heat radiating member 4 is formed thinner than the first block 11 and the second block 12 by the thickness of the semiconductor element 1. ing.
  • the upper surface of the heat radiating member frame 15 thus formed is first attached to an adhesive release film 16 as shown in FIGS. 11 (a) and 12 (a).
  • the release film 16 is removed after the sealing molding process.
  • the base material of the release film 16 for example, polyimide or Teflon (registered trademark) is used, and a material having heat resistance of 170 ° C. or higher such as olefin is used as an adhesive.
  • a liquid sealing material 5 is formed on the heat dissipation member frame 15 by coating or printing.
  • the granular sealing material 5 may be spread and then melted by heating.
  • a thermosetting material such as a glass epoxy resin is used.
  • the base frame 18 on which the semiconductor element 1 is mounted for each base 2 and the connection member bonding process is performed is mounted on the heat dissipation member frame 15. Positioning is performed while facing the sealing material 5. The alignment here is performed so that at least each notch 4a overlaps with the arrangement region of each connection member 3 and does not come into contact with the heat dissipation member 4.
  • the heat radiating member frame 15 is pressed against the base frame 18 through the sealing material 5 in a molten state, and the heat radiating member frame 15 and the base The base frame 18 is pasted together.
  • the heat radiating member frame 15 and the base frame 18 are compressed (compressed) by applying pressure. Thereby, the heat radiating member frame 15, the sealing material 5, each semiconductor element 1, and the base frame 18 are integrated.
  • the step h1 between the first block 11 and the third block 13 and the step h1 between the second block 12 and the third block 13 are shown. Is preferably larger than the total thickness h2 of the semiconductor element 1 and the adhesive layer 6. In this way, when the heat radiating member frame 15 and the base frame 18 are bonded and compressed, the first block 11 and the second block 12 before the third block 13 hits the semiconductor element 1. Since the base 2 comes into contact with the base 2 and stops, it is possible to prevent damage to the element formation surface of the semiconductor element 1 due to interference between the third block 13 and the semiconductor element 1.
  • the heat radiating member 4 can be brought close to the element forming surface which is the upper surface of the semiconductor element 1 by adopting such a configuration.
  • the heat dissipation member 4 can increase the volume of the heat dissipation member 4 in the region excluding the region where the semiconductor element 1 and the connection member 3 are arranged, the heat dissipation effect of the heat dissipation member 4 can be enhanced.
  • the distance between the heat radiating member 4 and the semiconductor element 1 is as close as possible from the viewpoint of the heat radiating effect.
  • the first block 11 and the second block 12 constituting the heat dissipation member 4 function as spacers. The distance between the element 1 and the heat dissipation member 4 can be arbitrarily adjusted.
  • the thickness of each of the semiconductor element 1 and the heat radiating member 4, the variation in parallelism between the semiconductor element 1 and the heat radiating member 4, the size of the filler dispersed in the sealing material 5 and the filling property thereof are taken into consideration.
  • the distance between the semiconductor element 1 and the heat dissipation member 4 is desirably 50 ⁇ m or more and 100 ⁇ m or less.
  • the size of the filler dispersed in the sealing material 5 can be reduced, or further, the filler can be made without filler.
  • the filler size is reduced with the same dispersion amount, the viscosity of the sealing material 5 increases and the fluidity decreases.
  • the reliability of the sealing material 5 will fall. Therefore, the composition of the sealing material 5 may be properly used depending on the distance between the semiconductor element 1 and the heat dissipation member 4.
  • different sealing materials may be used in the gap between the semiconductor element 1 and the heat dissipation member 4 and other portions.
  • a sealing material 5 in which a filler having a small size is dispersed may be used only in a gap between the semiconductor element 1 and the heat dissipation member 4 or a filler-less sealing material 5 may be used.
  • Thermal conductivity may be increased.
  • the thickness of the semiconductor device can be adjusted by the heat radiating member frame 15 including the plurality of heat radiating members 4 and the heat radiating member frame portion 14 holding the heat radiating members 4. For this reason, it is also possible to omit the mold cavity. When the mold cavity is omitted, it is possible to perform sealing molding using a flat mold, so that it is not necessary to prepare a special mold, and the compatibility of the mold with other semiconductor devices is improved. Therefore, mass productivity is improved.
  • the sealing molding process in this manufacturing method can also be performed by using a mold cavity as in the past so that the sealing material 5 does not leak outside.
  • the thickness of the sealing material 5 is influenced by the usage amount of the applied sealing material 5, it is necessary to adjust the usage amount of the sealing material 5.
  • the sealing material 5 is injected into each opening of the heat radiating member frame 15.
  • a potting method or a printing method can be used.
  • the heat radiation member frame 15 and the base frame 18 are bonded together with the sealing material 5 interposed therebetween, and then the sealing material 5 is thermally cured in a compressed state, thereby sealing. The stopping process is complete.
  • the sealing method is not limited to compression molding.
  • a normal transfer mold method can also be applied.
  • the release film 16 is peeled off from the heat radiating member frame 15, and as shown in FIGS. 7, 9 (e) and 10 (e), the heat radiating member frame 15, the sealing material 5 and the base frame 18. Dicing.
  • the release film 16 can be used as a dicing film without being peeled off before dicing.
  • FIG. 8 As shown in FIG. 8, FIG. 9 (f) and FIG. 10 (f), a semiconductor device separated into pieces is obtained by dicing. At this time, since the semiconductor device is divided by cutting the heat radiating member 4 by dicing, the cut surface of the heat radiating member 4 is exposed on the outer peripheral surface of the semiconductor device.
  • the heat radiating member 4 When the plurality of heat radiating members 4 held by the heat radiating member frame portion 14 are formed integrally with the plurality of bases 2 held by the base frame portion 17 and then diced, the heat radiating member is caused by the displacement of the dicing. There is a concern that the outer shape of 4 is cut off halfway and the cross-section is uneven for each piece. However, as shown in FIG. 7, in the semiconductor device according to the present embodiment, the heat radiating member 4 has, for example, a planar H shape, so that each side of the opening that becomes the notch 4 a after cutting becomes a dicing line. On the other hand, since they always intersect perpendicularly, uncut portions are hardly generated, and the cut surfaces of all the semiconductor devices are aligned.
  • solder ball when a solder ball is required for each of the plurality of external terminals 9 arranged on the back surface of the base 2, it can be formed in a collective mounting process before the dicing process.
  • the planar shape of the heat radiating member 4 is formed to be larger than the planar shape of the base 2, and the first block 11 and the second block 12 in the heat radiating member 4 are arranged in an area outside the base 2. Is arranged. Thereby, the surface area and volume of the heat radiating member 4 can be enlarged, and the heat dissipation effect can be enhanced.
  • the first block 11 and the second block 12 in the heat radiating member 4 are each along the side surface of the base 2 on the side where the plurality of internal terminals 8 are not provided. And is formed so as to cover the side surface.
  • the width of the base 2 in the XIVb-XIVb line direction is the same as the width of the semiconductor element 1, but the width of the base 2 and the width of the semiconductor element 1 in the XIVb-XIVb line direction. Are not necessarily the same.
  • the semiconductor device according to this modification is obtained by the same process as the manufacturing method of the first embodiment described above by using the base frame 18 shown in FIGS. 15A and 15B.
  • each heat radiating member 4 can be extended to the area
  • the first block 11 and the second block 12 can be extended to the outside of the substrate, and the side surface excluding the wiring region of the connection member 3 can be formed by the heat radiating member 4. It is possible to improve characteristics, reduce warping, improve strength, and improve reliability.
  • the space provided in the heat radiating member 4 and preventing interference with the arrangement region of the connecting member 3 is an opening 4b instead of the notch 4a.
  • the first block 11 and the second block 12 in the heat radiating member 4 are arranged outside the base 2, and the internal terminals in the base 2 are arranged. It is good also as a structure which covers the side surface in which 8 is not formed.
  • each of the notch 4a and the opening 4b is not limited to the shape shown in FIGS. 1A and 16A, and may be any shape that does not interfere with the connection member 3.
  • the shapes as shown in FIGS. 17A to 17C Can be considered.
  • FIG. 17A and 17B show a modification of the notch 4a in the heat radiating member 4, and FIG. 17C shows a modification of the opening 4b in the heat radiating member 4.
  • W1 is the inner width of the notch 4a or the opening 4b
  • W2 is the outer width of the notch 4a or the opening 4b. In either case, the outer width W2 is larger than the inner width W1.
  • the notch 4a or each opening 4b is easy to distinguish between the arrangement region of the heat radiating member 4 and the arrangement region of the connection member 3, and has two high symmetry.
  • the number may be one, or three or more.
  • the heat radiating member 4 is fixed to the main surface of the base 2 with an adhesive 10, and the semiconductor device is placed on the heat radiating member 4.
  • the back surface which is the surface opposite to the element formation surface in the element 1, is fixed by the adhesive layer 6.
  • the heat dissipating member 4 includes a first block 11 and a second block 12 having a shape along two sides where the electrode 7 in the semiconductor element 1 is not formed, and the first block 11 and the second block 11 below the semiconductor element 1. It has a planar H-shaped outer shape constituted by a third block 13 that connects the second blocks 12 to each other. With this planar configuration, a plurality of internal terminals 8 provided on the main surface of the base 2 are exposed from the notches 4 a of the heat dissipation member 4.
  • the plurality of electrodes 7 provided on the upper surface of the semiconductor element 1 and the plurality of internal terminals 8 provided on the main surface of the base 2 and exposed from the cutout portions 4a of the heat radiating member 4 are respectively connected by the connection members 3. It is connected.
  • the upper surface and side surfaces of the first block 11 and the second block 12 constituting the heat radiating member 4 coincide with the outer shape of the semiconductor device, and each form one plane. .
  • the back surface of the semiconductor element 1 can be brought close to the heat radiating member 4 without interference between the heat radiating member 4 and the arrangement region of the connecting member 3,
  • the heat conduction to 4 is good.
  • the volume of the heat radiating member 4 can be increased in the region excluding the region where the connection member 3 is disposed inside the semiconductor device, the heat radiating effect by the heat radiating member 4 can be further enhanced.
  • the side surface of the semiconductor device and the lower region of the semiconductor element 1 are formed by the heat radiating member 4, in addition to high heat radiating characteristics, reduction of warpage, improvement in strength, and high reliability as a semiconductor device are achieved. realizable.
  • the height from the upper surface of the third block 13 in the first block 11 and the second block 12 constituting the heat radiating member 4 is the apex of the connecting member 3 (wire loop).
  • the height is higher than the height of the semiconductor device and is exposed from the upper surface of the semiconductor device.
  • the present embodiment arranges the third block 13 in the heat dissipation member 4 below the semiconductor element 1.
  • the thickness of the device increases.
  • the first block 11 and the second block 12 can be arranged in an empty space outside the arrangement area of the connection member 3 on the main surface side of the base 2 of the semiconductor device.
  • the manufacturing method of the semiconductor device uses the base frame 18 and the heat dissipation member frame 15 as in the manufacturing method of the first embodiment, and the base 2 and the heat dissipation member arranged in a matrix. 4 is molded and sealed at once.
  • the process sequence includes a frame bonding process for bonding the base frame 18 and the heat dissipation member frame 15, a die bonding process for mounting the semiconductor element 1 on each base 2, and each internal terminal 8 on the base 2.
  • a wire bonding step of wiring the electrodes 7 on the semiconductor element 1 by the connecting member 3 a sealing step of molding the sealing material 5 so as to cover the base 2, the heat dissipation member 4 and the semiconductor element 1,
  • 20A and 20B show the state of the base frame 18 and the heat dissipation member frame 15 after the wire bonding step in the semiconductor device manufacturing method according to the second embodiment.
  • sealing molding is performed by filling the semiconductor element 1, the connecting member 3, and the base 2 with the sealing material 5 in a sealing process.
  • the first block 11 and the second block 12 are arranged by the third block 13 having a low height. Are formed in a straight line. Since this linear gap becomes a flow path of the sealing material 5, sealing molding can be performed easily.
  • the heat dissipation member 4 is incorporated in the manufacturing process of the semiconductor device, and can be molded as a semiconductor device in a lump. Compared to external products to be attached in the process, the process can be simplified and mass productivity can be maintained.
  • the first block 11 and the second block 12 in the heat dissipation member 4 are arranged outside the base 2. It is good also as a structure which covers the side surface in which this internal terminal 8 in this base 2 is not formed.
  • the first embodiment configured to cover the heat dissipation member 4 from above the semiconductor element 1 and the second embodiment configured to incorporate the heat dissipation member 4 under the semiconductor element 1.
  • the heat dissipation characteristics of the semiconductor device can be further enhanced.
  • the first and second embodiments and the respective modifications have been described as examples of the technology disclosed in the present application.
  • the technology in the present disclosure is not limited to this, and can also be applied to an embodiment in which changes, replacements, additions, omissions, and the like are appropriately performed.
  • the wiring board using a glass epoxy resin was demonstrated as an example of the base 2 and the base frame 18, it is not restricted to this.
  • a wiring board such as a ceramic or polyimide film, a silicon (Si) interposer, a lead frame including a die pad and leads, or another semiconductor element may be used.
  • the base 2 may be anything as long as the semiconductor element 1 is mounted and the connection member 3 can be electrically connected.
  • a copper (Cu) or a gold (Au) wire has been mentioned as an example of the connection member 3, the present invention is not limited to this.
  • ribbon bonding or lead bonding may be performed instead of wire bonding.
  • the metal and its alloy were demonstrated as an example of the heat radiating member 4, if it consists of a material provided with heat conductivity, it will not be restricted to this.
  • the semiconductor device according to the present invention can be applied to a semiconductor device mounted on an electronic device, and is particularly useful for a semiconductor device mounted on a small electronic device such as a portable device.

Abstract

　半導体装置は、主面上に内部端子が配置された基台と、基台の主面上に保持され、上面に電極が配置された半導体素子と、内部端子と電極とを接続する接続部材と、基台の主面上に内部端子、半導体素子及び接続部材を覆うように配置された封止材と、封止材の上に配置された放熱部材とを備えている。放熱部材における接続部材の上側部分には空間部である切り欠き部が形成され、切り欠き部には、封止材が配されている。基台の側面方向から見て、接続部材の頂点は、切り欠き部の内側に位置している。

Description

放熱部材を備えた半導体装置
　本開示は、放熱部材を備えた半導体装置及びその製造方法に関する。
　近年、搭載する半導体素子の大容量化且つ高集積化に伴って消費電力が増大し、半導体装置における放熱特性の向上が必要とされている。
　この問題に対し、従来の半導体装置においては、該半導体装置の主面上に放熱板を貼り付けることにより、該半導体装置の放熱特性の向上を図っている。
　以下、従来の半導体装置の構成について説明する。
　従来の半導体装置は、半導体素子、基板、接続部材、封止樹脂及び放熱板から構成される。半導体素子は、基板上にダイボンドペーストにより固着され、半導体素子の電極と基板の内部端子とが接続部材により接続される。半導体素子、接続部材及び基板の内部端子は、封止樹脂によって被覆され、封止樹脂の上に放熱板が接着材によって貼り付けられる（例えば特許文献１、２を参照）。
特許第２６７９８０６号公報 特許第３５１４１０１号公報
　以下、図２１を参照しながら、特許文献１に開示された第１の従来例に係る半導体装置について説明する。
　図２１に示すように、第１の従来例に係る半導体装置は、半導体素子１０１、基板１０２、ワイヤ１０３、放熱板１０４及び封止樹脂１０５により構成される。半導体素子１０１は、基板１０２の上にダイボンドペースト１０６により固着される。半導体素子１０１に設けられた電極と基板１０２に設けられた内部端子とは、ワイヤ１０３によって接続される。半導体素子１０１の上方には、封止樹脂１０５を介在させて放熱板１０４が配置される。半導体素子１０１、基板１０２、ワイヤ１０３及び放熱板１０４は、封止樹脂１０５により一体に封止成形される。
　放熱板１０４は、ワイヤ１０３と干渉する位置に凹部を形成することにより、半導体装置の薄型化を図っている。放熱板１０４は、あらかじめ、半導体装置ごとに個片状の放熱板１０４を用意し、成形時に封止樹脂１０５の上部に埋め込む工法を採る。この工法によると、放熱板１０４の外形は半導体装置の外形とくらべて、やや小さいサイズとなるため、放熱板１０４は、半導体装置の上面からのみ露出し、側面からは露出しない。
　しかしながら、放熱板１０４にワイヤ１０３を避ける凹部を形成することで半導体装置の厚さを薄くできるものの、凹部の残厚は残るため、その分だけ半導体装置の厚さが大きくなってしまう。また、複雑な加工形状と、封止樹脂１０５の充填性及びその流路の確保という問題から、放熱板１０４と半導体素子１０１との間隙、及び放熱板１０４と基板１０２との間隙を縮小するには限界があり、薄型化に課題を有する。さらに、放熱板１０４の露出面が半導体装置の上面に限られるため、放熱特性が低くなるという問題もある。
　以下、図２２を参照しながら、特許文献２に開示された第２の従来例に係る半導体装置の構成及び製造方法について説明する。
　図２２（ｅ）に示すように、第２の従来例に係る半導体装置は、半導体素子２０１、基板２０２、放熱板２０４及び封止樹脂２０５により構成されている。半導体素子２０１は、その主面が基板２０２の主面と対向して配置され、該半導体素子２０１の主面の電極と基板２０２の内部端子２０８とが接合される。半導体素子２０１の裏面には、平板状の放熱板２０４が固着され、基板２０２と放熱板２０４との隙間を封止樹脂２０５によって充填することにより、一体に封止成形されている。
　さらに、図２２（ａ）～図２２（ｅ）に示すように、第２の従来例に係る半導体装置の製造方法は、複数の半導体素子２０１の主面を一枚の基板２０２の主面に対向させて実装し、その後、複数の半導体素子２０１の裏面に１枚の放熱板２０４を接着材により固着する。続いて、基板２０２と放熱板２０４との隙間に封止樹脂２０５を充填して一体に成形する。続いて、半導体装置を、放熱板２０４と共に切断して個片化された半導体装置を得る。
　以上のように、第２の従来例では、フリップチップ工法を用いるため、半導体素子２０１の裏面に放熱板２０４を、接続部材を避けることなく直接に貼り付けることができる。これにより、半導体装置における放熱特性の向上と薄型化とを両立することができる。
　しかしながら、第２の従来例を第１の従来例のようなワイヤボンド工法に適用することは困難である。なぜなら、ワイヤボンド工法においては、半導体素子の主面を上側に向けてダイボンドし、ワイヤを配線するため、配線されたワイヤが放熱板と干渉する。さらには、半導体素子の主面が、放熱板を封止樹脂に加圧する際にダメージを受けるおそれがある。
　また、フリップチップ工法は、配線の仕様によっては、コスト及び信頼性がワイヤボンド工法に劣るため、該フリップチップ工法を適用できない場合がある。
　本開示は、上述の問題を解決し、ワイヤボンド工法で製造された放熱部材を設ける半導体装置において、高い放熱特性及び薄型化を実現できるようにすることを目的とする。
　前述の目的を達成するため、本開示は、半導体装置を、基台及び半導体素子の上方に封止材を介して設ける放熱板における接続部材と対向する領域に、空間部を設ける構成とする。
　具体的に、本開示の一態様に係る半導体装置は、主面上に内部端子が配置された基台と、基台の主面上に保持され、上面に電極が配置された第１の半導体素子と、内部端子と電極とを接続する接続部材と、基台の主面上に内部端子、第１の半導体素子及び接続部材を覆うように配置された封止材と、封止材の上に配置された放熱部材とを備える。放熱部材における接続部材の上側部分には空間部が形成され、空間部には封止材が配されており、基台の側面方向から見て、接続部材の頂点は空間部の内側に位置する。
　本開示の他の態様に係る半導体装置は、主面上に内部端子が配置された基台と、基台の主面上における内部端子を除く領域に配置された放熱部材と、放熱部材の上に保持され、上面に電極が配置された第１の半導体素子と、内部端子と電極とを接続する接続部材と、基台の主面上に内部端子、第１の半導体素子及び接続部材を覆うように配置された封止材とを備える。放熱部材は、基台上の接続部材の配置領域を除く領域の上面が、接続部材の頂点よりも高く形成されている。
　本発明に係る半導体装置によると、放熱部材を備えた半導体装置において、高い放熱特性、小型化及び薄型化並びに高い量産性を実現することができる。
図１Ａは、第１の実施形態に係る半導体装置の構成を模式的に示す平面図である。 図１Ｂは、第１の実施形態に係る半導体装置の構成を模式的に示す正面図である。 図１Ｃは、第１の実施形態に係る半導体装置の構成を模式的に示す右側面図である。 図２Ａは、第１の実施形態に係る半導体装置の構成を示す模式図であり、図１Ａにおいて封止材を透視した場合の平面図である。 図２Ｂは、第１の実施形態に係る半導体装置の構成を示す模式図であり、図２ＡのIIｂ－IIｂ線における断面図である。 図２Ｃは、第１の実施形態に係る半導体装置の構成を示す模式図であり、図２ＡのIIｃ－IIｃ線における断面図である。 図３は、第１の実施形態に係る半導体装置の製造方法の一工程を模式的に示す平面図である。 図４は、第１の実施形態に係る半導体装置の製造方法の一工程を模式的に示す平面図である。 図５は、第１の実施形態に係る半導体装置の製造方法の一工程を模式的に示す平面図である。 図６は、第１の実施形態に係る半導体装置の製造方法の一工程を模式的に示す平面図である。 図７は、第１の実施形態に係る半導体装置の製造方法の一工程を模式的に示す平面図である。 図８は、第１の実施形態に係る半導体装置の製造方法の一工程を模式的に示す平面図である。 図９（ａ）～図９（ｆ）は、第１の実施形態に係る半導体装置の製造方法を工程順に示す模式図であり、図２ＡのIIｃ－IIｃ線における断面図である。 図１０（ａ）～図１０（ｆ）は、第１の実施形態に係る半導体装置の製造方法を工程順に示す模式図であり、図２ＡのIIｂ－IIｂ線における断面図である。 図１１（ａ）～図１１（ｅ）は、第１の実施形態に係る半導体装置の他の製造方法を工程順示す模式図であり、図２ＡのIIｃ－IIｃ線における断面図である。 図１２（ａ）～図１２（ｅ）は、第１の実施形態に係る半導体装置の他の製造方法を工程順に示す模式図であり、図２ＡのIIｂ－IIｂ線における断面図である。 図１３Ａは、第１の実施形態に係る半導体装置の製造工程で用いる放熱部材フレームの構成を模式図的に示す平面図である。 図１３Ｂは、第１の実施形態に係る半導体装置の製造工程で用いる放熱部材フレームの構成を示す模式図であり、図１３ＡのXIIIｂ－XIIIｂ線における断面図である。 図１３Ｃは、第１の実施形態に係る半導体装置の製造工程で用いる放熱部材フレームの構成を示す模式図であり、図１３ＡのXIIIｃ－XIIIｃ線における断面図である。 図１４Ａは、第１の実施形態の第１変形例に係る半導体装置の構成を示す模式図であり、封止材を透視した場合の平面図である。 図１４Ｂは、第１の実施形態の第１変形例に係る半導体装置の構成を示す模式図であり、図１４ＡのXIVｂ－XIVｂ線における断面図である。 図１４Ｃは、第１の実施形態の第１変形例に係る半導体装置の構成を示す模式図であり、図１４ＡのXIVｃ－XIVｃ線における断面図である。 図１５Ａは、第１の実施形態の第１変形例に係る半導体装置の製造工程で用いる基台フレームの構成を模式的に示す平面図である。 図１５Ｂは、第１の実施形態の第１変形例に係る半導体装置の製造工程で用いる基台フレームの構成を模式的に示す正面図である。 図１６Ａは、第１の実施形態の第２変形例に係る半導体装置の構成を示す模式図であり、封止材を透視した場合の平面図である。 図１６Ｂは、第１の実施形態の第２変形例に係る半導体装置の構成を示す模式図であり、図１６ＡのXVIｂ－XVIｂ線における断面図である。 図１６Ｃは、第１の実施形態の第２変形例に係る半導体装置の構成を示す模式図であり、図１６ＡのXVIｃ－XVIｃ線における断面図である。 図１７Ａは、第１の実施形態および第１の変形例に係る半導体装置が備える放熱部材の変形例を、模式的に示す平面図である。 図１７Ｂは、第１の実施形態および第１の変形例に係る半導体装置が備える放熱部材の変形例を、模式的に示す平面図である。 図１７Ｃは、第１の実施形態の第２の変形例に係る半導体装置が備える放熱部材の変形例を、模式的に示す平面図である。 図１８Ａは、第２の実施形態に係る半導体装置の構成を模式的に示す平面図である。 図１８Ｂは、第２の実施形態に係る半導体装置の構成を模式的に示す正面図である。 図１８Ｃは、第２の実施形態に係る半導体装置の構成を模式的に示す右側面図である。 図１９Ａは、第２の実施形態に係る半導体装置を示す模式図であり、図１８Ａにおいて封止材を透視した場合の平面図である。 図１９Ｂは、第２の実施形態に係る半導体装置を示す模式図であり、図１９ＡのXIXｂ－XIXｂ線における断面図である。 図１９Ｃは、第２の実施形態に係る半導体装置を示す模式図であり、図１９ＡのXIXｃ－XIXｃ線における断面図である。 図２０Ａは、第２の実施形態に係る半導体装置の一製造工程における放熱部材フレームの構成を模式的に示す平面図である。 図２０Ｂは、第２の実施形態に係る半導体装置の一製造工程における放熱部材フレームの構成を示す模式図であり、図２０ＡのXXｂ－XXｂ線における断面図である。 図２１は、第１の従来例に係る半導体装置の構成を示す断面図である。 図２２（ａ）～図２２（ｅ）は、第２の従来例に係る半導体装置の製造方法を工程順に示す断面図である。
　以下、本開示の半導体装置について図面を参照しながら説明する。但し、詳細な説明は省略する場合がある。例えば、既によく知られた事項の詳細説明や実質的に同一の構成に対する重複説明を省略する場合がある。これは、以下の説明が不必要に冗長になるのを避け、当業者の理解を容易にするためである。
　なお、添付図面および以下の説明は当業者が本開示を十分に理解するためのものであって、これらによって請求の範囲に記載の主題を限定することを意図するものではない。
　（第１の実施形態）
　以下、第１の実施形態に係る半導体装置について、図１Ａ～図１Ｃ及び図２Ａ～図２Ｃを参照しながら説明する。
　図２Ａ～図２Ｃに示すように、第１の実施形態に係る半導体装置は、主面上に複数の内部端子８が配置された基台２と、該基台２の主面上に接着層６を介して固着され、上面に複数の電極７が配置された半導体素子１とを有している。基台２は、例えば基材の上に配線層が形成された配線基板であり、接着層６は、例えばダイボンドペーストである。基台２の複数の内部端子８は、半導体素子１の複数の電極７とそれぞれ接続部材３によって接続されている。接続部材３は、例えば銅（Ｃｕ）や金（Ａｕ）等を主な材料とするワイヤである。基台２の主面上には、封止材５が複数の内部端子８、半導体素子１及び複数の接続部材３を一体に覆うように形成されている。基台２の主面と反対側の裏面上には、複数の外部端子９が配置されている。
　半導体素子１の素子形成面である上面には、該半導体素子１における互いに対向する２辺に沿って複数の電極７が設けられている。
　封止材５の上には、放熱部材４が配置されている。放熱部材４には、例えばアルミニウム（Ａｌ）若しくは銅（Ｃｕ）等の金属材料又はその合金材料を用いることができる。放熱部材４は、例えば露出面が平坦な板状であってもよい。放熱部材４における内部端子８、接続部材３及び電極７の上側部分には空間部である切り欠き部４ａがそれぞれ形成され、且つ各切り欠き部４ａには、封止材５がそれぞれ充填されている。
　より詳細には、放熱部材４は、図１Ａ及び図２Ａに示すように、半導体素子１における電極７が形成されていない他の対向する２辺に沿った形状を持つ第１のブロック１１及び第２のブロック１２と、半導体素子１の上方に配置され、第１のブロック１１及び第２のブロック１２を互いに連結する第３のブロック１３により構成された平面Ｈ字状の外形を有している。この平面構成により、放熱部材４の切り欠き部４ａの下方には、半導体素子１の電極７と基台２の内部端子８と接続部材３とが配置される。また、図２Ｃに示すように、基台２の側面から見て、各接続部材３の頂点は、切り欠き部４ａの内側に位置する。
　このように、第１の実施形態に係る半導体装置によると、放熱部材４は、接続部材３の配置領域の直上に切り欠き部４ａが設けられているため、接続部材３と干渉することがない。このため、ワイヤ等の接続部材３をワイヤボンド方式で接続する半導体装置においても、半導体素子１に放熱部材４を近接させて配置することが可能となる。また、半導体素子１の上における接続部材３の配置領域を除く領域全体に、第３のブロック１３を重ねられる。
　以上の構成により、本実施形態に係る半導体装置は、従来の半導体装置と比べて、薄型化を図りながら、放熱部材４への熱伝導性を格段に向上することが可能となる。
　なお、本実施形態に係る半導体装置では、放熱部材４における半導体素子１の上方に位置する第３のブロック１３は、第１のブロック１１及び第２のブロック１２よりも薄くすることが望ましい。このようにすると、図２Ｂに示すように、半導体素子１の上面と第３のブロックとの間、及び基台２の主面と第１のブロック１１及び第２のブロック１２との間を、それぞれ近接して固着することができ、半導体装置の薄型化を容易に図ることが可能となる。このとき、第３のブロック１３の厚さを、第１のブロック１１、第２のブロック１２より、おおよそ半導体素子１の厚さ分だけ薄くすると、半導体素子１と放熱部材４をより近接して配置できる。また、第３のブロック１３の厚さを、おおよそ封止材５の厚さ、言い換えると半導体素子１の上面から封止材５の上面までの高さ（図２Ｃに示す厚さｈ０）よりも薄くすれば、半導体装置の厚さを、放熱部材４を設けない状態と変えることなく、放熱部材４を備えた半導体装置を形成することができる。
　なお、第１のブロック１１及び第２のブロック１２と基台２との隙間、並びに第３のブロック１３と半導体素子１との隙間に、封止材５が充填される構成について上述したが、隙間に封止材５を介在させない形態でもよく、放熱部材４を、基台２及び／又は半導体素子１と直接に接触させてもよい。
　また、図１Ａ～図１Ｃに示すように、放熱部材４は封止材５に埋め込まれて半導体装置に内蔵され、放熱部材４における上面及び側面が半導体装置の外形と一致して、それぞれ一平面をなすのが望ましい。このようにすると、上面及び側面に放熱部材４が露出するため放熱性が高まり、半導体装置の信頼性が向上する。また、半導体装置としての反りの低減、強度の向上といった効果も期待できる。
　また、封止材５の厚さは、接続部材３の頂点の高さ、すなわちワイヤループの高さよりも数十μｍ以上厚くして、封止材５の形成後に、接続部材３が封止材５の表面から露出しないようにしてもよい。このようにすることで、接続部材３が半導体装置外の構成と接触することによるショートを防げるため、半導体装置の信頼性が向上する。
　なお、放熱部材４の形状は、必ずしも平面Ｈ字状の形状に限定されず、接続部材３の配置領域と干渉しない切り欠き部４ａが設けてあれば、他の平面形状でも同様の機能を得られる（第１の実施形態の製造方法）。
　以下、第１の実施形態に係る半導体装置の製造方法について、図３～図８、図９（ａ）～図９（ｆ）及び図１０（ａ）～図１０（ｆ）を参照しながら説明する。ここで、図３～図８は図１Ａに対応する平面を製造工程順に示し、図９（ａ）～図９（ｆ）は図２Ｃに対応する断面を製造工程順に示し、図１０（ａ）～図１０（ｆ）は図２Ｂに対応する断面を製造工程順に示している。
　第１の実施形態に係る半導体装置における製造方法は、半導体装置の量産性を高めるため、複数の半導体装置の形成領域を行列状に配置した基台フレーム１８に放熱部材フレーム１５を一括に取り付け、これらを封止材５により一括に封止し、その後、個片に分割する工法を採る。
　まず、図３、図９（ａ）及び図１０（ａ）に示すように、本製造方法で用いる基台フレーム１８を用意する。
　基台フレーム１８は、複数の基台２と該複数の基台２を保持する基台枠部１７とから構成される。各基台２は、その主面に複数の内部端子８が互いに対向する２辺に沿って形成されている。また、各基台２の裏面に複数の外部端子９がそれぞれ形成されている。
　基台２は、主面と裏面とに銅配線が設けられており、その主面と裏面とはスルーホール（図示せず）によって接続されている。内部端子８及び外部端子９の各表面には、ニッケル（Ｎｉ）／金（Ａｕ）めっきが形成されて、その表面が保護されている。ここで、複数の基台２における行列状の配置形態は、製品のサイズ及び製造ラインが許容する基台サイズに合わせて任意に決定することができる。本実施形態においては、説明を簡単にするため、基台フレーム１８の行列状の配置形態を２行×２列の４個としている。
　次に、図４、図９（ｂ）及び図１０（ｂ）に示すように、各基台２における所定の領域に、半導体素子１をそれぞれ搭載する。上面に複数の電極７が設けられた半導体素子１は、その裏面を基台２の主面と対向させ、接着層６を介して固着される。このとき、半導体素子１を搭載する方向は、該半導体素子１に設けられた２列の電極７が基台２の上の２列の内部端子８とそれぞれ対向する方向とする。
　半導体素子１は、例えばシリコン（Ｓｉ）からなり、電極７は、例えばアルミニウム（Ａｌ）からなる。また、接着層６は、例えばガラスエポキシ樹脂を用いたダイボンドペーストであり、フィラー（図示せず）を含む。
　次に、図５、図９（ｃ）及び図１０（ｃ）に示すように、それぞれ対向する半導体素子１の各電極７と基台２の内部端子８とを接続部材３により接続する。接続部材３には、例えば金（Ａｕ）線を用いる。
　次に、図６、図９（ｄ）及び図１０（ｄ）に示すように、別途用意した放熱部材フレーム１５を基台フレーム１８の所定の位置に位置合わせした状態で、放熱部材フレーム１５と半導体素子１との隙間、及び放熱部材フレーム１５と基台フレーム１８との隙間に封止材５を充填する。その後、充填された封止材５を硬化して、基台フレーム１８、接続部材３を含む複数の半導体素子１及び放熱部材フレーム１５を一体に成形する。封止材５には、例えば熱硬化性のガラスエポキシ材を用いる。なお、放熱部材フレーム１５は、複数の放熱部材４と該複数の放熱部材４を外側部分で保持する放熱部材枠部１４とから構成される。
　この際、放熱部材４の放熱効果を大きくするには、放熱部材４と半導体素子１との隙間及び放熱部材４と基台２との隙間を小さくすることが望ましい。しかしながら、これらの隙間が狭くなると、一括モールドを行う際に、封止材５が流れにくくなって、該封止材５の注入が困難となる場合がある。すなわち、通常のトランスファモールド法では、封止成形が困難となる場合がある。この傾向は、基台２のサイズ及び行列状の配列数が大きくなる程強くなる。
　そこで、本実施形態においては、他の製造方法として、樹脂封止工程に圧縮成形工法を応用して、放熱部材４と半導体素子１との隙間及び放熱部材４と基台２との隙間に封止材５が容易に且つ確実に充填できる方法を採用することも可能である。
　圧縮成形工法の応用による封止工程を、図１１（ａ）～図１１（ｅ）及び図１２（ａ）～図１２（ｅ）を参照しながら順に説明する。図１１（ａ）～図１１（ｅ）は、図２Ｃに対応する断面を製造工程順に示し、図１２（ａ）～図１２（ｅ）は図２Ｂに対応する断面を製造工程順に示している。
　また、本実施形態で用いる放熱部材フレーム１５の構成図を、図１３Ａ～図１３Ｃに示す。上述したように、放熱部材フレーム１５は、複数の放熱部材４とそれを保持する放熱部材枠部１４とからなり、各放熱部材４の行列状配置は、複数の基台２の行列状配置に合わせて配置される。
　図１３Ａに示すように、放熱部材フレーム１５は、XIIIｂ－XIIIｂ線方向に第１のブロック１１同士及び第２のブロック１２同士がそれぞれ連結され、XIIIｃ－XIIIｃ線方向に第１のブロック１１と第２のブロック１２とが連結されて一体に形成されている。このように、この段階では各放熱部材４は互いに連結されており、個片にした際のそれぞれの切り欠き部４ａ、も、平面四角形状の複数の開口部として形成されている。また、図１３Ａ及び図１３Ｃに示すように、各放熱部材４における第３のブロック１３は、第１のブロック１１及び第２のブロック１２と比べておおよそ半導体素子１の厚さ分だけ薄く形成されている。
　このように形成された放熱部材フレーム１５の上面を、まず、図１１（ａ）及び図１２（ａ）に示すように、粘着性を持つリリースフィルム１６に貼り付ける。リリースフィルム１６は、封止成形工程の後に、除去される。リリースフィルム１６の基材には、例えば、ポリイミド系又はテフロン（登録商標）系等を用い、粘着剤としてオレフィン等の１７０℃以上の耐熱性を有する材料を用いる。
　次に、図１１（ｂ）及び図１２（ｂ）に示すように、放熱部材フレーム１５の上に、液状の封止材５を塗布又は印刷により成膜する。また、顆粒状の封止材５を撒布し、その後、加熱により溶融してもよい。封止材５には、例えば、ガラスエポキシ樹脂等の熱硬化性材料を用いる。
　次に、図１１（ｃ）及び図１２（ｃ）に示すように、基台２ごとに半導体素子１を搭載し、接続部材ボンド工程までを行った基台フレーム１８を、放熱部材フレーム１５上の封止材５と対向させて位置合わせを行う。ここでの位置合わせは、少なくとも各切り欠き部４ａが各接続部材３の配置領域と重なり、放熱部材４と接触しないように行う。
　次に、図１１（ｄ）及び図１２（ｄ）に示すように、放熱部材フレーム１５を、溶融状態にある封止材５を介して基台フレーム１８に押し付けて、放熱部材フレーム１５と基台フレーム１８と互いに貼り合わせる。
　次に、図１１（ｅ）及び図１２（ｅ）に示すように、放熱部材フレーム１５と基台フレーム１８とを加圧により圧縮（圧着）する。これにより、放熱部材フレーム１５、封止材５、各半導体素子１及び基台フレーム１８が一体化される。
　このとき、図１１（ｄ）及び図１１（ｅ）に示すように、あらかじめ、放熱部材フレーム１５の開口部（切り欠き部４ａが連結した部分）と基台フレーム１８における接続部材３の配置領域との位置合わせを行っていることにより、各放熱部材４と各接続部材３との干渉を防ぐことができる。
　なお、図１２（ｄ）及び図１２（ｅ）に示すように、第１のブロック１１と第３のブロック１３との段差ｈ１、及び第２のブロック１２と第３のブロック１３との段差ｈ１は、半導体素子１と接着層６との厚さの総和ｈ２よりも大きくすることが望ましい。このようにすると、放熱部材フレーム１５と基台フレーム１８とを貼り合わせて圧縮する際に、第３のブロック１３が半導体素子１に当たるよりも先に、第１のブロック１１及び第２のブロック１２と基台２とが接触して止まるため、第３のブロック１３と半導体素子１との干渉による、半導体素子１の素子形成面へのダメージを防ぐことが可能となる。
　さらに、放熱部材４は、このような構成を採ることにより、半導体素子１の上面である素子形成面に近接させることができる。その上、放熱部材４は、半導体素子１及び接続部材３の配置領域を除く領域において放熱部材４の体積を大きくできるので、該放熱部材４による放熱効果を高めることができる。
　なお、放熱部材４と半導体素子１との間隔は、放熱効果の観点からはできる限り近づけることが望ましい。しかしながら、半導体素子１における素子形成面へのダメージを考慮すると、封止材５に分散されるフィラーサイズよりも大きくする必要がある。第１の実施形態に係る半導体装置の構成においては、図１２（ｅ）に示したように、放熱部材４を構成する第１のブロック１１及び第２のブロック１２がスペーサとして機能するため、半導体素子１と放熱部材４との間隔を任意に調整することができる。
　また、実用上、半導体素子１及び放熱部材４のそれぞれの厚さ、半導体素子１と放熱部材４との平行度のばらつき、並びに封止材５に分散されるフィラーのサイズ及びその充填性を考慮すると、半導体素子１と放熱部材４との間隔は、５０μｍ以上且つ１００μｍ以下が望ましい。
　半導体素子１と放熱部材４との間隔を、より小さくするには、封止材５に分散するフィラーのサイズを小さくするか、さらには、フィラーを分散しないフィラーレスにすることもできる。但し、同一の分散量でフィラーサイズを小さくすると、封止材５の粘度が上昇して流動性が低下する。また、フィラーの分散量が少ないと、封止材５の信頼性が低下する。従って、半導体素子１と放熱部材４との間隔によって、封止材５の組成を使い分けてもよい。例えば、半導体素子１と放熱部材４との間隙と、それ以外の部分で異なる封止材を用いてもよい。具体的には、半導体素子１と放熱部材４との隙間にのみ、サイズが小さいフィラーが分散された封止材５を用いるか、フィラーレスの封止材５を用いてもよい。
　また、封止材５との間で絶縁性が保たれる状態にある半導体素子１と放熱部材４との隙間にのみ金属粒子を分散した封止材５を用いることにより、封止材５における熱伝導性を高めてもよい。
　また、本実施形態の製造方法においては、複数の放熱部材４とそれを保持する放熱部材枠部１４とからなる放熱部材フレーム１５によって、半導体装置の厚さを調整することができる。このため、モールドキャビティを省略することも可能である。モールドキャビティを省略する場合は、平板の金型を用いた封止成形が可能となるので、特別な金型を用意する必要がなく、該金型における他の半導体装置との共用性が向上するため、量産性が向上する。
　なお、本製造方法における封止成形工程は、従来と同様にモールドキャビティを用いて、封止材５が外部に漏れないようにして行うことも可能である。この場合は、塗布した封止材５の使用量によって封止材５の厚さが影響を受けるため、封止材５の使用量に対しても調整する必要がある。但し、本実施形態の有効性に実質的な影響はない。
　また、図９（ｄ）及び図１０（ｄ）に示したように、放熱部材フレーム１５を基台フレーム１８に張り合わせてから、放熱部材フレーム１５の各開口部に封止材５を注入する方法の場合は、ポッティング法又は印刷法を用いることも可能である。
　いずれの方法であっても、放熱部材フレーム１５と基台フレーム１８とを、封止材５を間に挟んで貼り合わせ、その後、圧縮した状態で封止材５を熱硬化させることにより、封止工程は完了する。
　なお、封止工法は圧縮成形に限られず、例えば、封止材５の流路が確保できれば、通常のトランスファモールド工法も適用が可能である。
　封止工程の後、リリースフィルム１６を放熱部材フレーム１５から剥がし、図７、図９（ｅ）及び図１０（ｅ）に示すように、放熱部材フレーム１５、封止材５及び基台フレーム１８をダイシングする。なお、リリースフィルム１６は、ダイシング前に剥がさずにダイシングフィルムとして利用することも可能である。
　ダイシングにより、図８、図９（ｆ）及び図１０（ｆ）に示すように、個片化された半導体装置を得る。このとき、半導体装置は、放熱部材４をダイシングにより切断して分割されるため、半導体装置の外周面には、放熱部材４の切断面が露出する。
　放熱部材枠部１４に保持された複数の放熱部材４は、基台枠部１７に保持された複数の基台２と一体に成形された後にダイシングする場合に、ダイシングの位置ずれにより、放熱部材４の外形が中途半端に切り残されて、個片ごとに断面が不揃いになるという懸念がある。しかしながら、図７に示すように、本実施形態に係る半導体装置においては、放熱部材４が例えば平面Ｈ字状であることにより、切断後に切り欠き部４ａとなる開口部の各辺がダイシングラインに対して常に垂直に交わるため、切り残しが発生しにくく、且つ、いずれの半導体装置の切断面も揃った状態となる。
　なお、基台２の裏面に配置されている複数の外部端子９に、それぞれ半田ボールが必要な場合は、ダイシング工程の前の一括マウント工程において形成することができる。
　（第１の実施形態の第１変形例）
　以下、第１の実施形態の第１変形例に係る半導体装置について、図１４Ａ～図１４Ｃを参照しながら説明する。
　第１変形例においては、放熱部材４の平面形状を基台２の平面形状よりも大きく形成し、放熱部材４における第１のブロック１１及び第２のブロック１２を、基台２の外側の領域に配置している。これにより、放熱部材４の表面積及び体積を大きくして、放熱効果を高めることができる。
　具体的には、図１４Ａ及び図１４Ｂに示すように、放熱部材４における第１のブロック１１及び第２のブロック１２は、それぞれ基台２における複数の内部端子８を設けない側の側面に沿って、且つ該側面を覆うように形成されている。ここでは、図１４Ｂに示すように、XIVｂ－XIVｂ線方向における基台２の幅は半導体素子１の幅と同一としているが、XIVｂ－XIVｂ線方向における基台２の幅と半導体素子１の幅とは、必ずしも同一とする必要はない。
　本変形例に係る半導体装置は、図１５Ａ及び図１５Ｂに示す基台フレーム１８を用いることにより、上述の第１の実施形態の製造方法と同様の工程により得られる。
　すなわち、本変形例に係る基台フレーム１８において、行列状に配置された複数の基台２における内部端子８を設けない側の側面にスリット（開口部）２ａを設ける。さらに、基台フレーム１８の裏面の全面にリリースフィルム１６を貼り付ける。これにより、各放熱部材４を基台２の外側の領域にまで延伸することができ、且つ、封止成形工程における封止材５の基台２の裏面への漏れを防ぐことができる。
　このように、本変形例によると、第１のブロック１１及び第２のブロック１２を基板の外側にまで延伸し、且つ接続部材３の配線領域を除く側面を放熱部材４によって形成できるため、放熱特性の向上、反りの低減、強度の向上、ひいては信頼性の向上が可能となる。
　（第１の実施形態の第２変形例）
　以下、第１の実施形態の第２変形例に係る半導体装置について、図１６Ａ～図１６Ｃを参照しながら説明する。
　第２変形例においては、放熱部材４に設けられる、接続部材３の配置領域との干渉を防ぐ空間部を、切り欠き部４ａに代えて開口部４ｂとしている。この構成により、放熱部材４の側面が半導体装置の周囲の全面にわたって露出するため、半導体装置として放熱特性が向上すると共に、その強度を高めることができる。
　なお、第２変形例においても、第１変形例と同様に、放熱部材４における第１のブロック１１及び第２のブロック１２を基台２の外側に配置して、該基台２における内部端子８が形成されていない側面を覆う構成としてもよい。
　（放熱部材の変形例）
　以下、第１の実施形態およびその変形例に係る半導体装置が備える放熱部材４の変形例を説明する。
　切り欠き部４ａ及び開口部４ｂのそれぞれの平面形状は、図１Ａや図１６Ａの形状に限られず、接続部材３と干渉しない形状であればよいが、例えば、図１７Ａ～図１７Ｃのような形状が考えられる。
　図１７Ａ及び図１７Ｂは、放熱部材４における切り欠き部４ａの変形例を示し、図１７Ｃは、放熱部材４における開口部４ｂの変形例を示す。図１７Ａ～図１７Ｃにおいて、Ｗ１は切り欠き部４ａ又は開口部４ｂの内側の幅であり、Ｗ２は切り欠き部４ａ又は開口部４ｂの外側の幅である。いずれも、内側の幅Ｗ１よりも外側の幅Ｗ２を大きくしている。
　この構成により、半導体素子１に設けられる電極７同士の間隔よりも、基台２に設けられる内部端子８同士の間隔を大きくすることができるため、ワイヤボンド工程における接続部材のボンディングが容易となる。
　また、切り欠き部４ａ又は各開口部４ｂは、放熱部材４の配置領域と接続部材３の配置領域との区分が容易で、対称性が高い２箇所としたが、接続部材３の配置領域に応じて１箇所でもよく、また、３箇所以上であってもよい。
　（第２の実施形態）
　以下、第２の実施形態に係る半導体装置について、図１８Ａ～図１８Ｃ及び図１９Ａ～図１９Ｃを参照しながら説明する。ここでは、第１の実施形態と異なる構成を主に説明する。
　図１９Ａ～図１９Ｃに示すように、第２の実施形態に係る半導体装置は、基台２の主面上に、放熱部材４が接着材１０により固着され、該放熱部材４の上に、半導体素子１における素子形成面の反対側の面である裏面が接着層６により固着されている。
　放熱部材４は、半導体素子１における電極７が形成されていない２辺に沿った形状を持つ第１のブロック１１及び第２のブロック１２と、半導体素子１の下側で第１のブロック１１及び第２のブロック１２を互いに連結する第３のブロック１３により構成された平面Ｈ字状の外形を有している。この平面構成により、放熱部材４の切り欠き部４ａからは、基台２の主面上に設けられた複数の内部端子８が露出する。
　半導体素子１の上面に設けられた複数の電極７と、基台２の主面上に設けられ、放熱部材４の切り欠き部４ａから露出する複数の内部端子８とは、それぞれ接続部材３により接続されている。
　また、放熱部材４を構成する第１のブロック１１並びに第２のブロック１２の上面及び側面は、図１８Ａ～図１８Ｃに示すように、半導体装置の外形と一致しており、それぞれ一平面をなす。
　このように、本実施形態においては、放熱部材４と接続部材３の配置領域とが干渉することなく、半導体素子１の裏面を放熱部材４に近接させることができるので、半導体素子１から放熱部材４への熱伝導が良好となる。また、半導体装置の内部における接続部材３の配置領域を除く領域では、放熱部材４の体積を大きくできるので、放熱部材４による放熱効果をより高めることができる。また、半導体装置の側面と、半導体素子１の下側の領域とを放熱部材４で形成するため、高い放熱特性に加えて、反りの低減、強度の向上、ひいては半導体装置としての高い信頼性を実現できる。
　図１９Ｂ及び図１９Ｃに示すように、放熱部材４を構成する第１のブロック１１及び第２のブロック１２における第３のブロック１３の上面からの高さは、接続部材３の頂点（ワイヤループ）の高さよりも高くしており、半導体装置の上面から露出する構成としている。
　本実施形態は、第１の実施形態に係る半導体装置と比較すると、放熱部材４における第３のブロック１３を半導体素子１の下側に配置するため、第３のブロック１３の厚さ分だけ半導体装置の厚さが大きくなる。しかしながら、第１のブロック１１及び第２のブロック１２を、半導体装置の基台２の主面側において、接続部材３の配置領域外の空きスペースに配置することができる。これにより、従来のワイヤボンド方式を採る半導体装置における外付けの放熱部材と比べて、半導体装置の薄型化、高放熱化及び高強度化を実現することができる。
　（第２の実施形態の製造方法）
　以下、第２の実施形態に係る半導体装置の製造方法について、図２０Ａ及び図２０Ｂを参照しながら説明する。
　本実施形態に係る半導体装置の製造方法は、第１の実施形態の製造方法と同様に、基台フレーム１８と放熱部材フレーム１５とを用いて、行列状に配置された基台２及び放熱部材４を一括に成形して封止する。工程順には、基台フレーム１８と放熱部材フレーム１５とを接着するフレームボンド工程と、各基台２の上に半導体素子１をそれぞれ搭載するダイボンド工程と、基台２の上の各内部端子８と半導体素子１の上の各電極７とを接続部材３により配線するワイヤボンド工程と、基台２、放熱部材４及び半導体素子１を覆うように封止材５を成形する封止工程と、放熱部材フレーム１５、封止材５及び基台フレーム１８を個片に分割して複数の半導体装置を得るダイシング工程と、である。
　図２０Ａ、図２０Ｂは、第２の実施形態に係る半導体装置の製造方法におけるワイヤボンド工程後の基台フレーム１８及び放熱部材フレーム１５の状態を示している。
　この後、封止工程により、半導体素子１、接続部材３及び基台２の上に封止材５を充填することにより、封止成形が行われる。
　第２の実施形態においては、基台フレーム１８の上に各放熱部材４を行列状に配置した際に、高さが低い第３のブロック１３により、第１のブロック１１と第２のブロック１２との隙間が直線状に繋がって形成される。この直線状の隙間が、封止材５の流路となるため、封止成形を容易に行うことができる。
　上記のように、本実施形態においては、ワイヤボンド工法を採る半導体装置において、放熱部材４が半導体装置の製造工程において内部に組み込まれており、半導体装置として一括に成形できるため、放熱板を別工程で貼り付ける外付け品と比べて、工程を簡易にし、量産性を保つことができる。
　なお、第２の実施形態においても、第１の実施形態の第１変形例と同様に、放熱部材４における第１のブロック１１及び第２のブロック１２を基台２の外側に配置して、該基台２における内部端子８が形成されていない側面を覆う構成としてもよい。
　さらに、放熱部材４を半導体素子１の上から覆う構成の第１の実施形態と、放熱部材４を半導体素子１の下に組み込む構成の第２の実施形態とを組み合わせることも可能である。この場合は、半導体装置における放熱特性をより一層高めることができる。
　以上のように、本出願において開示する技術の例示として、第１、第２の実施形態および各変形例を説明した。しかしながら、本開示における技術は、これに限定されず、適宜、変更、置き換え、付加、省略などを行った実施の形態にも適用可能である。
　なお、各実施形態及びその変形例においては、基台２および基台フレーム１８の一例として、ガラスエポキシ樹脂を用いた配線基板を説明したが、これに限られない。例えば、ガラスエポキシ樹脂に代えて、セラミック又はポリイミドフィルム等の配線基板、シリコン（Ｓｉ）インタポーザ、ダイパッドとリードを備えたリードフレーム、又は他の半導体素子を用いてもよい。要するに、基台２は半導体素子１を搭載し、接続部材３で電気的接続ができるものであればよい。また、接続部材３の一例として銅（Ｃｕ）や金（Ａｕ）ワイヤを挙げたが、これに限られない。例えば、ワイヤボンディングに替えてリボンボンディングやリードボンディングを行ってもよい。また、放熱部材４の一例として、金属やその合金を説明したが、熱伝導性を備えた材料からなるものであれば、これに限られない。
　以上のように、本開示における技術の例示として、実施の形態および変形例を説明した。そのために、添付図面および詳細な説明を提供した。
　したがって、添付図面および詳細な説明に記載された構成要素の中には、課題解決のために必須な構成要素だけでなく、上記技術を例示するために、課題解決のためには必須でない構成要素も含まれ得る。そのため、それらの必須ではない構成要素が添付図面や詳細な説明に記載されていることをもって、直ちに、それらの必須ではない構成要素が必須であるとの認定をするべきではない。
　また、上述の実施の形態は、本開示における技術を例示するためのものであるから、請求の範囲又はその均等の範囲において種々の変更、置き換え、付加、省略などを行うことができる。
　本発明に係る半導体装置は、電子機器に搭載される半導体装置に適用可能であり、特に、携帯機器等の小型の電子機器に搭載される半導体装置に有用である。
１，１０１，２０１　　半導体素子
２　　基台
２ａ　　スリット
３　　接続部材
４　　放熱部材
４ａ　　切り欠き部（空間部）
４ｂ　　開口部（空間部）
５　　封止材
６　　接着層
７　　電極
８，２０８　　内部端子
９　　外部端子
１０　　接着材
１１　　第１のブロック
１２　　第２のブロック
１３　　第３のブロック
１４　　放熱部材枠部
１５　　放熱部材フレーム
１６　　リリースフィルム
１７　　基台枠部
１８　　基台フレーム

Claims (20)

  1. 　主面上に端子が配置された基台と、
    　前記基台の主面上に保持され、上面に電極が配置された第１の半導体素子と、
    　前記端子と前記電極とを接続する接続部材と、
    　前記基台の主面上に、前記端子、前記第１の半導体素子及び前記接続部材を覆うように配置された封止材と、
    　前記封止樹脂の上に配置された放熱部材とを備え、
    　前記放熱部材における前記接続部材の上側部分には空間部が形成され、
    　前記空間部には、前記封止材が配されており、
    　前記基台の側面方向から見て、前記接続部材の頂点は、前記空間部の内側に位置することを特徴とする半導体装置。
  2. 　前記放熱部材の側面と前記封止材の側面と前記基台の側面とは一平面をなすことを特徴とする請求項１に記載の半導体装置。
  3. 　前記放熱部材の上面と前記封止材の上面とは一平面をなすことを特徴とする請求項２に記載の半導体装置。
  4. 　前記放熱部材は、前記第１の半導体素子の上側部分と前記接続部材の配置領域の上側部分とを除く領域を覆う第１のブロック及び第２のブロックと、前記第１のブロックと前記第２のブロックとを互いに連結し且つ前記第１の半導体素子の上側部分を覆う第３のブロックとから構成される
    平面Ｈ字状を有していること特徴とする請求項１に記載の半導体装置。
  5. 　前記第３のブロックは、前記基台の第１の側面から前記第１の側面と対向する第２の側面までの上側の領域を覆っており、
    　前記第１のブロックは、前記基台の前記第１の側面の外側に位置して前記第１の側面を覆うと共に、前記第２のブロックは、前記基台の前記第２の側面の外側に位置して前記第２の側面を覆うことを特徴とする請求項４に記載の半導体装置。
  6. 前記放熱部材は、前記第１および第２のブロックよりも、前記第３のブロックの厚みが薄いことを特徴とする請求項５に記載の半導体装置。
  7. 前記放熱部材において前記第３のブロックの厚みが、前記半導体素子の上面から前記封止材の上面までの厚みよりも薄いことを特徴とする請求項５に記載の半導体装置。
  8. 　前記放熱部材における前記空間部は、前記接続部材の配置領域から前記封止材の側面までを露出する切り欠き部であることを特徴とする請求項１に記載の半導体装置。
  9. 　前記切り欠き部は、その平面形状が前記放熱部材の中心部から外側に向かうに連れて切り欠き幅が大きくなるように形成されていることを特徴とする請求項８に記載の半導体装置。
  10. 　前記空間部は、前記接続部材の配置領域の上側部分を開口する開口部であることを特徴とする請求項１に記載の半導体装置。
  11. 　前記開口部は、その平面形状が前記放熱部材の中心部から外側に向かうに連れて開口幅が大きくなるように形成されていることを特徴とする請求項１０に記載の半導体装置。
  12. 　前記放熱部材は、前記基台の少なくとも１つの側面から外側の領域に拡張して形成され、前記基台の少なくとも１つの側面は、前記放熱部材により覆われていることを特徴とする請求項１０又は１１に記載の半導体装置。
  13. 　前記放熱部材と前記第１の半導体素子との隙間は、５０μｍ以上且つ１００μｍ以下であることを特徴とする請求項１に記載の半導体装置。
  14. 　前記封止材は、フィラーを含有しない第１の封止材と、フィラーを含有する第２の封止材とを含み、
    　前記放熱部材と前記第１の半導体素子との隙間には、前記第１の封止材が封入され、
    　前記放熱部材と前記第１の半導体素子との隙間を除く領域には、前記第２の封止材が封入されていることを特徴とする請求項１に記載の半導体装置。
  15. 　前記封止材は、金属を含有しない第１の封止材と、金属を含有する第２の封止材とを含み、
    　前記放熱板と前記第１の半導体素子との隙間には、前記第１の封止材が封入され、
    　前記放熱板と前記第１の半導体素子との隙間を除く領域には、前記第２の封止材で封入されていることを特徴とする請求項１に記載の半導体装置。
  16. 　主面上に端子が配置された基台と、
    　前記基台の主面上における前記端子を除く領域に配置された放熱部材と、
    　前記放熱部材の上に保持され、上面に電極が配置された第１の半導体素子と、
    　前記端子と前記電極とを接続する接続部材と、
    　前記基台の主面上に、前記端子、前記第１の半導体素子及び前記接続部材を覆うように配置された封止材とを備え、
    　前記放熱部材は、前記基台上の前記接続部材の配置領域を除く領域の上面が、前記接続部材の頂点よりも高く形成されていることを特徴とする半導体装置。
  17. 　前記放熱部材は、前記基台上における前記第１の半導体素子と前記接続部材の配置領域の上側部分とを除く領域を覆う第１のブロック及び第２のブロックと、前記第１のブロックと前記第２のブロックとを互いに連結する第３のブロックとから構成される平面Ｈ字状を有していること特徴とする請求項１６に記載の半導体装置。
  18. 　前記放熱部材の側面と前記封止材の側面と前記基台の側面とは、一平面をなすことを特徴とする請求項１７に記載の半導体装置。
  19. 　前記基台は、リードフレームであることを特徴とする請求項１又は１６に記載の半導体装置。
  20. 　前記基台は、第２の半導体素子であることを特徴とする請求項１又は１６に記載の半導体装置。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020505791A (ja) * 2017-01-25 2020-02-20 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ 電子構成素子を機械的に接続させる方法及び電子構成素子アセンブリ
JP2021061437A (ja) * 2021-01-04 2021-04-15 昭和電工マテリアルズ株式会社 半導体コンプレッション成型用離型シート及びこれを用いて成型される半導体パッケージ

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298695B (zh) 2015-06-05 2019-05-10 台达电子工业股份有限公司 封装模组、封装模组堆叠结构及其制作方法
FR3065319B1 (fr) * 2017-04-13 2019-04-26 Institut Vedecom Module electronique de puissance et convertisseur electrique de puissance l’incorporant

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142627A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 半導体装置及びその製造方法
JPH10209348A (ja) * 1997-01-21 1998-08-07 Ind Technol Res Inst 放熱効果を増進する半導体のパッケージ構造
JPH10308466A (ja) * 1995-11-15 1998-11-17 Anam Ind Co Inc ヒートシンク付着ボールグリッドアレイ半導体パッケージ
JP2006059871A (ja) * 2004-08-17 2006-03-02 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2010514208A (ja) * 2006-12-21 2010-04-30 アギア システムズ インコーポレーテッド 回路ダイの熱的性能の高いパッケージング
JP2010114256A (ja) * 2008-11-06 2010-05-20 Panasonic Corp 半導体装置、および半導体装置の製造方法
JP2012009726A (ja) * 2010-06-28 2012-01-12 Fujitsu Semiconductor Ltd 半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2679806B2 (ja) 1988-05-10 1997-11-19 シチズン時計株式会社 樹脂封止型ピングリッドアレイ
US5233225A (en) 1988-02-05 1993-08-03 Citizen Watch Co., Ltd. Resin encapsulated pin grid array and method of manufacturing the same
US5289039A (en) 1988-02-05 1994-02-22 Citizen Watch Co., Ltd. Resin encapsulated semiconductor device
US5179039A (en) 1988-02-05 1993-01-12 Citizen Watch Co., Ltd. Method of making a resin encapsulated pin grid array with integral heatsink
US5108955A (en) 1988-10-27 1992-04-28 Citizen Watch Co., Ltd. Method of making a resin encapsulated pin grid array with integral heatsink
JP3514101B2 (ja) 1998-01-28 2004-03-31 セイコーエプソン株式会社 半導体装置及びその製造方法並びに電子機器
US8039951B2 (en) * 2006-01-19 2011-10-18 United Test And Assembly Center Ltd. Thermally enhanced semiconductor package and method of producing the same
US7998791B2 (en) * 2008-02-01 2011-08-16 National Semiconductor Corporation Panel level methods and systems for packaging integrated circuits with integrated heat sinks
US8581374B1 (en) * 2010-10-04 2013-11-12 Marvell International Ltd. Placing heat sink into packaging by strip formation assembly

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142627A (ja) * 1993-11-18 1995-06-02 Fujitsu Ltd 半導体装置及びその製造方法
JPH10308466A (ja) * 1995-11-15 1998-11-17 Anam Ind Co Inc ヒートシンク付着ボールグリッドアレイ半導体パッケージ
JPH10209348A (ja) * 1997-01-21 1998-08-07 Ind Technol Res Inst 放熱効果を増進する半導体のパッケージ構造
JP2006059871A (ja) * 2004-08-17 2006-03-02 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP2010514208A (ja) * 2006-12-21 2010-04-30 アギア システムズ インコーポレーテッド 回路ダイの熱的性能の高いパッケージング
JP2010114256A (ja) * 2008-11-06 2010-05-20 Panasonic Corp 半導体装置、および半導体装置の製造方法
JP2012009726A (ja) * 2010-06-28 2012-01-12 Fujitsu Semiconductor Ltd 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020505791A (ja) * 2017-01-25 2020-02-20 ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ 電子構成素子を機械的に接続させる方法及び電子構成素子アセンブリ
JP2021061437A (ja) * 2021-01-04 2021-04-15 昭和電工マテリアルズ株式会社 半導体コンプレッション成型用離型シート及びこれを用いて成型される半導体パッケージ
JP7052891B2 (ja) 2021-01-04 2022-04-12 昭和電工マテリアルズ株式会社 半導体コンプレッション成型用離型シート及びこれを用いて成型される半導体パッケージ

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