WO2014087877A1 - Substrat d'interposeur et procédé permettant de fabriquer ce dernier - Google Patents

Substrat d'interposeur et procédé permettant de fabriquer ce dernier Download PDF

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WO2014087877A1
WO2014087877A1 PCT/JP2013/081714 JP2013081714W WO2014087877A1 WO 2014087877 A1 WO2014087877 A1 WO 2014087877A1 JP 2013081714 W JP2013081714 W JP 2013081714W WO 2014087877 A1 WO2014087877 A1 WO 2014087877A1
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substrate
single crystal
crystal silicon
silicon
base material
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PCT/JP2013/081714
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English (en)
Japanese (ja)
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弘 茂木
芳宏 久保田
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信越化学工業株式会社
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Priority to JP2014551045A priority Critical patent/JP6137196B2/ja
Publication of WO2014087877A1 publication Critical patent/WO2014087877A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an interposer substrate, and more specifically, a semiconductor device or other electronic device inserted between a wiring substrate and an electronic element (for example, a semiconductor chip) mounted on the wiring substrate.
  • the present invention relates to an interposer substrate for producing an interposer used for constituting.
  • the present invention also relates to a method for manufacturing such an interposer substrate.
  • a semiconductor device is configured by mounting a semiconductor chip such as an IC chip or LSI chip on a wiring board (also called a mounting board or the like) such as a multilayer circuit board. Further, in order to electrically connect the wiring substrate and the semiconductor chip, a wire bonding method (WB method) using bonding wires as connection means is used.
  • WB method wire bonding method
  • the bonding wire used as a connection means has a weakness such as a low mechanical strength and requires a wide wiring space, and demands for recent high-density wiring and miniaturization and thinning of devices are required. There was a problem that it was not possible to respond sufficiently.
  • a method of mounting a semiconductor chip such as an IC chip or an LSI chip on a wiring board such as a multilayer circuit board via solder bumps has been widely used. This method is called a flip chip (FC) method.
  • solder is raised on an aluminum electrode on a circuit forming surface of the semiconductor chip, and the solder is further formed.
  • solder is raised on an aluminum electrode on a circuit forming surface of the semiconductor chip, and the solder is further formed.
  • solder is further formed.
  • gold wires are bonded to aluminum electrodes to form small spherical bumps.
  • an insulating sealing resin also referred to as an underfill material
  • an epoxy resin such as an epoxy resin in order to increase the mechanical strength of the device and increase the water resistance.
  • the semiconductor device in which the wiring is formed with high density by the FC method has a drawback. That is, since the wiring board and the semiconductor chip are merely joined by solder bumps, even if the semiconductor device is stressed from below or from the side, even if it is resin-sealed, the wiring board and the semiconductor chip May come off. In addition, since the wiring board, semiconductor chip, and underfill material have different linear expansion coefficients, the wiring board and the semiconductor chip are greatly warped due to mismatch of the linear expansion coefficients, and the chip is damaged or detached. The occurrence of motion is a problem. In addition, it may be possible to prevent the problem of warping by configuring the wiring board with a hard material. However, as a recent trend, the substrate of the semiconductor chip is formed of a thin and brittle material. The problem cannot be solved.
  • Patent Document 1 in order to prevent a semiconductor chip from being easily detached from a wiring board, solder bumps are formed on an interposer having electrodes for soldering on the lower surface. A method of placing a semiconductor chip via the above method is proposed.
  • the side surface of the interposer further includes electrodes that can be soldered to the wiring board at four corners (end surfaces).
  • Patent Document 2 in order to prevent damage to the surface (wiring, etc.) of the semiconductor chip when the underfill material after filling is hardened, the semiconductor chip is soldered with a solder bump.
  • a method of connecting with an interposer and further connecting an electrode pad of the interposer to a wiring board has been proposed.
  • the underfill material is composed of an epoxy resin-based sealing resin and a filler such as silica or alumina dispersed therein, and the distribution density of the filler is "closely" on the interposer side.
  • the semiconductor chip is adjusted to be “sparse”. According to the above method, the interposer is interposed between the wiring board and the semiconductor chip, so that the mounting strength is improved and the chip is prevented from coming off.
  • the present invention has been made in view of the above circumstances, and is useful for increasing the heat dissipation of semiconductor devices and increasing the speed (making good high-frequency characteristics), making it easy to mount semiconductor chips and the like, and to wiring boards and semiconductor chips. It is an object of the present invention to provide an interposer substrate that can be firmly bonded and a method for manufacturing the same.
  • the inventors of the present invention have a thermal conductivity of a single crystal silicon substrate and at least one selected from the group of sapphire, alumina, diamond, aluminum nitride, and silicon nitride.
  • the interposer substrate having the insulating layer it has been found that the semiconductor device can achieve high heat dissipation and high speed response (high frequency characteristics), and intensive studies including its manufacturing method have been made. It came to make.
  • the present invention provides the following interposer substrate and method for producing the same.
  • An interposer substrate having a single crystal silicon substrate and a thermally conductive insulating layer made of sapphire, alumina, diamond, aluminum nitride, or silicon nitride provided on the single crystal silicon substrate.
  • the insulating layer is a chemical vapor deposition film or a physical vapor deposition film made of alumina, diamond, aluminum nitride, or silicon nitride.
  • the insulating layer is made of a sapphire, alumina, aluminum nitride, or silicon nitride substrate.
  • An insulating layer made of alumina, diamond, aluminum nitride or silicon nitride is formed on a plate-like single crystal silicon base material by chemical vapor deposition or physical vapor deposition, and then the single crystal silicon base material is An interposer substrate manufacturing method for obtaining an interposer substrate which is formed with a single crystal silicon substrate and has a thermally conductive insulating layer on the single crystal silicon substrate.
  • ions are implanted from the surface of the single crystal silicon base material to form an ion implantation region, and after forming the insulating layer, a part of the single crystal silicon base material is peeled off in the ion implantation region.
  • a thin film is formed, and then the single crystal silicon base material and the insulating substrate are bonded together via the silicon-containing inorganic thin film, and then the single crystal silicon base material is formed into a single crystal silicon substrate, and the insulating substrate is formed.
  • the silicon-containing inorganic thin film is a thin film made of silicon oxide, silicon nitride or silicon oxynitride formed by chemical vapor deposition or physical vapor deposition, or a polysilazane heat-generated film.
  • the heat-generated film of polysilazane is a silicon-containing inorganic thin film formed by forming a coating film containing polysilazane and performing a baking treatment in which the coating film is heated to 600 ° C. or more and 1,200 ° C. or less.
  • Ions are implanted from the surface of the insulating substrate or the surface of the silicon-containing inorganic thin film formed on the insulating substrate to form an ion implantation region, and the single crystal silicon base material and the insulating substrate are bonded to the silicon-containing inorganic thin film.
  • the present invention by including a single crystal silicon substrate and a thermally conductive insulating layer made of sapphire, alumina, diamond, aluminum nitride, or silicon nitride provided on the single crystal silicon substrate, It is possible to provide a useful interposer substrate capable of achieving high heat dissipation and high speed response (good high frequency characteristics) of a semiconductor device. Moreover, the interposer substrate as described above can be easily manufactured by the method for manufacturing an interposer substrate of the present invention.
  • FIG. 4C is a cross-sectional view showing a state where the single crystal silicon base material is peeled off in the ion implantation region
  • FIG. 4D is a cross-sectional view of the interposer substrate.
  • a cross-sectional view showing a state where the insulating substrate is thinned by polishing (f) is a cross-sectional view showing a state where the single crystal silicon base material is peeled off in the ion implantation region, and (g) is a cross-sectional view of the interposer substrate. is there.
  • the method for manufacturing a substrate for an interposer according to the present invention includes a step of implanting hydrogen ions (rare gas ions) into a single crystal silicon base material (step 11), a step of forming an insulating layer (step 12), The processing is performed in the order of the thinning (peeling) treatment step (step 13) and the damage layer removal step (step 14).
  • Step 11 Hydrogen ion (rare gas ion) implantation step into single crystal silicon base material
  • hydrogen ions or rare gas that is, helium, neon, argon, krypton, xenon, radon
  • the single crystal silicon base material 1A is a base material for a base substrate of an interposer substrate, and is not particularly limited.
  • the single crystal silicon base material 1A is obtained by slicing a single crystal grown by the Czochralski (CZ) method.
  • the diameter may be 100 to 300 mm
  • the conductivity type may be P-type or N-type
  • the resistivity may be about 10 ⁇ ⁇ cm.
  • the plate thickness of the single crystal silicon base material 1A is preferably 100 to 700 ⁇ m from the viewpoint of handling and ease of thinning described later.
  • the formation method of the ion implantation region 2 is not particularly limited.
  • Rare gas ions are implanted.
  • the implantation energy can be set to 1 to 10 MeV, and the implantation dose can be set to 2 ⁇ 10 16 to 3 ⁇ 10 17 / cm 2 .
  • hydrogen ions to be implanted hydrogen ions (H + ) with a dose of 2 ⁇ 10 16 to 3 ⁇ 10 17 (atoms / cm 2 ), or 1 ⁇ 10 16 to 2 ⁇ 10 16 (atoms / cm 2 ).
  • a hydrogen molecular ion (H 2 + ) having a dose amount of 1 to 5 is preferable.
  • the depth from the ion-implanted substrate surface to the ion-implanted region 2 corresponds to the desired thickness of the interposer substrate as the single crystal silicon substrate 1, but is preferably Is about 20 to 400 ⁇ m, more preferably about 100 ⁇ m.
  • Step 12 Insulating layer forming step
  • an insulating layer 4 having thermal conductivity made of alumina, diamond, aluminum nitride, or silicon nitride is formed on the ion-implanted surface of the single crystal silicon base material 1A by chemical vapor deposition or physical vapor deposition (see FIG. 1 (b)).
  • the chemical vapor deposition method and the physical vapor deposition method are not particularly limited as long as an inorganic thin film having high thermal conductivity and high electrical insulation can be formed.
  • the chemical vapor deposition method includes a microwave plasma CVD method and a high frequency plasma CVD method. Any of the above methods and high-density plasma CVD method may be used.
  • the physical vapor deposition method any of an ion plating method and a sputtering method may be used.
  • the film thickness of the insulating layer 4 is preferably 0.1 to 100 ⁇ m, more preferably 1 to 10 ⁇ m. If the film thickness is less than the lower limit, necessary insulation may not be ensured. If the film thickness exceeds the upper limit, the shape of the substrate may deteriorate due to internal stress of the film.
  • Step 13 Thinning (peeling) treatment step
  • thermal energy, mechanical energy, or optical energy is applied to the ion-implanted portion of the single crystal silicon base material 1 ⁇ / b> A, and a part of the single crystal silicon base material 1 ⁇ / b> A is peeled along the ion implantation region 2.
  • the remainder on the insulating layer 4 side is a single crystal silicon substrate 1 (FIG. 1C).
  • the peeling is preferably performed by cleaving from one end of the single crystal silicon base material 1 ⁇ / b> A to the other end along the ion implantation region 2.
  • heating is preferably performed at 200 ° C. or more, more preferably 250 to 350 ° C., and thermal energy is applied to the ion-implanted portion to generate minute bubble bodies in the ion-implanted portion. Since the ion-implanted portion is embrittled by the above heat treatment, a pressure that does not damage a wafer of, for example, 1 MPa or more and 5 MPa or less is appropriately selected in this embrittled portion, and a fluid such as gas or liquid is selected.
  • a method of peeling by applying mechanical energy such as an impact force that blows a jet.
  • the amorphous part When the ion-implanted part is in an amorphous state, the amorphous part is irradiated with light of a wavelength that is absorbed to absorb light energy.
  • One method selected from methods of peeling from the injection interface or a combination of two or more methods When you do a release Iyoi.
  • the ion-implanted damage layer is preferably removed by wet etching or dry etching.
  • the wet etching such as KOH solution, NH 4 OH solution, NaOH solution, CsOH solution, ammonia water (28 mass%), hydrogen peroxide (30-35 wt%), SC-l solution consisting of water (balance) , EDP (ethylenediamine pyrocatechol) solution, TMAH (4-methyl ammonium hydroxide) solution, and hydrazine solution may be used.
  • dry etching for example, reactive gas etching in which the substrate surface of the single crystal silicon substrate 1 is exposed in a fluorine-based gas or etching, and reactivity in which the fluorine-based gas is ionized and radicalized by plasma to etch the substrate surface is etched. Examples include ion etching.
  • the region to be removed in this step is at least the entire ion-implanted damage layer 7 of the single crystal silicon substrate 1 related to crystal defects, and the surface layer of the single crystal silicon substrate 1 is preferably 120 nm or more in thickness. Is a thickness of 150 nm or more.
  • the substrate surface of the single crystal silicon substrate 1 may be mirror-finished. Specifically, the substrate surface of the single crystal silicon substrate 1 is subjected to chemical mechanical polishing (CMP polishing) and finished to a mirror surface.
  • CMP polishing chemical mechanical polishing
  • a conventionally known CMP polishing used for planarization of a silicon wafer or the like may be used.
  • the CMP polishing may also serve as the removal of the ion implantation damage layer.
  • the interposer substrate 10 in which the insulating layer 4 is laminated on the single crystal silicon substrate 1 can be manufactured (FIG. 1D).
  • the thickness of the interposer substrate 10 is not particularly limited, but a substrate in the vicinity of the normal SEMI standard / JEIDA standard is preferable because it is easy to handle.
  • the method using the ion implantation delamination method has been described as a method for obtaining the single crystal silicon substrate 1 by thinning the single crystal silicon base material 1A.
  • the single crystal silicon base material 1A may be thinned by using a mechanical method such as grinding, lapping, polishing, a chemical method such as etching, or a combination thereof.
  • the method for producing a substrate for an interposer includes a step of forming a silicon-containing inorganic thin film on a single crystal silicon base material (step 21), a hydrogen ion (noble gas) on the single crystal silicon base material.
  • Ions) implantation step (step 22), hydrogen ion (rare gas ion) implantation step into the insulating substrate (step 23), surface activation treatment step of the single crystal silicon base material and / or insulating substrate (step 24), single crystal
  • the silicon base material and insulating substrate are bonded together (step 25), the thinning (peeling) treatment step (step 26), and the damaged layer removal step (step 27).
  • Step 21 Step of forming silicon-containing inorganic thin film on single crystal silicon base material
  • the silicon-containing inorganic thin film 3 is formed on the surface to be bonded to the insulating substrate 4A in the single crystal silicon base material 1A (FIG. 2A).
  • the single crystal silicon base material 1A is the same as that shown in the first embodiment.
  • the silicon-containing inorganic thin film 3 is a thin film made of silicon oxide, silicon nitride, or silicon oxynitride, and is preferably a chemical vapor deposition film, a physical vapor deposition film, or a heat-generated film of polysilazane. Any of these films may be used as long as they do not peel off after the substrates are bonded together, and any voids are not generated between the substrates and the substrate interface by heat treatment in the manufacturing process. From the nature, cost, purity, etc. of each film A film formation method may be selected.
  • a chemical vapor deposition film may be formed by a low pressure CVD method, a microwave plasma CVD method, a high frequency plasma CVD method, a high density plasma CVD method, or the like, and a physical vapor deposition film may be formed by an ion plating method or a sputtering method.
  • the smoothness of the formed silicon-containing inorganic thin film 3 surface is insufficient in the bonding described later, the smoothness may be improved by CMP polishing, chemical etching, or the like as necessary.
  • the polysilazane heating film as the silicon-containing inorganic thin film 3 is formed as follows. First, a coating film containing polysilazane is formed on the single crystal silicon base material 1A. At this time, the coating composition used in order to form the coating film containing polysilazane shall contain polysilazane and a solvent.
  • perhydropolysilazane represented by the general formula — (SiH 2 NH) n — is preferable because there are few impurities remaining in the film after conversion.
  • Perhydropolysilazane is an inorganic polymer having — (SiH 2 NH) — as a basic unit, all of its side chains being hydrogen, and being soluble in an organic solvent.
  • the solvent may be any solvent that does not react with perhydropolysilazane.
  • Aromatic solvents such as hexane, aliphatic solvents, and ether solvents.
  • the concentration of polysilazane in the solvent is preferably 1 to 30% by mass, more preferably 3 to 20% by mass. If it is less than 1% by mass, the film thickness after coating becomes thin and the effect of improving the surface roughness of the substrate (single crystal silicon base material 1A or insulating substrate 4A) may be insufficient. Stability may be reduced.
  • the coating composition As a coating method of the coating composition, known methods such as spray coating, spin coating, dip coating, roll coating, screen printing, and slit coating can be used.
  • the thickness to be applied is determined by the roughness of the substrate surface to be applied, the level of the step, and the thickness of the buried layer required as a semiconductor device, but the thickness as the inorganic thin film 3 after firing is 10 nm to 10 ⁇ m. Is preferred. When it is not formed by a single application, the application may be repeated for lamination. After coating, in order to remove the solvent, it is dried at about 50 to 200 ° C. for 1 minute to 2 hours to form a coating film.
  • a baking treatment is performed in which the coating film is heated at 600 ° C. or more and 1,200 ° C. or less to convert the polysilazane of the coating film into SiO 2 or SiN to obtain the silicon-containing inorganic thin film 3.
  • a baking treatment is performed at a heating temperature of 600 ° C. or more and 1,200 ° C. or less, preferably 800 ° C. or more and 1,000 ° C. or less in an atmosphere containing oxygen and / or water vapor. .
  • the heating temperature is less than 600 ° C., for example, when treated at 450 ° C., the polysilazane skeleton is converted to a siloxane skeleton, but silanol groups remain, and the leakage current is higher as the insulation resistance than the thermal oxide film of silicon. There is. Further, the higher the heating temperature, the more the surface roughness of the silicon-containing inorganic thin film 3 tends to be improved. However, if it exceeds 1,200 ° C., the SiO 2 may be denatured.
  • heating temperature 600 ° C. or more and 1,200 ° C. or less, preferably 800 ° C. or more and 1,000 ° C. or less, under an inert atmosphere containing nitrogen or under reduced pressure. Process. If the heating temperature is less than 600 ° C., conversion to SiN may not proceed. Moreover, although there exists a tendency for the surface roughness of the silicon-containing inorganic thin film 3 to improve, so that heating temperature is high, when it exceeds 1200 degreeC, there exists a possibility that SiN may modify
  • Calcination treatment time is preferably 10 seconds to 12 hours, more preferably 1 minute to 1 hour. If the treatment time is shorter than 10 seconds, the conversion reaction from polysilazane may be insufficient, and if it is longer than 12 hours, the firing treatment cost may increase.
  • the silicon-containing inorganic thin film 3 can be formed on the surface on which the single crystal silicon base material 1A is bonded.
  • the thickness of the silicon-containing inorganic thin film 3 is preferably 10 nm to 10 ⁇ m, more preferably 100 nm to 1 ⁇ m. If the thickness is less than 10 nm, the effect of improving the surface roughness of the substrate may be insufficient, and if it exceeds 10 ⁇ m, warpage may occur due to the difference in thermal expansion coefficient from the single crystal silicon substrate, which may be inappropriate.
  • the silicon-containing inorganic thin film 3 has an insulation resistance comparable to that of a conventional silicon thermal oxide film. Thereby, it becomes a smooth surface to the extent that bonding is possible with the thickness at the time of the baking treatment without polishing the surface of the silicon-containing inorganic thin film 3.
  • the silicon-containing inorganic thin film 3 with the thickness at the time of the baking treatment means that the treatment for changing the surface roughness such as polishing and etching is not performed, and the surface activation treatment described later is allowed. .
  • the smoothness of the surface is insufficient for bonding, it does not hinder the processing such as polishing and etching.
  • the silicon-containing inorganic thin film 3 may be similarly formed on an insulating substrate 4A described later.
  • the silicon-containing inorganic thin film 3 becomes an intermediate layer between the single crystal silicon substrate 1 and the insulating layer 4 in the interposer substrate 20 and can improve thermal shock resistance and adhesion.
  • Step 22 Step of implanting hydrogen ions (rare gas ions) into the single crystal silicon base material
  • hydrogen ions or rare gas that is, helium, neon, argon, krypton, xenon, radon
  • ions or rare gas that is, helium, neon, argon, krypton, xenon, radon
  • the ion implantation conditions are the same as those shown in the first embodiment.
  • the depth from the ion-implanted substrate surface to the ion implantation region 2 is preferably about 20 to 400 ⁇ m, more preferably about 100 ⁇ m.
  • Step 23 Hydrogen ion (rare gas ion) implantation step into an insulating substrate
  • Hydrogen ions or rare gas (ie, helium, neon, argon, krypton, xenon, radon) ions are implanted from the surface of the insulating substrate 4A to be bonded to the single crystal silicon base material 1A to form an ion implantation region 5 in the substrate.
  • rare gas ie, helium, neon, argon, krypton, xenon, radon
  • the insulating substrate 4A is a base material that becomes the insulating layer 4 in the interposer substrate 20 of the present invention, and is a substrate made of sapphire, alumina, aluminum nitride, or silicon nitride.
  • the composition, purity, crystal structure, and the like of the insulating substrate 4A may be any as long as high thermal conductivity and high electrical insulation can be secured as the insulating layer.
  • the ion implantation conditions are basically the same as the ion implantation conditions for the single crystal silicon base material 1A, but the implantation energy is 1 to 10 MeV.
  • the depth from the ion-implanted substrate surface to the ion-implanted region 5 corresponds to the desired thickness of the insulating layer 4 provided on the single crystal silicon substrate 1, but is preferably Is about 1 to 100 ⁇ m, more preferably about 10 ⁇ m.
  • Step 24 Surface activation treatment step of single crystal silicon base material and / or insulating substrate
  • both or one of the surface of the silicon-containing inorganic thin film 3 of the single crystal silicon base material 1A and the surface of the insulating substrate 4A on which ions are implanted (or the surface of the silicon-containing inorganic thin film formed thereon) Surface activation treatment is performed.
  • Surface activation treatment is intended to activate by removing dirt on the substrate surface, exposing highly reactive dangling bonds (dangling bonds), or adding OH groups to the dangling bonds. Yes, for example, by plasma treatment or ion beam irradiation.
  • the single crystal silicon base material 1A and / or the insulating substrate 4A When processing with plasma, for example, the single crystal silicon base material 1A and / or the insulating substrate 4A is placed in a vacuum chamber, and after introducing a plasma gas, it is exposed to high-frequency plasma of about 100 W for about 5 to 10 seconds.
  • the surface is plasma treated.
  • the plasma gas hydrogen gas, nitrogen gas, oxygen gas, argon gas, a mixed gas thereof, a mixed gas of hydrogen gas and helium gas, or the like is used.
  • organic substances on the surface of the single crystal silicon base material 1A (silicon-containing inorganic thin film 3) and / or the insulating substrate 4A are removed, and the OH groups on the surface are further increased and activated.
  • the treatment by ion beam irradiation is a treatment in which the surface is sputtered by irradiating the single crystal silicon base material 1A (silicon-containing inorganic thin film 3) and / or the insulating substrate 4A with an ion beam using a gas used in plasma treatment.
  • the single crystal silicon base material 1A silicon-containing inorganic thin film 3
  • a gas used in plasma treatment it is possible to remove the dirt on the surface and expose the unbonded hands to increase the bonding force.
  • heat is applied to the bonded substrate 6 to perform a heat treatment (second heat treatment).
  • second heat treatment the bonding between the single crystal silicon base material 1A and the insulating substrate 4A through the silicon-containing inorganic thin film 3 is strengthened.
  • a temperature at which the bonded substrate 6 is not damaged by the influence (thermal stress) of the difference in thermal expansion coefficient between the single crystal silicon base material 1A and the insulating substrate 4A is selected.
  • the heat treatment temperature is preferably 300 ° C. or less, more preferably 150 to 250 ° C., still more preferably 150 to 200 ° C.
  • the heat treatment time is, for example, 1 to 24 hours.
  • Step 26 Thinning (peeling) treatment step
  • thermal energy, mechanical energy, or optical energy is applied to the ion-implanted portions of the single-crystal silicon base material 1A and the insulating substrate 4A in the bonded substrate 6 to peel along the ion-implanted regions 2 and 5.
  • a part of the single crystal silicon base material 1A on the silicon-containing inorganic thin film 3 side is left as the single crystal silicon substrate 1
  • a part of the insulating substrate 4A on the silicon-containing inorganic thin film 3 side is left as the insulating layer 4 (FIG. 2 ( e)).
  • the single crystal silicon base material 1A is thinned (thinned) to form a single crystal silicon substrate 1 having a thickness of about 10 to 400 ⁇ m, and the insulating substrate 4A is thinned (thinned).
  • the insulating layer 4 has a thickness of about 1 to 100 ⁇ m.
  • the peeling is preferably performed by cleaving from one end to the other end of the bonded substrate 6 along the ion implantation regions 2 and 5.
  • heating is preferably performed at 200 ° C. or more, more preferably 300 to 600 ° C., and thermal energy is applied to the ion-implanted portion to generate minute bubble bodies in the ion-implanted portion. Since the ion-implanted portion is embrittled by the above heat treatment, a pressure that does not damage a wafer of, for example, 1 MPa or more and 5 MPa or less is appropriately selected in this embrittled portion, and a fluid such as gas or liquid is selected.
  • a method of peeling by applying mechanical energy such as an impact force that blows a jet.
  • the amorphous part When the ion-implanted part is in an amorphous state, the amorphous part is irradiated with light of a wavelength that is absorbed to absorb light energy.
  • Step 27 Damaged layer removal step
  • the layers (ion implantation damage layers 7 and 8) that are damaged by the ion implantation and cause crystal defects are removed.
  • the removal of the ion-implanted damage layers 7 and 8 is preferably performed by polishing, wet etching, or dry etching.
  • the wet etching such as KOH solution, NH 4 OH solution, NaOH solution, CsOH solution, ammonia water (28 mass%), hydrogen peroxide (30-35 wt%), SC-l solution consisting of water (balance) , EDP (ethylenediamine pyrocatechol) solution, TMAH (4-methyl ammonium hydroxide) solution, and hydrazine solution may be used.
  • dry etching for example, reactive gas etching in which the ion-implanted damage layers 7 and 8 are exposed in a fluorine-based gas or etching is performed, and the fluorine-based gas is ionized and radicalized by plasma to etch the ion-implanted damage layers 7 and 8. Reactive ion etching and the like.
  • the region to be removed in this step is at least all of the ion implantation damage layers 7 and 8 related to crystal defects, and the thickness of the surface layer of the single crystal silicon substrate 1 and the insulating layer 4 is preferably 120 nm or more, more preferably. Is a thickness of 150 nm or more.
  • the surface of the single crystal silicon substrate 1 and / or the insulating layer 4 is mirror finished.
  • chemical mirror polishing CMP polishing
  • CMP polishing may be performed to finish the mirror surface.
  • a conventionally known CMP polishing used for planarization of a silicon wafer or the like may be used.
  • the CMP polishing may also serve as the removal of the ion implantation damage layer.
  • the interposer substrate 20 in which the silicon-containing inorganic thin film 3 and the insulating layer 4 made of an inorganic material having high electrical insulation and high thermal conductivity are laminated on the single crystal silicon substrate 1 can be manufactured. (FIG. 2 (f)).
  • the method for manufacturing a substrate for an interposer according to the present invention includes a step of implanting hydrogen ions (rare gas ions) into a single crystal silicon base material (step 31), and formation of a silicon-containing inorganic thin film on an insulating substrate.
  • Step (step 32), polishing step of silicon-containing inorganic thin film (step 33), surface activation treatment step of single crystal silicon base material and / or insulating substrate (step 34), bonding of single crystal silicon base material and insulating substrate Processing is performed in the order of the step (step 35), the thinning (polishing) processing step (step 36), the thinning (peeling) processing step (step 37), and the damaged layer removal step (step 38).
  • Step 31 Hydrogen ion (rare gas ion) implantation step into single crystal silicon base material
  • hydrogen ions or rare gas that is, helium, neon, argon, krypton, xenon, radon
  • the single crystal silicon base material 1A and the ion implantation region 2 are the same as those shown in the first and second embodiments.
  • Step 32 Step of forming a silicon-containing inorganic thin film on an insulating substrate
  • the silicon-containing inorganic thin film 3 is formed on the surface of the insulating substrate 4A to be bonded to the single crystal silicon base material 1A (FIG. 3B).
  • the insulating substrate 4A and the silicon-containing inorganic thin film 3 are the same as those shown in the second embodiment.
  • polishing for flattening the surface of the silicon-containing inorganic thin film 3 on the insulating substrate 4A is performed (FIG. 3C).
  • the polishing treatment is preferably chemical mechanical polishing (CMP polishing). This is flattened to such an extent that it can be bonded to a single crystal silicon base material 1A, which will be described later. For example, it is flattened to a surface roughness Ra (arithmetic average roughness) of about 0.1 to 5 nm. Note that this polishing step may be omitted when the silicon-containing inorganic thin film 3 is a heat-generated film of polysilazane.
  • Step 34 Surface activation treatment step of single crystal silicon base material and / or insulating substrate
  • surface activation treatment is performed on both or one of the surface of the single crystal silicon base material 1A on which ions are implanted and the surface of the silicon-containing inorganic thin film 3 on the insulating substrate 4A.
  • the surface activation treatment is the same as that shown in the second embodiment.
  • Step 36 Thinning (polishing) treatment step
  • the insulating substrate 4A in the bonded substrate 6 is polished to leave a part of the insulating substrate 4A on the silicon-containing inorganic thin film 3 side as the insulating layer 4 (FIG. 3E). That is, the thickness of the insulating substrate 4A is reduced (thinned) to form the insulating film 4 having a thickness of about 1 to 100 ⁇ m, preferably about 5 to 10 ⁇ m.
  • the thinning of the insulating substrate 4A here is not limited to polishing, but a mechanical method such as grinding, lapping, polishing, a chemical method such as etching, or a combination thereof is used. Good.
  • Step 37 Thinning (peeling) treatment step
  • thermal energy, mechanical energy, or optical energy is applied to the ion-implanted portion of the single-crystal silicon base material 1A in the bonded substrate 6 so as to be peeled off along the ion-implanted region 2, and the single-crystal silicon base material is separated.
  • a part of the material 1A on the silicon-containing inorganic thin film 3 side is left as the single crystal silicon substrate 1 (FIG. 3F). That is, the thickness of the single crystal silicon base material 1A is reduced (thinned) to obtain a single crystal silicon substrate 1 having a thickness of about 20 to 400 ⁇ m.
  • the peeling treatment conditions are the same as those shown in the second embodiment.
  • Step 38 Damaged layer removal step
  • the layer (ion implantation damage layer 7) that is damaged by the ion implantation and causes crystal defects is removed.
  • the removal conditions are the same as those shown in the second embodiment.
  • the surface of the single crystal silicon substrate 1 is mirror finished. Specifically, chemical mirror polishing (CMP polishing) may be performed to finish the mirror surface.
  • CMP polishing chemical mirror polishing
  • the interposer substrate 20 in which the silicon-containing inorganic thin film 3 and the insulating layer 4 made of an inorganic material having high electrical insulation and high thermal conductivity are laminated on the single crystal silicon substrate 1 can be manufactured. (Fig. 3 (g)).
  • interposer substrates 10 and 20 obtained as described above are applied to a semiconductor device, it is possible to achieve high heat dissipation and high speed response (good high frequency characteristics) of the semiconductor device.
  • Example 1 An evaluation sample was prepared by the following procedure. Hydrogen ions were implanted into a 6-inch single crystal silicon base material (thickness: 625 ⁇ m) at a dose of 6.0 ⁇ 10 16 atoms / cm 2 . Next, diamond nuclei were generated on the ion-implanted surface of the single crystal silicon base material with diamond powder having an average particle diameter of 500 nm, and then a diamond layer was formed as an insulating layer by CVD. Specifically, hydrogen gas and methane gas were used as source gases, and a diamond film was produced by processing for 3 hours at a pressure of 130 Torr and a microwave power of 5 kW in a microwave plasma CVD apparatus. At this time, the thickness of the diamond layer was 1000 nm.
  • a process of peeling in the ion implantation region of the single crystal silicon base material is performed, and a diamond layer (diamond / single crystal silicon) having a diamond layer having a thickness of 1 ⁇ m on a single crystal silicon substrate having a thickness of 100 ⁇ m is formed.
  • a substrate for Pose was obtained.
  • Example 2 An evaluation sample was prepared by the following procedure. 2 mL of a solution containing 20% by mass of perhydropolysilazane in a solvent n-dibutyl ether (Tresmile made by Sanwa Chemical, model number ANN120-20) was spin-coated on a 6-inch single crystal silicon base material (the same as in Example 1), The solvent was removed by heating at 150 ° C. for 3 minutes. Then, the resulting mixture was fired process heating 3 minutes at 800 ° C. in air, it was converted to the coating film to SiO 2 film (silicon-containing inorganic films). The film thickness after the baking treatment was 100 nm.
  • hydrogen ions were implanted at a dose of 6.0 ⁇ 10 16 atoms / cm 2 from the surface of the single crystal silicon base material on which the SiO 2 film was formed.
  • the ion implantation depth at this time is 100 ⁇ m.
  • hydrogen ions were implanted at a dose of 6.0 ⁇ 10 16 atoms / cm 2 from one surface of a separately prepared 6-inch sapphire substrate (thickness: 625 ⁇ m).
  • the ion implantation depth at this time is 10 ⁇ m.
  • the SiO 2 film formation surface of the single crystal silicon base material and the ion implantation surface of the sapphire substrate were subjected to plasma treatment, and then both were bonded and laminated with the SiO 2 film interposed therebetween.
  • the single crystal silicon base material of the bonded substrate and the hydrogen ion implantation region of each of the sapphire substrates are peeled off to form a 100 nm thick SiO 2 film and a thickness on the 100 ⁇ m thick single crystal silicon substrate.
  • a (sapphire / SiO 2 / single crystal silicon) laminated substrate (interposer substrate) in which 10 ⁇ m sapphire layers were laminated in this order was obtained.
  • the ion-implanted surface of the single crystal silicon base material and the silicon nitride sintered substrate were bonded together with a silicon nitride film interposed therebetween and laminated.
  • the silicon nitride sintered substrate was polished to a thickness of 10 ⁇ m.
  • the silicon nitride film having a thickness of 100 nm and the silicon nitride layer having a thickness of 10 ⁇ m are stacked in this order on a single crystal silicon substrate having a thickness of 100 ⁇ m, separated from the hydrogen ion implantation region of the single crystal silicon base material.
  • a (silicon nitride / silicon nitride / single crystal silicon) laminated substrate (interposer substrate) was obtained.
  • Example 2 the baking temperature of the SiO 2 film (silicon-containing inorganic thin film) was changed to 450 ° C., and a laminated substrate was produced in the same manner as in Example 2 except that.
  • Comparative Example 1 that is, the SiO 2 film having a baking temperature of 450 ° C.
  • Comparative Example 2 shows significant voids at the bonding interface.
  • Examples 1 to 3 no peeling or void was observed at the bonding interface.
  • Comparative Example 1 it is considered that voids were generated because condensation of silanol groups in the SiO 2 film or moisture in the film became gas by the heat treatment for bonding, and was diffused and held at the bonding interface.
  • connection bumps formed on the semiconductor element were lead-free solder made of tin and silver, the size was ⁇ 100 ⁇ m, and the bump pitch was 200 ⁇ m.
  • An underfill material (CRP-4152D manufactured by Sumitomo Bakelite Co., Ltd.) was filled in the gap between the semiconductor element and the interposer connected by the flip chip method by a capillary filling method and cured. Further, a predetermined number of ⁇ 500 ⁇ m solder balls were formed on conductor pads provided on the outer periphery of the semiconductor element mounting portion, thereby obtaining a semiconductor package on which two semiconductor elements were mounted.
  • the semiconductor package obtained in this way is mounted on a predetermined printed wiring board and used for an operation check test as a semiconductor device, and there is no problem in the operation as a semiconductor device in Examples 1 to 3. Was confirmed, and it was confirmed that it could operate at high speed.
  • the high speed operability was evaluated by the double pulse method.
  • a laser beam such as a YAG laser is irradiated at an energy density of 3 J / cm 2 , for example, and the response speed is measured from an oscilloscope using a pattern generator DG-8000 manufactured by Iwatatsu Corporation. The judgment of good or bad was made from the response speed, and 100 ns or less was judged good and less than 100 ns was judged bad. Further, Comparative Example 1 and the single crystal silicon substrate had poor high-speed operation.
  • thermal conductivity and volume resistivity were measured under the following conditions.
  • ⁇ Measurement of thermal conductivity> In accordance with the unsteady hot wire method (probe method) described in JIS R2618, the thermal conductivity was measured with a thermal conductivity meter (QTM-500: Kyoto Electronics Industry Co., Ltd.).
  • ⁇ Measurement of volume resistivity> Based on JIS H0602-1995, it was measured by a direct current four-probe method. The results are shown in Table 1.

Abstract

Selon la présente invention, sur un matériau de base en silicium monocristallin en forme de carte, une couche isolante (4) est composée d'alumine, de diamant, de nitrure d'aluminium ou de nitrure de silicium au moyen d'un dépôt chimique en phase vapeur ou d'un dépôt physique en phase vapeur ; ensuite, le matériau de base en silicium monocristallin (1A) est formé en tant que substrat en silicium monocristallin (1) et on obtient un substrat d'interposeur (10) qui comporte la couche isolante thermoconductrice (4) sur la substrat en silicium monocristallin (1). Le substrat d'interposeur est utile pour permettre une dissipation thermique plus importante et une application haute vitesse (de meilleures caractéristiques à fréquence élevée) des dispositifs semi-conducteurs, comporte des puces de semi-conducteur, ou analogues, qui sont facilement montées sur ces derniers, et peut être fermement fixé à des cartes de câblage et aux puces de semi-conducteur.
PCT/JP2013/081714 2012-12-07 2013-11-26 Substrat d'interposeur et procédé permettant de fabriquer ce dernier WO2014087877A1 (fr)

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