JP2008187203A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP2008187203A JP2008187203A JP2008115279A JP2008115279A JP2008187203A JP 2008187203 A JP2008187203 A JP 2008187203A JP 2008115279 A JP2008115279 A JP 2008115279A JP 2008115279 A JP2008115279 A JP 2008115279A JP 2008187203 A JP2008187203 A JP 2008187203A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor
- semiconductor device
- die attach
- adhesive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01076—Osmium [Os]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
【解決手段】 層間絶縁膜405および銅からなる配線407からなる配線層が複数層積層し、最上層にソルダーレジスト層408を形成し、多層配線構造体を構成する。その表面に第一の半導体チップ410および第二の半導体チップ430と、回路素子440とを設ける。第一の半導体チップ410および第二の半導体チップ430を、接着層510を介して密着させる。第二の半導体チップ430の下面はプラズマ処理面とし、この面を覆う接着層510に第一の半導体チップ410を接着する。
【選択図】 図5
Description
図2および図3は、本実施形態に係る半導体チップの工程断面図である。図2(a)は半導体ウエハ500を示す図であり、上面が素子形成面501である。まず、図2(b)
のように素子形成面501上に素子層502を形成する。次に、図2(c)のように半導体ウエハの裏面を平坦化するために研磨し、さらに純水でリンス洗浄する。さらに、図2(d)のように裏面を研磨・洗浄した半導体ウエハ500の裏面をプラズマ処理する。プラズマ照射条件は、優れた界面密着性が発現する表面特性が得られるよう、用いる樹脂材料に応じて適宜設定する。たとえば、半導体ウエハ裏面に付着した有機物の除去効率が向上するように、プラズマガスにアルゴンなどの不活性ガスが含まれる条件とする。こうすることにより、半導体ウエハ裏面に付着した有機物の除去効率が向上する。また、アルゴンは窒素ガスや希ガス等の他の不活性ガスを用いてもよく、これらのガスに酸素などの酸化性ガスを混合して用いてもよい。
バイアス: 無印加
RFパワー(W): 500
圧力(Pa): 20
処理時間(sec): 20
このプラズマ処理により、半導体ウエハ500の裏面に付着した有機物が除去されて清浄化されるとともに、密着性に優れる表面に改質される。この結果、その下に形成される半導体チップやソルダーレジスト層との接着性が向上する。
図6は、接着層510を介して接着されている第一の半導体チップ410と第二の半導体チップ430とを、第一の半導体チップ410の下面を接着層510を介してソルダー
レジスト層408上に接着させた断面構造を示す図である。この半導体装置は、層間絶縁膜405および銅からなる配線407からなる配線層が複数層積層し、最上層にソルダーレジスト層408が形成された多層配線構造体と、その表面に形成された第一の半導体チップ410および第二の半導体チップ430と、ワイヤ412と、回路素子440とにより構成されている。多層配線構造体の裏面には、半田ボール420が設けられている。第一の半導体チップ410と第二の半導体チップ430との間、第一の半導体チップ410と配線407との間、および第二の半導体チップ430と配線407との間はワイヤ412により接続されている。
本実施例では、Arプラズマ処理が施されたウエハ裏面の炭素、酸素、窒素、ケイ素の付着量を、Quantera SXM(PHI社製)を用いたX線光電子分光法により測定した。ウエハとしてはシリコンを用い、研削、リンス洗浄した面にArプラズマ処理を施した。また、測定の正確性を期すために、2枚のウエハAとウエハBを準備し、それぞれについて同様の処理を施して測定した。
X線径:200μm
光電子検出角度:45°
データ処理は、中性炭素C1sのメインピーク位置を284.60eVに合わせた。このような条件で、Arプラズマ処理が施されたウエハ裏面の炭素、酸素、窒素、ケイ素の付着量を測定した。
本実施例では、実施例1と同様の装置、同様の測定条件、同様のデータ処理により、O2プラズマ処理が施されたウエハ裏面の炭素、酸素、窒素、ケイ素の付着量を、Quantera SXM(PHI社製)を用いたX線光電子分光法により測定した。ウエハとしてはシリコンを用い、研削、リンス洗浄した面にO2プラズマ処理を施した。
本比較例では、実施例1と同様の装置、同様の測定条件、同様のデータ処理により、プラズマ処理が施されていないウエハ裏面の炭素、酸素、窒素、ケイ素の付着量を、Quantera SXM(PHI社製)を用いたX線光電子分光法により測定した。ウエハとしてはシリコンを用い、研削、リンス洗浄した。
Claims (4)
- 素子が形成された半導体ウエハの裏面を研磨した後、
前記半導体ウエハの裏面をプラズマ処理して、前記半導体ウエハの裏面を改質し、
その改質された前記半導体ウエハの裏面にダイアタッチ用フィルムを設け、前記ダイアタッチ用フィルムを介して前記半導体ウエハをダイシングシートに貼付けた後、前記半導体ウエハをダイシングして、前記ダイアタッチ用フィルムを貼付けた状態の複数の半導体チップに分離することを特徴とする半導体装置の製造方法。 - 前記ダイアタッチ用フィルムを貼付けた状態の各半導体チップは、前記ダイアタッチ用フィルムを介して基材と接着されていることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記ダイアタッチ用フィルムを貼付けた状態の各半導体チップは、前記ダイアタッチ用フィルムを介して接着されて積層されていることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記ダイアタッチ用フィルムを介して接着されて積層された複数の半導体チップは、貼付けられた前記ダイアタッチ用フィルムを介して前記基材に接着されていることを特徴とする請求項3に記載の半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008115279A JP2008187203A (ja) | 2008-04-25 | 2008-04-25 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008115279A JP2008187203A (ja) | 2008-04-25 | 2008-04-25 | 半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004079282A Division JP2005268552A (ja) | 2004-03-18 | 2004-03-18 | 半導体装置およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2008187203A true JP2008187203A (ja) | 2008-08-14 |
Family
ID=39729987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008115279A Pending JP2008187203A (ja) | 2008-04-25 | 2008-04-25 | 半導体装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2008187203A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010073893A (ja) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2015233066A (ja) * | 2014-06-09 | 2015-12-24 | 株式会社ディスコ | 板状物の分割方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002093752A (ja) * | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | 半導体素子分離方法及び半導体素子分離装置 |
JP2002217154A (ja) * | 2001-01-16 | 2002-08-02 | Hitachi Ltd | ドライ洗浄方法 |
JP2002305171A (ja) * | 2001-04-05 | 2002-10-18 | Matsushita Electric Ind Co Ltd | シリコン系基板の表面処理方法 |
JP2003077892A (ja) * | 2002-08-02 | 2003-03-14 | Matsushita Electric Ind Co Ltd | プラズマエッチング装置およびプラズマエッチング方法 |
JP2003151957A (ja) * | 2001-08-27 | 2003-05-23 | Matsushita Electric Ind Co Ltd | プラズマ処理装置及びプラズマ処理方法 |
JP2004079597A (ja) * | 2002-08-12 | 2004-03-11 | Disco Abrasive Syst Ltd | 半導体チップの加工方法 |
-
2008
- 2008-04-25 JP JP2008115279A patent/JP2008187203A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002093752A (ja) * | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | 半導体素子分離方法及び半導体素子分離装置 |
JP2002217154A (ja) * | 2001-01-16 | 2002-08-02 | Hitachi Ltd | ドライ洗浄方法 |
JP2002305171A (ja) * | 2001-04-05 | 2002-10-18 | Matsushita Electric Ind Co Ltd | シリコン系基板の表面処理方法 |
JP2003151957A (ja) * | 2001-08-27 | 2003-05-23 | Matsushita Electric Ind Co Ltd | プラズマ処理装置及びプラズマ処理方法 |
JP2003077892A (ja) * | 2002-08-02 | 2003-03-14 | Matsushita Electric Ind Co Ltd | プラズマエッチング装置およびプラズマエッチング方法 |
JP2004079597A (ja) * | 2002-08-12 | 2004-03-11 | Disco Abrasive Syst Ltd | 半導体チップの加工方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010073893A (ja) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2015233066A (ja) * | 2014-06-09 | 2015-12-24 | 株式会社ディスコ | 板状物の分割方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7495344B2 (en) | Semiconductor apparatus | |
TWI446419B (zh) | 堆疊裝置的製造方法及裝置晶圓處理方法 | |
JP5161732B2 (ja) | 半導体装置の製造方法 | |
US6784530B2 (en) | Circuit component built-in module with embedded semiconductor chip and method of manufacturing | |
US7691672B2 (en) | Substrate treating method and method of manufacturing semiconductor apparatus | |
TWI352412B (en) | Multi-chip package structure and method of fabrica | |
US7807507B2 (en) | Backgrinding-underfill film, method of forming the same, semiconductor package using the backgrinding-underfill film, and method of forming the semiconductor package | |
US8334602B2 (en) | Die package including encapsulated die and method of manufacturing the same | |
JP2005109067A (ja) | 半導体装置およびその製造方法 | |
JP2003234359A (ja) | 半導体装置の製造方法 | |
JP2010239126A5 (ja) | パッケージ基板および半導体装置の製造方法 | |
WO2014087877A1 (ja) | インターポーザー用基板及びその製造方法 | |
TW201218317A (en) | Method of multi-chip stacking for decreasing void between chips | |
JP2003289128A (ja) | 回路部品内蔵モジュールおよびその製造方法 | |
JP2004165277A (ja) | 電子部品実装構造及びその製造方法 | |
JP2005005632A (ja) | チップ状電子部品及びその製造方法、並びにその実装構造 | |
US20090127665A1 (en) | Semiconductor device and manufacturing method thereof | |
JP2008187203A (ja) | 半導体装置の製造方法 | |
JP4067507B2 (ja) | 半導体モジュールおよびその製造方法 | |
JP2004343088A (ja) | 半導体装置及びその製造方法 | |
WO2012116482A1 (en) | Non-uniform vacuum profile die attach tip | |
JP2005268552A (ja) | 半導体装置およびその製造方法 | |
CN114171413A (zh) | 扇出式堆叠芯片的封装方法及封装结构 | |
JP4416553B2 (ja) | 半導体装置およびその製造方法 | |
US20070114672A1 (en) | Semiconductor device and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20080523 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100803 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110823 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111024 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20111117 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20111130 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120710 |