WO2014056252A1 - 薄膜晶体管主动装置及其制作方法 - Google Patents

薄膜晶体管主动装置及其制作方法 Download PDF

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WO2014056252A1
WO2014056252A1 PCT/CN2012/083390 CN2012083390W WO2014056252A1 WO 2014056252 A1 WO2014056252 A1 WO 2014056252A1 CN 2012083390 W CN2012083390 W CN 2012083390W WO 2014056252 A1 WO2014056252 A1 WO 2014056252A1
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Prior art keywords
layer
thin film
film transistor
oxide
gate insulating
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English (en)
French (fr)
Inventor
江政隆
陈柏林
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/806,821 priority Critical patent/US20140252343A1/en
Publication of WO2014056252A1 publication Critical patent/WO2014056252A1/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739Conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • H10D86/0221Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO

Definitions

  • the present invention relates to the field of flat display, and more particularly to a thin film transistor active device and a method of fabricating the same. Background technique
  • the active matrix flat panel display has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • Most of the flat display devices on the market are backlight type liquid crystal display devices, which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates, to control the liquid crystal molecules to change direction by turning on or off the glass substrate, and to refract light of the backlight module to produce a picture.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a TFT (Thin Film Transistor) substrate, a liquid crystal (LC, Liquid Crystal) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant), the molding process generally includes: front array (Array) process (film, yellow, etching and stripping), middle cell (cell) process (TFT substrate and CF substrate bonding) and rear module assembly Process (drive IC is pressed with printed circuit board).
  • Array array
  • LCD Thin Film Transistor
  • LC Liquid Crystal
  • the front Array process mainly forms a TFT substrate to control the movement of liquid crystal molecules; the middle Cell process mainly adds liquid crystal between the TFT substrate and the CF substrate; the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate, displaying images.
  • the thin film transistor substrate generally includes a glass substrate and a thin film transistor formed on the glass substrate, and the thin film transistor is formed on the glass substrate by a plurality of photomask processes.
  • FIG. 1A to FIG. 1E it is a process flow diagram of a thin film transistor in the prior art.
  • IGZO Indium Gallium Zinc Oxide
  • TFT oxide semiconductor transistor
  • a gate electrode (GE) 101 is first formed on the substrate 100; then a gate insulating layer (GI layer) 102 is covered on the gate electrode 101, and is gated.
  • GE gate electrode
  • GI layer gate insulating layer
  • An oxide semiconductor layer is formed on the insulating layer 102, specifically an IGZO (Indium Gallium Zinc Oxide) layer 103.
  • a first protective layer (ES layer) 104 an ES layer is formed on the IGZO layer 103.
  • ES layer Usually obtained by chemical vapor deposition (CVD) using a precursor material; then sputtering a metal layer to form a source 105 and a drain 106, the metal layer forming a source 105 and a drain 106, which is also connected as a wiring material to the IGZO layer 103.
  • CVD chemical vapor deposition
  • the prior art generally deposits metal on the IGZO layer 103, and separately forms a source electrode and a drain electrode by etching; and then on the source 105 and the drain 106.
  • the second protective layer (PV layer) 107 Covering the second protective layer (PV layer) 107, up to now, mainly formed by the gate electrode 101, the gate insulating layer 102, the IGZO layer 103, the first protective layer 104, the source 105, the drain 106, and the second protective layer A thin film transistor active device composed of 107 or the like. Summary of the invention
  • An object of the present invention is to provide a thin film transistor active device in which a low-N-H bond content in a gate insulating layer of a thin film transistor is effective, thereby effectively preventing electrical deterioration of a thin film transistor.
  • Another object of the present invention is to provide a method for fabricating a thin film transistor active device, which has a flow ratio of nitrous oxide to silicon tetrahydride of more than 30% by controlling a gate insulating layer forming a thin film transistor active device, so that the gate electrode
  • the active layer of the insulating layer is between 1.43 and 1.47, which effectively reduces the NH bond content in the gate insulating layer, thereby improving the product of the thin film transistor active device.
  • the present invention provides a thin film transistor active device, including And a plurality of thin film transistors formed on the substrate, the thin film transistor having a gate insulating layer and an oxide semiconductor active layer, wherein the gate insulating layer is a silicon oxide layer having a refractive index of between 1.43 and 1.47.
  • the thin film transistor further includes a gate electrode, and the gate insulating layer is formed on the gate electrode by chemical vapor deposition.
  • the flow ratio of nitrous oxide to silicon tetrahydride is more than 30%.
  • the active layer of the oxide semiconductor contains at least one of oxidized, tin oxide, indium oxide, and gallium oxide, which is formed on the gate insulating layer by sputtering.
  • the thin film transistor further includes a first protective layer formed on the active layer of the oxide semiconductor, which is formed on the oxide semiconductor layer by chemical vapor deposition.
  • the thin film transistor further includes a source and a drain formed on the first protective layer, the source and the drain are sputtered on the first protective layer by a metal to form a metal layer, and then formed by a photomask process,
  • the metal layer is one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof.
  • the thin film transistor further includes a second protective layer formed on the source and the drain, which are formed on the source and the drain by chemical vapor deposition.
  • the present invention also provides a thin film transistor active device, comprising: a substrate and a plurality of thin film transistors formed on the substrate, the thin film transistor having a gate insulating layer and an oxide semiconductor active layer, wherein the gate insulating layer is a silicon oxide layer , its refractive index is between 1.43 ⁇ 1.47;
  • the thin film transistor further includes a gate, and the gate insulating layer is formed on the gate by chemical vapor deposition;
  • the flow ratio of nitrous oxide to silicon tetrahydride is greater than 30%;
  • the active layer of the oxide semiconductor contains at least one of oxidized, tin oxide, indium oxide and gallium oxide, which is formed on the gate insulating layer by sputtering;
  • the thin film transistor further includes a first protective layer formed on the active layer of the oxide semiconductor, which is formed on the oxide semiconductor layer by chemical vapor deposition;
  • the thin film transistor further includes a source and a drain formed on the first protective layer, the source and the drain are sputtered on the first protective layer by a metal to form a metal layer, and then formed by a photomask process.
  • the metal layer is one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof;
  • the thin film transistor further includes a second protective layer formed on the source and the drain, which are formed on the source and the drain by chemical vapor deposition.
  • the invention also provides a method for fabricating a thin film transistor active device, comprising the following steps: Step 1. providing a substrate;
  • Step 2 forming a gate on the substrate by sputtering and a mask process
  • Step 3 forming a gate insulating layer by chemical vapor deposition on the gate, wherein a flow ratio of nitrous oxide to silicon hydride is more than 30% in chemical vapor deposition, and a refractive index of the gate insulating layer formed is 1.43 ⁇ Between 1.47;
  • Step 4 forming an oxide semiconductor active layer on the gate insulating layer by sputtering and a mask process
  • Step 5 forming a first protective layer on the active layer of the oxide semiconductor by chemical vapor deposition and a mask process
  • Step 6 forming a metal layer on the first protective layer by a sputtering process, and forming a source and a drain through a photomask process;
  • Step 7 forming a second protective layer on the metal layer, and forming a bridge hole on the second protective layer;
  • Step 8 Form a transparent conductive layer on the second protective layer by sputtering and a mask process, thereby preparing a thin film transistor active device.
  • the gate layer comprises one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof.
  • the active layer of the oxide semiconductor contains at least one of oxidized words, tin oxide, indium oxide, and gallium oxide.
  • the metal layer contains one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof.
  • the transparent conductive layer is composed of an indium tin oxide layer, an indium oxide layer, an aluminum oxide layer or an oxidation layer.
  • the present invention provides a thin film transistor active device and a method of fabricating the same, which control a flow ratio of nitrous oxide to silicon tetrahydride by more than 30% when controlling a chemical vapor deposition by forming a gate insulating layer of a thin film transistor. And further controlling the refractive index of the gate insulating layer formed of silicon oxide to be between 1.43 and 1.47; at the same time, reducing the NH bond content in the gate insulating layer, effectively avoiding the high content of NH bonds in the gate insulating layer The high interface trap density of the gate insulating layer and the oxide semiconductor layer effectively avoids the electrical deterioration of the oxide TFT, and further the quality of the thin film transistor active device.
  • FIG. 1A to FIG. 1E are flowcharts showing a process of a thin film transistor in the prior art
  • FIG. 2 is a schematic structural view of a thin film transistor active device of the present invention.
  • 3 is a graph showing the relationship between the ratio of nitrogen oxide to silicon tetrahydride flow rate and the ratio of nitrogen to silicon in the gate insulating layer formed by vapor deposition of the gate insulating layer;
  • FIG. 4 is a graph showing the relationship between the flow ratio of nitrous oxide to silicon tetrahydride and the refractive index of the formed gate insulating layer when vapor-deposited to form a gate insulating layer;
  • FIG. 5 is a flow chart of a method for fabricating a thin film transistor active device according to the present invention. detailed description
  • the present invention provides a thin film transistor active device, including: a substrate 20 and a plurality of thin film transistors 220 formed on the substrate, the thin film transistor 220 having a gate 221 and being formed on the gate 221
  • the gate insulating layer 222 is a silicon oxide layer formed on the gate electrode 221 by chemical vapor deposition.
  • the thin film transistor 220 further includes an oxide semiconductor active layer 223 formed on the gate insulating layer 222, the oxide semiconductor active layer 223 containing at least one of oxidized words, tin oxide, indium oxide, and gallium oxide. The shot is formed on the gate insulating layer 222. Referring to FIG. 3 and FIG.
  • the ratio of the nitrous oxide to the silicon tetrahydride flow has a great influence on the performance of the formed gate insulating layer, especially the gate insulating formed.
  • the content of the NH bond in the layer when the content of the NH bond is large, the interface trap density between the gate insulating layer and the active layer of the oxide semiconductor is large, which causes electrical deterioration of the formed thin film transistor. This in turn reduces the quality of the entire thin film transistor active device.
  • the refractive index of the gate insulating layer formed by chemical vapor deposition is between 1.43 and 1.47, and at this time, the NH of the gate insulating layer The bond content is relatively low, and the electrical degradation of the formed thin film transistor active device can be effectively avoided.
  • the flow ratio of nitrous oxide to silicon hydride is greater than 30%, and the refractive index of the gate insulating layer 222 formed is controlled to be 1.43 to 1.47. between.
  • the thin film transistor 220 further includes a first protective layer 224 formed on the active layer 223 of the oxide semiconductor, which is formed on the oxide semiconductor layer 223 by chemical vapor deposition.
  • the thin film transistor 220 further includes a source 225 and a drain 226 formed on the first protective layer 224.
  • the source 225 and the drain 226 are sputtered from the metal on the first protective layer 224 to form a metal layer, and then pass through the photomask. Process made.
  • the metal layer contains one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof.
  • the thin film transistor 220 further includes a second protective layer 227 formed on the source 225 and the drain 226, which is formed on the source 225 and the drain 226 by chemical vapor deposition.
  • the present invention also provides a method for fabricating a thin film transistor active device, which includes the following steps:
  • Step 1 Provide a substrate.
  • Step 2 Form a gate on the substrate by sputtering and a mask process.
  • the gate layer comprises one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof.
  • Step 3 forming a gate insulating layer by chemical vapor deposition on the gate, wherein a flow ratio of nitrous oxide to silicon hydride is more than 30% in chemical vapor deposition, and a refractive index of the gate insulating layer formed is 1.43 ⁇ Between 1.47.
  • Step 4 Form an oxide semiconductor active layer on the gate insulating layer by sputter deposition and a mask process.
  • the oxide semiconductor active layer contains at least one of oxidized, tin oxide, indium oxide, and gallium oxide.
  • Step 5 Forming a first protective layer on the oxide semiconductor layer by chemical vapor deposition and a photomask process.
  • Step 6 Form a metal layer on the first protective layer by a sputtering process, and form a source and a drain through a photomask process.
  • the metal layer contains one of a molybdenum layer, an aluminum layer, a titanium layer or a copper layer or a laminate thereof.
  • Step 7 Form a second protective layer on the metal layer and form a bridge hole on the second protective layer.
  • Step 8 Forming a transparent conductive layer on the second protective layer by sputtering deposition and a photomask process, thereby preparing a thin film transistor active device.
  • the transparent conductive layer contains one of an indium tin oxide layer, an indium oxide layer, an aluminum oxide layer or an oxidized gallium layer or a laminate thereof.
  • the present invention provides a thin film transistor active device and a method for fabricating the same, which, when forming a gate insulating layer of a thin film transistor, controls a flow ratio of nitrous oxide to silicon tetrahydride when chemical vapor deposition is greater than 30%, Further controlling the refractive index of the gate insulating layer formed of silicon oxide is between 1.43 and 1.47; at the same time, reducing the NH bond content in the gate insulating layer, effectively avoiding the high content of NH bonds in the gate insulating layer
  • the high interface trap density of the gate insulating layer and the oxide semiconductor layer effectively avoids electrical deterioration of the oxide TFT, and further improves the quality of the thin film transistor active device.

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Description

薄膜晶体管主动装置及其制作方法 技术领域
本发明涉及平面显示领域, 尤其涉及一种薄膜晶体管主动装置及其制 作方法。 背景技术
主动矩阵式平面显示器具有机身薄、 省电、 无辐射等众多优点, 得到 了广泛的应用。 现有市场上的平面显示装置大部分为背光型液晶显示装 置, 其包括液晶显示面板及背光模组 ( backlight module ) 。 液晶显示面板 的工作原理是在两片平行的玻璃基板当中放置液晶分子, 通过玻璃基板通 电与否来控制液晶分子改变方向, 将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜 (CF , Color Filter ) 基板、 薄膜晶体管 ( TFT, Thin Film Transistor)基板、 夹于彩膜基板与薄膜晶体管基板之间的 液晶 (LC , Liquid Crystal )及密封胶框 ( Sealant )组成, 其成型工艺一般 包括: 前段阵列 (Array ) 制程 (薄膜、 黄光、 蚀刻及剥膜) 、 中段成盒 ( Cell )制程(TFT基板与 CF基板贴合)及后段模组组装制程(驱动 IC 与印刷电路板压合) 。 其中, 前段 Array制程主要是形成 TFT基板, 以便 于控制液晶分子的运动; 中段 Cell制程主要是在 TFT基板与 CF基板之间 添加液晶; 后段模组组装制程主要是驱动 IC 压合与印刷电路板的整合, 进而驱动液晶分子转动, 显示图像。
所述薄膜晶体管基板一般包括玻璃基板及形成于玻璃基板上的薄膜晶 体管, 所述薄膜晶体管通过数次光罩制程形成于玻璃基板上。
参见图 1A 至图 1E , 其为现有技术中薄膜晶体管的制程流程图。 IGZO(Indium Gallium Zinc Oxide)为氧化铟镓辞的缩写, 它是一种氧化物半 导体晶体管 (TFT )技术, 是指在晶体管栅极绝缘层之上, 设置一层金属 氧化物主动层, 是一种基于 TFT驱动的技术。 按照图 1A至图 1E所示的 制程流程图, 首先在基板 100 上形成栅极电极 ( GE ) 101 ; 接下来在栅极 电极 101上覆盖栅极绝缘层(GI层) 102, 并在栅极绝缘层 102上形成一 层氧化物半导体层, 具体为 IGZO ( Indium Gallium Zinc Oxide , 铟镓辞氧 化物)层 103; 接下来在 IGZO层 103上形成第一保护层(ES层) 104, ES 层通常是使用前体物质进行化学气相沉积 (CVD ) 来获得; 然后溅射 金属层, 以形成源极 105 及漏极 106 , 该金属层除形成源极 105 及漏极 106, 还作为布线材料连接至 IGZO层 103 , 现有制程一般是将金属沉积于 IGZO 层 103 上, 并利用蚀刻分别形成源极电极和漏极电极; 接下来在源 极 105及漏极 106上覆盖第二保护层 (PV层) 107, 至此, 形成了主要由 栅极电极 101、 栅极绝缘层 102、 IGZO 层 103、 第一保护层 104、 源极 105、 漏极 106及第二保护层 107等组成的薄膜晶体管主动装置。 发明内容
本发明的目的在于提供一种薄膜晶体管主动装置, 薄膜晶体管的栅极 绝缘层中的 N-H键含量较低, 有效避免薄膜晶体管的电性劣化。
本发明的另一目的在于提供一种薄膜晶体管主动装置的制作方法, 其 通过控制形成薄膜晶体管主动装置的栅极绝缘层时的氧化二氮与四氢化硅 的流量比率大于 30%, 使得栅极绝缘层的折射率介于 1.43〜1.47 之间, 有 效降低栅极绝缘层中的 N-H键含量, 进而提升薄膜晶体管主动装置的品 、 为实现上述目的, 本发明提供一种薄膜晶体管主动装置, 包括: 基板 及形成于基板上的数个薄膜晶体管, 所述薄膜晶体管具有栅极绝缘层与氧 化物半导体主动层, 该栅极绝缘层为氧化硅层, 其折射率介于 1.43〜1.47 之间。
所述薄膜晶体管还包括栅极, 所述栅极绝缘层通过化学气相沉积形成 于栅极上。
所述栅极绝缘层化学气相沉积时, 其氧化二氮与四氢化硅的流量比率 大于 30%。
所述氧化物半导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化镓中至 少一种, 其通过溅射形成于栅极绝缘层上。
所述薄膜晶体管还包括形成于氧化物半导体主动层上的第一保护层, 其通过化学气相沉积形成于氧化物半导体层上。
所述薄膜晶体管还包括形成于第一保护层上的源极与漏极, 该源极与 漏极由金属溅射于第一保护层上形成金属层, 再通过光罩制程制成, 所述 金属层为钼层、 铝层、 钛层或铜层其中之一或其叠层。
所述薄膜晶体管还包括形成于源极与漏极上的第二保护层, 其通过化 学气相沉积形成于源极与漏极上。
本发明还提供一种薄膜晶体管主动装置, 包括: 基板及形成于基板上 的数个薄膜晶体管, 所述薄膜晶体管具有栅极绝缘层与氧化物半导体主动 层, 该栅极绝缘层为氧化硅层, 其折射率介于 1.43〜1.47之间; 其中, 所述薄膜晶体管还包括栅极, 所述栅极绝缘层通过化学气相沉 积形成于栅极上;
其中, 所述栅极绝缘层化学气相沉积时, 其氧化二氮与四氢化硅的流 量比率大于 30%;
其中, 所述氧化物半导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化 镓中至少一种, 其通过溅射形成于栅极绝缘层上;
其中, 所述薄膜晶体管还包括形成于氧化物半导体主动层上的第一保 护层, 其通过化学气相沉积形成于氧化物半导体层上;
其中, 所述薄膜晶体管还包括形成于第一保护层上的源极与漏极, 该 源极与漏极由金属溅射于第一保护层上形成金属层, 再通过光罩制程制 成, 所述金属层为钼层、 铝层、 钛层或铜层其中之一或其叠层;
其中, 所述薄膜晶体管还包括形成于源极与漏极上的第二保护层, 其 通过化学气相沉积形成于源极与漏极上。
本发明还提供一种薄膜晶体管主动装置的制作方法, 包括以下步骤: 步骤 1、 提供基板;
步骤 2、 在基板上通过溅射及光罩制程形成栅极;
步骤 3、 在栅极上通过化学气相沉积形成栅极绝缘层, 其化学气相沉 积时氧化二氮与四氢化硅的流量比率大于 30%, 且形成的栅极绝缘层的折 射率介于 1.43〜1.47之间;
步骤 4、 在栅极绝缘层上通过溅射及光罩制程形成氧化物半导体主动 层;
步骤 5、 在氧化物半导体主动层上通过化学气相沉积及光罩制程形成 第一保护层;
步骤 6、 在第一保护层上通过溅射制程形成金属层, 并通过光罩制程 形成源极与漏极;
步骤 7、 在金属层上形成第二保护层, 并在该第二保护层上形成桥接 孔;
步骤 8、 在第二保护层上通过溅射及光罩制程形成透明导电层, 进而 制得薄膜晶体管主动装置。
所述栅极含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
所述氧化物半导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化镓中至 少一种。
所述金属层含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
所述透明导电层含有为氧化铟锡层、 氧化铟辞层、 氧化铝辞层或氧化 辞镓层其中之一或其叠层。
本发明的有益效果: 本发明提供的薄膜晶体管主动装置及其制作方 法, 其通过在薄膜晶体管的栅极绝缘层形成时, 控制化学气相沉积时氧化 二氮与四氢化硅的流量比率大于 30%, 进而控制由氧化硅形成的栅极绝缘 层的折射率介于 1.43〜1.47之间; 同时, 降低栅极绝缘层中 N-H键含量, 有效避免由于栅极绝缘层中的高含量 N-H键所导致的栅极绝缘层与氧化物 半导体层的高界面陷阱密度, 有效避免氧化物 TFT的电性劣化, 进而薄膜 晶体管主动装置的品质。
为了能更进一步了解本发明的特征以及技术内容, 请参阅以下有关本 发明的详细说明与附图, 然而附图仅提供参考与说明用, 并非用来对本发 明加以限制。 附图说明
下面结合附图, 通过对本发明的具体实施方式详细描述, 将使本发明 的技术方案及其它有益效果显而易见。
附图中,
图 1A至图 1E为现有技术中薄膜晶体管的制程流程图;
图 2为本发明薄膜晶体管主动装置的结构示意图;
图 3 为气相沉积形成栅极绝缘层时氧化二氮与四氢化硅流量比与形成 的栅极绝缘层中氮与硅比例关系图;
图 4为气相沉积形成栅极绝缘层时氧化二氮与四氢化硅流量比与形成 的栅极绝缘层的折射率关系图;
图 5为本发明薄膜晶体管主动装置的制作方法的流程图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果, 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 2 至图 4, 本发明提供一种薄膜晶体管主动装置, 包括: 基 板 20及形成于基板上的数个薄膜晶体管 220, 所述薄膜晶体管 220具有栅 极 221及形成于栅极 221上的栅极绝缘层 222, 该栅极绝缘层 222为氧化 硅层, 其通过化学气相沉积形成于栅极 221上。 所述薄膜晶体管 220还包 括形成于栅极绝缘层 222上的氧化物半导体主动层 223 , 该氧化物半导体 主动层 223含有氧化辞、 氧化锡、 氧化铟及氧化镓中至少一种, 其通过溅 射形成于栅极绝缘层 222上。 请参阅图 3及图 4, 在化学气相沉积栅极绝缘层时, 氧化二氮与四氢 化硅流量比率对形成的栅极绝缘层的性能具有较大影响, 尤为突出的为形 成的栅极绝缘层中的 N-H键含量, 当该 N-H键含量较大时, 栅极绝缘层 与氧化物半导体主动层之间的界面陷阱密度就会很大, 这就造成所形成的 薄膜晶体管的电性劣化, 进而降低了整个薄膜晶体管主动装置的质量。
由图 3可知, 当氧化二氮与四氢化硅的流量比率大于 30%时, 有利于 使化学气相沉积形成的栅极绝缘层中氮与硅的比例小于 0.1 , 进而降低栅 极绝缘层中 N-H键含量, 能有效避免所形成的薄膜晶体管主动装置的电性 劣化。
由图 4可知, 当氧化二氮与四氢化硅的流量比率大于 30%时, 化学气 相沉积形成的栅极绝缘层的折射率介于 1.43〜1.47 之间, 而这时栅极绝缘 层中 N-H键含量相对较低, 能有效避免所形成的薄膜晶体管主动装置的电 性劣化。
所以在本发明中, 化学气相沉积形成栅极绝缘层 222 时, 其氧化二氮 与四氢化硅的流量比率大于 30%, 且控制所形成的栅极绝缘层 222的折射 率介于 1.43〜1.47之间。
所述薄膜晶体管 220还包括形成于氧化物半导体主动层 223上的第一 保护层 224, 其通过化学气相沉积形成于氧化物半导体层 223上。
所述薄膜晶体管 220还包括形成于第一保护层 224的源极 225与漏极 226, 该源极 225 与漏极 226 由金属溅射于第一保护层 224 上形成金属 层, 再通过光罩制程制成。
所述金属层含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
所述薄膜晶体管 220还包括形成于源极 225与漏极 226上的第二保护 层 227 , 其通过化学气相沉积形成于源极 225与漏极 226上。
请参阅图 5 , 本发明还提供一种薄膜晶体管主动装置的制作方法, 包 括以下步骤:
步骤 1、 提供基板。
步骤 2、 在基板上通过溅射及光罩制程形成栅极。
所述栅极含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
步骤 3、 在栅极上通过化学气相沉积形成栅极绝缘层, 其化学气相沉 积时氧化二氮与四氢化硅的流量比率大于 30%, 且形成的栅极绝缘层的折 射率介于 1.43〜1.47之间。
步骤 4、 在栅极绝缘层上通过溅射沉积及光罩制程形成氧化物半导体 主动层。 所述氧化物半导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化镓中至 少一种。
步骤 5、 在氧化物半导体层上通过化学气相沉积及光罩制程形成第一 保护层。
步骤 6、 在第一保护层上通过溅射制程形成金属层, 并通过光罩制程 形成源极与漏极。
所述金属层含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
步骤 7、 在金属层上形成第二保护层, 并在该第二保护层上形成桥接 孔。
步骤 8、 在第二保护层上通过溅射沉积及光罩制程形成透明导电层, 进而制得薄膜晶体管主动装置。
所述透明导电层含有为氧化铟锡层、 氧化铟辞层、 氧化铝辞层或氧化 辞镓层其中之一或其叠层。
综上所述, 本发明提供的薄膜晶体管主动装置及其制作方法, 其通过 在薄膜晶体管的栅极绝缘层形成时, 控制化学气相沉积时氧化二氮与四氢 化硅的流量比率大于 30%, 进而控制由氧化硅形成的栅极绝缘层的折射率 介于 1.43〜1.47之间; 同时, 降低栅极绝缘层中 N-H键含量, 有效避免由 于栅极绝缘层中的高含量 N-H键所导致的栅极绝缘层与氧化物半导体层的 高界面陷阱密度, 有效避免氧化物 TFT的电性劣化, 进而薄膜晶体管主动 装置的品质。
以上所述, 对于本领域的普通技术人员来说, 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形, 而所有这些改变和变形 都应属于本发明权利要求的保护范围。

Claims

权 利 要 求
1、 一种薄膜晶体管主动装置, 包括: 基板及形成于基板上的数个薄 膜晶体管, 所述薄膜晶体管具有栅极绝缘层与氧化物半导体主动层, 该栅 极绝缘层为氧化硅层, 其折射率介于 1.43〜1.47之间。
2、 如权利要求 1 所述的薄膜晶体管主动装置, 其中, 所述薄膜晶体 管还包括栅极, 所述栅极绝缘层通过化学气相沉积形成于栅极上。
3、 如权利要求 2 所述的薄膜晶体管主动装置, 其中, 所述栅极绝缘 层化学气相沉积时, 其氧化二氮与四氢化硅的流量比率大于 30%。
4、 如权利要求 1 所述的薄膜晶体管主动装置, 其中, 所述氧化物半 导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化镓中至少一种, 其通过溅 射形成于栅极绝缘层上。
5、 如权利要求 1 所述的薄膜晶体管主动装置, 其中, 所述薄膜晶体 管还包括形成于氧化物半导体主动层上的第一保护层, 其通过化学气相沉 积形成于氧化物半导体层上。
6、 如权利要求 1 所述的薄膜晶体管主动装置, 其中, 所述薄膜晶体 管还包括形成于第一保护层上的源极与漏极, 该源极与漏极由金属溅射于 第一保护层上形成金属层, 再通过光罩制程制成, 所述金属层为钼层、 铝 层、 钛层或铜层其中之一或其叠层。
7、 如权利要求 1 所述的薄膜晶体管主动装置, 其中, 所述薄膜晶体 管还包括形成于源极与漏极上的第二保护层, 其通过化学气相沉积形成于 源极与漏极上。
8、 一种薄膜晶体管主动装置, 包括: 基板及形成于基板上的数个薄 膜晶体管, 所述薄膜晶体管具有栅极绝缘层与氧化物半导体主动层, 该栅 极绝缘层为氧化硅层, 其折射率介于 1.43〜1.47之间;
其中, 所述薄膜晶体管还包括栅极, 所述栅极绝缘层通过化学气相沉 积形成于栅极上;
其中, 所述栅极绝缘层化学气相沉积时, 其氧化二氮与四氢化硅的流 量比率大于 30%;
其中, 所述氧化物半导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化 镓中至少一种, 其通过溅射形成于栅极绝缘层上;
其中, 所述薄膜晶体管还包括形成于氧化物半导体主动层上的第一保 护层, 其通过化学气相沉积形成于氧化物半导体层上; 其中, 所述薄膜晶体管还包括形成于第一保护层上的源极与漏极, 该 源极与漏极由金属溅射于第一保护层上形成金属层, 再通过光罩制程制 成, 所述金属层为钼层、 铝层、 钛层或铜层其中之一或其叠层;
其中, 所述薄膜晶体管还包括形成于源极与漏极上的第二保护层, 其 通过化学气相沉积形成于源极与漏极上。
9、 一种薄膜晶体管主动装置的制作方法, 包括以下步骤:
步骤 1、 提供基板;
步骤 2、 在基板上通过溅射及光罩制程形成栅极;
步骤 3、 在栅极上通过化学气相沉积形成栅极绝缘层, 其化学气相沉 积时氧化二氮与四氢化硅的流量比率大于 30%, 且形成的栅极绝缘层的折 射率介于 1.43〜1.47之间;
步骤 4、 在栅极绝缘层上通过溅射及光罩制程形成氧化物半导体主动 层;
步骤 5、 在氧化物半导体主动层上通过化学气相沉积及光罩制程形成 第一保护层;
步骤 6、 在第一保护层上通过溅射制程形成金属层, 并通过光罩制程 形成源极与漏极;
步骤 7、 在金属层上形成第二保护层, 并在该第二保护层上形成桥接 孔;
步骤 8、 在第二保护层上通过溅射及光罩制程形成透明导电层, 进而 制得薄膜晶体管主动装置。
10、 如权利要求 9所述的薄膜晶体管主动装置的制作方法, 其中, 所 述栅极含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
11、 如权利要求 9所述的薄膜晶体管主动装置的制作方法, 其中, 所 述氧化物半导体主动层含有氧化辞、 氧化锡、 氧化铟及氧化镓中至少一 种。
12、 如权利要求 9所述的薄膜晶体管主动装置的制作方法, 其中, 所 述金属层含有钼层、 铝层、 钛层或铜层其中之一或其叠层。
13、 如权利要求 9所述的薄膜晶体管主动装置的制作方法, 其中, 所 述透明导电层含有为氧化铟锡层、 氧化铟辞层、 氧化铝辞层或氧化辞镓层 其中之一或其叠层。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI486563B (zh) * 2012-08-16 2015-06-01 E Ink Holdings Inc 光感測器及其光電晶體的驅動方法
CN103236441B (zh) * 2013-04-22 2015-11-25 深圳市华星光电技术有限公司 开关管及其制备方法、显示面板
CN105845690A (zh) * 2015-01-14 2016-08-10 南京瀚宇彩欣科技有限责任公司 半导体装置及其制造方法
CN119653860B (zh) * 2024-11-19 2025-09-26 武汉华星光电技术有限公司 阵列基板和显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1599056A (zh) * 2003-09-19 2005-03-23 株式会社半导体能源研究所 发光器件及其制造方法
CN1794889A (zh) * 2005-11-03 2006-06-28 友达光电股份有限公司 低温多晶硅薄膜晶体管显示面板及其制造方法
US20120032263A1 (en) * 2009-04-03 2012-02-09 Sharp Kabushiki Kaisha Semiconductor device and method of producing same
CN102664194A (zh) * 2012-04-10 2012-09-12 深超光电(深圳)有限公司 薄膜晶体管

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0608633B1 (en) * 1993-01-28 1999-03-03 Applied Materials, Inc. Method for multilayer CVD processing in a single chamber
JP3818561B2 (ja) * 1998-10-29 2006-09-06 エルジー フィリップス エルシーディー カンパニー リミテッド シリコン酸化膜の成膜方法および薄膜トランジスタの製造方法
JP2002208592A (ja) * 2001-01-09 2002-07-26 Sharp Corp 絶縁膜の形成方法、半導体装置、製造装置
US6902960B2 (en) * 2002-11-14 2005-06-07 Sharp Laboratories Of America, Inc. Oxide interface and a method for fabricating oxide thin films
JP4485184B2 (ja) * 2003-12-15 2010-06-16 株式会社半導体エネルギー研究所 発光装置および電子機器
US7792489B2 (en) * 2003-12-26 2010-09-07 Semiconductor Energy Laboratory Co., Ltd. Light emitting device, electronic appliance, and method for manufacturing light emitting device
US7521368B2 (en) * 2004-05-07 2009-04-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7221039B2 (en) * 2004-06-24 2007-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer
WO2009018509A1 (en) * 2007-08-02 2009-02-05 Applied Materials, Inc. Thin film transistors using thin film semiconductor materials
JP2011040647A (ja) * 2009-08-17 2011-02-24 Hitachi Ltd 固体撮像素子
KR101460869B1 (ko) * 2009-09-04 2014-11-11 가부시끼가이샤 도시바 박막 트랜지스터 및 그 제조 방법
US9715845B2 (en) * 2009-09-16 2017-07-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device
KR20120094013A (ko) * 2009-11-13 2012-08-23 가부시키가이샤 한도오따이 에네루기 켄큐쇼 스퍼터링 타겟 및 그 제조방법, 및 트랜지스터
KR20120099450A (ko) * 2009-11-27 2012-09-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
KR102089200B1 (ko) * 2009-11-28 2020-03-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제조 방법
KR102719739B1 (ko) * 2009-12-04 2024-10-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN102754022B (zh) * 2010-02-26 2016-11-09 株式会社半导体能源研究所 液晶显示装置
CN103210494B (zh) * 2010-11-10 2016-01-06 夏普株式会社 显示装置用基板及其制造方法、显示装置
JP2012119664A (ja) * 2010-11-12 2012-06-21 Kobe Steel Ltd 配線構造
US9064962B2 (en) * 2010-12-09 2015-06-23 Sharp Kabushiki Kaisha Thin film transistor array substrate
JP5766467B2 (ja) * 2011-03-02 2015-08-19 株式会社東芝 薄膜トランジスタ及びその製造方法、表示装置
WO2013021632A1 (ja) * 2011-08-11 2013-02-14 出光興産株式会社 薄膜トランジスタ
WO2013069045A1 (ja) * 2011-11-07 2013-05-16 パナソニック株式会社 薄膜トランジスタ装置の製造方法、薄膜トランジスタ装置および表示装置
CN102646595A (zh) * 2011-11-11 2012-08-22 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、显示器件
CN103493186A (zh) * 2011-11-29 2014-01-01 松下电器产业株式会社 薄膜晶体管阵列的制造方法、薄膜晶体管阵列及显示装置
CN102683422B (zh) * 2012-03-21 2016-03-23 京东方科技集团股份有限公司 氧化物薄膜晶体管及制作方法、阵列基板、显示装置
CN102800709B (zh) * 2012-09-11 2015-07-01 深圳市华星光电技术有限公司 薄膜晶体管主动装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1599056A (zh) * 2003-09-19 2005-03-23 株式会社半导体能源研究所 发光器件及其制造方法
CN1794889A (zh) * 2005-11-03 2006-06-28 友达光电股份有限公司 低温多晶硅薄膜晶体管显示面板及其制造方法
US20120032263A1 (en) * 2009-04-03 2012-02-09 Sharp Kabushiki Kaisha Semiconductor device and method of producing same
CN102664194A (zh) * 2012-04-10 2012-09-12 深超光电(深圳)有限公司 薄膜晶体管

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