WO2014030309A1 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
WO2014030309A1
WO2014030309A1 PCT/JP2013/004722 JP2013004722W WO2014030309A1 WO 2014030309 A1 WO2014030309 A1 WO 2014030309A1 JP 2013004722 W JP2013004722 W JP 2013004722W WO 2014030309 A1 WO2014030309 A1 WO 2014030309A1
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WO
WIPO (PCT)
Prior art keywords
base layer
wiring board
layer
insulating layer
wall surface
Prior art date
Application number
PCT/JP2013/004722
Other languages
English (en)
French (fr)
Inventor
智弘 西田
聖二 森
若園　誠
Original Assignee
日本特殊陶業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本特殊陶業株式会社 filed Critical 日本特殊陶業株式会社
Priority to EP13831747.4A priority Critical patent/EP2750172A4/en
Priority to KR1020147010585A priority patent/KR101603453B1/ko
Priority to JP2013554712A priority patent/JP5523641B1/ja
Priority to US14/352,299 priority patent/US20140284081A1/en
Priority to CN201380003704.8A priority patent/CN103907180B/zh
Priority to TW102129936A priority patent/TW201419949A/zh
Publication of WO2014030309A1 publication Critical patent/WO2014030309A1/ja

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    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0594—Insulating resist or coating with special shaped edges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Definitions

  • the present invention relates to a wiring board.
  • a wiring board that is configured so that a semiconductor chip can be mounted is known (see, for example, Patent Documents 1 and 2).
  • connection terminals configured to be connectable to the semiconductor chip are formed.
  • Patent Document 1 in order to prevent an electrical short circuit between connection terminals due to a plating material, an insulating layer having an opening exposing a plurality of connection terminals is formed, and insulation is performed between the plurality of connection terminals in the openings. It is described that a plurality of connection terminals are plated after an object is formed.
  • Patent Document 2 describes that in order to prevent an electrical short circuit between connection terminals due to solder, the insulating layer formed between the connection terminals is thinned to be equal to or less than the thickness of the connection terminals.
  • connection terminal of the wiring board is soldered to the semiconductor chip, and a liquid curable property called underfill is formed in the gap between the wiring board and the semiconductor chip around the connection terminal.
  • the resin is filled (see, for example, Patent Document 3).
  • the present invention has been made to solve the above-described problems, and can be realized as the following modes.
  • a wiring board includes an insulating base layer; an insulating layer stacked on the base layer, a first surface on which an opening is formed, and the base layer side with respect to the first surface inside the opening.
  • An insulating layer having an indented second surface and a wall surface connecting the first surface and the second surface along a stacking direction of the insulating layer with respect to the base layer inside the opening; 2 is a wiring board including a conductive connection terminal exposed from the surface, wherein the second surface has a deepest portion located closest to the base layer on the second surface, and is convex to the base layer side.
  • the curved shape of the second surface improves the flowability of the underfill, and the space on the second surface on the wall surface side from the deepest portion becomes narrower toward the wall surface. The formation of voids in the region from the second surface to the wall surface can be suppressed.
  • the deepest portion may include a connection portion connected to the connection terminal in the second surface. According to the wiring board of this embodiment, the flowability of the underfill can be further improved as compared with the case where the deepest part is away from the connection terminal.
  • the insulating layer may further include a curved surface that curves and connects the first surface and the wall surface outwardly. According to the wiring board of this embodiment, it is possible to improve the pouring property of the underfill onto the second surface as compared with the case where the space between the first surface and the wall surface is angular.
  • the surface roughness of the second surface may be rougher than that of the first surface.
  • the underfill can be spread to each part on the second surface using the capillary phenomenon without hindering the flowability of the underfill.
  • the present invention can be realized in various forms other than the wiring board.
  • it is realizable with forms, such as an apparatus provided with a wiring board, and a manufacturing method of a wiring board.
  • FIG. 1 is a partial cross-sectional view schematically showing the configuration of the wiring board 10 in the first embodiment.
  • the wiring substrate 10 is a plate-like member that is formed using an organic material and is also called an organic substrate (organic substrate).
  • the wiring substrate 10 is a flip chip mounting substrate configured to be capable of mounting a semiconductor chip (not shown).
  • the wiring board 10 includes a base layer 120, a conductor layer 130, and an insulating layer 140.
  • the wiring substrate 10 is formed by forming a conductor layer 130 on a base layer 120 and further forming an insulating layer 140 thereon.
  • the wiring board 10 may have a multilayer structure in which a plurality of conductor layers and a plurality of insulating layers are alternately stacked on the base layer 120, and such a multilayer structure is provided on both surfaces of the base layer 120. You may have each.
  • FIG. 1 shows XYZ axes orthogonal to each other.
  • the axis along the stacking direction of the insulating layer 140 with respect to the base layer 120 is taken as the Z axis.
  • the + Z-axis direction from the base layer 120 toward the insulating layer 140 is defined as the ⁇ Z-axis direction.
  • two axes along the layer surface direction orthogonal to the Z axis are defined as an X axis and a Y axis.
  • the + X-axis direction is from the left side to the right side, and the opposite direction to the + X-axis direction is the ⁇ X-axis direction.
  • the + Y-axis direction is from the front of the paper to the back of the paper, and the opposite direction of the + Y-axis is the ⁇ Y-axis direction.
  • the base layer 120 of the wiring board 10 is a plate-like member made of an insulating material.
  • the insulating material of the base layer 120 is a thermosetting resin, such as a bismaleimide-triazine resin (BT) or an epoxy resin.
  • the insulating material of the base layer 120 may be a fiber reinforced resin (eg, a glass fiber reinforced epoxy resin).
  • a through hole, a through hole conductor, or the like may be formed inside the base layer 120 to constitute part of the wiring connected to the conductor layer 130.
  • the conductor layer 130 of the wiring board 10 is a conductor pattern made of a conductive material formed on the base layer 120.
  • the conductor layer 130 is formed by etching a copper plating layer formed on the surface of the base layer 120 into a desired shape.
  • the conductor layer 130 includes connection terminals 132 and internal wiring 136.
  • the connection terminal 132 of the conductor layer 130 is a conductor pattern exposed from the insulating layer 140, and is configured to be connectable to a semiconductor chip (not shown).
  • the internal wiring 136 of the conductor layer 130 is a conductor pattern covered with the insulating layer 140.
  • the insulating layer 140 of the wiring board 10 is a layer made of an insulating material also called a solder resist.
  • the insulating layer 140 has a first surface 141, a second surface 142, and a wall surface 148.
  • the first surface 141 of the insulating layer 140 is the surface of the insulating layer 140 in which the opening 150 is formed.
  • the first surface 141 is a surface facing the + Z-axis direction side along the X-axis and the Y-axis, and constitutes the surface of the insulating layer 140 on the + Z-axis direction side.
  • the second surface 142 of the insulating layer 140 is the surface of the insulating layer 140 that is recessed toward the base layer 120 with respect to the first surface 141 inside the opening 150.
  • the connection terminal 132 of the conductor layer 130 is exposed from the second surface 142, and in the present embodiment, the connection terminal 132 protrudes from the second surface 142 in the + Z-axis direction side.
  • the second surface 142 is a surface that curves convexly toward the base layer 120 side (the ⁇ Z-axis direction side) and connects the wall surface 148 and the connection terminal 132, and the insulating layer 140 is formed inside the opening 150.
  • the surface on the + Z-axis direction side is configured.
  • the second surface 142 has a deepest portion DP located closest to the base layer 120 ( ⁇ Z axis direction side) on the second surface 142.
  • the relation of L1> L2 is satisfied.
  • a corner 145 where the second surface 142 and the wall surface 148 are connected is a base point having a length L1.
  • the connection portion 143 connected to the connection terminal 132 in the second surface 142 is a base point having a length L2.
  • the surface roughness of the second surface 142 is rougher than that of the first surface 141.
  • the center line average roughness Ra of the second surface 142 is 0.06 to 0.8 ⁇ m (micrometer), and the ten-point average roughness Rz of the second surface 142 is 1.0 to 9. 0.0 ⁇ m.
  • the center line average roughness Ra of the first surface 141 is 0.02 to 0.25 ⁇ m, and the ten-point average roughness Rz of the first surface 141 is 0.6 to 5.0 ⁇ m.
  • the wall surface 148 of the insulating layer 140 is a surface connecting the first surface 141 and the second surface 142 along the stacking direction (Z-axis direction) inside the opening 150.
  • the wall surface 148 is connected to the first surface 141 in an angular shape as shown in FIG.
  • the insulating layer 140 is formed by applying a photocurable insulating resin on the base layer 120 on which the conductor layer 130 is formed, and then exposing and developing.
  • the opening 150 in the insulating layer 140 corresponds to a masked portion at the time of exposure, and the uncured portion is washed away at the time of development, whereby the second surface 142 and the wall surface 148 in the insulating layer 140 are formed.
  • the first surface 141, the second surface 142, and the wall surface 148 of the insulating layer 140 are integrally formed as a portion constituting a single layer.
  • the shape of the second surface 142 and the wall surface 148 adjusts the material of the photocurable insulating resin, the shape of the mask at the time of exposure, the intensity of irradiation light at the time of exposure, the irradiation time, the irradiation angle, and the like. It is realized by doing.
  • connection terminal 132 is illustrated between the wall surface 148 on the + X axis direction side and the wall surface 148 on the ⁇ X axis direction side, but in another embodiment, the wall surface 148 on the + X axis direction side and the ⁇ Two or more connection terminals 132 may be provided between the wall surface 148 on the X-axis direction side.
  • connection terminal 132 and the insulating layer 140 may be configured in the Y-axis direction as in the X-axis direction.
  • the flow of the underfill is improved by the curved shape of the second surface 142 that satisfies L1> L2, and the second surface 142 on the wall surface 148 side of the deepest portion DP is improved. Since the space becomes narrower toward the wall surface 148, formation of voids at the corners 145 from the second surface 142 to the wall surface 148 can be suppressed. Further, since the surface roughness of the second surface 142 is rougher than that of the first surface 141, the underfill is spread to each part on the second surface 142 by utilizing capillary action without hindering the flowability of the underfill. Can be made.
  • FIG. 2 is a partial cross-sectional view schematically showing the configuration of the wiring board 10b in the second embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.
  • the wiring board 10b of the second embodiment is the same as that of the first embodiment except that the shape of the second surface 142 is different.
  • the deepest portion DP of the second surface 142 is located between the connection portion 143 and the corner portion 145, but in the second embodiment, the deepest portion DP of the second surface 142 is the second surface.
  • 142 is located in the connection part 143 connected to the connection terminal 132. That is, the deepest part DP includes the connection part 143.
  • FIG. 3 is a partial cross-sectional view schematically showing the configuration of the wiring board 10c in the third embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.
  • the wiring board 10c of the third embodiment is the same as that of the first embodiment except that the shape of the second surface 142 is different.
  • the deepest portion DP of the second surface 142 is the first point located closest to the base layer 120 ( ⁇ Z axis direction side) on the second surface 142 in the middle from the wall surface 148 to the connection portion 143. .
  • the second surface 142 protrudes in the + Z-axis direction from the deepest portion DP toward the connection portion 143.
  • the second surface 142 is connected from the deepest portion DP. It has a shape parallel to the X axis toward the portion 143.
  • the relationship between the length L1 and the length L2 satisfies L1> L2, as in the first embodiment.
  • FIG. 4 is a partial cross-sectional view schematically showing the configuration of the wiring board 10d in the fourth embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.
  • the wiring board 10d of the fourth embodiment is the same as that of the first embodiment except that the wiring board 10d has a curved surface 149 that curves and connects the first surface 141 and the wall surface 148 outwardly.
  • the shape of the curved surface 149 is the same as that of the second surface 142 and the wall surface 148, the material of the photocurable insulating resin, the shape of the mask at the time of exposure, the intensity of irradiation light at the time of exposure, and the irradiation This is realized by adjusting time and irradiation angle.
  • the fourth embodiment described above it is possible to suppress the formation of voids in the corners 145 extending from the second surface 142 to the wall surface 148, as in the first embodiment.
  • the curved surface 149 is formed between the first surface 141 and the wall surface 148, compared with the case where the space between the first surface 141 and the wall surface 148 is angular as in the first embodiment, The pouring property of the underfill onto the second surface 142 can be improved.
  • the curved surface 149 of the fourth embodiment may be applied to the wiring board 10b of the second embodiment and the wiring board 10c of the third embodiment.
  • FIG. 5 is a partial cross-sectional view schematically showing the configuration of the wiring board 10e in the fifth embodiment.
  • the same components as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.
  • the wiring board 10e of the fifth embodiment is the same as that of the first embodiment except that the + Z-axis direction side of the wall surface 148 is inclined toward the outer peripheral side of the opening 150.
  • the shape of the wall surface 148 in the fifth embodiment adjusts the material of the photocurable insulating resin, the shape of the mask at the time of exposure, the intensity of irradiation light at the time of exposure, the irradiation time, the irradiation angle, and the like. It is realized by doing.
  • the space between the first surface 141 and the wall surface 148 is angular, but in other embodiments, the curved surface 149 is interposed between the first surface 141 and the wall surface 148 as in the fourth embodiment. May be formed.
  • the shape of the second surface 142 is the same as that of the first embodiment, but in other embodiments, it may be the same as that of the second embodiment or the same as that of the third embodiment. May be.
  • the fifth embodiment described above it is possible to suppress the formation of voids in the corners 145 extending from the second surface 142 to the wall surface 148, as in the first embodiment. Further, since the + Z-axis direction side of the wall surface 148 is inclined toward the outer peripheral side of the opening 150, the underfill flowability can be further improved.
  • the second surface 142 and the wall surface 148 of the insulating layer 140 may be formed through the following steps.
  • Step 1. A photocurable insulating resin, which is a material of the insulating layer 140, is applied or laminated on the base layer 120 on which the conductor layer 130 is formed. 2. After performing step 1, pattern exposure step for photocurable insulating resin on base layer 120; 3. After performing step 2, the uncured portion of the photocurable insulating resin on the base layer 120 is removed by a development process using an alkaline aqueous solution so that the connection terminal 132 is exposed from the insulating layer 140.
  • the insulating layer 140 is cured by heating (thermal curing) and the insulating layer 140 is cured by ultraviolet rays (photocuring).
  • the integrated light quantity in the photocuring of step 4 is 500 mJ / cm 2 (mm cm) is preferably at least 2,500 mJ / cm 2 or less per Joule, more preferably 1000 mJ / cm 2 or more 2000 mJ / cm 2 or less.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

　配線基板は、絶縁性の基層と、基層に積層された絶縁層と、導電性の接続端子とを備える。絶縁層は、開口部が形成された第１表面と、記開口部の内側において第１表面に対し基層側に窪んだ第２表面と、開口部の内側において基層に対する絶縁層の積層方向に沿って第１表面と第２表面との間を繋ぐ壁面とを有する。接続端子は、第２表面から露出する。第２表面は、第２表面において最も基層側に位置する最深部を有し、基層側に凸状に湾曲して壁面と接続端子との間を繋ぐ。積層方向に直交する層面方向に沿った壁面と最深部との間の長さＬ１と、層面方向に沿った最深部と接続端子との間の長さＬ２との関係は、Ｌ１＞Ｌ２を満たす。

Description

配線基板
　本発明は、配線基板に関する。
　配線基板には、半導体チップを実装可能に構成されたものが知られている（例えば、特許文献１，２を参照）。このような配線基板には、半導体チップと接続可能に構成された接続端子が形成されている。
　特許文献１には、メッキ材料による接続端子間の電気的な短絡を防止するために、複数の接続端子を露出させる開口を有する絶縁層を形成し、その開口における複数の接続端子の間に絶縁物を形成した後、複数の接続端子にメッキを施すことが記載されている。特許文献２には、ハンダによる接続端子間の電気的な短絡を防止するために、接続端子間に形成した絶縁層を接続端子の厚み以下になるまで薄くすることが記載されている。
　配線基板に対する半導体チップの実装時には、配線基板の接続端子は、半導体チップに対してハンダ付けされると共に、接続端子の周囲における配線基板と半導体チップとの隙間には、アンダーフィルとも呼ばれる液状硬化性樹脂が充填される（例えば、特許文献３を参照）。
特開２００７－１０３６４８号公報 特開２０１１－１９２６９２号公報 特開２０１０－１５３４９５号公報
　特許文献１，２の配線基板では、メッキやハンダによる接続端子間の短絡防止について考慮されているが、接続端子の周囲に対するアンダーフィルの充填について十分に考慮されておらず、アンダーフィルの流れが阻害され、アンダーフィルの充填不良によるボイド（空洞）が形成されてしまう可能性があった。
　特許文献３の配線基板においても、配線基板と半導体チップとの隙間に吸い込まれた後のアンダーフィルの流れについて十分に考慮されておらず、アンダーフィルの充填不良によるボイドが形成されてしまう可能性があった。
　本発明は、上述の課題を解決するためになされたものであり、以下の形態として実現することが可能である。
（１）本発明の一形態によれば、配線基板が提供される。この配線基板は、絶縁性の基層と；前記基層に積層された絶縁層であって、開口部が形成された第１表面と、前記開口部の内側において前記第１表面に対して前記基層側に窪んだ第２表面と、前記開口部の内側において前記基層に対する前記絶縁層の積層方向に沿って前記第１表面と前記第２表面との間を繋ぐ壁面とを有する絶縁層と；前記第２表面から露出した導電性の接続端子とを備える配線基板であって、前記第２表面は、前記第２表面において最も前記基層側に位置する最深部を有し、前記基層側に凸状に湾曲して前記壁面と前記接続端子との間を繋ぐ面であり、前記積層方向に直交する層面方向に沿った前記壁面と前記最深部との間の長さＬ１と、前記層面方向に沿った前記最深部と前記接続端子との間の長さＬ２との関係は、Ｌ１＞Ｌ２を満たす。この形態の配線基板によれば、第２表面の湾曲した形状によってアンダーフィルの流れ性を向上させつつ、最深部よりも壁面側における第２表面上の空間が壁面に向かうに連れて狭くなるため、第２表面から壁面に至る領域におけるボイドの形成を抑制することができる。
（２）上記形態の配線基板において、前記最深部は、前記第２表面のうち前記接続端子と接続する接続部を含むとしてもよい。この形態の配線基板によれば、最深部が接続端子から離れている場合と比較して、アンダーフィルの流れ性を更に向上させることができる。
（３）上記形態の配線基板において、前記絶縁層は、更に、前記第１表面と前記壁面との間を外側に凸状に湾曲して繋ぐ湾曲面を有するとしてもよい。この形態の配線基板によれば、第１表面と壁面との間が角張っている場合と比較して、第２表面上に対するアンダーフィルの流し込み性を向上させることができる。
（４）上記形態の配線基板において、前記第２表面の表面粗さは、前記第１表面よりも粗いとしてもよい。この形態の配線基板によれば、アンダーフィルの流れ性を阻害することなく、毛細管現象を利用してアンダーフィルを第２表面上の各部に行き渡らせることができる。
　本発明は、配線基板以外の種々の形態で実現することも可能である。例えば、配線基板を備える装置、配線基板の製造方法などの形態で実現することができる。
第１実施形態における配線基板の構成を模式的に示す部分断面図である。 第２実施形態における配線基板の構成を模式的に示す部分断面図である。 第３実施形態における配線基板の構成を模式的に示す部分断面図である。 第４実施形態における配線基板の構成を模式的に示す部分断面図である。 第５実施形態における配線基板の構成を模式的に示す部分断面図である。
Ａ．第１実施形態：
　図１は、第１実施形態における配線基板１０の構成を模式的に示す部分断面図である。配線基板１０は、有機材料を用いて形成され、有機基板（オーガニック基板）とも呼ばれる板状の部材である。配線基板１０は、半導体チップ（図示しない）を実装可能に構成されたフリップチップ実装基板である。
　配線基板１０は、基層１２０と、導体層１３０と、絶縁層１４０とを備える。本実施形態では、配線基板１０は、基層１２０上に導体層１３０を形成した後、その上に更に絶縁層１４０を形成してなる。他の実施形態では、配線基板１０は、基層１２０上に複数の導体層と複数の絶縁層とを交互に積層した多層構造を有するとしてもよいし、このような多層構造を基層１２０の両面にそれぞれ有するとしてもよい。
　図１には、相互に直交するＸＹＺ軸を図示した。図１のＸＹＺ軸のうち、基層１２０に対する絶縁層１４０の積層方向に沿った軸をＺ軸とする。Ｚ軸に沿ったＺ軸方向のうち、基層１２０から絶縁層１４０に向かって＋Ｚ軸方向とし、＋Ｚ軸方向の反対方向を－Ｚ軸方向とする。図１のＸＹＺ軸のうち、Ｚ軸に直交する層面方向に沿った２つの軸をＸ軸およびＹ軸とする。図１の説明では、Ｘ軸に沿ったＸ軸方向のうち、紙面左から紙面右に向かって＋Ｘ軸方向とし、＋Ｘ軸方向の反対方向を－Ｘ軸方向とする。図１の説明では、Ｙ軸に沿ったＹ軸方向のうち、紙面手前から紙面奥に向かって＋Ｙ軸方向とし、＋Ｙ軸方向の反対方向を－Ｙ軸方向とする。
　配線基板１０の基層１２０は、絶縁性材料からなる板状の部材である。本実施形態では、基層１２０の絶縁性材料は、熱硬化性樹脂、例えば、ビスマレイミドトリアジン樹脂（Bismaleimide-Triazine Resin、ＢＴ）やエポキシ樹脂等である。他の実施形態では、基層１２０の絶縁性材料は、繊維強化樹脂（例えば、ガラス繊維強化エポキシ樹脂）であってもよい。図１には図示しないが、基層１２０の内部に、スルーホール、スルーホール導体などを形成して、導体層１３０に接続する配線の一部を構成してもよい。
　配線基板１０の導体層１３０は、基層１２０上に形成された導電性材料からなる導体パターンである。本実施形態では、導体層１３０は、基層１２０の表面上に形成された銅メッキ層を所望の形状にエッチングすることによって形成される。
　導体層１３０は、接続端子１３２と、内部配線１３６とを含む。導体層１３０の接続端子１３２は、絶縁層１４０から露出した導体パターンであり、半導体チップ（図示しない）と接続可能に構成されている。導体層１３０の内部配線１３６は、絶縁層１４０によって被覆された導体パターンである。
　配線基板１０の絶縁層１４０は、ソルダレジストとも呼ばれる絶縁性材料からなる層である。絶縁層１４０は、第１表面１４１と、第２表面１４２と、壁面１４８とを有する。
　絶縁層１４０の第１表面１４１は、開口部１５０が形成された絶縁層１４０の表面である。本実施形態では、第１表面１４１は、Ｘ軸およびＹ軸に沿って＋Ｚ軸方向側を向いた面であり、絶縁層１４０の＋Ｚ軸方向側の表面を構成する。
　絶縁層１４０の第２表面１４２は、開口部１５０の内側において第１表面１４１に対して基層１２０側に窪んだ絶縁層１４０の表面である。第２表面１４２からは、導体層１３０の接続端子１３２が露出しており、本実施形態では、接続端子１３２は、第２表面１４２から＋Ｚ軸方向側に突出している。配線基板１０に対する半導体チップの実装時には、接続端子１３２は、半導体チップに対してハンダ付けされると共に、開口部１５０における配線基板１０と半導体チップとの隙間には、アンダーフィルが充填される。
　第２表面１４２は、基層１２０側（－Ｚ軸方向側）に向けて凸状に湾曲して壁面１４８と接続端子１３２との間を繋ぐ面であり、開口部１５０の内側において絶縁層１４０の＋Ｚ軸方向側の表面を構成する。第２表面１４２は、第２表面１４２において最も基層１２０側（－Ｚ軸方向側）に位置する最深部ＤＰを有する。
　接続端子１３２を横切る層面方向であるＸ軸方向に沿った壁面１４８と最深部ＤＰとの間の長さＬ１と、Ｘ軸方向に沿った最深部ＤＰと接続端子１３２との間の長さＬ２との関係は、Ｌ１＞Ｌ２を満たす。第２表面１４２と壁面１４８とが繋がる隅部１４５は、長さＬ１の基点である。第２表面１４２のうち接続端子１３２と接続する接続部１４３は、長さＬ２の基点である。
　本実施形態では、第２表面１４２の表面粗さは、第１表面１４１よりも粗い。本実施形態では、第２表面１４２の中心線平均粗さＲａは、０．０６～０．８μｍ（マイクロメートル）であり、第２表面１４２の十点平均粗さＲｚは、１．０～９．０μｍである。このような第２表面１４２の表面粗さに対して、第１表面１４１の中心線平均粗さＲａは、０．０２～０．２５μｍであり、第１表面１４１の十点平均粗さＲｚは、０．６～５．０μｍである。
　絶縁層１４０の壁面１４８は、開口部１５０の内側において積層方向（Ｚ軸方向）に沿って第１表面１４１と第２表面１４２との間を繋ぐ面である。本実施形態では、壁面１４８は、図１に示すように、角張った形状で第１表面１４１に繋がる。
　本実施形態では、絶縁層１４０は、導体層１３０が形成された基層１２０上に光硬化型絶縁性樹脂を塗布した後、露光、現像を経て形成される。絶縁層１４０における開口部１５０は、露光時にマスクされた部分に相当し、現像時に未硬化部分が洗い流されることによって、絶縁層１４０における第２表面１４２および壁面１４８が形成される。このように、絶縁層１４０における第１表面１４１、第２表面１４２および壁面１４８は、単一の層を構成する部位として一体的に形成される。本実施形態では、第２表面１４２および壁面１４８の形状は、光硬化型絶縁性樹脂の材質、露光時におけるマスクの形状、並びに、露光時における照射光の強度、照射時間および照射角度などを調整することによって実現される。
　図１には、＋Ｘ軸方向側の壁面１４８と－Ｘ軸方向側の壁面１４８との間に１つの接続端子１３２を図示したが、他の実施形態では、＋Ｘ軸方向側の壁面１４８と－Ｘ軸方向側の壁面１４８との間に２つ以上の接続端子１３２を設けてもよい。図１には図示しないが、Ｙ軸方向においても、Ｘ軸方向と同様に、接続端子１３２および絶縁層１４０を構成してもよい。
　以上説明した第１実施形態によれば、Ｌ１＞Ｌ２を満たす第２表面１４２の湾曲した形状によってアンダーフィルの流れ性を向上させつつ、最深部ＤＰよりも壁面１４８側における第２表面１４２上の空間が壁面１４８に向かうに連れて狭くなるため、第２表面１４２から壁面１４８に至る隅部１４５におけるボイドの形成を抑制することができる。また、第２表面１４２の表面粗さが、第１表面１４１よりも粗いため、アンダーフィルの流れ性を阻害することなく、毛細管現象を利用してアンダーフィルを第２表面１４２上の各部に行き渡らせることができる。
Ｂ．第２実施形態：
　図２は、第２実施形態における配線基板１０ｂの構成を模式的に示す部分断面図である。第２実施形態の説明において、第１実施形態と同様の構成については同一符号を付すと共に説明を省略する。
　第２実施形態の配線基板１０ｂは、第２表面１４２の形状が異なる点を除き、第１実施形態と同様である。第１実施形態では、第２表面１４２の最深部ＤＰは、接続部１４３と隅部１４５との間に位置するが、第２実施形態では、第２表面１４２の最深部ＤＰは、第２表面１４２が接続端子１３２に接続する接続部１４３に位置する。すなわち、最深部ＤＰは、接続部１４３を含む。第２実施形態では、長さＬ１と長さＬ２との関係は、Ｌ１＞Ｌ２＝０である。
　以上説明した第２実施形態によれば、Ｌ１＞Ｌ２＝０を満たす第２表面１４２の湾曲した形状によってアンダーフィルの流れ性を、第１実施形態よりも更に向上させつつ、最深部ＤＰよりも壁面１４８側における第２表面１４２上の空間が壁面１４８に向かうに連れて狭くなるため、第２表面１４２から壁面１４８に至る隅部１４５におけるボイドの形成を抑制することができる。
Ｃ．第３実施形態：
　図３は、第３実施形態における配線基板１０ｃの構成を模式的に示す部分断面図である。第３実施形態の説明において、第１実施形態と同様の構成については同一符号を付すと共に説明を省略する。
　第３実施形態の配線基板１０ｃは、第２表面１４２の形状が異なる点を除き、第１実施形態と同様である。第３実施形態では、第２表面１４２の最深部ＤＰは、第２表面１４２において壁面１４８から接続部１４３に向かう途中で最も基層１２０側（－Ｚ軸方向側）に位置する最初の点とする。第１実施形態では、第２表面１４２は、最深部ＤＰから接続部１４３に向かうに連れて＋Ｚ軸方向へと隆起するが、第３実施形態では、第２表面１４２は、最深部ＤＰから接続部１４３に向けてＸ軸に平行な形状を有する。第３実施形態では、長さＬ１と長さＬ２との関係は、第１実施形態と同様に、Ｌ１＞Ｌ２を満たす。
　以上説明した第３実施形態によれば、第１実施形態と同様に、第２表面１４２から壁面１４８に至る隅部１４５におけるボイドの形成を抑制することができる。
Ｄ．第４実施形態：
　図４は、第４実施形態における配線基板１０ｄの構成を模式的に示す部分断面図である。第４実施形態の説明において、第１実施形態と同様の構成については同一符号を付すと共に説明を省略する。
　第４実施形態の配線基板１０ｄは、第１表面１４１と壁面１４８との間を外側に凸状に湾曲して繋ぐ湾曲面１４９を有する点を除き、第１実施形態と同様である。本実施形態では、湾曲面１４９の形状は、第２表面１４２および壁面１４８と同様に、光硬化型絶縁性樹脂の材質、露光時におけるマスクの形状、並びに、露光時における照射光の強度、照射時間および照射角度などを調整することによって実現される。
　以上説明した第４実施形態によれば、第１実施形態と同様に、第２表面１４２から壁面１４８に至る隅部１４５におけるボイドの形成を抑制することができる。また、第１表面１４１と壁面１４８との間に湾曲面１４９が形成されているため、第１実施形態のように第１表面１４１と壁面１４８との間が角張っている場合と比較して、第２表面１４２上に対するアンダーフィルの流し込み性を向上させることができる。第４実施形態の変形例として、第４実施形態の湾曲面１４９を、第２実施形態の配線基板１０ｂや第３実施形態の配線基板１０ｃに適用してもよい。
Ｅ．第５実施形態：
　図５は、第５実施形態における配線基板１０ｅの構成を模式的に示す部分断面図である。第５実施形態の説明において、第１実施形態と同様の構成については同一符号を付すと共に説明を省略する。
　第５実施形態の配線基板１０ｅは、壁面１４８の＋Ｚ軸方向側が開口部１５０の外周側に向かって傾斜している点を除き、第１実施形態と同様である。本実施形態では、第５実施形態における壁面１４８の形状は、光硬化型絶縁性樹脂の材質、露光時におけるマスクの形状、並びに、露光時における照射光の強度、照射時間および照射角度などを調整することによって実現される。
　本実施形態では、第１表面１４１と壁面１４８との間は、角張っているが、他の実施形態では、第４実施形態のように、第１表面１４１と壁面１４８との間に湾曲面１４９が形成されていてもよい。本実施形態では、第２表面１４２の形状は、第１実施形態と同様であるが、他の実施形態では、第２実施形態と同様であってもよいし、第３実施形態と同様であってもよい。
　以上説明した第５実施形態によれば、第１実施形態と同様に、第２表面１４２から壁面１４８に至る隅部１４５におけるボイドの形成を抑制することができる。また、壁面１４８の＋Ｚ軸方向側が開口部１５０の外周側に向かって傾斜しているため、アンダーフィルの流れ性を更に向上させることができる。
Ｆ．他の実施形態：
　本発明は、上述の実施形態や実施例、変形例に限られるものではなく、その趣旨を逸脱しない範囲において種々の構成で実現することができる。例えば、発明の概要の欄に記載した各形態中の技術的特徴に対応する実施形態、実施例、変形例中の技術的特徴は、上述の課題の一部または全部を解決するために、あるいは、上述の効果の一部または全部を達成するために、適宜、差し替えや、組み合わせを行うことが可能である。また、その技術的特徴が本明細書中に必須なものとして説明されていなければ、適宜、削除することが可能である。
　上述の実施形態において、絶縁層１４０の第２表面１４２および壁面１４８は、次の工程を経て形成されてもよい。
工程１．導体層１３０が形成された基層１２０上に、絶縁層１４０の材料である光硬化型絶縁性樹脂を、塗布またはラミネート加工
工程２．工程１を行った後、基層１２０上の光硬化型絶縁性樹脂に対してパターン露光
工程３．工程２を行った後、絶縁層１４０から接続端子１３２が露出するように、アルカリ水溶液を用いた現像処理によって、基層１２０上の光硬化型絶縁性樹脂における未硬化部分を除去
工程４．工程３を行った後、加熱による絶縁層１４０の硬化（熱硬化）と、紫外線による絶縁層１４０の硬化（光硬化）とを実施
　工程４の光硬化における積算光量は、５００ｍＪ／ｃｍ2（ミリジュール毎平方センチメートル）以上２５００ｍＪ／ｃｍ2以下が好ましく、１０００ｍＪ／ｃｍ2以上２０００ｍＪ／ｃｍ2以下がさらに好ましい。
　　１０，１０ｂ，１０ｃ，１０ｄ，１０ｅ…配線基板
　　１２０…基層
　　１３０…導体層
　　１３２…接続端子
　　１３６…内部配線
　　１４０…絶縁層
　　１４１…第１表面
　　１４２…第２表面
　　１４３…接続部
　　１４５…隅部
　　１４８…壁面
　　１４９…湾曲面
　　１５０…開口部
　　ＤＰ…最深部

Claims (4)

  1. 　絶縁性の基層と、
    　前記基層に積層された絶縁層であって、
    　　開口部が形成された第１表面と、
    　　前記開口部の内側において前記第１表面に対して前記基層側に窪んだ第２表面と、
    　　前記開口部の内側において前記基層に対する前記絶縁層の積層方向に沿って前記第１表面と前記第２表面との間を繋ぐ壁面と
    　を有する絶縁層と、
    　前記第２表面から露出した導電性の接続端子と
    　を備える配線基板であって、
    　前記第２表面は、前記第２表面において最も前記基層側に位置する最深部を有し、前記基層側に凸状に湾曲して前記壁面と前記接続端子との間を繋ぐ面であり、
    　前記積層方向に直交する層面方向に沿った前記壁面と前記最深部との間の長さＬ１と、前記層面方向に沿った前記最深部と前記接続端子との間の長さＬ２との関係は、Ｌ１＞Ｌ２を満たすことを特徴とする配線基板。
  2. 　前記最深部は、前記第２表面のうち前記接続端子と接続する接続部を含むことを特徴とする請求項１に記載の配線基板。
  3. 　前記絶縁層は、更に、前記第１表面と前記壁面との間を外側に凸状に湾曲して繋ぐ湾曲面を有することを特徴とする請求項１または請求項２に記載の配線基板。
  4. 　前記第２表面の表面粗さは、前記第１表面よりも粗いことを特徴とする請求項１から請求項３のいずれか一項に記載の配線基板。
PCT/JP2013/004722 2012-08-24 2013-08-05 配線基板 WO2014030309A1 (ja)

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EP13831747.4A EP2750172A4 (en) 2012-08-24 2013-08-05 WIRING SUBSTRATE
KR1020147010585A KR101603453B1 (ko) 2012-08-24 2013-08-05 배선기판
JP2013554712A JP5523641B1 (ja) 2012-08-24 2013-08-05 配線基板
US14/352,299 US20140284081A1 (en) 2012-08-24 2013-08-05 Wiring substrate
CN201380003704.8A CN103907180B (zh) 2012-08-24 2013-08-05 布线基板
TW102129936A TW201419949A (zh) 2012-08-24 2013-08-22 配線基板

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JP2017098306A (ja) * 2015-11-18 2017-06-01 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

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JP2017098306A (ja) * 2015-11-18 2017-06-01 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法

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EP2750172A4 (en) 2015-05-06
CN103907180B (zh) 2016-08-31
US20140284081A1 (en) 2014-09-25
JP5523641B1 (ja) 2014-06-18
KR101603453B1 (ko) 2016-03-14
CN103907180A (zh) 2014-07-02
TW201419949A (zh) 2014-05-16
EP2750172A1 (en) 2014-07-02
KR20140069213A (ko) 2014-06-09
JPWO2014030309A1 (ja) 2016-07-28

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