JPWO2014030309A1 - 配線基板 - Google Patents
配線基板 Download PDFInfo
- Publication number
- JPWO2014030309A1 JPWO2014030309A1 JP2013554712A JP2013554712A JPWO2014030309A1 JP WO2014030309 A1 JPWO2014030309 A1 JP WO2014030309A1 JP 2013554712 A JP2013554712 A JP 2013554712A JP 2013554712 A JP2013554712 A JP 2013554712A JP WO2014030309 A1 JPWO2014030309 A1 JP WO2014030309A1
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- base layer
- layer
- insulating layer
- wall surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003746 surface roughness Effects 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 79
- 239000004020 conductor Substances 0.000 description 18
- 229920005989 resin Polymers 0.000 description 11
- 239000011347 resin Substances 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000016 photochemical curing Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10977—Encapsulated connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0594—Insulating resist or coating with special shaped edges
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
図1は、第1実施形態における配線基板10の構成を模式的に示す部分断面図である。配線基板10は、有機材料を用いて形成され、有機基板(オーガニック基板)とも呼ばれる板状の部材である。配線基板10は、半導体チップ(図示しない)を実装可能に構成されたフリップチップ実装基板である。
図2は、第2実施形態における配線基板10bの構成を模式的に示す部分断面図である。第2実施形態の説明において、第1実施形態と同様の構成については同一符号を付すと共に説明を省略する。
図3は、第3実施形態における配線基板10cの構成を模式的に示す部分断面図である。第3実施形態の説明において、第1実施形態と同様の構成については同一符号を付すと共に説明を省略する。
図4は、第4実施形態における配線基板10dの構成を模式的に示す部分断面図である。第4実施形態の説明において、第1実施形態と同様の構成については同一符号を付すと共に説明を省略する。
図5は、第5実施形態における配線基板10eの構成を模式的に示す部分断面図である。第5実施形態の説明において、第1実施形態と同様の構成については同一符号を付すと共に説明を省略する。
本発明は、上述の実施形態や実施例、変形例に限られるものではなく、その趣旨を逸脱しない範囲において種々の構成で実現することができる。例えば、発明の概要の欄に記載した各形態中の技術的特徴に対応する実施形態、実施例、変形例中の技術的特徴は、上述の課題の一部または全部を解決するために、あるいは、上述の効果の一部または全部を達成するために、適宜、差し替えや、組み合わせを行うことが可能である。また、その技術的特徴が本明細書中に必須なものとして説明されていなければ、適宜、削除することが可能である。
工程1.導体層130が形成された基層120上に、絶縁層140の材料である光硬化型絶縁性樹脂を、塗布またはラミネート加工
工程2.工程1を行った後、基層120上の光硬化型絶縁性樹脂に対してパターン露光
工程3.工程2を行った後、絶縁層140から接続端子132が露出するように、アルカリ水溶液を用いた現像処理によって、基層120上の光硬化型絶縁性樹脂における未硬化部分を除去
工程4.工程3を行った後、加熱による絶縁層140の硬化(熱硬化)と、紫外線による絶縁層140の硬化(光硬化)とを実施
工程4の光硬化における積算光量は、500mJ/cm2(ミリジュール毎平方センチメートル)以上2500mJ/cm2以下が好ましく、1000mJ/cm2以上2000mJ/cm2以下がさらに好ましい。
120…基層
130…導体層
132…接続端子
136…内部配線
140…絶縁層
141…第1表面
142…第2表面
143…接続部
145…隅部
148…壁面
149…湾曲面
150…開口部
DP…最深部
Claims (4)
- 絶縁性の基層と、
前記基層に積層された絶縁層であって、
開口部が形成された第1表面と、
前記開口部の内側において前記第1表面に対して前記基層側に窪んだ第2表面と、
前記開口部の内側において前記基層に対する前記絶縁層の積層方向に沿って前記第1表面と前記第2表面との間を繋ぐ壁面と
を有する絶縁層と、
前記第2表面から露出した導電性の接続端子と
を備える配線基板であって、
前記第2表面は、前記第2表面において最も前記基層側に位置する最深部を有し、前記基層側に凸状に湾曲して前記壁面と前記接続端子との間を繋ぐ面であり、
前記積層方向に直交する層面方向に沿った前記壁面と前記最深部との間の長さL1と、前記層面方向に沿った前記最深部と前記接続端子との間の長さL2との関係は、L1>L2を満たすことを特徴とする配線基板。 - 前記最深部は、前記第2表面のうち前記接続端子と接続する接続部を含むことを特徴とする請求項1に記載の配線基板。
- 前記絶縁層は、更に、前記第1表面と前記壁面との間を外側に凸状に湾曲して繋ぐ湾曲面を有することを特徴とする請求項1または請求項2に記載の配線基板。
- 前記第2表面の表面粗さは、前記第1表面よりも粗いことを特徴とする請求項1から請求項3のいずれか一項に記載の配線基板。
Priority Applications (1)
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JP2013554712A JP5523641B1 (ja) | 2012-08-24 | 2013-08-05 | 配線基板 |
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JP2012184962 | 2012-08-24 | ||
JP2012184962 | 2012-08-24 | ||
JP2013554712A JP5523641B1 (ja) | 2012-08-24 | 2013-08-05 | 配線基板 |
PCT/JP2013/004722 WO2014030309A1 (ja) | 2012-08-24 | 2013-08-05 | 配線基板 |
Publications (2)
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JP5523641B1 JP5523641B1 (ja) | 2014-06-18 |
JPWO2014030309A1 true JPWO2014030309A1 (ja) | 2016-07-28 |
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JP2013554712A Expired - Fee Related JP5523641B1 (ja) | 2012-08-24 | 2013-08-05 | 配線基板 |
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US (1) | US20140284081A1 (ja) |
EP (1) | EP2750172A4 (ja) |
JP (1) | JP5523641B1 (ja) |
KR (1) | KR101603453B1 (ja) |
CN (1) | CN103907180B (ja) |
TW (1) | TW201419949A (ja) |
WO (1) | WO2014030309A1 (ja) |
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JP6139457B2 (ja) * | 2014-04-22 | 2017-05-31 | 京セラ株式会社 | 配線基板の製造方法 |
US9620446B2 (en) * | 2014-12-10 | 2017-04-11 | Shinko Electric Industries Co., Ltd. | Wiring board, electronic component device, and method for manufacturing those |
JP6543559B2 (ja) * | 2015-11-18 | 2019-07-10 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
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TW318321B (ja) * | 1995-07-14 | 1997-10-21 | Matsushita Electric Ind Co Ltd | |
JP3346263B2 (ja) * | 1997-04-11 | 2002-11-18 | イビデン株式会社 | プリント配線板及びその製造方法 |
US5889655A (en) * | 1997-11-26 | 1999-03-30 | Intel Corporation | Integrated circuit package substrate with stepped solder mask openings |
JP3922151B2 (ja) * | 2002-09-27 | 2007-05-30 | ブラザー工業株式会社 | フレキシブル配線基板の接続構造および接続方法 |
TWI231028B (en) * | 2004-05-21 | 2005-04-11 | Via Tech Inc | A substrate used for fine-pitch semiconductor package and a method of the same |
DE102005014665A1 (de) * | 2005-03-29 | 2006-11-02 | Infineon Technologies Ag | Substrat zur Herstellung einer Lötverbindung mit einem zweiten Substrat |
JP4747770B2 (ja) | 2005-10-04 | 2011-08-17 | 日立化成工業株式会社 | プリント配線板の製造方法、及び半導体チップ搭載基板の製造方法 |
KR100850243B1 (ko) * | 2007-07-26 | 2008-08-04 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조방법 |
JP5117371B2 (ja) | 2008-12-24 | 2013-01-16 | 新光電気工業株式会社 | 半導体装置およびその製造方法 |
US8222538B1 (en) * | 2009-06-12 | 2012-07-17 | Amkor Technology, Inc. | Stackable via package and method |
JP5255545B2 (ja) * | 2009-09-29 | 2013-08-07 | 三菱製紙株式会社 | ソルダーレジストの形成方法 |
JP5444050B2 (ja) | 2010-03-12 | 2014-03-19 | 三菱製紙株式会社 | ソルダーレジストパターンの形成方法 |
JP5479233B2 (ja) * | 2010-06-04 | 2014-04-23 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
CN102480849B (zh) * | 2010-11-29 | 2014-09-24 | 宏恒胜电子科技(淮安)有限公司 | 电路板及其制作方法 |
JP2013062472A (ja) * | 2011-09-15 | 2013-04-04 | Toppan Printing Co Ltd | 半導体パッケージおよびその製造方法 |
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2013
- 2013-08-05 KR KR1020147010585A patent/KR101603453B1/ko active IP Right Grant
- 2013-08-05 CN CN201380003704.8A patent/CN103907180B/zh active Active
- 2013-08-05 WO PCT/JP2013/004722 patent/WO2014030309A1/ja active Application Filing
- 2013-08-05 JP JP2013554712A patent/JP5523641B1/ja not_active Expired - Fee Related
- 2013-08-05 EP EP13831747.4A patent/EP2750172A4/en not_active Withdrawn
- 2013-08-05 US US14/352,299 patent/US20140284081A1/en not_active Abandoned
- 2013-08-22 TW TW102129936A patent/TW201419949A/zh unknown
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US20140284081A1 (en) | 2014-09-25 |
KR20140069213A (ko) | 2014-06-09 |
TWI562686B (ja) | 2016-12-11 |
JP5523641B1 (ja) | 2014-06-18 |
CN103907180A (zh) | 2014-07-02 |
EP2750172A4 (en) | 2015-05-06 |
TW201419949A (zh) | 2014-05-16 |
EP2750172A1 (en) | 2014-07-02 |
CN103907180B (zh) | 2016-08-31 |
WO2014030309A1 (ja) | 2014-02-27 |
KR101603453B1 (ko) | 2016-03-14 |
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