WO2014024266A1 - 半導体装置の製造方法、及び、半導体装置 - Google Patents

半導体装置の製造方法、及び、半導体装置 Download PDF

Info

Publication number
WO2014024266A1
WO2014024266A1 PCT/JP2012/070145 JP2012070145W WO2014024266A1 WO 2014024266 A1 WO2014024266 A1 WO 2014024266A1 JP 2012070145 W JP2012070145 W JP 2012070145W WO 2014024266 A1 WO2014024266 A1 WO 2014024266A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon layer
fin
resist
forming
gate
Prior art date
Application number
PCT/JP2012/070145
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
舛岡　富士雄
広記 中村
Original Assignee
ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ユニサンティス エレクトロニクス シンガポール プライベート リミテッド filed Critical ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
Priority to JP2014508629A priority Critical patent/JP5595619B2/ja
Priority to PCT/JP2012/070145 priority patent/WO2014024266A1/ja
Priority to TW102128020A priority patent/TW201407788A/zh
Publication of WO2014024266A1 publication Critical patent/WO2014024266A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
  • SGT Surrounding Gate Transistor
  • a thick gate material when the distance between the silicon pillars becomes narrow, a thick gate material must be deposited between the silicon pillars, and a hole called a void may be formed between the silicon pillars. Once the void is formed, a hole is made in the gate material after etch back. Thereafter, when an insulating film is deposited to form an insulating film sidewall, the insulating film is deposited in the void. Therefore, it is difficult to process the gate material.
  • a gate oxide film is formed, and after depositing thin polysilicon, a resist for covering the upper part of the silicon pillar and forming a gate wiring is formed, the gate wiring is etched, and then the oxide film is thickened. It has been shown that the upper part of the silicon pillar is deposited, the thin polysilicon on the upper part of the silicon pillar is removed, and the thick oxide film is removed by wet etching (see Non-Patent Document 1, for example).
  • a resist for forming the gate wiring must be formed so as to cover the upper part of the silicon pillar, and therefore, the upper part of the silicon pillar must be covered, which is not a self-alignment process.
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A
  • an object of the present invention is to provide a method for manufacturing SGT that is a self-aligned process using a thin gate material, a metal gate, and a self-aligned process, and a SGT structure obtained as a result, by reducing the parasitic capacitance between the gate wiring and the substrate. .
  • a method for manufacturing a semiconductor device of the present invention includes: Forming a fin-like silicon layer on a silicon substrate, forming a first insulating film around the fin-like silicon layer, and forming a columnar silicon layer on the fin-like silicon layer; and The diameter of the columnar silicon layer is the same as the width of the fin-shaped silicon layer, After the first step, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and a third wiring for forming a gate wiring is formed.
  • the method may further include a fifth step of forming silicide on the first diffusion layer, the second diffusion layer, and the gate wiring.
  • a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer.
  • a second step of forming a third resist for forming a gate wiring and performing the anisotropic etching to form the gate wiring after the second process, Depositing a resist to expose the polysilicon film on the upper side wall of the columnar silicon layer; removing the exposed polysilicon film by etching; stripping the fourth resist; removing the metal film by etching;
  • a self-alignment process is realized by the third step of forming a gate electrode connected to the gate wiring. Since it is a self-alignment process, high integration is possible.
  • the gate wiring has a laminated structure of the metal film and silicide. Since the silicide and the metal film are in direct contact, the resistance can be reduced.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which concerns on the manufacturing method of the
  • a fin-like silicon layer 103 is formed on a silicon substrate 101, a first insulating film 104 is formed around the fin-like silicon layer 103, and a columnar silicon layer 106 is formed on the fin-like silicon layer 103. Indicates. As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.
  • the silicon substrate 101 is etched to form a fin-like silicon layer 103.
  • the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.
  • the first resist 102 is removed.
  • the second resist 105 is removed.
  • a fourth resist 112 is deposited, the polysilicon film 109 on the upper side wall of the columnar silicon layer 106 is exposed, the exposed polysilicon film 109 is removed by etching, the fourth resist 112 is stripped, and a metal film A manufacturing method in which 108 is removed by etching and a gate electrode 111a connected to the gate wiring 111b is formed will be described.
  • the first diffusion layer 114 is formed on the top of the columnar silicon layer 106 and the second diffusion layer 113 is formed on the bottom of the columnar silicon layer 106 and the top of the fin-like silicon layer 103 will be described.
  • the gate wiring 111b tends to have a laminated structure of the metal film 108 and the silicide 119. Since the silicide 119 and the metal film 108 are in direct contact with each other, the resistance can be reduced.
  • the interlayer insulating film 121 is etched to form contact holes 123 and 124.
  • the fifth resist 122 is removed.
  • the interlayer insulating film 121 is etched to form a contact hole 126.
  • the sixth resist 125 is removed.
  • the contact stopper 140 at the bottom of the contact holes 123, 124, 126 is removed by etching.
  • seventh resists 131, 132, 133 for forming metal wiring are formed.
  • the seventh resists 131, 132, 133 are peeled off.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/JP2012/070145 2012-08-08 2012-08-08 半導体装置の製造方法、及び、半導体装置 WO2014024266A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2014508629A JP5595619B2 (ja) 2012-08-08 2012-08-08 半導体装置の製造方法、及び、半導体装置
PCT/JP2012/070145 WO2014024266A1 (ja) 2012-08-08 2012-08-08 半導体装置の製造方法、及び、半導体装置
TW102128020A TW201407788A (zh) 2012-08-08 2013-08-06 半導體裝置的製造方法以及半導體裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2012/070145 WO2014024266A1 (ja) 2012-08-08 2012-08-08 半導体装置の製造方法、及び、半導体装置

Publications (1)

Publication Number Publication Date
WO2014024266A1 true WO2014024266A1 (ja) 2014-02-13

Family

ID=50067550

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/070145 WO2014024266A1 (ja) 2012-08-08 2012-08-08 半導体装置の製造方法、及び、半導体装置

Country Status (3)

Country Link
JP (1) JP5595619B2 (zh)
TW (1) TW201407788A (zh)
WO (1) WO2014024266A1 (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015125205A1 (ja) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
WO2015125204A1 (ja) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
WO2015132912A1 (ja) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
WO2015132913A1 (ja) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP5798276B1 (ja) * 2014-06-16 2015-10-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
WO2015193940A1 (ja) * 2014-06-16 2015-12-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP2016105500A (ja) * 2016-02-01 2016-06-09 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
US9530793B2 (en) 2014-03-03 2016-12-27 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009532903A (ja) * 2006-04-04 2009-09-10 マイクロン テクノロジー， インク． 成長型ナノＦｉｎトランジスタ
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法
JP2011071235A (ja) * 2009-09-24 2011-04-07 Toshiba Corp 半導体装置及びその製造方法
JP2011077437A (ja) * 2009-10-01 2011-04-14 Unisantis Electronics Japan Ltd 半導体装置
JP2011100826A (ja) * 2009-11-05 2011-05-19 Elpida Memory Inc 半導体装置の製造方法および半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009532903A (ja) * 2006-04-04 2009-09-10 マイクロン テクノロジー， インク． 成長型ナノＦｉｎトランジスタ
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法
JP2011071235A (ja) * 2009-09-24 2011-04-07 Toshiba Corp 半導体装置及びその製造方法
JP2011077437A (ja) * 2009-10-01 2011-04-14 Unisantis Electronics Japan Ltd 半導体装置
JP2011100826A (ja) * 2009-11-05 2011-05-19 Elpida Memory Inc 半導体装置の製造方法および半導体装置

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015125204A1 (ja) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
US10811535B2 (en) 2014-02-18 2020-10-20 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device including surrounding gate transistor having a gate electrode with inclined side surface
US10804397B2 (en) 2014-02-18 2020-10-13 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device with surrounding gate transistor (SGT)
WO2015125205A1 (ja) * 2014-02-18 2015-08-27 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP5822326B1 (ja) * 2014-02-18 2015-11-24 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
US9812547B2 (en) 2014-02-18 2017-11-07 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having fin-shaped semiconductor layer
US9755053B2 (en) 2014-02-18 2017-09-05 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having fin-shaped semiconductor layer
US9640628B2 (en) 2014-02-18 2017-05-02 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device having fin-shaped semiconductor layer
US9530793B2 (en) 2014-03-03 2016-12-27 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device
US9865741B2 (en) 2014-03-05 2018-01-09 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US9893179B2 (en) 2014-03-05 2018-02-13 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US10923591B2 (en) 2014-03-05 2021-02-16 Unisantis Electronics Singapore Pte. Ltd. Method for producing a semiconductor device
JP5838529B1 (ja) * 2014-03-05 2016-01-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
JP5838530B1 (ja) * 2014-03-05 2016-01-06 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
WO2015132912A1 (ja) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
WO2015132913A1 (ja) * 2014-03-05 2015-09-11 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
US10475922B2 (en) 2014-03-05 2019-11-12 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US9960277B2 (en) 2014-03-05 2018-05-01 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device
US9647142B2 (en) 2014-06-16 2017-05-09 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
JP5798276B1 (ja) * 2014-06-16 2015-10-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
WO2015193939A1 (ja) * 2014-06-16 2015-12-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
US10026842B2 (en) 2014-06-16 2018-07-17 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device
US9780215B2 (en) 2014-06-16 2017-10-03 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
WO2015193940A1 (ja) * 2014-06-16 2015-12-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置の製造方法、及び、半導体装置
JP5902868B1 (ja) * 2014-06-16 2016-04-13 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置
JP2016105500A (ja) * 2016-02-01 2016-06-09 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． 半導体装置の製造方法、及び、半導体装置

Also Published As

Publication number Publication date
TW201407788A (zh) 2014-02-16
JP5595619B2 (ja) 2014-09-24
JPWO2014024266A1 (ja) 2016-07-21

Similar Documents

Publication Publication Date Title
JP5595619B2 (ja) 半導体装置の製造方法、及び、半導体装置
US8823085B2 (en) Method for producing a semiconductor device and semiconductor device
WO2014203304A1 (ja) 半導体装置の製造方法、及び、半導体装置
US20130328138A1 (en) Method for producing semiconductor device and semiconductor device
WO2015019444A1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5604019B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5692886B1 (ja) 半導体装置の製造方法、及び、半導体装置
US9287396B2 (en) Semiconductor device
WO2014170949A1 (ja) 半導体装置の製造方法、及び、半導体装置
JP5903139B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5749818B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP6114425B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5646116B1 (ja) 半導体装置の製造方法、及び、半導体装置
JP6405026B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5928566B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP6375316B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5685344B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP5869079B2 (ja) 半導体装置の製造方法、及び、半導体装置
JP2015057852A (ja) 半導体装置の製造方法、及び、半導体装置
JP2017135428A (ja) 半導体装置の製造方法、及び、半導体装置
JP2016021598A (ja) 半導体装置の製造方法、及び、半導体装置
JP2015046623A (ja) 半導体装置の製造方法、及び、半導体装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2014508629

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12882598

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12882598

Country of ref document: EP

Kind code of ref document: A1