WO2014019300A1 - 多晶硅tft、多晶硅阵列基板及其制备方法、显示装置 - Google Patents

多晶硅tft、多晶硅阵列基板及其制备方法、显示装置 Download PDF

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WO2014019300A1
WO2014019300A1 PCT/CN2012/084780 CN2012084780W WO2014019300A1 WO 2014019300 A1 WO2014019300 A1 WO 2014019300A1 CN 2012084780 W CN2012084780 W CN 2012084780W WO 2014019300 A1 WO2014019300 A1 WO 2014019300A1
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tft
polysilicon
doping
layer
array substrate
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PCT/CN2012/084780
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English (en)
French (fr)
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张方振
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京东方科技集团股份有限公司
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Priority to EP12867729.1A priority Critical patent/EP2881993B1/en
Priority to US13/985,336 priority patent/US9502446B2/en
Publication of WO2014019300A1 publication Critical patent/WO2014019300A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure

Definitions

  • Polysilicon TFT Polysilicon TFT, polysilicon array substrate, preparation method thereof, and display device
  • Embodiments of the present invention relate to a polysilicon TFT, a polysilicon array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • Embodiments of the present invention provide a polysilicon TFT, a polycrystalline silicon array substrate, and a method of fabricating the same, which are simple in process and low in cost.
  • One embodiment of the present invention provides a method of fabricating a polysilicon TFT, the polysilicon
  • the TFT includes a doping region, including the steps of: forming a polysilicon layer on the substrate, forming an active layer by a patterning process; forming a first insulating layer covering the active layer; and patterning the photo in the first insulating layer a predetermined position of the source electrode and the drain electrode is formed in a later step to form a via hole exposing the active layer; and the active layer is doped through the via hole by a doping process to form a doped region; The metal layer is drained, and the source electrode and the drain electrode are formed by a patterning process.
  • the method for preparing the polysilicon TFT may further include: forming a gate metal layer, forming a gate by a patterning process; and forming a second insulating layer on the substrate on which the gate is formed.
  • the polysilicon TFT is an N-TFT
  • the doped region may be N Type doped region.
  • the doping element may be one or a mixture of a monument, an arsenic, and a cerium.
  • the polysilicon TFT may be a P-TFT, and the doped region may be a P-type doped region.
  • the doping element may be one or a mixture of two of boron and indium.
  • Another embodiment of the present invention also provides a polysilicon obtained by the above preparation method.
  • Still another embodiment of the present invention also provides a polysilicon array substrate, including the above polysilicon
  • a further embodiment of the present invention further provides a method for fabricating a polysilicon array substrate, the polysilicon array substrate comprising an N-TFT and a P-TFT, the N-TFT comprising an N-type doped region, and the P-TFT comprising
  • the P-type doped region comprises the steps of: forming a polysilicon layer on the substrate, forming an active layer by a patterning process, and doping the active layer of the N-TFT or the P-TFT by a first doping process to form An N-type doped region or a P-type doped region; forming a first insulating layer covering the active layer; and a source electrode and a leakage current of the N-TFT to be formed in the first insulating layer in a subsequent step by a patterning process a predetermined position of the source electrode and the drain electrode of the P-TFT forms a via hole; and the exposed active layer region is doped through the via hole by a second doping process to form a P-type do
  • the preparation method may further include: forming a gate metal layer, forming a gate by a patterning process; and forming a second insulating layer on the substrate on which the gate is formed.
  • the element doping amount of the second doping process may be 1/3 to 2/3 of the element doping amount in the first doping process.
  • the element doping amount of the second doping process may be 1/2 of the element doping amount in the first doping process.
  • a polysilicon layer is formed on a substrate, an active layer is formed by a patterning process, and an active layer of the N-TFT or the P-TFT is doped by a first doping process to form an N-type doping.
  • the patterning process includes a halftone mask process, a grayscale mask process, or a single slit mask process.
  • the above method may further include: forming a third insulating layer, and using a patterning process in the subsequent steps
  • the pixel electrode is formed in the step to form a via hole with a predetermined connection position of the drain of the TFT.
  • the above method may further include: forming a transparent conductive layer, and forming a pixel electrode by a patterning process.
  • the method further includes: forming a buffer layer on the substrate.
  • the doping element of the N-type doping region of the N-TFT may be one or a mixture of phosphorus, arsenic, and antimony.
  • the doping element of the P-type doping region of the P-TFT may be one or a mixture of boron and indium.
  • Still another embodiment of the present invention provides a polycrystalline silicon array substrate obtained by the above production method.
  • Still another embodiment of the present invention provides a display device comprising the above polysilicon array substrate.
  • a polysilicon TFT, a polysilicon array substrate and a preparation method thereof are provided by the embodiment of the present invention, and doping processes are performed through via holes to form doped regions on both sides of the active layer to form corresponding TFTs, thereby avoiding the need to set a dedicated
  • the masking process is performed by a doping process, which reduces the number of masks used in preparing the TFT array substrate and reduces the production cost.
  • FIG. 1 is a schematic cross-sectional view showing the steps of the polysilicon TFT according to an embodiment of the present invention
  • FIG. 8 is a cross-sectional structural view of another polysilicon TFT according to an embodiment of the present invention
  • This embodiment provides a method of preparing a polysilicon TFT, which includes the following steps.
  • the patterning process is, for example, a photolithographic patterning process, for example, comprising: coating a photoresist layer on a structure layer to be patterned, exposing the photoresist layer using a mask, and developing the exposed photoresist layer to obtain The photoresist pattern is etched using a photoresist pattern, and then the photoresist pattern is optionally removed; the mask may be, for example, a mask such as a monotone or a double tone.
  • the substrate 1 Before the preparation of the TFT array substrate, the substrate 1 can be first cleaned to remove dust on the substrate 1 to prevent dust from deteriorating the performance of the prepared TFT.
  • the substrate 1 may be a plastic substrate or a glass substrate, wherein the glass substrate can be used to prepare a rigid array substrate, and the plastic substrate can be used to prepare a flexible array substrate.
  • a polysilicon layer is formed on the substrate 1.
  • the polysilicon layer can be formed by directly forming a polysilicon layer on the substrate, or an amorphous silicon (a-Si) layer can be formed on the substrate first, and then amorphous.
  • the silicon layer is subjected to a crystallization treatment to obtain a polysilicon layer.
  • the method of directly forming the polysilicon layer or the amorphous silicon layer may specifically employ chemical vapor deposition or the like.
  • the method of crystallizing amorphous silicon may include solid phase crystallization (SPC), laser crystallization, or metal induced crystallization (MIC).
  • SPC solid phase crystallization
  • MIC metal induced crystallization
  • a first insulating layer 3 is formed on the substrate on which the active layer is formed, and the first insulating layer 3 can be prepared by spin coating, chemical vapor deposition or the like. The resulting structure is shown in Figure 2.
  • a gate metal layer is formed on a substrate on which a first insulating layer is formed by chemical vapor deposition or sputtering.
  • the gate electrode 4 is formed by a patterning process, and a specific example of the patterning process includes the following steps:
  • a second insulating layer 5 is formed on the substrate subjected to the step S3, and the second insulating layer 5 can be prepared by a process such as spin coating or chemical vapor deposition.
  • the resulting structure is shown in Figure 4.
  • the via hole 6 is formed on the substrate subjected to the step S4 by a patterning process, and a specific example of the patterning process includes the following steps: 5501, coating a photoresist on the substrate subjected to the step S4;
  • exposing and developing the photoresist-coated substrate by a mask process to form a photoresist pattern including a photoresist completely reserved region and a photoresist completely non-retained region;
  • the first insulating layer 3 and the second insulating layer 5 are completely etched by the etching process to form a via hole 6 extending through the first insulating layer 3 and the second layer. Insulation layer 5;
  • FIG. 1 A schematic diagram of the structure formed is shown in FIG. 1
  • the doping process in this step can be specifically carried out by using ion implantation or the like.
  • the structure formed after doping is shown in Fig. 6.
  • the source/drain metal layer is formed on the substrate subjected to the doping process, for example, by sputtering or the like. Thereafter, the source electrode and the drain electrode are formed by a patterning process, and the source electrode and the drain electrode are connected to the doped region of the active layer through the via hole formed in the step S5.
  • a specific example of the patterning process includes: S701, coating a photoresist on a substrate forming a source/drain metal layer;
  • exposing and developing the photoresist-coated substrate by a mask process to form a photoresist pattern including a photoresist completely reserved region and a photoresist completely non-retained region;
  • the source/drain metal layer in the completely non-retained region of the photoresist is etched by an etching process to form a source electrode 7 and a drain electrode 8.
  • the above polysilicon TFT may be an N-TFT or a P-TFT.
  • the doping region is an N-TFT.
  • the N-doped region may be doped with one or more of phosphorus, arsenic or antimony; when it is a P-TFT, the doped region is a P-doped region, and the doping element may be specifically used. It is a mixture of one or two of boron and indium.
  • the source electrode and the drain electrode of the TFT may be prepared first, and then the gate electrode and the second insulating layer are prepared.
  • the preparation method is the same as that in the above steps, and details are not described herein again.
  • the structure is as shown in FIG. .
  • the present embodiment further provides a polysilicon TFT obtained by the above method for preparing a polysilicon TFT, and the structure of the polysilicon TFT is as shown in FIG. 7 or FIG. 8.
  • this embodiment further provides a polysilicon array substrate including the above polysilicon TFT.
  • the polycrystalline silicon array substrate can be used for various display devices such as liquid crystal display devices, organic light emitting diode (OLED) display devices, electronic paper display devices, and the like.
  • the method for preparing a polysilicon TFT and the polysilicon TFT provided by the embodiment provide a doping process on the two sides of the active layer to form a corresponding TFT, thereby avoiding the need to provide a dedicated mask.
  • the doping process of the plate reduces the number of masks used in the preparation of the TFT array substrate and reduces the production cost.
  • the embodiment further provides a method for preparing a polycrystalline silicon array substrate.
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor and a pixel as a switching element electrode.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode.
  • the following description is mainly made for a single or a plurality of pixel units, but other pixel units may be formed identically.
  • the polysilicon array substrate of the present embodiment includes an N-TFT and a P-TFT, the N-TFT includes an N-type doped region, and the P-TFT includes a P-type doped region.
  • the pixel region (display region) 2 of the array substrate and the peripheral driving region 3 located around the pixel region 2 an N-TFT or a P-TFT may be formed, respectively.
  • the pixel region 2 and the peripheral driving region 3 may form the same type of polysilicon TFT, and may also form different types of polysilicon TFTs.
  • a P-TFT is formed in the peripheral driving region 3, and an N-TFT is formed in the pixel region 2.
  • the preparation method of this embodiment may include the following steps.
  • Al forming a polysilicon layer on the substrate, forming an active layer by a patterning process, doping the active layer of the N-TFT or the P-TFT by a first doping process, forming an N-type doped region or a P-type Doped area.
  • the method of forming a polysilicon layer on the substrate 1 may be performed by directly forming a polysilicon layer on the substrate, or by forming an amorphous silicon (a-Si) layer on the substrate, and then crystallizing the amorphous silicon. Processing to obtain a polysilicon layer.
  • the method of directly forming the polysilicon layer or the amorphous silicon layer may specifically employ chemical vapor deposition or the like.
  • the method of crystallizing amorphous silicon may include solid phase crystallization (SPC), Laser crystallization or metal induced crystallization (MIC).
  • the active layer is formed by a patterning process, and a specific example of the patterning process includes:
  • A101 coating a photoresist on the substrate forming the polysilicon layer
  • A102 Exposing and developing the photoresist-coated substrate by a mask process to form a photolithography including a photoresist completely reserved region 403, a photoresist portion remaining region 402, and a photoresist completely non-retained region 401.
  • the glue pattern is etched by the etching process to the polysilicon layer of the photoresist non-retained region 401 to form an active layer 201 of the N-TFT and an active layer 301 of the P-TFT, as shown in FIG.
  • the mask process in step A102 can be specifically implemented by using a two-tone mask such as a halftone mask, a gray scale mask or a single slit mask.
  • the photoresist for removing a portion of the remaining region 402 may be specifically implemented by an ashing process. In this step, the photoresist completely remaining region 403 is also thinned and partially retained.
  • step A104 doping the doping process to dope the exposed active layer in step A103 after removing the photoresist portion remaining region 402 to form a doped region 202.
  • the doping process can be performed by ion implantation or the like. If an N-type doped region is formed first, the doping element in the step may be one or a mixture of a monument, an arsenic or a germanium; if a P-type doped region is formed first, the doping element in the step may be It is one or a mixture of boron and indium.
  • the order of forming the P-type doped region and the N-type doped region has no effect on the method provided in this embodiment. It is only necessary to replace the doping element with the element corresponding to the doped region, and details are not described herein. The description will be made by taking an N-type doped region in which an N-TFT is formed first as an example. The resulting structure is shown in Figure 10.
  • A105 removing the remaining photoresist, forming the active layer 201 of the N-TFT with the N-type doping region 202 and the active layer 301 of the P-TFT.
  • A2 forming a first insulating layer.
  • a first insulating layer 5 is formed on the substrate on which the active layer is formed, and the first insulating layer 5 can be prepared by spin coating, chemical vapor deposition or the like.
  • a schematic diagram of the structure formed is shown in FIG.
  • A3 forming a gate metal layer, and forming a gate by a patterning process.
  • a gate metal layer is formed on the substrate on which the first insulating layer 5 is formed, and a method of forming the gate metal layer may specifically be sputtering or chemical vapor deposition.
  • the gate is formed by a patterning process, and a specific example of the patterning process includes the following steps:
  • A301 coating a photoresist on the substrate formed with the gate metal layer;
  • A302 exposing and developing the photoresist-coated substrate by using a mask process to form a photoresist pattern including a photoresist completely reserved region and a photoresist completely non-retained region;
  • gate metal layer of the photoresist without leaving the region by etching to form gate electrodes 203 and 303.
  • a second insulating layer 6 is formed on the substrate on which the gate is formed, and the second insulating layer 6 can be prepared by spin coating or the like. The resulting structure is shown in Figure 14.
  • the patterning process forms a via hole for forming a source electrode and a drain electrode of the N-TFT, a source electrode and a drain electrode of the P-TFT in a later step, and the source electrode and the drain electrode of the N-TFT pass
  • the via is connected to the active layer of the N-TFT, and the source and drain electrodes of the P-TFT are connected to the active layer of the P-TFT through the via;
  • patterning process includes the following steps.
  • A501 coating a photoresist on the substrate formed with the second insulating layer
  • A502 exposing and developing the photoresist-coated substrate by a mask process to form a photoresist pattern including a photoresist completely reserved region and a photoresist completely non-retained region;
  • the via holes 204, 205, 304, and 305 are formed at predetermined positions of the drain electrodes.
  • the source and drain electrodes of the N-TFT are connected to the active layer of the N-TFT through vias 204 and 205; the source and drain electrodes of the P-TFT are connected to the active layer of the P-TFT through vias 304 and 305.
  • the active layer is doped through the via hole by a second doping process to form a P-type doped region or an N-type doped region; and the formed structure is as shown in FIG. 16.
  • this step is to form an N-type doped region in the step A1, and a P-type doped region is formed in this step as an example.
  • the second doping process can be specifically implemented by ion implantation or the like.
  • the active layer of the P-TFT is doped through the via holes 304, 305 without a mask.
  • the doping element of the P-type doping region 302 may specifically be used in one or a mixture of two of boron and indium.
  • the P-type doping element When the second doping process is performed, since the via holes 204 and 205 are also present on the N-type doping region 202 of the N-TFT, the P-type doping element also enters the N through the via holes 204 and 205 during doping. Type doped region 202, so when the second doping process is performed, the doping amount of the P-type doping element is smaller than the doping amount of the N-type doping element in the first doping process, and the doping amount is controlled. This can be achieved by controlling the conditions of the doping process (eg, voltage, ion beam distribution, etc.).
  • the conditions of the doping process eg, voltage, ion beam distribution, etc.
  • the P-type doping element enters the N-type doped region 202 and is neutralized with the N-type doping element in the N-type doped region 202, the doping amount is smaller than the N-type doping element. Therefore, the doped region 202 still exhibits N-type semiconductor characteristics.
  • the doping amount of the second doping process is 1/3 ⁇ 2/3 of the doping amount of the first doping process, and more preferably, the doping amount of the second doping process is the first doping amount. 1/2 of the doping amount of the hybrid process. Under this preferred condition, the process flow is saved, the cost of the mask is eliminated, and the semiconductor characteristics of the N-doped region and the P-doped region are ensured.
  • A7 forming a source/drain metal layer, and forming a source electrode and a drain electrode by a patterning process.
  • a method of forming a source/drain metal layer on the substrate subjected to the step A6 to form a source/drain metal layer may specifically be a sputtering method, a chemical vapor deposition method or the like.
  • a source electrode and a drain electrode are formed by a patterning process on a substrate on which an active metal leakage layer is formed.
  • a specific example of the patterning process includes the following steps:
  • A701 coating a photoresist on the substrate forming the source/drain metal layer
  • A702 exposing and developing the photoresist-coated substrate by a mask process to form a photoresist pattern including a photoresist completely reserved region and a photoresist completely non-retained region;
  • A703 etching the source/drain metal layer of the photoresist completely non-retained region by an etching process to form source electrodes 206, 306, N-TFT and P-TFT drain electrodes 207 of the N-TFT and P-TFT 307;
  • the source electrode and the drain electrode of the N-TFT and the P-TFT may be prepared first, and then the second insulating layer is prepared, and the gate electrode is further prepared on the second insulating layer. The same effect can be achieved.
  • the method for preparing the above array substrate further includes: A8. Forming a transparent conductive layer, and forming a pixel electrode by a patterning process.
  • a transparent conductive layer is formed on the substrate on which the active electrode and the drain electrode are formed, and the transparent conductive layer may be formed by sputtering, chemical vapor deposition or the like.
  • the material of the transparent conductive layer may be selected from ITO, ruthenium, etc., preferably ruthenium material.
  • ⁇ forming a pixel electrode by a patterning process includes the following steps:
  • ⁇ 802 exposing and developing the photoresist-coated substrate by a mask process to form a photoresist pattern including a photoresist completely reserved region and a photoresist completely non-retained region;
  • an insulating layer may be selectively formed on the source electrode and the drain electrode of the N-TFT and the P-TFT to protect the source and drain electrodes, and the source and drain electrodes are prevented from being subjected to the process of preparing the pixel electrode. influences.
  • a via hole is formed in the insulating layer, and the pixel electrode is connected to the drain electrode of the P-TFT through the via hole.
  • the method further includes:
  • a buffer layer is formed on the substrate.
  • impurities in the substrate can be prevented from entering the polysilicon layer, thereby affecting the performance of the TFT.
  • This embodiment also provides a polysilicon array substrate prepared by the above method.
  • the method for preparing a polysilicon array substrate, the polysilicon array substrate, the display panel and the display device provided by the embodiment doping process through via holes, forming doped regions on both sides of the active layer to form corresponding TFTs, thereby avoiding A special mask is required for the doping process, which reduces the number of masks used in preparing the TFT array substrate and reduces the production cost.
  • the embodiment further provides a display panel including the above polycrystalline silicon array substrate.
  • the embodiment further provides a display device including the above display panel, such as a liquid crystal display device, an organic light emitting diode (OLED) display device, an electronic paper display device, and the like.
  • the display device includes the array substrate of any of the above embodiments.
  • the array substrate and the counter substrate are opposed to each other to form a liquid crystal cell, and the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode of each pixel unit of the array substrate is used to apply an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the liquid crystal display device further includes a backlight that provides backlighting for the array substrate.
  • a pixel electrode of each pixel unit of the array substrate serves as an anode or a cathode for driving the organic light-emitting material to emit light for a display operation.
  • the pixel electrode of each pixel unit of the array substrate is used to drive the movement of charged particles, e.g., in electronic ink, to effect display of the image.

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  • Liquid Crystal (AREA)

Abstract

一种多晶硅薄膜晶体管（TFT）、多晶硅阵列基板及其制备方法、显示装置，为了解决现有技术的制备工艺之中掩膜版数量过多、工艺复杂且成本过高的问题。多晶硅TFT包括掺杂区域（201），该多晶硅TFT的制备方法包括如下步骤：在基板（1）上形成多晶硅层，采用构图工艺形成有源层（2）；形成第一绝缘层（3）；采用构图工艺形成露出有源层（2）的过孔（6），源电极（7）和漏电极（8）通过所述过孔（6）与有源层（2）连接；采用掺杂工艺通过所述过孔（6）对所述有源层（2）进行掺杂，形成掺杂区域（201）；形成源漏金属层，采用构图工艺形成源电极（7）和漏电极（8）。

Description

多晶硅 TFT、 多晶硅阵列基板及其制备方法、 显示装置 技术领域
本发明的实施例涉及一种多晶硅 TFT、 多晶硅阵列基板及其制备方法、 显示装置。 背景技术
薄膜晶体管液晶显示器 ( Thin Film Transistor Liquid Crystal Display, TFT-LCD )具有体积小、 功耗较低、 制造成本相对较低等特点， 已经在当前 平板显示器市场占据主导地位。
对于釆用低温多晶硅（Low Temperature Poly-Silicon, LTPS )作为有源 层的 TFT, 因为 LTPS的迁移率较高等优点， 可以进一步降低成本、 降低不 良率，而且 TFT的性能能够得到提高。但是在现有技术中，在制备 LTPS-TFT 的过程中， 为保证所制备的 N型和 P型的 LTPS-TFT的性能良好， 需要进行 至少 7-9次的曝光显影过程， 这样一来， 不仅增加了制备 LTPS-TFT的流程， 还增加了需要准备掩膜版的数量， 工艺流程过于复杂且成本过高。 发明内容
本发明的实施例提供一种工艺简单， 成本较低的多晶硅 TFT、 多晶硅阵 列基板及其制备方法。
本发明的一个实施例提供了一种多晶硅 TFT 的制备方法， 所述多晶硅
TFT包括掺杂区域， 包括如下步骤： 在基板上形成多晶硅层， 釆用构图工艺 形成有源层； 形成覆盖该有源层的第一绝缘层； 釆用构图工艺在该第一绝缘 层中在以后步骤中将形成源电极和漏电极的预设位置形成露出有源层的过 孔； 釆用掺杂工艺通过所述过孔对所述有源层进行掺杂， 形成掺杂区域； 形 成源漏金属层， 釆用构图工艺形成源电极和漏电极。
例如， 上述多晶硅 TFT的制备方法， 还可以包括： 形成栅金属层， 釆用 构图工艺形成栅极； 在形成栅极的基板上形成第二绝缘层。
在该方法中， 例如， 所述多晶硅 TFT为 N-TFT, 所述掺杂区域可以为 N 型掺杂区域。
在该方法中， 例如， 所述掺杂元素可以为碑、砷、锑中一种或几种混合。 在该方法中， 例如， 所述多晶硅 TFT可以为 P-TFT, 所述掺杂区域可以 为 P型掺杂区域。
在该方法中， 例如， 所述掺杂元素可以为硼、 铟中的一种或两种混合。 本发明的另一个实施例还提供一种釆用上述制备方法得到的多晶硅
TFT。
本发明的再一个实施例还提供一种多晶硅阵列基板， 包括上述的多晶硅
TFT。
本发明的再一个实施例还提供一种多晶硅阵列基板的制备方法， 所述多 晶硅阵列基板包括 N-TFT和 P-TFT, 所述 N-TFT包括 N型掺杂区域， 所述 P-TFT包括 P型掺杂区域， 包括如下步骤： 在基板上形成多晶硅层， 釆用构 图工艺形成有源层， 通过第一次掺杂工艺对 N-TFT或 P-TFT的有源层进行 掺杂，形成 N型掺杂区域或 P型掺杂区域；形成覆盖该有源层的第一绝缘层； 釆用构图工艺在该第一绝缘层中在以后步骤中将形成的 N-TFT 的源电极和 漏电极、 P-TFT的源电极和漏电极的预设位置形成过孔； 釆用第二次掺杂工 艺通过所述过孔对露出的有源层区域进行掺杂，形成 P型掺杂区域或 N型掺 杂区域， 所述第二次掺杂工艺的元素掺杂量小于第一次掺杂工艺中的元素掺 杂量； 形成源漏金属层， 釆用构图工艺形成源电极和漏电极。
例如， 该制备方法还可以包括： 形成栅金属层， 釆用构图工艺形成栅极； 在形成栅极的基板上形成第二绝缘层。
在该方法中， 例如， 第二次掺杂工艺的元素掺杂量可以为第一次掺杂工 艺中的元素掺杂量的 1/3~2/3。
在该方法中， 例如， 第二次掺杂工艺的元素掺杂量可以为第一次掺杂工 艺中的元素掺杂量的 1/2。
在该方法中， 例如，在基板上形成多晶硅层， 釆用构图工艺形成有源层， 通过第一次掺杂工艺对 N-TFT或 P-TFT的有源层进行掺杂， 形成 N型掺杂 区域或 P型掺杂区域的步骤中， 所述构图工艺包括半色调掩膜工艺、 灰阶掩 膜工艺或单狭缝掩膜工艺。
例如， 上述方法还可以包括： 形成第三绝缘层， 釆用构图工艺在以后步 骤中形成像素电极与 TFT的漏极预设的连接位置形成过孔。
例如， 上述方法还可以包括： 形成透明导电层， 釆用构图工艺形成像素 电极。
在该方法中， 例如， 在形成多晶硅层之前还可以包括： 在基板上形成緩 冲层。
在该方法中， 例如， 所述 N-TFT的 N型掺杂区域的掺杂元素可以为磷、 砷、 锑中一种或几种混合。
在该方法中， 例如， 所述 P-TFT的 P型掺杂区域的掺杂元素可以为硼、 铟中的一种或两种混合。
本发明的再一个实施例还提供一种釆用上述制备方法得到的多晶硅阵列 基板。
本发明的再一个实施例还提供一种显示装置， 包括上述的多晶硅阵列基 板。
本发明实施例提供的一种多晶硅 TFT、 多晶硅阵列基板及其制备方法， 通过过孔进行掺杂工艺， 形成有源层两侧的掺杂区域， 以形成对应的 TFT, 从而避免了需要设置专用的掩膜版进行掺杂工艺，减少了制备 TFT阵列基板 时所使用的掩膜版的数量， 降低了生产成本。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1〜图 7为本发明实施例提供的多晶硅 TFT各步骤的截面结构示意图； 图 8为本发明实施例提供的另一种多晶硅 TFT的截面结构示意图； 图 9〜图 18为本发明实施例提供的多晶硅阵列基板各步骤的截面结构示 意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对 象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
实施例 1
该实施例提供了一种多晶硅 TFT的制备方法， 其包括如下步骤。
Sl、 在基板上形成多晶硅层， 釆用构图工艺形成有源层。
构图工艺例如为光刻构图工艺， 例如包括： 在需要被构图的结构层上涂 覆光刻胶层， 使用掩膜板对光刻胶层进行曝光， 对曝光的光刻胶层进行显影 以得到光刻胶图案， 使用光刻胶图案对结构层进行蝕刻， 然后可选地去除光 刻胶图案； 掩膜板例如可以为单色调或双色调等掩模板。
在进行 TFT阵列基板的制备之前， 首先可以对基板 1进行清洗， 从而除 净基板 1上的灰尘， 以避免灰尘导致所制备的 TFT的性能的变差等。 所述基 板 1可以为塑料基板或玻璃基板， 其中玻璃基板可用于制备硬质阵列基板， 塑料基板可以用于制备软质阵列基板。
清洗完成后， 在基板 1上形成多晶硅层， 多晶硅层可以通过在基板上直 接形成多晶硅层的方法， 也可釆用先在基板上形成非晶硅（a-Si )层， 然后 再对非晶硅层进行晶化处理以得到多晶硅层。 直接形成多晶硅层或非晶硅层 的方法具体可以釆用化学气相沉积等。 对非晶硅进行晶化处理的方法可以包 括固相结晶法（SPC ) 、 激光结晶法或者金属诱导结晶法（MIC )等。 形成多晶硅层后， 釆用构图工艺形成有源层 2, 该构图工艺的具体示例 包括以下步骤：
S 101、 在形成有多晶硅层的基板上涂覆光刻胶；
5102、 釆用掩膜工艺对所述涂覆有光刻胶的基板进行曝光和显影， 形成 包括光刻完全胶保留区域和光刻胶完全不保留区域的光刻胶图案；
5103、 釆用刻蚀工艺对光刻胶完全不保留区域的多晶硅层进行刻蚀， 形 成多晶硅 TFT的有源层 2;
5104、 去除剩余的光刻胶。
形成的结构示意图如图 1所示。
S2、 形成第一绝缘层 3。
在形成有源层的基板上形成第一绝缘层 3 , 该第一绝缘层 3可以釆用旋 涂、 化学气相沉积等方法制备。 形成的结构示意图如图 2所示。
53、 形成栅金属层， 釆用构图工艺形成栅极 4。
例如， 釆用化学气相沉积或溅射法在形成第一绝缘层的基板上形成栅金 属层。
釆用构图工艺形成栅极 4, 该构图工艺的一个具体示例包括以下步骤：
5301、 在栅金属层上涂覆光刻胶；
5302、 对所述涂覆有光刻胶的基板进行曝光和显影， 形成包括光刻胶完 全保留区域和光刻胶完全不保留区域的光刻胶图案；
S303、 釆用刻蚀工艺对光刻胶完全不保留区域的栅金属层进行刻蚀， 形 成栅极 4;
S304、 去除剩余的光刻胶。
形成的结构示意图如图 3所示。
54、 形成第二绝缘层 5。
在经过 S3步骤的基板上形成第二绝缘层 5 ,该第二绝缘层 5可釆用旋涂、 化学气相沉积等工艺制备。 形成的结构示意图如图 4所示。
55、 釆用构图工艺在以后步骤中形成源电极和漏电极的预设位置形成露 出有源层的过孔。
在经过 S4步骤的基板上釆用构图工艺形成过孔 6 ,该构图工艺的一个具 体示例包括以下步骤： 5501、 在经过 S4步骤的基板上涂覆光刻胶；
5502、 釆用掩膜工艺对所述涂覆有光刻胶的基板进行曝光和显影， 形成 包括光刻胶完全保留区域和光刻胶完全不保留区域的光刻胶图案；
5503、 釆用刻蚀工艺对光刻胶完全不保留区域的第一绝缘层 3和第二绝 缘层 5进行刻蚀，形成过孔 6,该过孔贯穿所述第一绝缘层 3和第二绝缘层 5;
5504、 去除剩余的光刻胶。
形成的结构示意图如图 5所示。
56、 釆用掺杂工艺通过过孔对所述有源层进行掺杂， 形成掺杂区域 201。 本步骤中的掺杂工艺具体可以釆用离子注入等方法实现。 掺杂后形成的 结构如图 6所示。
57、 形成源漏金属层， 釆用构图工艺形成源电极和漏电极。
在经过掺杂工艺的基板上形成源漏金属层， 例如可以釆用溅射等方法实 现。之后釆用构图工艺形成源电极和漏电极， 该源电极和漏电极通过步骤 S5 中形成的过孔与有源层的掺杂区域连接。 该构图工艺的一个具体示例包括： S701、 在形成源漏金属层的基板上涂覆光刻胶；
5702、 釆用掩膜工艺对所述涂覆有光刻胶的基板进行曝光和显影， 形成 包括光刻胶完全保留区域和光刻胶完全不保留区域的光刻胶图案；
5703、 釆用刻蚀工艺对光刻胶完全不保留区域的源漏金属层进行刻蚀， 形成源电极 7和漏电极 8。
上述多晶硅 TFT可以是 N-TFT或 P-TFT。 当为 N-TFT时 , 掺杂区域为
N型掺杂区域， 掺杂元素具体可以釆用磷、 砷、 锑中一种或几种混合； 当为 P-TFT时， 掺杂区域为 P型掺杂区域， 掺杂元素具体可以釆用为硼、 铟中的 一种或两种混合。
5704、 去除剩余的光刻胶。
形成的结构示意图如图 7所示。
本实施例中 , 也可先制备 TFT的源电极和漏电极， 之后再制备栅极和第 二绝缘层， 制备方法与上述步骤中相同， 在此不再赘述， 形成的结构如图 8 所示。
另夕卜，本实施例还提供了一种通过上述多晶硅 TFT的制备方法得到的多 晶硅 TFT , 多晶硅 TFT的结构如图 7或图 8所示。 与上述多晶硅 TFT对应的， 本实施例还提供一种包括上述多晶硅 TFT 的多晶硅阵列基板。 该多晶硅阵列基板可以用于多种显示装置， 例如液晶显 示装置、 有机发光二极管 （OLED )显示装置、 电子纸显示装置等。
本实施例提供的一种多晶硅 TFT的制备方法和多晶硅 TFT,通过过孔进 行掺杂工艺， 形成有源层两侧的掺杂区域， 以形成对应的 TFT, 从而避免了 需要设置专用的掩膜版进行掺杂工艺，减少了制备 TFT阵列基板时所使用的 掩膜版的数量， 降低了生产成本。
实施例 2
与上述一种多晶硅 TFT的制备方法相对应，本实施例还提供了一种多晶 硅阵列基板的制备方法。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管和像素电极。 例如， 每个像素的薄膜晶体管的栅极与相应 的栅线电连接或一体形成， 源极与相应的数据线电连接或一体形成， 漏极与 相应的像素电极电连接或一体形成。 下面的描述主要针对单个或多个像素单 元进行， 但是其他像素单元可以相同地形成。
本实施的多晶硅阵列基板包括 N-TFT和 P-TFT, 所述 N-TFT包括 N型 掺杂区域， 所述 P-TFT包括 P型掺杂区域。 在该阵列基板的像素区域（显示 区域）2和位于像素区域 2周边的周边驱动区域 3中，可以分别形成有 N-TFT 或 P-TFT。 像素区域 2和周边驱动区域 3可形成相同类型的多晶硅 TFT, 也 可形成不同类型的多晶硅 TFT。 在一个应用中， 在周边驱动区域 3 中形成 P-TFT, 在像素区域 2中形成 N-TFT, 但可以根据实际需要调整形成的 TFT 类型和位置， 在此不作限定。 该实施例的制备方法可以包括如下步骤。
Al、 在基板上形成多晶硅层， 釆用构图工艺形成有源层， 通过第一次掺 杂工艺对 N-TFT或 P-TFT的有源层进行掺杂， 形成 N型掺杂区域或 P型掺 杂区域。
在基板 1上形成多晶硅层的方法可以釆用在基板上直接形成多晶硅层的 方法， 也可釆用先在基板上形成非晶硅（a-Si )层， 然后再对非晶硅进行晶 化处理以得到多晶硅层。 直接形成多晶硅层或非晶硅层的方法具体可以釆用 化学气相沉积等。对非晶硅进行晶化处理的方法可以包括固相结晶法（SPC )、 激光结晶法或者金属诱导结晶法（ MIC )等。
釆用构图工艺形成有源层， 该构图工艺的一个具体示例包括：
A101、 在形成多晶硅层的基板上涂覆光刻胶；
A102、 对涂覆有光刻胶的基板釆用掩膜工艺进行曝光和显影， 形成包括 光刻胶完全保留区域 403、 光刻胶部分保留区域 402和光刻胶完全不保留区 域 401的光刻胶图案， 釆用刻蚀工艺对光刻胶完全不保留区域 401的多晶硅 层进行刻蚀，形成 N-TFT的有源层 201和 P-TFT的有源层 301，如图 9所示。
步骤 A102中掩膜工艺具体可以釆用双色调掩模板，例如半色调掩膜板、 灰阶掩膜板或单狭缝掩膜板， 来实现。
A103、 去除部分保留区域 402的光刻胶， 具体可以釆用灰化工艺实现。 在此步骤中， 光刻胶完全保留区域 403也被减薄， 部分保留。
A104、 釆用掺杂工艺对步骤 A103中去除光刻胶部分保留区域 402后露 出的有源层进行掺杂， 形成掺杂区域 202。
掺杂工艺可以釆用离子注入等方法。 若先形成 N型掺杂区域， 则该步骤 中的掺杂元素可以是碑、砷、锑中一种或几种混合； 若先形成 P型掺杂区域， 则该步骤中的掺杂元素可以是硼、 铟中的一种或两种混合。 P型掺杂区域和 N型掺杂区域的形成顺序对本实施例提供的方法没有影响， 只需将掺杂元素 换成与掺杂区域对应的元素即可， 在此不再赘述， 以下各步骤的介绍均以先 形成 N-TFT的 N型掺杂区域为例进行说明。 形成的结构如图 10所示。
A105、 去除剩余的光刻胶， 形成带有 N型掺杂区域 202的 N-TFT的有 源层 201和 P-TFT的有源层 301。
形成的结构如图 11所示。
A2、 形成第一绝缘层。
在形成有源层的基板上形成第一绝缘层 5, 该第一绝缘层 5可以釆用旋 涂、 化学气相沉积等方法制备。 形成的结构示意图如图 12所示。
A3、 形成栅金属层， 釆用构图工艺形成栅极。
在形成第一绝缘层 5的基板上形成栅金属层， 形成栅金属层的方法具体 可以釆用溅射或化学气相沉积等。形成栅金属层后，釆用构图工艺形成栅极， 该构图工艺的一个具体示例包括以下步骤：
A301、 在形成有栅金属层的基板上涂覆光刻胶； A302、 釆用掩膜工艺对涂覆有光刻胶的基板进行曝光和显影， 形成包括 光刻胶完全保留区域和光刻胶完全不保留区域的光刻胶图案；
A303、 釆用刻蚀工艺对光刻胶完全不保留区域的栅金属层进行刻蚀， 形 成栅极 203、 303。
形成的结构如图 13所示。
A4、 形成第二绝缘层。
在形成栅极的基板上形成第二绝缘层 6, 该第二绝缘层 6可以釆用旋涂 等方法制备。 形成的结构如图 14所示。
A5、 釆用构图工艺在以后步骤中形成 N-TFT的源电极和漏电极、 P-TFT 的源电极和漏电极的预设位置形成过孔，所述 N-TFT的源电极和漏电极通过 所述过孔与所述 N-TFT的有源层连接， 所述 P-TFT的源电极和漏电极通过 所述过孔与所述 P-TFT的有源层连接；
该构图工艺的具体示例包括如下步骤。
A501、 在形成有第二绝缘层的基板上涂覆光刻胶；
A502、 釆用掩膜工艺对涂覆有光刻胶的基板进行曝光和显影， 形成包括 光刻胶完全保留区域和光刻胶完全不保留区域的光刻胶图案；
A503、釆用刻蚀工艺对光刻胶完全不保留区域的第一绝缘层和第二绝缘 层进行刻蚀， 在以后步骤中形成 N-TFT的源电极和漏电极、 P-TFT的源电极 和漏电极的预设位置形成过孔 204、 205、 304和 305。 N-TFT的源电极和漏 电极通过过孔 204和 205与 N-TFT的有源层连接； P-TFT的源电极和漏电极 通过过孔 304和 305与 P-TFT的有源层连接。
A504、 去除剩余的光刻胶。
形成的结构如图 15所示。
A6、 釆用第二次掺杂工艺通过所述过孔对所述有源层进行掺杂， 形成 P 型掺杂区域或 N型掺杂区域； 形成的结构如图 16所示。
本步骤的介绍以在 A1步骤中形成的是 N型掺杂区域， 本步骤中形成 P 型掺杂区域为例进行说明。
第二次掺杂工艺具体可以釆用离子注入等方法实现。利用第一绝缘层 5、 第二绝缘层 6和栅极 203、 303的阻挡作用， 在没有掩膜版的条件下，通过过 孔 304、 305对 P-TFT的有源层进行掺杂， 形成 P型掺杂区域 302。 P型掺杂区域 302的掺杂元素具体可以釆用为硼、 铟中的一种或两种混 合。
在进行第二次掺杂工艺时， 由于 N-TFT的 N型掺杂区域 202上也存在 有过孔 204和 205, 在掺杂时 P型掺杂元素也会通过过孔 204和 205进入 N 型掺杂区域 202, 因此在进行第二次掺杂工艺时， P型掺杂元素的掺杂量要 小于第一次掺杂工艺中 N型掺杂元素的掺杂量，掺杂量的控制具体可以通过 控制掺杂工艺的条件（如电压、 离子束分布等）来实现。 在此条件下， 尽管 P型掺杂元素会进入 N型掺杂区域 202,与 N型掺杂区域 202中的 N型掺杂 元素发生中和， 但由于其掺杂量小于 N型掺杂元素， 因此， 在掺杂区域 202 还是呈现 N型半导体特性。
优选第二次掺杂工艺的掺杂量为第一次掺杂工艺掺杂量的 1/3~2/3,更为 优选地， 第二次掺杂工艺的掺杂量为第一次掺杂工艺掺杂量的 1/2。 在此优 选条件下， 既节省了工艺流程， 省去了掩膜版的费用， 又可以保证 N型掺杂 区域和 P型掺杂区域的半导体特性良好。
A7、 形成源漏金属层， 釆用构图工艺形成源电极和漏电极。
在经过步骤 A6的基板上形成源漏金属层， 形成源漏金属层的方法具体 可以釆用溅射法、 化学气相沉积法等。 对形成有源漏金属层的基板釆用构图 工艺形成源电极和漏电极。 该构图工艺的具体示例包括以下步骤：
A701、 在形成源漏金属层的基板上涂覆光刻胶；
A702、 釆用掩膜工艺对涂覆有光刻胶的基板进行曝光和显影， 形成包括 光刻胶完全保留区域和光刻胶完全不保留区域的光刻胶图案；
A703、 釆用刻蚀工艺对光刻胶完全不保留区域的源漏金属层进行刻蚀， 形成 N-TFT和 P-TFT的源电极 206、 306 , N-TFT和 P-TFT的漏电极 207、 307;
A704、 去除剩余的光刻胶。
形成的结构如图 17所示。
本实施例提供的多晶硅阵列基板的制备方法， 也可先制备 N-TFT 和 P-TFT的源电极和漏电极， 之后再制备第二绝缘层， 在第二绝缘层上再制备 栅极， 也可达到相同的效果。
上述阵列基板的制备方法还包括： A8、 形成透明导电层， 釆用构图工艺形成像素电极。
在形成有源电极和漏电极的基板上形成透明导电层， 形成透明导电层的 方法具体可以釆用溅射、化学气相沉积等。透明导电层的材料可以选择 ITO、 ΙΖΟ等， 优选 ΙΤΟ材料制备。
釆用构图工艺形成像素电极， 该构图工艺的具体示例包括以下步骤：
Α801、 在形成有透明导电层的基板上涂覆光刻胶；
Α802、 釆用掩膜工艺对涂覆有光刻胶的基板进行曝光和显影， 形成包括 光刻胶完全保留区域和光刻胶完全不保留区域的光刻胶图案；
Α803、 釆用刻蚀工艺对光刻胶完全不保留区域的透明导电层进行刻蚀， 形成像素电极；
Α804、 去除完全保留区域的光刻胶。
形成的结构如图 18所示。
在制备像素电极之前， 还可选择性的在 N-TFT和 P-TFT的源电极和漏 电极上制备一层绝缘层， 以保护源漏电极， 防止源漏电极在制备像素电极的 过程中受到影响。 制备绝缘层后， 在绝缘层上形成过孔， 像素电极通过过孔 与 P-TFT的漏电极相连接。
优选地， 在制备多晶硅层之前， 还可以包括：
Α0、 在基板上形成緩冲层。
通过在基板上制备一层緩冲层，可以防止基板中的杂质进入到多晶硅层， 从而影响 TFT的性能。
本实施例还提供一种釆用上述方法制备的多晶硅阵列基板。
本实施例提供的多晶硅阵列基板的制备方法、 多晶硅阵列基板、 显示面 板和显示装置， 通过过孔进行掺杂工艺， 形成有源层两侧的掺杂区域， 以形 成对应的 TFT, 从而避免了需要设置专用的掩膜版进行掺杂工艺， 减少了制 备 TFT阵列基板时所使用的掩膜版的数量， 降低了生产成本。
与上述多晶硅阵列基板相对应的， 本实施例还提供一种包括上述多晶硅 阵列基板的显示面板。
与上述显示面板相对应的， 本实施例还提供一种包括上述显示面板的显 示装置， 例如液晶显示装置、 有机发光二极管 （OLED )显示装置、 电子纸 显示装置等。 该显示装置包括上述任一实施例的阵列基板。 对于液晶显示装置， 阵列基板与对置基板彼此对置以形成液晶盒， 在液 晶盒中填充有液晶材料。 该对置基板例如为彩膜基板。 阵列基板的每个像素 单元的像素电极用于施加电场对液晶材料的旋转的程度进行控制从而进行显 示操作。 在一些示例中， 该液晶显示装置还包括为阵列基板提供背光的背光 源。
对于 OLED显示装置， 阵列基板的每个像素单元的像素电极作为阳极或 阴极用于驱动有机发光材料发光以进行显示操作。
对于电子显示装置， 阵列基板的每个像素单元的像素电极用于驱动例如 电子墨水之中的带电颗粒的运动以实现图像的显示。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种多晶硅薄膜晶体管 （TFT ) 的制备方法， 所述多晶硅 TFT 包括 掺杂区域， 该方法包括如下步骤：
在基板上形成多晶硅层， 釆用构图工艺形成有源层；
形成覆盖该有源层的第一绝缘层；
釆用构图工艺在该第一绝缘层中在以后步骤中将形成源电极和漏电极的 预设位置形成露出有源层的过孔；
釆用掺杂工艺通过所述过孔对所述有源层进行掺杂， 形成掺杂区域； 形成源漏金属层， 釆用构图工艺形成源电极和漏电极。
2、 根据权利要求 1所述的多晶硅 TFT的制备方法， 还包括：
形成栅金属层， 釆用构图工艺形成栅极；
在形成栅极的基板上形成第二绝缘层。
3、 根据权利要求 1~2任一所述的多晶硅 TFT的制备方法， 其中， 所述 多晶硅 TFT为 N-TFT, 所述掺杂区域为 N型掺杂区域。
4、 根据权利要求 3所述的多晶硅 TFT的制备方法， 其中， 所述掺杂元 素为磷、 砷、 锑中一种或几种混合。
5、 根据权利要求 1~2任一所述的多晶硅 TFT的制备方法， 其中， 所述 多晶硅 TFT为 P-TFT, 所述掺杂区域为 P型掺杂区域。
6、 根据权利要求 5所述的多晶硅 TFT的制备方法， 其中， 所述掺杂元 素为硼、 铟中的一种或两种混合。
7、 一种釆用权利要求 1~6任一所述的制备方法得到的多晶硅 TFT。
8、 一种多晶硅阵列基板， 包括权利要求 7所述的多晶硅 TFT。
9、 一种多晶硅阵列基板的制备方法， 所述多晶硅阵列基板包括 N-TFT 和 P-TFT, 所述 N-TFT包括 N型掺杂区域， 所述 P-TFT包括 P型掺杂区域， 包括如下步骤：
在基板上形成多晶硅层， 釆用构图工艺形成有源层， 通过第一次掺杂工 艺对 N-TFT或 P-TFT的有源层进行掺杂， 形成 N型掺杂区域或 P型掺杂区 域；
形成覆盖该有源层的第一绝缘层； 釆用构图工艺在该第一绝缘层中在以后步骤中将形成的 N-TFT 的源电 极和漏电极、 P-TFT的源电极和漏电极的预设位置形成过孔；
釆用第二次掺杂工艺通过所述过孔对露出的有源层区域进行掺杂， 形成 P型掺杂区域或 N型掺杂区域， 所述第二次掺杂工艺的元素掺杂量小于第一 次掺杂工艺中的元素掺杂量；
形成源漏金属层， 釆用构图工艺形成源电极和漏电极。
10、 根据权利要求 9所述的多晶硅阵列基板的制备方法， 还包括： 形成栅金属层， 釆用构图工艺形成栅极；
在形成栅极的基板上形成第二绝缘层。
11、 根据权利要求 10 所述的多晶硅阵列基板的制备方法， 其中， 第二 次掺杂工艺的元素掺杂量为第一次掺杂工艺中的元素掺杂量的 1/3~2/3。
12、根据权利要求 11所述的多晶硅阵列基板的制备方法， 其中， 第二次 掺杂工艺的元素掺杂量为第一次掺杂工艺中的元素掺杂量的 1/2。
13、根据权利要求 10所述的多晶硅阵列基板的制备方法， 其中，在基板 上形成多晶硅层， 釆用构图工艺形成有源层， 通过第一次掺杂工艺对 N-TFT 或 P-TFT的有源层进行掺杂， 形成 N型掺杂区域或 P型掺杂区域的步骤中， 所述构图工艺包括半色调掩膜工艺、 灰阶掩膜工艺或单狭缝掩膜工艺。
14、 根据权利要求 10 所述的多晶硅阵列基板的制备方法， 还包括： 形成第三绝缘层，釆用构图工艺在以后步骤中形成像素电极与 TFT的漏 极预设的连接位置形成过孔。
15、 根据权利要求 10所述的多晶硅阵列基板的制备方法， 还包括： 形成透明导电层， 釆用构图工艺形成像素电极。
16、根据权利要求 10所述的多晶硅阵列基板的制备方法， 其中，在形成 多晶硅层之前还包括： 在基板上形成緩冲层。
17、 根据权利要求 10 所述的多晶硅阵列基板的制备方法， 其中， 所述
N-TFT的 N型掺杂区域的掺杂元素为磷、 砷、 锑中一种或几种混合。
18、 根据权利要求 10 所述的多晶硅阵列基板的制备方法， 其中， 所述 P-TFT的 P型掺杂区域的掺杂元素为硼、 铟中的一种或两种混合。
19、 一种釆用权利要求 9~18任一所述制备方法得到的多晶硅阵列基板。
20、 一种显示装置， 包括权利要求 19所述的多晶硅阵列基板。
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