WO2014015583A1 - 传感器的制造方法 - Google Patents

传感器的制造方法 Download PDF

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Publication number
WO2014015583A1
WO2014015583A1 PCT/CN2012/084775 CN2012084775W WO2014015583A1 WO 2014015583 A1 WO2014015583 A1 WO 2014015583A1 CN 2012084775 W CN2012084775 W CN 2012084775W WO 2014015583 A1 WO2014015583 A1 WO 2014015583A1
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Prior art keywords
pattern
layer
electrode
photoresist
gate
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PCT/CN2012/084775
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English (en)
French (fr)
Inventor
李田生
姜晓辉
徐少颖
谢振宇
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北京京东方光电科技有限公司
京东方科技集团股份有限公司
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Priority to JP2015523366A priority Critical patent/JP6053929B2/ja
Priority to KR1020137035100A priority patent/KR101530143B1/ko
Priority to US14/123,992 priority patent/US9171879B2/en
Priority to EP12881532.1A priority patent/EP2879180B1/en
Publication of WO2014015583A1 publication Critical patent/WO2014015583A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Definitions

  • Embodiments of the present invention relate to a method of fabricating a sensor. Background technique
  • CT computed tomography
  • the sensor 12 includes a plurality of scan lines 15, a plurality of data lines 16, and a plurality of sensing units, each of which includes a photodiode 13 and a field effect transistor ( Field Effect Transistor, FET) 14.
  • the gate of field effect transistor 14 is coupled to a corresponding scan line 15 in sensor 12
  • the source of field effect transistor 14 is coupled to a corresponding data line 16 in sensor 12
  • the drain of transistor 14 is connected.
  • One end of these data lines 16 is connected to the data readout circuit 18 via a connection pin 17.
  • the above sensor operates on the principle that the sensor 12 applies a drive scan signal through the scan line 15 to control the switching state of the field effect transistor 14 of each sense unit.
  • the photocurrent signal generated by the photodiode 13 is sequentially output through the data line 16 connected to the field effect transistor 14 and the data readout circuit 18, by controlling the timing of the signal on the scan line 15 and the data line 16.
  • the collecting function of the photocurrent signal is realized, that is, the control effect of the photocurrent signal generation generated by the photodiode 13 is realized by controlling the switching state of the FET 14.
  • each sensing unit includes a substrate, a gate layer, a gate insulating layer, an active layer, a source and drain layer, a passivation layer, a PIN junction of a PIN photosensor, and a transparent electrode window layer, and a bias line Layer and light barrier layer, etc.
  • TFT Thin Film Transistor
  • Each layer of the sensor is typically formed by a patterning process, and each patterning process typically includes steps such as masking, exposure, development, etching, and stripping. That is, in order to achieve multiple sensors Layers require multiple patterning processes.
  • the above-mentioned sensor having a plurality of layers usually requires 9 to 11 patterning processes at the time of manufacture, so that 9 to 11 mask masks are required correspondingly, thereby making the manufacturing cost of the sensor high, and the manufacturing process is relatively high. Complex, and the production capacity is difficult to upgrade. Summary of the invention
  • a method of manufacturing a sensor comprising:
  • a pattern of transparent electrodes over the bias line in conductive contact with the bias line by a second patterning process, a pattern of photodiodes over the transparent electrode, over the photodiode a pattern of a receiving electrode, a pattern of a source connected to the receiving electrode, a pattern of a drain formed to face the source opposite to the source, and a pattern and a location of a data line connected to the drain a pattern of the ohmic layer above the source and the drain;
  • the method of the invention can reduce the number of use of the mask, reduce the manufacturing cost, simplify the production process, and greatly improve the equipment productivity and the product yield.
  • the light is directly transmitted through the substrate to the photodiode sensor device.
  • the light loss is greatly reduced, the light absorption and utilization ratio is improved, and the imaging quality is improved. The consumption is also reduced.
  • FIG. 1 is a schematic perspective view of a conventional sensor
  • 2a is a top plan view of a sensing unit after a first patterning process in accordance with an embodiment of the present invention
  • 2b is a cross-sectional view of a sensing unit after a first patterning process of a fabrication method in accordance with an embodiment of the present invention
  • 3a is a top plan view of a sensing unit after a second patterning process in accordance with an embodiment of the present invention
  • 3b is a cross-sectional view of the sensing unit after the second patterning process of the manufacturing method according to an embodiment of the present invention
  • FIG. 4a is a top plan view of a sensing unit after a third patterning process in accordance with an embodiment of the present invention
  • 4b is a cross-sectional view of the sensing unit after the third patterning process of the manufacturing method according to an embodiment of the present invention
  • 5a is a top view of a sensing unit after a fourth patterning process of the manufacturing method according to an embodiment of the present invention.
  • Figure 5b is a cross-sectional view of the sensing unit after the fourth patterning process of the fabrication method in accordance with an embodiment of the present invention.
  • the senor may comprise a plurality of types, such as an X-ray sensor or the like.
  • a sensor according to an embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, a plurality of sensing units arranged in an array defined by the gate lines and the data lines; each sensing unit includes a thin film transistor device And photodiode sensor devices.
  • each sensing unit includes a thin film transistor device And photodiode sensor devices.
  • other sensing units may be formed identically.
  • an embodiment of the present invention provides a method for manufacturing a sensor, which includes the following steps:
  • Step 101 A pattern of the bias line 42 is formed on the base substrate 32 by one patterning process.
  • FIG. 2a and Figure 2b for the substrate structure after the first patterning process.
  • Fig. 2b shows only a cross-sectional view of one of the sensing units on the substrate.
  • Figures 3b, 4b and 5b are also shown in a similar manner.
  • the one-time patterning process generally includes steps of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist removal, and the like.
  • Substrate cleaning includes cleaning with deionized water, organic cleaning solution, and the like.
  • the film forming process is used to form a structural layer to be patterned. For example, for a metal layer, a film is formed by physical vapor deposition (for example, magnetron sputtering), and a pattern is formed by wet etching.
  • a non-metal layer a film is formed by chemical vapor deposition, and dried. Etching forms a pattern.
  • the composition process in the following steps is the same as this, and will not be described again.
  • the base substrate 32 may be a glass substrate, a plastic substrate or a substrate of other materials; the bias wire 42 may be made of aluminum-niobium alloy (AlNd), aluminum (A1), or copper.
  • AlNd aluminum-niobium alloy
  • a single layer film of (Cu), molybdenum (Mo), molybdenum-tungsten alloy (MoW) or chromium (Cr) may be a composite film composed of any combination of these metal elements or alloy materials. The thickness of these single or composite films is, for example, between 150 nm and 450 nm.
  • Step 102 forming a bias line 42 and a bias line 42 by a patterning process
  • the pattern of the transparent electrode 41 in electrical contact, the pattern of the photodiode 40 above the transparent electrode 41, the pattern of the receiving electrode 39 on the photodiode 40, the pattern of the source 33 connected to the receiving electrode 39, and the source 33 is a pattern of the drain 34 forming the channel, and a pattern of the data line 31 connected to the drain 34 and a pattern of the ohmic layer 35 over the source 33 and the drain 34.
  • the structure of the substrate after the second patterning process is shown in Figures 3a and 3b.
  • the material of the transparent electrode 41 may be a transparent conductive material such as indium tin oxide (ITO) or indium oxide (IZO).
  • ITO indium tin oxide
  • IZO indium oxide
  • the materials of the source 33, the drain 34, the data line 31, and the receiving electrode 39 may be the same or different. Preferably, they are made of the same material (for example, the specific selection of the material may be the same as the bias line 42), which can be formed by one deposition and etching, thereby making the production process simple and the production efficiency high.
  • the material of the ohmic layer 35 may be a doped semiconductor (n+a-Si).
  • the photodiode 40 may be a PIN type photodiode because the PIN type photodiode has the advantages of small junction capacitance, short transit time, high sensitivity, and the like.
  • the photodiode may also employ other types of photodiodes such as MIS type photodiodes.
  • the above step 102 may include the following steps: 102a. sequentially depositing a transparent conductive material layer, a photodiode material layer, a data line metal layer, and an ohmic material layer, and in the ohmic material layer Coating a photoresist;
  • a positive photoresist is taken as an example.
  • the completely transparent region, the semi-transmissive region and the opaque region of the mask are used for performing full exposure, partial exposure and non-exposure operations on the photoresist, after development.
  • a photoresist complete removal region, a photoresist partial removal region, and a photoresist complete retention region are obtained.
  • the photoresist is substantially completely retained in the photoresist complete retention area.
  • Depositing the photodiode material layer on the transparent conductive material layer may specifically include sequentially depositing: a P-type semiconductor layer (p+a-Si), an I-type semiconductor layer (a-Si), and an N-type semiconductor layer (n+a-Si). . More specifically, a P-type semiconductor is deposited over the transparent electrode material, an I-type semiconductor is deposited over the P-type semiconductor, and an N-type semiconductor is deposited over the I-type semiconductor.
  • the semi-transmissive region of the mask corresponds to a region where the channel is formed, and the opaque region corresponds to a region where the source 33, the drain 34, the data line 31, and the receiving electrode 39 are formed.
  • the mask used may be a two-tone mask (for example, a gray tone or a halftone mask, etc.).
  • Step 103 forming a pattern of the active layer 36 on the ohmic layer 35 and the channel by one patterning process, a first passivation layer 43 on the active layer 36 and covering the substrate, and located in the first passivation layer 43
  • the material of the active layer 36 may be a semiconductor material, such as amorphous silicon (a-Si), having a thickness of, for example, between 30 nm and 250 nm;
  • the first passivation layer 43 (and the following The second passivation layer 57 ) may be formed of an inorganic insulating film (for example, silicon nitride or the like) or an organic insulating film (for example, a photosensitive resin material or a non-photosensitive resin material, etc.), and the thickness of the passivation layer is, for example, 1000 nm to 2000 nm.
  • the material of the gate 38 and the gate line 30 may be the same as the bias line 42.
  • the step 103 includes the following steps: 103a. sequentially depositing an active material layer, a first passivation layer, and a gate metal layer;
  • the pattern of the active layer 36 is formed at the time of deposition without being formed by etching, because after the completion of the step 102, there is a broken region on the substrate exposing the substrate 32, due to the active
  • the thinner material layer e.g., between 30 nanometers and 250 nanometers in thickness
  • the thickness of the first passivation layer 43 is thick, no disconnection occurs.
  • Step 104 Form a pattern of the second passivation layer 57 covering the substrate by a patterning process, the second passivation layer 57 having a signal guiding region via.
  • the substrate is formed into a structure as shown in Figs. 5a and 5b after four patterning processes. Since Fig. 5b shows the cross-sectional structure of one of the sensing units of the sensor according to the embodiment of the present invention, the signal guiding region vias located at the periphery of the substrate are not shown in this figure.
  • step 104 is optional, because without performing step 104, the same The object of the invention can be achieved.
  • the method for fabricating a sensor may include only steps 101-103 described above.
  • the above-described method of manufacturing a sensor of the embodiment of the present invention uses a three- or four-time patterning process to fabricate a sensor. Compared with the prior art, not only the number of masks used is reduced, the manufacturing cost is reduced, the production process is simplified, and the equipment productivity and the yield of the products are greatly improved.
  • a sensor having the structure shown in Fig. 5a or 5b is obtained.
  • the sensor includes: a substrate substrate 32, a set of gate lines 30 and a set of data lines 31 arranged in a cross, a plurality of arrays arranged by the set of gate lines 30 and a set of data lines 31 arranged in an array A sensing unit, each of which includes a thin film transistor device and a photodiode sensor device.
  • the photodiode sensor device includes: a bias line 42 over the substrate substrate 32; a transparent electrode 41 over the bias line 42 in conductive contact with the bias line 42; and a photodiode over the transparent electrode 41 40; and a receiving electrode 39 located above the photodiode 40;
  • the thin film transistor device includes: a source 33 located above the photodiode 40 and connected to the receiving electrode 39, a drain 34 located above the photodiode 40 and connected to the adjacent data line 31, the source 33 and The drain 34 is oppositely formed to form a channel; an ohmic layer 35 over the source 33 and the drain 34; an active layer 36 over the ohmic layer 35 and the channel; over the active layer 36 and covering the substrate a first passivation layer 43; and a gate 38 over the first passivation layer 43 above the channel, the gate 38 being connected to the adjacent gate line 30.
  • the senor may further include: a second passivation layer 57 over the gate 38 and covering the substrate, the second passivation layer 57 having a signal guiding region via.
  • the bias lines 42 are in the form of a grid, and each grid corresponds to one sensing unit (as shown in FIG. 3a).
  • the specific shape of the bias line is not limited thereto, for example, it may be parallel to Data line settings, or parallel to the gate line settings, etc.
  • the bias line is prepared on the first layer of the substrate, and when the sensor is in operation, the light is incident from the side of the substrate, so that the light is directly transmitted through the substrate to the photodiode sensor, compared to the existing one.
  • the sensor greatly reduces the light loss, improves the light absorption and utilization rate, improves the image quality, and reduces the energy consumption.

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Abstract

一种传感器的制造方法，包括：在衬底基板（32）上通过第一次构图工艺形成偏压线（42）的图形；通过第二次构图工艺形成透明电极（41）的图形，光电二极管（40）的图形，接收电极（39）的图形，源极（33）的图形，漏极（34）的图形，数据线的图形和欧姆层（35）的图形；通过第三次构图工艺形成有源层（36）的图形，第一钝化层（43）、栅极（38）的图形和栅线的图形。如此减少了掩模板的使用数量，减低了制造成本，简化了生产工艺，提升了产能及产品的良品率。

Description

传感器的制造方法 技术领域
本发明的实施例涉及一种传感器的制造方法。 背景技术
由于保健的需要， 各种无损伤医疗检测方法逐渐受到人们的青睐。 在诸 多的无损伤检测方法中， 计算机断层扫描 （CT )技术已经得到广泛的应用。 在计算机断层扫描设备中必不可缺的一个部分就是传感器。
一种传感器的基本结构如图 1所示， 该传感器 12包括多条扫描线 15、 多条数据线 16以及多个感测单元， 每个感测单元包括一个光电二极管 13和 一个场效应晶体管 (Field Effect Transistor, FET) 14。 场效应晶体管 14的栅极 与传感器 12中相应的扫描线 (Scan Line) 15连接， 场效应晶体管 14的源极与 传感器 12中相应的数据线 (Data Line) 16连接， 光电二极管 13与场效应晶体 管 14的漏极连接。这些数据线 16的一端通过连接引脚 17连接数据读出电路 18。
上述传感器的工作原理为： 传感器 12通过扫描线 15施加驱动扫描信号 来控制每个感测单元的场效应晶体管 14的开关状态。 当场效应晶体管 14被 打开时， 光电二极管 13产生的光电流信号依次通过与场效应晶体管 14连接 的数据线 16、 数据读出电路 18而输出， 通过控制扫描线 15与数据线 16上 的信号时序来实现光电流信号的釆集功能，即通过控制场效应管 14的开关状 态来实现对光电二极管 13产生的光电流信号釆集的控制作用。
目前， 传感器通常釆用薄膜晶体管（ Thin Film Transistor, TFT )平板结 构， 这种传感器在断面上可具有多层。 例如， 每个感测单元包括基板、 栅极 层、 栅极绝缘层、 有源层、 源极与漏极层、 钝化层、 PIN光电传感器的 PIN 结和透明电极窗口层， 以及偏压线层和挡光条层等。 当然， 不同传感器由于 具体结构的差异， 在断面上的具体图层也不完全相同。
传感器的各个图层一般通过构图工艺形成， 而每一次构图工艺通常包括 掩模、 曝光、 显影、 刻蚀和剥离等步骤。 也就是说， 为了实现传感器的多个 图层， 需要釆用多次构图工艺。 例如， 上述具有多层的传感器在制造时通常 需要釆用 9至 11次构图工艺， 这样就对应的需要 9至 11张光罩掩模板， 由 此， 使传感器的制造成本较高， 制造工艺较为复杂， 且产能较难提升。 发明内容
本发明的目的是提供一种传感器的制造方法， 用以解决现有技术中存在 的传感器的制造成本较高，且制造工艺较为复杂，产能较难提升的技术问题。
根据本发明的一个方面， 提供一种传感器的制造方法， 包括：
在衬底基板上通过第一次构图工艺形成偏压线的图形；
通过第二次构图工艺形成位于所述偏压线之上、 与所述偏压线导电接触 的透明电极的图形， 位于所述透明电极之上的光电二极管的图形， 位于所述 光电二极管之上的接收电极的图形、 与所述接收电极连接的源极的图形和与 所述源极相对而置形成沟道的漏极的图形， 以及与所述漏极连接的数据线的 图形和位于所述源极和所述漏极之上的欧姆层的图形； 以及
通过第三次构图工艺形成位于所述欧姆层和所述沟道之上的有源层的图 形、 位于所述有源层之上并覆盖基板的第一钝化层， 以及位于所述第一钝化 层之上、 所述沟道上方的栅极的图形和与所述栅极连接的栅线的图形。
本发明方法， 对比于现有技术， 可减少掩模板的使用数量， 降低制造成 本， 简化了生产工艺， 大大提升了设备产能及产品的良品率。 此外， 制成的 传感器在工作时， 光线经过衬底基板直接透射在光电二极管传感器件上， 对 比于现有技术， 大大减少了光损失， 提高了光的吸收利用率， 成像品质得到 提升， 能耗也有所降低。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有传感器的立体结构示意图；
图 2a为根据本发明实施例的制造方法在第一次构图工艺后的感测单元 俯视图； 图 2b 为根据本发明实施例的制造方法在第一次构图工艺后的感测单元 截面视图；
图 3a为根据本发明实施例的制造方法在第二次构图工艺后的感测单元 俯视图；
图 3b 为根据本发明实施例的制造方法在第二次构图工艺后的感测单元 截面视图；
图 4a为根据本发明实施例的制造方法在第三次构图工艺后的感测单元 俯视图；
图 4b 为根据本发明实施例的制造方法在第三次构图工艺后的感测单元 截面视图；
图 5a为根据本发明实施例的制造方法在第四次构图工艺后的感测单元 俯视图； 和
图 5b 为根据本发明实施例的制造方法在第四次构图工艺后的感测单元 截面视图。 附图标记：
12-传感器 13-光电二极管 14-场效应晶体管 15-扫描线 16-数据线 17-连接引脚
18-数据读出电路 30-栅线 31-数据线
32-衬底基板 33-源极 34-漏极
35-欧姆层 36-有源层 42-偏压线
38-栅极 39-接收电极 40-光电二极管 41-透明电极 57-第二钝化层 43-第一钝化层 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。 除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的术语 "连接" 并非限定于物理的或者机械的连接， 而是可 以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该 相对位置关系也相应地改变。
在本发明以下实施例中， 所述传感器可以包含多种类型， 例如 X射线传 感器等。 本发明一个实施例的传感器包括多条栅线和多条数据线、 由所述栅 线和数据线所界定的多个呈阵列状排布的感测单元； 每个感测单元包括薄膜 晶体管器件和光电二极管传感器件。 在下面的描述和图示中针对单个感测单 元进行， 其他感测单元可以同样地形成。
针对现有传感器中存在的制造成本较高， 制造工艺较为复杂， 产能较难 提升的技术问题， 本发明的实施例提供了一种传感器的制造方法， 其包括以 下步骤：
步骤 101、 在衬底基板 32上通过一次构图工艺形成偏压线 42的图形。 第一次构图工艺后的基板结构请参照图 2a和图 2b所示。为了方便起见， 图 2b仅示出了位于基板上的其中一个感测单元的截面图。 图 3b、 4b和 5b 也以类似的方式示出。
一次构图工艺通常依次包括基板清洗、 成膜、 光刻胶涂覆、 曝光、 显影、 刻蚀、 光刻胶去除等步骤。 基板清洗包括使用去离子水、 有机清洗液进行清 洗等。 成膜工艺用于形成将被构图的结构层。 例如， 对于金属层通常釆用物 理气相沉积方式（例如磁控溅射法）成膜， 并通过湿法刻蚀形成图形； 而对 于非金属层通常釆用化学气相沉积方式成膜， 并通过干法刻蚀形成图形。 以 下步骤中的构图工艺与此相同， 不再赘述。
在本发明的实施例中，所述衬底基板 32可以为玻璃基板、塑料基板或其 他材料的基板； 所述偏压线 42的材质可以为铝钕合金 ( AlNd ) 、 铝（A1 ) 、 铜 （Cu ) 、 钼 （Mo ) 、 钼钨合金 ( MoW )或铬（Cr ) 的单层膜， 也可以为 这些金属单质或合金材料任意组合所构成的复合膜。 这些单层或复合膜的厚 度例如在 150纳米至 450纳米之间。
步骤 102、 通过一次构图工艺形成位于偏压线 42之上、 与偏压线 42导 电接触的透明电极 41的图形，位于透明电极 41之上的光电二极管 40的图形， 位于光电二极管 40之上的接收电极 39的图形、 与接收电极 39连接的源极 33的图形和与源极 33相对而置形成沟道的漏极 34的图形， 以及，与漏极 34 连接的数据线 31的图形和位于源极 33和漏极 34之上的欧姆层 35的图形。 第二次构图工艺后的基板结构请参照图 3a和图 3b所示。
在本发明的实施例中， 透明电极 41的材质可以为诸如氧化铟锡（ ITO ) 或氧化铟辞（IZO )等的透明导电材料。 源极 33、 漏极 34、 数据线 31和接 收电极 39的材质可以相同， 也可以不同。 优选地， 它们釆用相同的材质（例 如， 材质的具体选择可以同偏压线 42 ) , 这样可经一次沉积、 刻蚀形成， 从 而使生产工艺简单、 生产效率较高。 欧姆层 35 的材质可以为掺杂质半导体 ( n+a-Si ) 。
在本发明的一些实施例中， 所述光电二极管 40可为 PIN型光电二极管， 因为 PIN型光电二极管具有结电容小、渡越时间短、灵敏度高等优点。然而， 在本发明的其它实施例中，光电二极管也可以釆用 MIS型光电二极管等其他 类型的光电二极管。
更具体地， 在本发明的一个实施例中， 上述步骤 102可包括以下步骤： 102a.依次沉积透明导电材料层、 光电二极管材料层、 数据线金属层和 欧姆材料层， 并在欧姆材料层之上涂覆光刻胶；
102b. 釆用具有全透光区、 半透光区和不透光区的掩模板对基板上的光 刻胶进行曝光、 显影， 得到具有光刻胶完全去除区、 光刻胶部分去除区和光 刻胶完全保留区的光刻胶图形；
102c. 对基板上的光刻胶完全去除区进行刻蚀； 以及
102d. 对基板的光刻胶部分去除区进行灰化， 去除光刻胶部分去除区中 的光刻胶并且保留光刻胶完全保留区的光刻胶， 刻蚀和然后将光刻胶去除， 形成沟道的图形。
上述描述中以正性光刻胶为例进行说明， 掩模板的完全透光区、 半透光 区和不透光区用于对光刻胶进行完全曝光、 部分曝光和非曝光操作， 显影后 得到光刻胶完全去除区、 光刻胶部分去除区和光刻胶完全保留区。 光刻胶完 全保留区中光刻胶基本全部保留。
在光电二极管 40选用 PIN型光电二极管的情况下，在上述步骤 102a中 , 在透明导电材料层上沉积光电二极管材料层可具体包括依次沉积： P型半导 体层（p+a-Si ) 、 I型半导体层（a-Si )和 N型半导体层（n+a-Si ) 。 更具体 地， 在透明电极材料之上沉积 P型半导体， 在所述 P型半导体之上沉积 I型 半导体， 以及在所述 I型半导体之上沉积 N型半导体。
在上述步骤 102b中，掩膜板的半透光区对应形成沟道的区域，不透光区 对应形成源极 33、 漏极 34、 数据线 31和接收电极 39的区域。 在该步骤中， 所釆用的掩模板可以为双色调掩膜板（例如灰色调或半色调掩膜板等） 。
步骤 103、通过一次构图工艺形成位于欧姆层 35和沟道之上的有源层 36 的图形、 位于有源层 36之上并覆盖基板的第一钝化层 43、 位于第一钝化层 43之上且位于沟道上方的栅极 38的图形、 以及与栅极 38连接的栅线 30的 图形。 第三次构图工艺后的基板结构请参照图 4a和图 4b所示。
在本发明的实施例中，有源层 36的材质可以为半导体材料，例如非晶硅 ( a-Si ) , 厚度例如在 30纳米至 250纳米之间； 第一钝化层 43 (以及下文的 第二钝化层 57 )可以釆用无机绝缘膜 (例如氮化硅等）或有机绝缘膜 (例如 感光树脂材料或者非感光树脂材料等）构成，钝化层的厚度例如在 1000纳米 至 2000纳米之间； 栅极 38和栅线 30的材质可以同偏压线 42。
更具体地， 在本发明的一个实施例中， 上述步骤 103包括以下步骤： 103a.依次沉积有源材料层、 第一钝化层和栅金属层；
103b. 对栅金属进行刻蚀， 形成栅极 38的图形和栅线 30的图形。
在上述步骤 103a中， 有源层 36的图形在沉积时即形成， 而无需经刻蚀 形成，这是因为在步骤 102完成后，基板上存在暴露衬底基板 32的断线区域， 由于有源材料层较薄（例如厚度在 30纳米至 250纳米之间），会在断线区域 产生断线， 因此形成有源层 36图形。 但由于第一钝化层 43的厚度较厚， 则 不会产生断线。
步骤 104、 通过一次构图工艺形成覆盖基板的第二钝化层 57的图形， 所 述第二钝化层 57具有信号引导区过孔。 基板经四次构图工艺后形成图 5a和 图 5b所示的结构。 由于图 5b示出的是才艮据本发明实施例的传感器的其中一 个感测单元的截面结构， 因此位于基板周边的信号引导区过孔未在此图中示 出。
需注意的是， 该步骤 104为可选， 因为在不执行步骤 104的情况下， 同 样可以实现本发明的目的。 因此， 在一个实施例中， 用于制造传感器的方法 可仅包括上述步骤 101~103。
根据以上描述可知， 上述本发明实施例的制造传感器的方法共釆用三次 或四次构图工艺制成传感器。 对比于现有技术， 不仅减少了掩模板的使用数 量， 降低了制造成本， 而且简化了生产工艺， 大大提升了设备产能及产品的 良品率。
根据本发明上述实施例的制造方法， 得到具有如图 5a或 5b所示结构的 传感器。 该传感器包括： 衬底基板 32、 呈交叉排列的一组栅线 30和一组数 据线 31、由所述一组栅线 30和一组数据线 31所界定的多个呈阵列状排布的 感测单元， 每个感测单元包括薄膜晶体管器件和光电二极管传感器件。
所述光电二极管传感器件包括： 位于衬底基板 32之上的偏压线 42; 位 于偏压线 42之上、 与偏压线 42导电接触的透明电极 41 ; 位于透明电极 41 之上的光电二极管 40; 以及， 位于光电二极管 40之上的接收电极 39;
所述薄膜晶体管器件包括： 位于光电二极管 40之上并与接收电极 39连 接的源极 33、 位于光电二极管 40之上并与相邻的数据线 31连接的漏极 34 , 所述源极 33和漏极 34相对而置形成沟道； 位于源极 33和漏极 34之上的欧 姆层 35;位于欧姆层 35和沟道之上的有源层 36;位于有源层 36之上并覆盖 基板的第一钝化层 43; 以及，位于第一钝化层 43之上， 沟道上方的栅极 38, 所述栅极 38与相邻的栅线 30连接。
在一个实施例中，所述传感器还可以进一步包括：位于栅极 38之上并覆 盖基板的第二钝化层 57 , 所述第二钝化层 57具有信号引导区过孔。
该实施例中，偏压线 42为网格状，每一个网格对应一个感测单元 (如图 3a所示） ， 但是， 偏压线的具体形状绝不限于此， 例如， 还可以平行于数据 线设置， 或者平行于栅线设置等。
该传感器中， 偏压线制备于衬底基板的第一层， 传感器在工作时， 光线 从衬底基板一侧入射， 这样光线经过衬底基板直接透射在光电二极管传感器 件上， 对比于现有传感器， 大大减少了光损失， 提高了光的吸收利用率， 成 像品质得到提升， 能耗也有所降低。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种传感器的制造方法， 包括：
在衬底基板上通过第一次构图工艺形成偏压线的图形；
通过第二次构图工艺形成位于所述偏压线之上、 与所述偏压线导电接触 的透明电极的图形， 位于所述透明电极之上的光电二极管的图形， 位于所述 光电二极管之上的接收电极的图形、 与所述接收电极连接的源极的图形和与 所述源极相对而置形成沟道的漏极的图形， 以及与所述漏极连接的数据线的 图形和位于所述源极和所述漏极之上的欧姆层的图形； 以及
通过第三次构图工艺形成位于所述欧姆层和所述沟道之上的有源层的图 形、 位于所述有源层之上并覆盖基板的第一钝化层， 以及位于所述第一钝化 层之上、 所述沟道上方的栅极的图形和与所述栅极连接的栅线的图形。
2、如权利要求 1所述的制造方法，还包括在形成栅极的图形和栅线的图 形之后执行以下步骤：
通过第四次构图工艺形成覆盖基板的第二钝化层的图形， 所述第二钝化 层具有信号引导区过孔。
3、如权利要求 1或 2所述的制造方法， 其中， 所述通过第二次构图工艺 形成透明电极的图形、 光电二极管的图形、 接收电极的图形、 源极的图形、 漏极的图形、 数据线的图形和欧姆层的图形的步骤， 包括：
依次沉积透明导电材料层、 光电二极管材料层、 数据线金属层和欧姆材 料层， 并在所述欧姆材料层之上涂覆光刻胶；
釆用具有全透光区、 半透光区和不透光区的掩模板对基板上的光刻胶进 行曝光、 显影， 得到具有光刻胶完全去除区、 光刻胶部分去除区和光刻胶完 全保留区的光刻胶图形；
对所述衬底基板上的光刻胶完全去除区进行刻蚀； 以及
对所述衬底基板上的光刻胶部分去除区进行灰化， 去除光刻胶部分去除 区中的光刻胶并且保留光刻胶完全保留区的光刻胶， 刻蚀和然后将光刻胶去 除， 形成沟道的图形。
4、如权利要求 3所述的制造方法， 其中， 所述半透光区对应形成沟道的 区域， 所述不透光区对应形成源极、 漏极、 数据线和接收电极的区域。
5、如权利要求 3或 4所述的制造方法， 其中， 沉积光电二极管材料层包 括依次沉积 P型半导体层、 I型半导体层和 N型半导体层。
6、 如权利要求 1-5中任一项所述的制造方法， 其中， 所述通过第三次构 图工艺形成有源层的图形、 第一钝化层、 栅极的图形和栅线的图形的步骤， 包括：
依次沉积有源材料层、 第一钝化层和栅金属层， 形成有源层图形； 对栅金属进行刻蚀， 形成栅极的图形和栅线的图形。
7、 如权利要求 1-6中任一项所述的制造方法， 其中， 所述源极、 漏极、 数据线和接收电极的材质相同。
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