WO2015070665A1 - X射线传感器的阵列基板及其制造方法 - Google Patents

X射线传感器的阵列基板及其制造方法 Download PDF

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WO2015070665A1
WO2015070665A1 PCT/CN2014/086069 CN2014086069W WO2015070665A1 WO 2015070665 A1 WO2015070665 A1 WO 2015070665A1 CN 2014086069 W CN2014086069 W CN 2014086069W WO 2015070665 A1 WO2015070665 A1 WO 2015070665A1
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layer
substrate
forming
gate
gate insulating
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PCT/CN2014/086069
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English (en)
French (fr)
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杨东
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/435,870 priority Critical patent/US9484384B2/en
Publication of WO2015070665A1 publication Critical patent/WO2015070665A1/zh
Priority to US15/260,798 priority patent/US9786711B2/en

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Definitions

  • Embodiments of the present invention relate to an array substrate of an X-ray sensor and a method of fabricating the same.
  • X-ray sensors are widely used not only in the field of medical imaging, but also in other fields such as metal flaw detection.
  • the array substrate of the conventional X-ray sensor generally includes a photodiode sensor device 200 and a thin film transistor device 300 in each pixel region.
  • the main function of the photodiode sensor device is to receive light and convert the optical signal into an electrical signal through the photovoltaic effect
  • the main function of the thin film transistor device is as an electrical signal generated by controlling the switch and transmitting the photovoltaic effect.
  • the working principle of the existing X-ray sensor is that when the X-ray 101 is bombarded on the phosphor 102, the visible light generated by the phosphor 102 is incident on the photodiode sensor device 200 of the array substrate, and the optical signal is converted into a photoelectric effect by the photovoltaic effect.
  • An electrical signal is transmitted to the control circuit of the X-ray sensor by control of the thin film transistor device 300.
  • the entire X-ray sensor array substrate is prepared by using 9 mask processes, and the main process steps are as follows:
  • Step 301 forming a gate electrode 11 on the base substrate 10 by a first masking process
  • Step 302 depositing a gate insulating layer 12 and an active material layer on the substrate of the step 301, and forming an active layer 13 on the array substrate by a second mask process;
  • Step 303 forming a channel barrier layer 14 on the substrate of step 302 by a third mask process
  • Step 304 depositing an ohmic contact layer 29 on the substrate on which step 303 is completed, and forming a source electrode 15, a drain electrode 16, and a light reflecting layer 17 through a fourth mask process;
  • Step 305 forming a semiconductor stack by a fifth mask process on the substrate on which step 304 is completed, for example, an N-type semiconductor 18, an I-type semiconductor 19, a P-type semiconductor 20, and a transparent electrode 21 (ie, a PIN type photodiode sensor) Part of the device);
  • Step 306 depositing a first passivation layer 22 on the substrate of step 305, and forming a first via 23 and a second via 25 in the first passivation layer 22 through a sixth mask process;
  • Step 307 forming a reticle 27, a bias electrode 24 and a signal line 26 through the seventh mask process on the substrate on which step 306 is completed;
  • Step 308 depositing a second passivation layer 28 on the substrate on which step 307 is completed, and forming a passivation layer via hole of the signal guiding region by an eighth mask process (not shown);
  • Step 309 forming a transparent electrode (not shown) of the signal guiding region through the ninth mask process on the substrate on which step 308 is completed.
  • a channel barrier layer needs to be formed on the active layer by a single mask process, and the X-ray sensor array substrate needs to undergo 9 mask processes, and the fabrication process is complicated. And the more the number of mask processes, the higher the manufacturing cost, and the lower the yield of the product.
  • the embodiment of the invention provides an array substrate of an X-ray sensor and a manufacturing method thereof, which reduces the number of mask processes, simplifies the manufacturing process, and improves the yield of the product.
  • Embodiments of the present invention provide a method of fabricating an array substrate of an X-ray sensor, including the steps of forming a thin film transistor device and a photodiode sensor device, wherein the step of forming a thin film transistor device includes: forming a mask process on a substrate substrate a gate electrode; a gate insulating layer is deposited on the substrate substrate forming the gate; the step of forming the photodiode sensor device includes: performing the same mask process on the substrate substrate while forming the gate electrode Forming an ohmic contact layer; forming a semiconductor layer and a transparent electrode by a mask process on the substrate forming the ohmic contact layer; and forming the semiconductor layer while depositing the gate insulating layer on the substrate substrate forming the gate electrode The gate insulating layer is deposited on the base substrate of the transparent electrode.
  • An embodiment of the present invention further provides an array substrate of an X-ray sensor, including a thin film transistor device and a photodiode sensor device connected to the thin film transistor device, wherein the thin film transistor device includes: a gate on the substrate substrate; a gate insulating layer thereon; the photodiode sensor device includes: an ohmic contact layer on the base substrate; a semiconductor layer and a transparent electrode on the ohmic contact layer; and a gate insulating layer on the semiconductor layer and the transparent electrode.
  • FIG. 1 is a cross-sectional structural view of an array substrate of a conventional X-ray sensor
  • FIG. 2 is a schematic view showing the working principle of a conventional X-ray sensor
  • FIG. 3 is a plan view showing the structure of an array substrate of an X-ray sensor according to an embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the array substrate of the X-ray sensor taken along line AA' of FIG. 3 according to an embodiment of the present invention
  • FIG. 5 is a cross-sectional view of the array substrate of the X-ray sensor taken along line BB' of FIG. 3 according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of a substrate after forming a gate in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention
  • FIG. 7 is a schematic diagram of a substrate after forming an ohmic contact layer in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention
  • FIG. 8 is a schematic diagram of a substrate after forming a semiconductor layer and a transparent electrode in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the present invention
  • FIG. 9 is a schematic diagram of a substrate after a gate insulating layer is deposited on a gate in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention.
  • FIG. 10 is a schematic diagram of a substrate after depositing a gate insulating layer and a first passivation layer on a semiconductor layer and a transparent electrode in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention
  • FIG. 11 is a schematic diagram of a substrate after forming an active layer in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the present invention
  • FIG. 12 is a schematic diagram of a substrate after depositing a first passivation layer in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention
  • FIG. 13 is a schematic diagram of a substrate after forming a first via in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention
  • FIG. 14 is a schematic diagram of a substrate after forming a second via and a third via in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the invention
  • 15 is a diagram showing a method of manufacturing an array substrate of an X-ray sensor according to an embodiment of the present invention. a schematic diagram of a substrate after the source and drain;
  • 16 is a schematic diagram of a substrate after a bias line is formed in a method of fabricating an array substrate of an X-ray sensor according to an embodiment of the present invention
  • 17 is a schematic cross-sectional view of an array substrate of an X-ray sensor according to an embodiment of the present invention.
  • a gate pattern and an ohmic contact layer are formed by the same mask process, and a semiconductor layer is formed on the ohmic contact layer by a single mask process.
  • a transparent electrode pattern a gate insulating layer is deposited on the substrate on which the semiconductor layer and the transparent electrode pattern and the gate pattern are formed, and an active layer pattern is formed on the substrate on which the gate insulating layer is formed by a mask process, and an active layer is formed
  • a passivation layer is deposited on the substrate of the layer pattern and a via hole is formed in the passivation layer, and the passivation layer can be used as a channel barrier layer, thereby omitting the formation of the channel barrier layer by a single mask process in the prior art.
  • the gate pattern and the ohmic contact layer are formed by a single mask process, thereby simplifying the manufacturing process of the entire substrate and improving the productivity, and the yield of the product is correspondingly improved due to the simplification of the process.
  • FIG. 3 is a plan view showing an array substrate of an X-ray sensor according to an embodiment of the present invention, wherein 401 is a gate line, 402 is a data line, 403 is a bias line, 404 is a photodiode sensor device, and 405 is a via.
  • 56 is the source of the thin film transistor device
  • 53 is the active layer of the thin film transistor device
  • 408 is the ohmic contact layer of the photodiode sensor device.
  • 4 is a cross-sectional view showing a portion of the AA' portion of FIG. 3, that is, a schematic cross-sectional view showing a portion of a thin film transistor device 400 including a gate electrode 51 on a substrate substrate 50, and a gate electrode 51. Gate insulating layer 52.
  • the thin film transistor device further includes: an active layer 53 on the gate insulating layer 52; a first passivation layer 54 on the active layer 53, a first via 55 is formed in the first passivation layer 54; The drain 57 and the source 56, the drain 57 and the source 56 on the layer 54 are connected to the active layer 53 through the first via 55.
  • the gate insulating layer 52 covers the gate electrode 51 and the substrate substrate 50 not covered by the gate electrode; the active layer 53 is formed on the gate insulating layer 52, and The active layer 53 overlaps the gate electrode 51; the first passivation layer 54 covers the active layer 53 and the gate insulating layer 52 not covered by the active layer 53, and the first passivation layer 54 is provided with the first passivation layer 54 A hole 55 through which the source 56 and the drain 57 formed on the first passivation layer 54 are connected to the active layer 53 through the first via 55.
  • the base substrate 50 may be a glass substrate, a plastic substrate or other kinds of substrates; the active layer 53 may be mainly formed of a-Si; the first passivation layer 54 may be an inorganic insulating film such as silicon nitride or the like. Or an organic insulating film, such as a resin material or the like.
  • Figure 5 is a cross-sectional view showing a portion of the BB' portion of Figure 3, that is, a cross-sectional view of a portion of the photodiode sensor device.
  • the photodiode sensor device 404 includes:
  • a second via 64 and a third via 65 are also formed in the gate insulating layer 52 and the first passivation layer 54.
  • the photodiode sensor device 404 further includes a bias line 66 on the first passivation layer 54 that is connected to the ohmic contact layer 61 through the second via 64, through the third via 65 and transparent The electrodes 63 are connected.
  • the transparent electrode 63 is on the semiconductor layer 62; the gate insulating layer 52 covers the transparent electrode 63, the ohmic contact layer 61 not covered by the transparent electrode, and the base substrate 50 not covered by the ohmic contact layer 61; the first passivation layer 54 is formed on the gate insulating layer 52; a second via hole 64 and a third via hole 65 are formed in the gate insulating layer 52 and the first passivation layer 54, and are formed on the second via hole and the third via hole.
  • the bias line 66 is connected to the ohmic contact layer 61 and the transparent electrode 63 through the second via hole and the third via hole, respectively.
  • the semiconductor layer 62 may include three layers, which are sequentially an N-type amorphous silicon layer formed on the ohmic contact layer 61, and an intrinsic amorphous silicon layer formed on the N-type amorphous silicon layer, which is formed in the intrinsic
  • the P-type amorphous silicon layer on the amorphous silicon layer, that is, the photodiode sensor device 404 is a PIN type photodiode.
  • photodiode sensor device 404 can also be formed as a MIS type photodiode.
  • the gate pattern of the thin film transistor device and the ohmic contact layer of the photodiode sensor device are formed by one mask process, thereby avoiding the use of the mask process for forming the gate pattern and using the mask process multiple times.
  • Ohmic contact layer reducing the number of mask processes, Low cost.
  • a first passivation layer is directly deposited on the substrate on which the active layer pattern is formed, and a first via hole is formed in the first passivation layer, so that the drain and the source are connected to the active layer through the first via hole.
  • the step of forming the channel barrier layer by one mask process is omitted, and the channel barrier layer is formed without using a mask process, and the passivation layer replaces the function of the channel barrier layer, preventing the influence of the channel on the subsequent process, and further simplification
  • the production process further reduces production costs.
  • the gate insulating layer covers the gate electrode and the ohmic contact layer, thereby avoiding the problem that the gate electrode and the ohmic contact layer need to separately cover the insulating layer, and the array is lowered.
  • an embodiment of the present invention further provides a method for fabricating an array substrate of an X-ray sensor, the method comprising the steps of forming a thin film transistor device and a photodiode sensor device, including:
  • the steps of forming a thin film transistor device include:
  • Step 701 forming a gate pattern on a substrate by a mask process
  • Step 702 depositing a gate insulating layer on the substrate on which the gate pattern is formed;
  • the steps of forming a photodiode sensor device include:
  • Step 801 forming an ohmic contact layer pattern by the same mask process while forming a gate pattern
  • Step 802 forming a semiconductor layer and a transparent electrode pattern by a mask process on a substrate on which an ohmic contact layer pattern is formed;
  • Step 803 The deposited gate insulating layer covers both the semiconductor layer and the transparent electrode pattern.
  • the gate pattern of the thin film transistor device and the ohmic contact layer of the photodiode sensor device are formed by one mask process, thereby avoiding the use of the mask process for forming the gate pattern and the ohmic contact layer multiple times, reducing masking.
  • the number of molding processes reduces costs.
  • the step of forming a thin film transistor device further includes: forming an active layer by a mask process on a substrate on which the gate insulating layer is formed; depositing a first passivation layer on the substrate on which the active layer is formed, and passing through the mask Forming a first via in the first passivation layer; forming a drain and a source through a mask process on the substrate forming the first via, connecting the drain and the source to the active layer through the first via .
  • the step of forming the photodiode sensor device further comprises: forming the semiconductor layer and the transparent electrode pattern by the same mask process while forming the first via hole in the first passivation layer Forming a second via hole and a third via hole in the gate insulating layer and the first passivation layer; forming the second via hole and the third via hole through the same mask process while forming the drain and the source A bias line pattern is formed on the substrate, and the bias line is connected to the ohmic contact layer through the second via hole, and is connected to the transparent electrode through the third via hole.
  • the first passivation layer is directly deposited on the substrate on which the active layer is formed, the first via hole is formed in the first passivation layer, and the drain and the source are connected to the active layer through the first via hole.
  • the step of forming the channel barrier layer by one mask process is omitted, and the channel barrier layer is formed without using a mask process, and the passivation layer replaces the role of the channel barrier layer to prevent the influence of the subsequent process on the channel. .
  • a second passivation layer is deposited on the entire substrate and formed in the second passivation layer by a mask process Through hole.
  • Step 901 forming a gate electrode 1001 and an ohmic contact layer 1002 on the base substrate 1000 by a first mask process, FIG. 6 shows the substrate after the gate electrode 1001 is formed, and FIG. 7 shows the substrate after the ohmic contact layer 1002 is formed. ;
  • Step 902 forming a semiconductor layer 1003 and a transparent electrode 1004 on the ohmic contact layer 1002 of the base substrate 1000 by a second mask process, and FIG. 8 shows the substrate after the semiconductor layer 1003 and the transparent electrode 1004 are formed;
  • Step 903 depositing a gate insulating layer 1005 on the substrate after forming the gate electrode 1001, the semiconductor layer 1003, and the transparent electrode 1004.
  • FIG. 9 shows the substrate after the gate insulating layer 1005 is deposited on the gate electrode 1001.
  • Step 904 forming an active layer 1006 on the substrate after forming the gate insulating layer by a third mask process, the active layer 1006 and the gate electrode 1001 overlapping each other, and FIG. 11 shows the formation after the active layer 1006 is formed.
  • Step 905 depositing a first passivation layer 1007 on the substrate after forming the active layer 1006, and FIG. 12 shows the substrate after depositing the first passivation layer;
  • Step 906 patterning the first passivation layer 1007 on the active layer 1006 and the gate insulating layer 1005 on the transparent electrode 1004 and the first passivation layer 1007 by a fourth mask process, A first via hole 1008 is formed at a position corresponding to the active layer of the first passivation layer 1007, and a second pass is formed at a position corresponding to the gate insulating layer 1005 and the first passivation layer 1007 and the transparent electrode 1004.
  • the hole 1009 forms a third via 1010 at a position corresponding to the gate insulating layer 1005 and the first passivation layer 1007 and the ohmic contact layer 1002, and FIG. 13 shows the substrate after the first via is formed, and FIG. 14 shows Forming a substrate after the second via and the third via;
  • Step 907 forming a source electrode 1011 and a drain electrode 1012 on the substrate forming the first via hole 1008 by a fifth mask process, and forming a bias line on the substrate forming the second via hole 1009 and the third via hole 1010. 1013, wherein the source 1011 and the drain 1012 are connected to the active layer 1006 through the first via 1008, and the bias line 1013 is connected to the transparent electrode 1004 through the second via 1009 through the third via 1010 and the ohmic contact layer 1002.
  • Connecting, as shown in FIG. 15 is a substrate after forming the source 1011 and the drain 1012
  • FIG. 16 is a substrate after forming a bias line;
  • Step 908 depositing a second passivation layer 1014 on the substrate after forming the bias line, the source and the drain, and forming the second passivation layer 1014 in the second passivation layer 1014 by the sixth mask process. Through hole.
  • FIG. 17 is a cross-sectional structural view of an array substrate according to an embodiment of the present invention, wherein 2101 is a base substrate, 2102 is an ohmic contact layer, 2103 is a semiconductor layer, 2104 is a transparent electrode, and 2105 is a gate insulating layer, 2106
  • 2107 is a bias line
  • 2108 is a gate
  • 2109 is an active layer
  • 2110 is a drain
  • 2111 is a source
  • 2112 is a second passivation layer.
  • each mask process in the embodiment of the present invention may include a process of substrate cleaning, photoresist coating, exposure, development, etching, photoresist stripping, etc.; in the embodiment of the invention, the substrate may be glass. Substrate, plastic substrate or other kind of substrate.
  • the main component of the material of the active layer is a-Si.
  • the first passivation layer may be an inorganic insulating film such as silicon nitride or the like, or an organic insulating film such as a resin material.
  • deposition when a gate electrode and an ohmic contact layer are formed, deposition may be performed by, for example, a chemical vapor deposition method, a physical vapor deposition method may be used for depositing a metal layer, and a non-metal layer may be used when depositing a metal layer. Chemical vapor deposition method. A dry pattern is formed for the passivation layer and the gate insulating layer to form a desired pattern.
  • the gate electrode and the ohmic contact layer are formed in one mask process in the implementation of the present invention, thereby effectively reducing the number of mask processes, and directly
  • the source layer, the transparent electrode and the semiconductor layer are covered with a passivation layer, and the passivation layer can effectively block the light, so that the channel leakage current is greatly reduced, and the trench is prevented from being formed by using a mask process again.
  • the channel barrier layer is further provided with an additional passivation layer on the source, drain and bias lines to further block light and further reduce the channel drain electrode.
  • Embodiments of the present invention provide a method for fabricating an array substrate of an X-ray sensor.
  • a gate and an ohmic contact layer are formed by the same mask process, and are once passed.
  • the mask process forms a semiconductor layer and a transparent electrode on the ohmic contact layer, deposits a gate insulating layer on the substrate on which the semiconductor layer, the transparent electrode, and the gate are formed, and forms an active layer, and further on the active layer Depositing a passivation layer, eliminating the masking process of forming a channel barrier layer in the prior art, the passivation layer functions as a channel barrier layer, preventing the influence of subsequent processes on the channel; and forming in the prior art
  • the gate electrode and the ohmic contact layer respectively require a mask process.
  • the positions of the gate electrode and the ohmic contact layer are changed, a mask process is omitted, the manufacturing process of the array substrate is simplified, and the productivity is improved.
  • the simplification of the process and the yield of the product are correspondingly improved.
  • Embodiments of the present invention also provide an X-ray sensor including an array substrate of an X-ray sensor according to an embodiment of the present invention.

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Abstract

一种X射线传感器的阵列基板及其制造方法，该方法包括形成薄膜晶体管器件和光电二极管传感器器件的步骤，其中形成薄膜晶体管器件的步骤包括：在衬底基板（1000）上通过掩模工艺形成栅极（1001）；在形成栅极（1001）的所述衬底基板（1000）上沉积栅极绝缘层（1005）；形成光电二极管传感器器件的步骤包括：在形成所述栅极（1001）的同时在所述衬底基板（1000）上通过同一次掩模工艺形成欧姆接触层（1002）；在形成欧姆接触层（1002）的基板（1000）上通过掩模工艺形成半导体层（1003）和透明电极（1004）；与在形成栅极（1001）的所述衬底基板（1000）上沉积栅极绝缘层（1005）同时，在形成有所述半导体层（1003）和透明电极（1004）的所述衬底基板上沉积所述栅极绝缘层。通过同一次掩模工艺形成了栅极图形和欧姆接触层，且采用钝化层替代了沟道阻挡层，从而减少了掩模工艺次数，简化了制造工艺，提高了产能以及良品率。

Description

X射线传感器的阵列基板及其制造方法 技术领域
本发明的实施例涉及一种X射线传感器的阵列基板及其制造方法。
背景技术
目前，X射线传感器不仅广泛应用于医学影像领域，而且也广泛应用于金属探伤等其他领域。
如图1和图2所示，现有X射线传感器的阵列基板在每个像素区通常包括：光电二极管传感器器件200和薄膜晶体管器件300。其中，光电二极管传感器器件的主要作用是接收光，并通过光伏效应把光信号转换成电信号，而薄膜晶体管器件的主要作用是作为控制开关和传递光伏效应产生的电信号。
现有X射线传感器的工作原理为：当X射线101轰击在荧光粉102上时，由荧光粉102产生的可见光线入射到阵列基板的光电二极管传感器器件200上，通过光伏效应将光信号转换为电信号，该电信号通过薄膜晶体管器件300的控制而传输到X射线传感器的控制电路。
示例性地，现有技术中采用9次掩模工艺完成整个X射线传感器阵列基板的制备，主要工艺步骤为：
步骤301，在衬底基板10上通过第一次掩模工艺形成栅极11；
步骤302，在完成步骤301的基板上沉积栅极绝缘层12以及有源材料层，并通过第二次掩模工艺在阵列基板上形成有源层13；
步骤303，在完成步骤302的基板上通过第三次掩模工艺形成沟道阻挡层14；
步骤304，在完成步骤303的基板上沉积欧姆接触层29，并通过第四次掩模工艺形成源极15、漏极16和反光层17；
步骤305，在完成步骤304的基板上通过第五次掩模工艺形成半导体叠层，例如，N型半导体18、I型半导体19、P型半导体20，和透明电极21(即PIN型光电二极管传感器器件的一部分)；
步骤306，在完成步骤305的基板上沉积第一钝化层22，并通过第六次掩模工艺形成第一钝化层22中的第一过孔23和第二过孔25；
步骤307，在完成步骤306的基板上通过第七次掩模工艺形成光罩27、偏压电极24和信号线26；
步骤308，在完成步骤307的基板上沉积第二钝化层28，并通过第八次掩模工艺形成信号引导区的钝化层过孔(图中未示出)；
步骤309，在完成步骤308的基板上通过第九次掩模工艺形成信号引导区的透明电极(图中未示出)。
现有技术中制造X射线传感器阵列基板时，需要经一次掩模工艺在有源层的上方形成沟道阻挡层，并且制造X射线传感器阵列基板需要经过9次掩模工艺，制作工艺较为复杂，并且掩模工艺次数越多，制造成本就越高，产品的良品率也就相应降低。
发明内容
本发明实施例提供一种X射线传感器的阵列基板及其制造方法，减少了掩模工艺次数，简化了制作工艺，提高了产品的良品率。
本发明实施例提供了一种X射线传感器的阵列基板的制造方法，包括形成薄膜晶体管器件和光电二极管传感器器件的步骤，其中形成薄膜晶体管器件的步骤包括：在衬底基板上通过掩模工艺形成栅极；在形成栅极的所述衬底基板上沉积栅极绝缘层；形成光电二极管传感器器件的步骤包括：在形成所述栅极的同时在所述衬底基板上通过同一次掩模工艺形成欧姆接触层；在形成欧姆接触层的基板上通过掩模工艺形成半导体层和透明电极；与在形成栅极的所述衬底基板上沉积栅极绝缘层同时，在形成有所述半导体层和透明电极的所述衬底基板上沉积所述栅极绝缘层。
本发明实施例还提供了一种X射线传感器的阵列基板，包括薄膜晶体管器件和与薄膜晶体管器件相连的光电二极管传感器器件，其中所述薄膜晶体管器件包括：衬底基板上的栅极；栅极之上的栅极绝缘层；所述光电二极管传感器器件包括：衬底基板上的欧姆接触层；欧姆接触层上的半导体层和透明电极；半导体层和透明电极上的栅极绝缘层。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为现有的X射线传感器的阵列基板的截面结构图；
图2为现有的X射线传感器的工作原理示意图；
图3为根据本发明实施例的X射线传感器的阵列基板的结构平面图；
图4为根据本发明实施例的X射线传感器的阵列基板沿图3的AA'线剖取的截面图；
图5为根据本发明实施例的X射线传感器的阵列基板沿图3的BB'线剖取的截面图；
图6为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成栅极后的基板的示意图；
图7为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成欧姆接触层后的基板的示意图；
图8为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成半导体层和透明电极后的基板的示意图；
图9为根据本发明实施例的X射线传感器的阵列基板的制造方法中在栅极上沉积栅极绝缘层后的基板的示意图；
图10为根据本发明实施例的X射线传感器的阵列基板的制造方法中在半导体层和透明电极上沉积栅极绝缘层以及第一钝化层后的基板的示意图；
图11为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成有源层后的基板的示意图；
图12为根据本发明实施例的X射线传感器的阵列基板的制造方法中沉积第一钝化层后的基板的示意图；
图13为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成第一过孔后的基板的示意图；
图14为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成第二过孔和第三过孔后的基板的示意图；
图15为根据本发明实施例的X射线传感器的阵列基板的制造方法中形 成源极和漏极后的基板的示意图；
图16为根据本发明实施例的X射线传感器的阵列基板的制造方法中形成偏压线后的基板的示意图；以及
图17为根据本发明实施例的X射线传感器的阵列基板的截面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明实施例的形成薄膜晶体管器件和光电二极管传感器器件的步骤中，通过同一次掩模工艺形成了栅极图形和欧姆接触层，通过一次掩模工艺在欧姆接触层上形成了半导体层和透明电极图形，在形成半导体层和透明电极图形以及栅极图形的基板上沉积栅极绝缘层，且在形成栅极绝缘层的基板上通过掩模工艺形成有源层图形，在形成有有源层图形的基板上沉积钝化层且在钝化层中形成过孔，该钝化层可以用作沟道阻挡层，由此省略了现有技术中通过一次掩模工艺形成沟道阻挡层的步骤，并且本发明实施例中栅极图形和欧姆接触层只需一次掩模工艺形成，从而简化了整列基板的制造工艺，提高了产能，由于工艺的简化，产品的良品率也相应提高。
下面结合说明书附图进一步说明。
图3示出了根据本发明实施例的X射线传感器的阵列基板的平面结构图，其中401为栅线，402为数据线，403为偏压线，404为光电二极管传感器器件，405为过孔，56为薄膜晶体管器件的源极，53为薄膜晶体管器件的有源层，408为光电二极管传感器器件的欧姆接触层。图4示出了图3中AA'部分的结构截面图，也就是示出了薄膜晶体管器件部分的截面示意图，薄膜晶体管器件400包括：衬底基板50上的栅极51，栅极51上的栅极绝缘层52。
薄膜晶体管器件还包括：栅极绝缘层52上的有源层53；有源层53上的第一钝化层54，第一钝化层54中开设有第一过孔55；第一钝化层54上的漏极57和源极56，漏极57和源极56通过第一过孔55与有源层53连接。
在图4示出的薄膜晶体管器件的截面结构图中，栅极绝缘层52覆盖栅极51以及未被栅极覆盖的衬底基板50；有源层53形成在栅极绝缘层52上，且有源层53与栅极51交叠；第一钝化层54覆盖有源层53和未被有源层53覆盖的栅极绝缘层52，而且第一钝化层54中开设有第一过孔55，通过该第一过孔55，形成在第一钝化层54上的源极56和漏极57通过第一过孔55与有源层53连接。
示例性地，衬底基板50可以为玻璃基板、塑料基板或其他种类的基板；有源层53可以主要由a-Si形成；第一钝化层54可以采用无机绝缘膜，如氮化硅等，或有机绝缘膜，如树脂材料等形成。
图5示出了图3中BB'部分的结构截面图，也就是光电二极管传感器器件部分的截面示意图，示例性地，光电二极管传感器器件404包括：
衬底基板50上的欧姆接触层61；欧姆接触层61上的半导体层62和透明电极63；半导体层62和透明电极63上的栅极绝缘层52以及第一钝化层54。
示例性地，在光电二极管传感器器件404中，栅极绝缘层52以及第一钝化层54中还开设有第二过孔64和第三过孔65。进一步地，光电二极管传感器器件404还包括：在第一钝化层54上的偏压线66，偏压线66通过第二过孔64与欧姆接触层61连接，通过第三过孔65与透明电极63连接。
这里，透明电极63在半导体层62上；栅极绝缘层52覆盖透明电极63、未被透明电极覆盖的欧姆接触层61以及未被欧姆接触层61覆盖的衬底基板50；第一钝化层54形成在栅极绝缘层52上；栅极绝缘层52以及第一钝化层54中开设有第二过孔64和第三过孔65，形成于第二过孔和第三过孔上的偏压线66通过第二过孔和第三过孔分别与欧姆接触层61和透明电极63连接。
示例性地，半导体层62可包括三层，依次为形成于欧姆接触层61上的N型非晶硅层，形成于N型非晶硅层上的本征非晶硅层，形成于本征非晶硅层上的P型非晶硅层，即光电二极管传感器器件404为PIN型光电二极管。示例性地，光电二极管传感器器件404也可以形成为MIS型光电二极管。
根据本发明实施例的X射线传感器的阵列基板中，通过一次掩模工艺形成薄膜晶体管器件的栅极图形和光电二极管传感器器件的欧姆接触层，避免了多次使用掩模工艺形成栅极图形和欧姆接触层，减少掩模工艺的次数，降 低了成本。
进一步地，在形成有源层图形的基板上直接沉积第一钝化层，在第一钝化层中形成第一过孔，使漏极和源极通过第一过孔与有源层连接，省略了通过一次掩模工艺形成沟道阻挡层的步骤，不使用掩模工艺形成沟道阻挡层，钝化层替代了沟道阻挡层的作用，防止在后续工艺对沟道的影响，进一步简化了生产工艺，进一步降低了生产成本。
而且，在根据本发明实施例的X射线传感器的阵列基板中，栅极绝缘层覆盖在栅极和欧姆接触层上，避免了栅极和欧姆接触层需要分别覆盖绝缘层的问题，降低了阵列基板结构的复杂性。
另一方面，本发明实施例还提供了一种X射线传感器的阵列基板的制造方法，该方法包括形成薄膜晶体管器件和光电二极管传感器器件的步骤，包括：
形成薄膜晶体管器件的步骤，包括：
步骤701：在衬底基板上通过掩模工艺形成栅极图形；
步骤702：在形成栅极图形的基板上沉积栅极绝缘层；
形成光电二极管传感器器件的步骤，包括：
步骤801：在形成栅极图形的同时通过同一次掩模工艺形成欧姆接触层图形；
步骤802：在形成有欧姆接触层图形的基板上通过掩模工艺形成半导体层和透明电极图形；
步骤803：沉积的栅极绝缘层同时覆盖半导体层和透明电极图形。
通过上述实施例可以看出，通过一次掩模工艺形成薄膜晶体管器件的栅极图形和光电二极管传感器器件的欧姆接触层，避免了多次使用掩模工艺形成栅极图形和欧姆接触层，减少掩模工艺的次数，降低了成本。
示例性地，形成薄膜晶体管器件的步骤还包括：在形成栅极绝缘层的基板上通过掩模工艺形成有源层；在形成有源层的基板上沉积第一钝化层，并通过掩模工艺在第一钝化层中形成第一过孔；在形成第一过孔的基板上通过掩模工艺形成漏极和源极，使漏极和源极通过第一过孔与有源层连接。
对应地，形成光电二极管传感器器件的步骤还包括：在第一钝化层中形成第一过孔的同时，通过同一次掩模工艺在形成在半导体层和透明电极图形 上的栅极绝缘层以及第一钝化层中形成第二过孔和第三过孔；在形成漏极和源极的同时通过同一次掩模工艺在形成第二过孔和第三过孔的基板上形成偏压线图形，偏压线通过第二过孔与欧姆接触层连接，通过第三过孔与透明电极连接。
上述实施例中在形成有有源层的基板上直接沉积第一钝化层，在第一钝化层中形成第一过孔，使漏极和源极通过第一过孔与有源层连接，由此省略了通过一次掩模工艺形成沟道阻挡层的步骤，不使用掩模工艺形成沟道阻挡层，钝化层替代了沟道阻挡层的作用，防止在后续工艺对沟道的影响。
示例性地，形成薄膜晶体管器件的漏极和源极以及形成光电二极管传感器器件的偏压线图形后，在整个基板上沉积第二钝化层，通过掩模工艺在第二钝化层中形成过孔。
示例性地，下面结合附图，对根据本发明实施例的X射线传感器的阵列基板的制造方法进行说明，该方法包括：
步骤901：通过第一次掩模工艺在衬底基板1000上形成栅极1001和欧姆接触层1002，图6示出了形成栅极1001后的基板，图7为形成欧姆接触层1002后的基板；
步骤902：通过第二次掩模工艺在衬底基板1000的欧姆接触层1002上形成半导体层1003和透明电极1004，图8示出了形成半导体层1003和透明电极1004后的基板；
步骤903：在形成栅极1001、半导体层1003和透明电极1004后的基板上沉积栅极绝缘层1005，图9示出了在栅极1001上沉积栅极绝缘层1005后的基板，图10示出了在半导体层1003和透明电极1004上沉积栅极绝缘层1005后的基板；
步骤904：通过第三次掩模工艺在形成栅极绝缘层后的基板上形成有源层1006，有源层1006与栅极1001彼此交叠，图11示出了形成有源层1006后的基板；
步骤905：在形成有源层1006后的基板上沉积第一钝化层1007，图12示出了沉积第一钝化层后的基板；
步骤906：通过第四次掩模工艺对有源层1006上的第一钝化层1007和透明电极1004上的栅极绝缘层1005以及第一钝化层1007进行构图工艺，其 中，在第一钝化层1007的与有源层对应的位置处形成第一过孔1008，在栅极绝缘层1005和第一钝化层1007与透明电极1004对应的位置处形成第二过孔1009，在栅极绝缘层1005和第一钝化层1007与欧姆接触层1002对应的位置处形成第三过孔1010，图13示出了形成第一过孔后的基板，图14示出了形成第二过孔和第三过孔后的基板；
步骤907：通过第五次掩模工艺在形成第一过孔1008的基板上形成源极1011和漏极1012，在形成第二过孔的1009和第三过孔1010的基板上形成偏压线1013，其中源极1011和漏极1012通过第一过孔1008与有源层1006连接，偏压线1013通过第二过孔1009与透明电极1004连接，通过第三过孔1010与欧姆接触层1002连接，如图15所示为形成源极1011和漏极1012后的基板，图16所示为形成偏压线后的基板；
步骤908：在形成偏压线、源极和漏极后的基板上沉积第二钝化层1014，在第二钝化层1014中通过第六次掩模工艺形成第二钝化层1014中的过孔。
如图17所示，为本发明实施例中阵列基板的截面结构图，其中2101为衬底基板，2102为欧姆接触层，2103为半导体层，2104为透明电极，2105为栅极绝缘层，2106为第一钝化层，2107为偏压线，2108为栅极，2109为有源层，2110为漏极，2111为源极，2112为第二钝化层。
示例性地，本发明实施例中每一次掩模工艺可以包括基板清洗，光刻胶涂覆，曝光、显影、刻蚀、光刻胶剥离等工艺；本发明实施例中衬底基板可以为玻璃基板、塑料基板或其他种类的基板。有源层的材料的主要成分为a-Si。第一钝化层可以采用无机绝缘膜，如氮化硅等，或有机绝缘膜，如树脂材料等。
在本发明的实施例中，示例性地，形成栅极和欧姆接触层时，可以采用例如化学气相沉积的方法进行沉积，沉积金属层时可以采用物理气相沉积方法，沉积非金属层时可以采用化学气相沉积方法。对于钝化层和栅极绝缘层采用干法刻蚀的方法形成所需图形。
从本发明实施例X射线传感器的阵列基板的制造方法中可以看出，本发明实施中在一次掩模工艺中形成栅极和欧姆接触层，有效减少了掩模工艺的次数，并且直接在有源层、透明电极和半导体层上覆盖钝化层，钝化层可有效遮挡光线，使得沟道漏电流大大减少，避免了再使用一次掩模工艺形成沟 道阻挡层，而且进一步在源极、漏极和偏压线设置有另外的钝化层，进一步遮挡了光线，进一步减小了沟道漏电极。
本发明实施例提供了一种X射线传感器的阵列基板的制造方法，在形成薄膜晶体管器件和光电二极管传感器器件的步骤中，通过同一次掩模工艺形成了栅极和欧姆接触层，且通过一次掩模工艺在欧姆接触层上形成了半导体层和透明电极，在形成有半导体层、透明电极以及栅极的基板上沉积栅极绝缘层，且形成有源层，且进一步地在有源层上沉积钝化层，省去了现有技术中沟道阻挡层的掩模工艺形成过程，钝化层起到沟道阻挡层的作用，防止后续工艺对沟道的影响；并且现有技术中形成栅极和欧姆接触层分别需要一次掩模工艺，本发明实施例中，改变了栅极和欧姆接触层的位置，省略了一次掩模工艺，简化了阵列基板的制造工艺，提高了产能，由于工艺的简化，产品的良品率也相应提高。
本发明实施例还提供了一种X射线传感器，该传感器包含根据本发明实施例的X射线传感器的阵列基板。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
本申请要求于2013年11月14日递交的中国专利申请第201310566270.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (17)

  1. 一种X射线传感器的阵列基板的制造方法，包括形成薄膜晶体管器件和光电二极管传感器器件的步骤，其中形成薄膜晶体管器件的步骤包括：
    在衬底基板上通过掩模工艺形成栅极；
    在形成栅极的所述衬底基板上沉积栅极绝缘层；
    形成光电二极管传感器器件的步骤包括：
    在形成所述栅极的同时在所述衬底基板上通过同一次掩模工艺形成欧姆接触层；
    在形成欧姆接触层的基板上通过掩模工艺形成半导体层和透明电极；
    与在形成栅极的所述衬底基板上沉积栅极绝缘层同时，在形成有所述半导体层和透明电极的所述衬底基板上沉积所述栅极绝缘层。
  2. 如权利要求1所述的方法，其中所述形成薄膜晶体管器件的步骤还包括：
    在形成栅极绝缘层的所述衬底基板上通过掩模工艺形成有源层；
    在形成所述有源层的所述衬底基板上沉积第一钝化层，并通过掩模工艺在第一钝化层中形成第一过孔；
    在形成第一过孔的所述衬底基板上通过掩模工艺形成漏极和源极，使所述漏极和所述源极通过所述第一过孔与有源层连接。
  3. 如权利要求2所述的方法，其中所述第一钝化层还覆盖形成有所述半导体层、所述透明电极以及所述栅极绝缘层的衬底基板，且形成光电二极管传感器器件的步骤还包括：
    在于所述第一钝化层中形成第一过孔的同时，通过同一次掩模工艺在形成在设置有所述半导体层和透明电极图形的基板上的所述栅极绝缘层和所述第一钝化层中形成第二过孔和第三过孔；
    在形成漏极和源极的同时通过同一次掩模工艺在形成第二过孔和第三过孔的基板上形成偏压线，所述偏压线通过所述第二过孔与透明电极连接，通过所述第三过孔与所述欧姆接触层连接。
  4. 如权利要求3所述的方法，该方法还包括：
    在形成有偏压线、漏极和源极的整个基板上沉积第二钝化层，通过掩模 工艺与所述第二钝化层中形成过孔。
  5. 如权利要求1-4中任一项所述的方法，其中所述衬底基板是玻璃基板或塑料基板。
  6. 如权利要求1-5中任一项所述的方法，其中所述有源层包括a-Si。
  7. 如权利要求1-6中任一项所述的方法，其中所述第一钝化层采用无机绝缘膜或有机绝缘膜。
  8. 如权利要求1-7中任一项所述的方法，其中所述光电二极管传感器器件的所述半导体层包括：形成在所述欧姆接触层上的N型非晶硅层；形成于所述N型非晶硅层上的本征非晶硅层以及形成在所述于本征非晶硅层上的P型非晶硅层。
  9. 一种X射线传感器的阵列基板，包括薄膜晶体管器件和与薄膜晶体管器件相连的光电二极管传感器器件，其中所述薄膜晶体管器件包括：
    衬底基板上的栅极；
    栅极之上的栅极绝缘层；
    所述光电二极管传感器器件包括：
    衬底基板上的欧姆接触层；
    欧姆接触层上的半导体层和透明电极；
    半导体层和透明电极上的栅极绝缘层。
  10. 如权利要求9所述的阵列基板，其中所述薄膜晶体管器件还包括：
    栅极绝缘层上的有源层；
    有源层上的第一钝化层，所述第一钝化层中开设有第一过孔；
    第一钝化层上的漏极和源极，所述漏极和源极通过所述第一过孔与所述有源层连接。
  11. 如权利要求10所述的阵列基板，其中所述光电二极管传感器器件还包括：
    所述栅极绝缘层上的所述第一钝化层，所述第一钝化层和所述栅极绝缘层中形成有第二过孔和第三过孔。
  12. 如权利要求11所述的阵列基板，其中所述光电二极管传感器器件还包括：
    所述第一钝化层上的偏压线，所述偏压线通过所述第二过孔与所述透明 电极连接，通过所述第三过孔与所述欧姆接触层连接。
  13. 如权利要求12所述的阵列基板，还包括：
    第二钝化层，形成在所述源极、所述漏极和所述偏压线上，其中所述第二钝化层中形成有过孔。
  14. 如权利要求9-12中任一项所述的阵列基板，其中所述衬底基板是玻璃基板或塑料基板。
  15. 如权利要求9-12中任一项所述的阵列基板，其中所述有源层包括a-Si。
  16. 如权利要求9-12中任一项所述的阵列基板，其中所述第一钝化层采用无机绝缘膜或有机绝缘膜。
  17. 如权利要求9-12中任一项所述的阵列基板，其中所述光电二极管传感器器件的所述半导体层包括：形成在所述欧姆接触层上的N型非晶硅层；形成于所述N型非晶硅层上的本征非晶硅层以及形成在所述于本征非晶硅层上的P型非晶硅层。
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