CN102790067A - 一种传感器及其制造方法 - Google Patents
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Abstract
本发明公开了一种传感器及其制造方法,所述传感器包括:衬底基板、呈交叉排列的一组栅线和一组数据线、由所述一组栅线和一组数据线所界定的多个呈阵列状排布的感测单元,每个感测单元包括薄膜晶体管器件和光电二极管传感器件,其中,所述薄膜晶体管器件的沟道区倒置,源极和漏极位于有源层和栅极之间。对比于现有技术,本发明所提出的传感器在制造工艺上减少了掩模板的使用数量,降低了制造成本,简化了生产工艺,大大提升了设备产能及产品的良品率。
Description
技术领域
本发明涉及影像检测技术,特别是涉及一种传感器及其制造方法。
背景技术
随着人们自我保健意识的逐渐增强,各种无损伤医疗检测方法受到人们的青睐。在诸多的无损伤检测方法中,计算机断层扫描技术已经被广泛的应用到我们的现实生活中。在计算机断层扫描设备的组成中,必不可缺的一个部分就是传感器。
传感器的基本结构如图l所示,该传感器12的每个感测单元包括一个光电二极管13和一个场效应晶体管(Field Effect Transistor,FET)14,场效应晶体管14的栅极与传感器12的扫描线(Gate Line)15连接,场效应晶体管14的漏极与传感器12的数据线(Data Line)16连接,光电二极管13与场效应晶体管14的源极连接;数据线16的一端通过连接引脚17连接数据读出电路18。
传感器的工作原理为:传感器12通过扫描线15施加驱动扫描信号来控制场效应晶体管14的开关状态。当场效应晶体管14被打开时,光电二极管13产生的光电流信号依次通过与场效应晶体管14连接的数据线16、数据读出电路18而输出,通过控制扫描线15与数据线16上的信号时序来实现光电流信号的采集功能,即通过控制场效应管14的开关状态来实现对光电二极管13产生的光电流信号采集的控制作用。
目前,传感器通常采用薄膜晶体管(Thin Film Transistor,TFT)平板结构,这种传感器在断面上分为多层,例如:在一个感测单元内包括:基板、栅极层、栅极绝缘层、有源层、源极与漏极层、钝化层、PIN光电传感器的PIN结和透明电极窗口层,以及偏压线层和挡光条层等。当然,不同传感器由于具体结构的差异,在断面上的具体图层也不尽相同。
通常,传感器的各个图层都是通过构图(MASK)工艺形成的,而每一次MASK工艺通常包括掩模、曝光、显影、刻蚀和剥离等工序。现有传感器在制造时通常需要采用9至11次构图工艺,这样就对应的需要9至11张光罩掩模板,传感器的制造成本较高,且制造工艺较为复杂,产能较难提升。
发明内容
本发明的目的是提供一种传感器及其制造方法,用以解决现有技术中存在的传感器的制造成本较高,且制造工艺较为复杂,产能较难提升的技术问题。
本发明传感器,包括:衬底基板、呈交叉排列的一组栅线和一组数据线、由所述一组栅线和一组数据线所界定的多个呈阵列状排布的感测单元,每个感测单元包括薄膜晶体管器件和光电二极管传感器件,其中,
所述薄膜晶体管器件包括:位于衬底基板之上并与栅线连接的栅极;位于栅极之上并覆盖基板的栅极绝缘层;位于栅极绝缘层之上并在栅极上方相对而置形成沟道的源极和漏极,所述漏极与数据线连接;位于源极和漏极之上的欧姆层,以及位于欧姆层和沟道之上的有源层;
所述光电二极管传感器件包括:位于栅极绝缘层之上并与源极连接的接收电极、位于接收电极之上的光电二极管、位于光电二极管之上的透明电极,以及在透明电极的上方与透明电极连接的偏压线。
本发明传感器的制造方法,包括:
在衬底基板上通过一次构图工艺形成栅线的图形、与栅线连接的栅极的图形;
形成覆盖基板的栅极绝缘层,并通过一次构图工艺形成位于栅极绝缘层之上并在栅极上方相对而置形成沟道的源极和漏极的图形、与源极连接的接收电极的图形,以及位于源极和漏极之上的欧姆层的图形;
通过一次构图工艺形成位于欧姆层和沟道之上的有源层的图形、位于接收电极之上的光电二极管的图形,以及位于光电二极管之上的透明电极的图形;
通过一次构图工艺形成第一钝化层的图形,所述第一钝化层在漏极的上方具有第一过孔,在透明电极的上方具有第二过孔;以及有源层和欧姆层的与第一过孔位置对应的第三过孔的图形;
通过一次构图工艺形成位于第一钝化层之上、并穿过第一过孔和第三过孔与漏极连接的数据线的图形,以及位于第一钝化层之上、并穿过第二过孔与透明电极连接的偏压线的图形。
本发明所提出的传感器中,薄膜晶体管器件的沟道区倒置,源极和漏极位于有源层和栅极之间,传感器可共采用六次构图工艺制作形成,对比于现有技术,减少了掩模板的使用数量,降低了制造成本,简化了生产工艺,大大提升了设备产能及产品的良品率。
附图说明
图1为现有传感器的立体结构示意图;
图2a为本发明传感器一实施例的一个感测单元的截面结构示意图(经六次构图工艺);
图2b为本发明传感器一实施例的一个感测单元的俯视结构示意图;
图3为本发明传感器的制造方法一实施例的流程示意图;
图4为本发明方法一实施例第一次构图工艺后一个感测单元的截面视图;
图5为本发明方法一实施例第二次构图工艺后一个感测单元的截面视图;
图6为本发明方法一实施例第三次构图工艺后一个感测单元的截面视图;
图7为本发明方法一实施例第四次构图工艺后一个感测单元的截面视图;
图8为本发明方法一实施例第五次构图工艺后一个感测单元的截面视图。
附图标记:
12-传感器 13-光电二极管(现有技术) 14-场效应晶体管
15-扫描线 16-数据线(现有技术) 17-连接引脚
18-数据读出电路 30-栅线 31-数据线
32-衬底基板 33-源极 34-漏极
35-欧姆层 36-有源层 37-栅极绝缘层
38-栅极 39-接收电极 40-光电二极管
41-透明电极 57-第二钝化层 40a-N型半导体
40c-P型半导体 43-第一钝化层 42-偏压线
43a-第一过孔 43b-第二过孔 403a-第三过孔
401b-I型半导体第一部分 402b-I型半导体第二部分
具体实施方式
为了解决现有技术中存在的传感器的制造成本较高,且制造工艺较为复杂的技术问题,本发明提供了一种传感器及其制造方法。
在本发明以下实施例中,所述传感器包含多种类型,例如X射线传感器等。如图2a、图2b所示,本发明传感器,包括:衬底基板32、呈交叉排列的一组栅线30和一组数据线31、由所述一组栅线30和一组数据线31所界定的多个呈阵列状排布的感测单元,每个感测单元包括薄膜晶体管器件和光电二极管传感器件,其中,
所述薄膜晶体管器件包括:位于衬底基板32之上并与栅线30连接的栅极38;位于栅极38之上并覆盖基板的栅极绝缘层37;位于栅极绝缘层37之上并在栅极38上方相对而置形成沟道的源极33和漏极34,所述漏极34与数据线31连接;位于源极33和漏极34之上的欧姆层35,以及位于欧姆层35和沟道之上的有源层36;
所述光电二极管传感器件包括:位于栅极绝缘层37之上并与源极33连接的接收电极39、位于接收电极39之上的光电二极管40、位于光电二极管40之上的透明电极41,以及在透明电极41的上方与透明电极41连接的偏压线42。
本发明中,所述衬底基板32可以为玻璃基板、塑料基板或其他材料的基板;所述栅线30、栅极38、数据线31、源极33、漏极34、接收电极39和偏压线42的材质可以为铝钕合金(AlNd)、铝(Al)、铜(Cu)、钼(Mo)、钼钨合金(MoW)或铬(Cr)的单层膜,也可以为这些金属材料任意组合所构成的复合膜,厚度通常在150纳米至450纳米之间;欧姆层35的材质为掺杂质半导体(n+a-Si);有源层36的材质为非晶硅(a-Si),厚度在30纳米至250纳米之间;栅极绝缘层37的材质可以为氮化硅,厚度在300纳米至500纳米之间;透明电极41的材质可以为氧化铟锡等。
在图2a所示的实施例中,所述光电二极管为PIN(positive,intrinsic,negative,简称PIN)型光电二极管,包括:N型半导体(n+a-Si)40a、I型半导体第一部分(a-Si)401b、I型半导体第二部分(a-Si)402b和P型半导体(p+a-Si)40c,其中,所述N型半导体40a位于接收电极39之上且与欧姆层35位于同一图层,所述I型半导体第一部分401b位于N型半导体40a之上且与有源层36位于同一图层,所述I型半导体第二部分402b位于I型半导体第一部分401b之上,所述P型半导体40c位于I型半导体第二部分402b之上。PIN型光电二极管具有结电容小、渡越时间短、灵敏度高等优点。在本发明的其它实施例中,光电二极管还可以采用MIS(metal,insulative,semiconductor,金属-绝缘体-半导体,简称MIS)型光电二极管等。
请继续参照图2a所示,所述传感器,还包括:位于透明电极41之上并覆盖基板的第一钝化层43,所述第一钝化层43具有第一过孔43a和第二过孔43b;所述有源层36和欧姆层35具有与第一过孔43a位置对应的第三过孔403a;所述数据线31位于第一钝化层43之上,并穿过第一过孔43a和第三过孔403a与漏极34连接,所述偏压线42位于第一钝化层43之上,并穿过第二过孔43b与透明电极41连接;
位于数据线31和偏压线42之上并覆盖基板的第二钝化层57,所述第二钝化层57具有信号引导区过孔(图2a和图2b为一个感测单元的结构示意图,因此位于基板周边的信号引导区过孔未在图中示出)。
第一钝化层43和第二钝化层57可以采用无机绝缘膜,例如氮化硅等,或有机绝缘膜,例如感光树脂材料或者非感光树脂材料等,厚度通常在1000纳米至2000纳米之间。设置第一钝化层43和第二钝化层57的目的是使整个基板平坦化,并且形成信号连接过孔。与现有技术相同,第一钝化层43和第二钝化层57的图形同样需要经过一次构图工艺。在本发明的其他实施例中,数据线31也可与源极33和漏极34在同一次构图工艺形成,这时,第一钝化层43可以没有第一过孔43a,有源层36和欧姆层35可以没有第三过孔403a,但第一钝化层43仍需经过一次构图工艺形成第二过孔43b。
该优选实施例中,所述源极33、漏极34和接收电极39的材质相同;所述数据线31和偏压线42的材质相同(这两个图层也可采用同一材质),其目的是为了减少构图工艺的次数。
本发明所提出的传感器中,薄膜晶体管器件的沟道区倒置,源极和漏极位于有源层和栅极之间,传感器可共采用六次构图工艺制作形成,对比于现有技术,减少了掩模板的使用数量,降低了制造成本,简化了生产工艺,大大提升了设备产能及产品的良品率。
如图3所示,本发明传感器的制造方法,包括:
步骤101、在衬底基板32上通过一次构图工艺形成栅线30的图形、与栅线30连接的栅极38的图形;第一次构图工艺后的截面结构请参照图4所示。
一次构图工艺通常包括基板清洗、成膜、光刻胶涂覆、曝光、显影、刻蚀、光刻胶剥离等工序;对于金属层通常采用物理气相沉积方式(例如磁控溅射法)成膜,通过湿法刻蚀形成图形,而对于非金属层通常采用化学气相沉积方式成膜,通过干法刻蚀形成图形,以下步骤道理相同,不再赘述。
步骤102、形成覆盖基板的栅极绝缘层37,并通过一次构图工艺形成位于栅极绝缘层37之上并在栅极38上方相对而置形成沟道的源极33和漏极34的图形、与源极33连接的接收电极39的图形,以及位于源极33和漏极34之上的欧姆层35的图形;第二次构图工艺后的截面结构请参照图5所示。
该步骤中,源极33、漏极34和接收电极39的材质相同,可一次沉积成膜;欧姆层35与N型半导体40a的材质相同(组分比例可根据制造工艺的调整有所差异),均为n+a-Si,在形成欧姆层36时,同时形成位于接收电极39之上、与欧姆层35位于同一图层的N型半导体40a。
步骤103、通过一次构图工艺形成位于欧姆层35和沟道之上的有源层36的图形、位于接收电极39之上的光电二极管40的图形,以及位于光电二极管40之上的透明电极41的图形;透明电极41图形可以单独采用湿法刻蚀形成,也可以与光电二极管40的图形同时通过干法刻蚀形成。第三次构图工艺后的截面结构请参照图6所示。
在本发明方法的一个实施例中,该步骤可具体包括:依次沉积有源材料层、I型半导体层、P型半导体层和透明电极层,通过一次构图工艺形成有源层36、位于N型半导体40a之上且与有源层36位于同一图层的I型半导体第一部分401b、位于I型半导体第一部分401b之上的I型半导体第二部分402b、位于I型半导体第二部分402b之上的P型半导体40c,以及位于P型半导体40c之上的透明电极41。
该步骤中,有源材料层和I型半导体层的材质均为a-Si,可与I型半导体层经一次沉积成膜,有源材料层在刻蚀后一部分形成有源层36,一部分形成I型半导体第一部分401b。在PIN型半导体中,I型半导体较厚,占耗尽层比例较大,绝大部分的入射光在I型半导体内被吸收并产生大量的电子空穴对,而P型半导体和N型半导体均较薄,吸收入射光的比例很小。由于同时形成的有源层36和I型半导体第一部分401b较薄,因此,需要通过I型半导体第二部分402b调节整个I型半导体的厚度。
步骤104、通过一次构图工艺形成第一钝化层43的图形,所述第一钝化层43在漏极34的上方具有第一过孔43a,在透明电极41的上方具有第二过孔43b;以及有源层36和欧姆层35的与第一过孔43a位置对应的第三过孔403a的图形;第四次构图工艺后的截面结构请参照图7所示;
步骤105、通过一次构图工艺形成位于第一钝化层43之上、并穿过第一过孔43a和第三过孔403a与漏极34连接的数据线31的图形,以及位于第一钝化层43之上、并穿过第二过孔43b与透明电极41连接的偏压线42的图形;该步骤中,数据线31和偏压线42的材质相同,可一次沉积成膜。第五次构图工艺后的截面结构请参照图8所示。
此外,在步骤105之后,还进一步包括:
步骤106、通过一次构图工艺形成覆盖基板的第二钝化层57的图形,所述第二钝化层57具有信号引导区过孔(位于基板周边,图中未示出)。第六次构图工艺后的截面结构请参照图2a所示。
可见,本发明传感器的制造方法可共采用六次构图工艺,对比于现有技术,减少了掩模板的使用数量,降低了制造成本,简化了生产工艺,大大提升了设备产能及产品的良品率。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (9)
1.一种传感器,其特征在于,包括:衬底基板、呈交叉排列的一组栅线和一组数据线、由所述一组栅线和一组数据线所界定的多个呈阵列状排布的感测单元,每个感测单元包括薄膜晶体管器件和光电二极管传感器件,其中,
所述薄膜晶体管器件包括:位于衬底基板之上并与栅线连接的栅极;位于栅极之上并覆盖基板的栅极绝缘层;位于栅极绝缘层之上并在栅极上方相对而置形成沟道的源极和漏极,所述漏极与数据线连接;位于源极和漏极之上的欧姆层,以及位于欧姆层和沟道之上的有源层;
所述光电二极管传感器件包括:位于栅极绝缘层之上并与源极连接的接收电极、位于接收电极之上的光电二极管、位于光电二极管之上的透明电极,以及在透明电极的上方与透明电极连接的偏压线。
2.如权利要求1所述的传感器,其特征在于,还包括:位于透明电极之上并覆盖基板的第一钝化层,所述第一钝化层具有第一过孔和第二过孔;所述有源层和欧姆层具有与第一过孔位置对应的第三过孔;所述数据线位于第一钝化层之上,并穿过第一过孔和第三过孔与漏极连接,所述偏压线位于第一钝化层之上,并穿过第二过孔与透明电极连接。
3.如权利要求1所述的传感器,其特征在于,还包括:位于数据线和偏压线之上并覆盖基板的第二钝化层,所述第二钝化层具有信号引导区过孔。
4.如权利要求1~3任一项所述的传感器,其特征在于,所述光电二极管为PIN型光电二极管,包括:N型半导体、I型半导体第一部分、I型半导体第二部分和P型半导体,其中,
所述N型半导体位于接收电极之上且与欧姆层位于同一图层,所述I型半导体第一部分位于N型半导体之上且与有源层位于同一图层,所述I型半导体第二部分位于I型半导体第一部分之上,所述P型半导体位于I型半导体第二部分之上。
5.如权利要求4所述的传感器,其特征在于,所述源极、漏极和接收电极的材质相同;所述数据线和偏压线的材质相同。
6.一种传感器的制造方法,其特征在于,包括:
在衬底基板上通过一次构图工艺形成栅线的图形、与栅线连接的栅极的图形;
形成覆盖基板的栅极绝缘层,并通过一次构图工艺形成位于栅极绝缘层之上并在栅极上方相对而置形成沟道的源极和漏极的图形、与源极连接的接收电极的图形,以及位于源极和漏极之上的欧姆层的图形;
通过一次构图工艺形成位于欧姆层和沟道之上的有源层的图形、位于接收电极之上的光电二极管的图形,以及位于光电二极管之上的透明电极的图形;
通过一次构图工艺形成第一钝化层的图形,所述第一钝化层在漏极的上方具有第一过孔,在透明电极的上方具有第二过孔;以及有源层和欧姆层的与第一过孔位置对应的第三过孔的图形;
通过一次构图工艺形成位于第一钝化层之上、并穿过第一过孔和第三过孔与漏极连接的数据线的图形,以及位于第一钝化层之上、并穿过第二过孔与透明电极连接的偏压线的图形。
7.如权利要求6所述的制造方法,其特征在于,在形成数据线的图形和偏压线的图形之后,进一步包括:
通过一次构图工艺形成覆盖基板的第二钝化层的图形,所述第二钝化层具有信号引导区过孔。
8.如权利要求6或7所述的制造方法,其特征在于,所述通过一次构图工艺形成源极和漏极的图形、接收电极的图形和欧姆层的图形,还包括:形成位于接收电极之上且与欧姆层位于同一图层的N型半导体的图形;
所述通过一次构图工艺形成有源层的图形、光电二极管的图形和透明电极的图形,具体包括:依次沉积有源材料层、I型半导体层、P型半导体层和透明电极层,通过一次构图工艺形成有源层、位于N型半导体之上且与有源层位于同一图层的I型半导体第一部分、位于I型半导体第一部分之上的I型半导体第二部分、位于I型半导体第二部分之上的P型半导体,以及位于P型半导体之上的透明电极。
9.如权利要求8所述的制造方法,其特征在于,所述源极、漏极和接收电极的材质相同;所述数据线和偏压线的材质相同。
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EP2879179A1 (en) | 2015-06-03 |
US9236518B2 (en) | 2016-01-12 |
EP2879179B1 (en) | 2017-09-27 |
EP2879179A4 (en) | 2016-03-16 |
WO2014015607A1 (zh) | 2014-01-30 |
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US20140231804A1 (en) | 2014-08-21 |
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