WO2014015592A1 - 传感器及其制造方法 - Google Patents

传感器及其制造方法 Download PDF

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Publication number
WO2014015592A1
WO2014015592A1 PCT/CN2012/085186 CN2012085186W WO2014015592A1 WO 2014015592 A1 WO2014015592 A1 WO 2014015592A1 CN 2012085186 W CN2012085186 W CN 2012085186W WO 2014015592 A1 WO2014015592 A1 WO 2014015592A1
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Prior art keywords
electrode
pattern
patterning process
layer
photodiode
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PCT/CN2012/085186
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English (en)
French (fr)
Inventor
徐少颖
谢振宇
陈旭
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北京京东方光电科技有限公司
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Priority to US14/128,263 priority Critical patent/US9312290B2/en
Publication of WO2014015592A1 publication Critical patent/WO2014015592A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14638—Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022466—Electrodes made of transparent conductive layers, e.g. TCO, ITO layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions

Definitions

  • the invention relates to a sensor and a method of manufacturing the same. Background technique
  • CT computed tomography
  • the sensor 12 includes a plurality of scan lines 15, a plurality of data lines 16, and a plurality of sensing units, each of which includes a photodiode 13 and a field effect transistor ( Field Effect Transistor (FET) 14, the gate of the field effect transistor 14 is connected to a corresponding scan line 15 in the sensor 12, the drain of the field effect transistor 14 and the corresponding data line in the sensor 12 (Data Line) 16
  • FET Field Effect Transistor
  • the photodiode 13 is connected to the source of the field effect transistor 14.
  • One end of these data lines 16 is connected to the data readout circuit 18 via a connection pin 17.
  • the above sensor operates on the principle that the sensor 12 applies a drive scan signal through the scan line 15 to control the switching state of the field effect transistor 14 of each sense unit.
  • the photocurrent signal generated by the photodiode 13 is sequentially output through the data line 16 connected to the field effect transistor 14 and the data readout circuit 18, by controlling the timing of the signal on the scan line 15 and the data line 16.
  • the collecting function of the photocurrent signal is realized, that is, the control effect of the photocurrent signal generation generated by the photodiode 13 is realized by controlling the switching state of the FET 14.
  • the senor usually adopts a thin film transistor (TFT) flat plate structure, and the sensor may have multiple layers in a cross section.
  • each sensing unit includes: a substrate, a gate layer, a gate insulating layer, Active layer, source and drain layers, passivation layer, PIN junction and transparent electrode window layer of PIN photosensor, and bias line layer and light barrier layer.
  • TFT thin film transistor
  • each sensing unit includes: a substrate, a gate layer, a gate insulating layer, Active layer, source and drain layers, passivation layer, PIN junction and transparent electrode window layer of PIN photosensor, and bias line layer and light barrier layer.
  • the specific layers on the cross-section are not exactly the same due to the difference in specific structures.
  • Each layer of the sensor is typically formed by a patterning process, and each patterning process typically includes steps such as masking, exposure, development, etching, and stripping. That is, in order to achieve multiple sensors Layers require multiple patterning processes.
  • the above-mentioned sensor having a plurality of layers usually requires 9 to 11 patterning processes at the time of manufacture, so that 9 to 11 mask masks are required correspondingly, thereby making the manufacturing cost of the sensor high, and the manufacturing process is relatively high. Complex, and the production capacity is difficult to upgrade. Summary of the invention
  • a sensor comprising:
  • a sensor comprising: a substrate substrate, a set of gate lines and a set of data lines arranged in a cross, and a plurality of sensing arrays arranged by the set of gate lines and a set of data lines a unit, each of the sensing units includes a thin film transistor device and a photodiode sensor device, wherein
  • the thin film transistor device includes: a source and a drain opposite to each other, a drain connected to an adjacent data line, and an ohmic layer located above the source and the drain An active layer over the ohmic layer and covering the channel, a gate insulating layer over the active layer, and over the gate insulating layer, above the channel and adjacent a gate line connected to the gate;
  • the photodiode sensor device includes: a receiving electrode coupled to the source, a photodiode over the receiving electrode, a transparent electrode over the photodiode, and a bias line connected to the transparent electrode above the transparent electrode, the bias line being disposed parallel to the gate line.
  • a method of manufacturing a sensor comprising: forming a pattern of a source and a drain by a first patterning process on a substrate, and a pattern of a data line connected to the drain, And a pattern of the receiving electrode connected to the source, wherein the source and the drain are opposite to each other to form a channel;
  • a method of manufacturing a sensor comprising: forming a pattern of a bias electrode on a base substrate by a first patterning process, and a bias voltage connected to the bias electrode a pattern of pole pins, a pattern of photodiodes over the bias electrode, and a pattern of transparent electrodes over the photodiode;
  • the thin film transistor device of the sensor according to the embodiment of the invention is of a top gate type.
  • the method for fabricating the sensor in the embodiment of the invention reduces the number of use of the mask, reduces the manufacturing cost, and simplifies the production process. Increased equipment capacity and product yield.
  • FIG. 1 is a schematic perspective view of a conventional sensor
  • FIG. 2 is a plan view of one of the sensing units of the sensor according to an embodiment of the present invention
  • FIG. 3a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along line AA of FIG. 2 after the first patterning process
  • 3b is a cross-sectional view of the sensing unit along line BB of FIG. 2 after the first patterning process according to an embodiment of the present invention
  • 4a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line A-A of FIG. 2 after the second patterning process;
  • 4b is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the second patterning process according to an embodiment of the present invention
  • 5a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line A-A of FIG. 2 after the third patterning process;
  • 5b is a cross-sectional view of the sensing unit taken along line B-B of FIG. 2 after the third patterning process according to an embodiment of the present invention
  • 6a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line A-A of FIG. 2 after the fourth patterning process;
  • 6b is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the fourth patterning process according to an embodiment of the present invention
  • 7a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line A-A of FIG. 2 after the fifth patterning process;
  • 7b is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the fifth patterning process according to an embodiment of the present invention
  • FIG. 8a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along line A-A of FIG. 2 after the sixth patterning process;
  • Figure 8b is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along the line B-B of Figure 2 after the sixth patterning process;
  • 9a is a cross-sectional view of the sensing unit of the embodiment of the present invention taken along line A-A of FIG. 2 after the seventh patterning process;
  • 9b is a cross-sectional view of the sensing unit along line B-B of FIG. 2 after the seventh patterning process according to an embodiment of the present invention.
  • FIG. 10 is a top plan view of one of the sensing units of the sensor according to another embodiment of the present invention
  • FIG. 11a is a cross-sectional view of the sensing unit along the line AA' of FIG. 10 after the first patterning process according to another embodiment of the present invention
  • FIG. 1 ib is a sensing unit according to another embodiment of the present invention, after the first patterning process, along FIG. 10 BB, a cross-sectional view of the line;
  • Figure 11c is a cross-sectional view of the sensing unit taken along line C-C of Figure 10 after the first patterning process according to another embodiment of the present invention.
  • Figure 12a is a cross-sectional view of the sensing unit taken along the line A-A' of Figure 10 after the second patterning process according to another embodiment of the present invention
  • Figure 12b is a cross-sectional view of the sensing unit taken along line BB' of Figure 10 after the second patterning process according to another embodiment of the present invention
  • Figure 12c is a cross-sectional view of the sensing unit taken along line C-C of Figure 10 after the second patterning process according to another embodiment of the present invention.
  • FIG. 13a is a perspective view of the sensing unit of FIG. 10 after the third patterning process according to another embodiment of the present invention.
  • Figure 13b is a cross-sectional view of the sensing unit taken along line BB' of Figure 10 after the third patterning process according to another embodiment of the present invention.
  • Figure 13c is a cross-sectional view of the sensing unit taken along the line C-C of Figure 10 after the third patterning process according to another embodiment of the present invention.
  • 14a is a cross-sectional view of the sensing unit taken along line AA' of FIG. 10 after the fourth patterning process according to another embodiment of the present invention.
  • 14b is a cross-sectional view of the sensing unit taken along line BB' of FIG. 10 after the fourth patterning process according to another embodiment of the present invention.
  • 14c is a perspective view of the sensing unit of FIG. 10 after the fourth patterning process according to another embodiment of the present invention.
  • Figure 15a is a cross-sectional view of the sensing unit taken along line A-A' of Figure 10 after the fifth patterning process according to another embodiment of the present invention.
  • Figure 15b is a cross-sectional view of the sensing unit taken along line BB' of Figure 10 after the fifth patterning process according to another embodiment of the present invention.
  • Figure 15c is a cross-sectional view of the sensing unit taken along line C-C of Figure 10 after the fifth patterning process according to another embodiment of the present invention.
  • Figure 16a is a cross-sectional view of the sensing unit taken along the line A-A' of Figure 10 after the sixth patterning process according to another embodiment of the present invention.
  • 16b is a perspective view of the sensing unit of FIG. 10 after the sixth patterning process according to another embodiment of the present invention.
  • BB a cross-sectional view of the line;
  • Figure 16c is a cross-sectional view of the sensing unit taken along line C-C of Figure 10 after the sixth patterning process according to another embodiment of the present invention.
  • the senor may be an X-ray sensor or other type of sensor, such as a sensor that transmits by photoelectric conversion.
  • other sensing units may be formed identically.
  • FIG. 2 shows a top view of one of the sensing units of the sensor in accordance with one embodiment of the present invention.
  • Figures 9a and 9b are cross-sectional views of the sensing unit of Figure 2 taken along line A-A, line and B-B.
  • the sensor comprises: a substrate substrate 32, a set of gate lines 30 and a set of data lines 31 arranged in a crosswise manner, and the set of gate lines 30 and a set of data lines a plurality of sensing units arranged in an array, each of which includes a thin film transistor device and a photodiode sensor device, wherein
  • the thin film transistor device includes: a source 33 and a drain 34 which are oppositely formed to form a channel, the drain 34 is connected to an adjacent data line 31, and an ohmic layer over the source 33 and the drain 34 35.
  • An active layer 36 over the ohmic layer 35 and covering the channel, a gate insulating layer 37 over the active layer 36, and over the gate insulating layer 37, above the channel and adjacent to the gate a wire 38 connected to the line 30;
  • the photodiode sensor device includes: a receiving electrode 39 connected to the source 33, a photodiode 40 above the receiving electrode 39, a transparent electrode 41 above the photodiode 40, and a transparent electrode above the transparent electrode 41. 41 is connected to a bias line 42 which is disposed parallel to the gate line 30.
  • the base substrate 32 may be a substrate of a glass substrate, a plastic substrate or other materials; the gate line 30, the gate 38, the data line 31, the source 33, the drain 34, and the receiving electrode.
  • the material of the 39 and the bias line 42 (and the bias electrode 42a and the bias electrode lead 42b hereinafter) may be the same, and may be, for example, an aluminum-niobium alloy (AlNd), aluminum (Al), or copper (Cu).
  • a single layer film of molybdenum (Mo), molybdenum-tungsten alloy (MoW) or chromium (Cr) may be a composite film composed of any combination of these metal elements or alloy materials. The thickness of these single or composite films is, for example, between 150 nm and 450 nm.
  • the material of the ohmic layer 35 may be, for example, a doped semiconductor (n+a-Si); the material of the active layer 36 may be a semiconductor material, such as amorphous silicon (a-Si), thickness, for example.
  • the material of the gate insulating layer 37 may be silicon nitride, and the thickness is, for example, between 300 nm and 500 nm; the material of the transparent electrode 41 may be, for example, indium tin oxide (ITO) or indium oxide.
  • Transparent conductive material such as (IZO).
  • the photodiode 40 is a PIN photodiode, including: An N-type semiconductor (n+a-Si) 40a over the receiving electrode 39, an I-type semiconductor (a-Si) 40b over the N-type semiconductor 40a, and a P-type semiconductor over the I-type semiconductor 40b ( p+a-Si ) 40c.
  • the PIN type photodiode is preferable because it has a small junction capacitance, a short transit time, and high sensitivity.
  • the photodiode may also utilize other types of photodiodes such as MIS type photodiodes.
  • the gate insulating layer 37 covers the substrate, and has a via hole connecting the transparent electrode 41 and the bias line 42 above the transparent electrode 41.
  • the sensor further includes: a passivation layer 44 over the bias line 42, the gate line 30, and the gate 38 and covering the substrate, the passivation layer 44 having a signal guiding area via (FIG. 9a and 9b are cross-sectional structures of one sensing unit, and thus signal guiding region vias located at the periphery of the substrate are not shown in the drawing).
  • the passivation layer 44 (and the first passivation layer 43 and the second passivation layer 57 hereinafter) may be an inorganic insulating film (for example, silicon nitride or the like) or an organic insulating film (for example, a photosensitive resin material or a non-photosensitive resin material). Etc.), the thickness is, for example, between 150 nm and 1500 nm.
  • the thin film transistor device of the sensor of this embodiment is a top gate type, and the sensor can be formed by using a seven-time patterning process. Compared with the prior art, the number of masks used in the manufacturing process can be reduced, the manufacturing cost is reduced, and the simplification is simplified. The production process has greatly improved the production capacity of the equipment and the yield of the products.
  • a method of manufacturing the above sensor includes:
  • Step 101 forming a pattern of the source 33 and the drain 34 by a patterning process on the base substrate 32, a pattern of the data line 31 connected to the drain 34, and a pattern of the receiving electrode 39 connected to the source 33, wherein The source 33 and the drain 34 are opposed to each other to form a channel.
  • a patterning process on the base substrate 32, a pattern of the data line 31 connected to the drain 34, and a pattern of the receiving electrode 39 connected to the source 33, wherein The source 33 and the drain 34 are opposed to each other to form a channel.
  • FIG. 3a and 3b are cross-sectional views of the substrate after the first patterning process.
  • Fig. 2 and Fig. 9a and Fig. 9b are respectively a plan view and a cross-sectional view of the sensing unit obtained after the final seven processes. Therefore, the substrate of Figs. 3a and 3b is only A-A, line and B-B shown in Fig. 2, and the direction of the line is cut away, which does not represent a sectional view of the substrate of Fig. 2.
  • Figures 4a through 8b are also shown in the same manner.
  • the one-time patterning process generally includes steps of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist removal, and the like.
  • Substrate cleaning includes cleaning with deionized water, organic cleaning solution, and the like.
  • the film forming process is used to form a structural layer to be patterned.
  • a film is usually formed by physical vapor deposition (for example, magnetron sputtering), and a pattern is formed by wet etching;
  • the non-metal layer is usually formed by chemical vapor deposition and patterned by dry etching.
  • the composition process in the following steps is the same as this, and will not be described again.
  • Step 102 forming a pattern of the photodiode 40 over the receiving electrode 39 and a pattern of the transparent electrode 41 over the photodiode 40 by one patterning process.
  • FIG. 4a and Figure 4b for the cross-sectional structure after the second patterning process.
  • step 102 can include:
  • the N-type semiconductor layer, the I-type semiconductor layer, the P-type semiconductor layer, and the transparent electrode layer are sequentially deposited, and the pattern of the photodiode 40 and the pattern of the transparent electrode 41 are formed by one patterning process.
  • the transparent electrode 41 pattern may be formed by wet etching alone or by dry etching simultaneously with the pattern of the photodiode 40.
  • Step 103 forming a pattern of the ohmic layer 35 over the source 33 and the drain 34 by one patterning process.
  • the cross-sectional structure after the third patterning process is shown in Figures 5a and 5b.
  • Step 104 forming a pattern of the active layer 36 over the ohmic layer 35 and covering the trench by a patterning process.
  • the cross-sectional structure after the fourth patterning process is shown in Figures 6a and 6b.
  • Step 105 Form a pattern of the gate insulating layer 37 by one patterning process, and the gate insulating layer 37 has a through hole above the transparent electrode 41. Refer to Figure 7a and Figure 7b for the cross-sectional structure after the fifth patterning process.
  • Step 106 forming a pattern of the gate electrode 38 over the gate insulating layer 37 and above the channel by a patterning process, a pattern of the gate line 30 connected to the gate electrode 38, and passing through the via hole over the transparent electrode 41.
  • step 106 the method of this embodiment may further include:
  • Step 107 Form a pattern of the passivation layer 44 covering the substrate by a patterning process, the passivation layer 44 having a signal guiding region via.
  • the cross-sectional structure after the seventh patterning process is shown in FIG. 9a and FIG. 9b (FIG. 9a and FIG. 9b are cross-sectional structures of one sensing unit, so the signal guiding area vias located at the periphery of the substrate are not shown in the figure) .
  • the method for fabricating a sensor may include only steps 101-106 described above. It can be seen from the above that the manufacturing method of the sensor of the embodiment of the present invention can use a total of six or seven patterning processes, which reduces the number of masks used, reduces the manufacturing cost, and simplifies the production compared with the prior art. The process has greatly improved the production capacity of the equipment and the yield of the products.
  • FIGS. 10, 16a, 16b and 16c there is further provided another sensor, as shown in FIGS. 10, 16a, 16b and 16c, the sensor comprising: a substrate substrate 32, a set of gate lines 30 arranged in a cross arrangement And a set of data lines 31, and a plurality of sensing units arranged in an array defined by the set of gate lines 30 and a set of data lines 31, each sensing unit comprising a thin film transistor device and a photodiode sensor Piece, of which
  • the thin film transistor device includes: a source 33 and a drain 34 which are oppositely formed to form a channel, the drain 34 is connected to an adjacent data line 31, and an ohmic layer over the source 33 and the drain 34 35.
  • An active layer 36 over the ohmic layer 35 and covering the channel, a gate insulating layer 37 over the active layer 36, and over the gate insulating layer 37, above the channel and adjacent to the gate a wire 38 connected to the line 30;
  • the photodiode sensor device includes: a bias electrode 42a over the base substrate 32 and a bias electrode lead 42b connected to the bias electrode 42a, and a photodiode 40 located above the bias electrode 42a.
  • a transparent electrode 41 located above the photodiode 40 and connected to the source 33.
  • the photodiode is a PIN photodiode comprising: an N-type semiconductor (n+a-Si) 40a over the bias electrode 42a, and an I-type semiconductor over the N-type semiconductor 40a. ( a - Si) 40b, and a P-type semiconductor (p+a-Si) 40c over the I-type semiconductor 40b.
  • the senor may further include:
  • a first passivation layer 43 is disposed over the transparent electrode 41 and the bias electrode lead 42b of each photodiode sensor device, and the first passivation layer 43 has a source 33 and a drain 34.
  • the data line 31 and the recess of the ohmic layer 35, and the via hole connecting the source 33 and the transparent electrode 41, the source 33, the drain 34 and the data line 31 are located above the first passivation layer 43.
  • the senor may further include: a second passivation layer 57 over the gate line 30 and the gate 38 of each thin film transistor device and covering the substrate, the second passivation layer 57 having The signal guiding region via holes (Fig. 16a and Fig. 16b are sectional structures of one sensing unit, and thus the signal guiding region via holes located at the periphery of the substrate are not shown in the drawing).
  • a method of manufacturing the above sensor includes: Step 101, forming a pattern of the bias electrode 42a by a patterning process on the base substrate 32, a pattern of the bias electrode lead 42b connected to the bias electrode 42a, and a photoelectric pattern located above the bias electrode 42a.
  • the pattern of diode 40, as well as the pattern of transparent electrode 41 over photodiode 40. Refer to Figure 11a, Figure lib, and Figure 11c for the cross-sectional structure of the first patterning process.
  • FIGS. 1a, 1b, and 11c The substrate of FIGS. 1a, 1b, and 11c is only cut in the direction of AA, line, BB, line, and CC line shown in FIG. 10, which does not represent a cross-sectional view of the substrate of FIG. .
  • Figures 12a to 15c are also shown in the same manner.
  • the step 101 may include:
  • a positive photoresist is taken as an example.
  • the completely transparent region, the semi-transmissive region and the opaque region of the mask are used for performing full exposure, partial exposure and non-exposure operations on the photoresist, after development.
  • a photoresist complete removal region, a photoresist partial removal region, and a photoresist complete retention region are obtained.
  • the photoresist is substantially completely retained in the photoresist complete retention area.
  • the opaque region corresponds to a region where the bias electrode 42a, the PIN photodiode 40, and the transparent electrode 41 are formed; the semi-transmissive region corresponds to a region where the bias electrode pin 42b is formed.
  • the mask used in this step may be specifically a two-tone mask (for example, a gray tone mask or a halftone mask, etc.).
  • Step 102 Form a pattern of the first passivation layer 43 over the transparent electrode 41 and the bias electrode lead 42b and covering the substrate by one patterning process.
  • the cross-sectional structure after the second patterning process is shown in Figures 12a, 12b and 12c.
  • Step 103 forming a pattern of the source 33, the drain 34, and the data line 31 by a patterning process, and a pattern of the ohmic layer 35 over the source 33 and the drain 34, wherein the source 33 and the drain 34 is formed to face the channel, the drain 34 is connected to the data line 31, and the source 33 is connected to the transparent electrode 41.
  • the cross-sectional structure after the third patterning process is shown in Figures 13a, 13b and 13c.
  • Step 104 forming a pattern of the active layer 36 over the ohmic layer 35 and covering the trench by a patterning process.
  • the cross-sectional structure after the fourth patterning process is shown in Figures 14a, 14b and 14c.
  • Step 105 forming a pattern of the gate insulating layer 37 on the active layer 36, a pattern on the gate insulating layer 37, a gate 38 above the channel, and a connection with the gate 38 by one patterning process.
  • the pattern of the grid lines 30 Refer to Figure 15a, Figure 15b, and Figure 15c for the cross-sectional structure after the fifth patterning process.
  • the method of the embodiment may further include:
  • Step 106 Form a pattern of the second passivation layer 57 covering the substrate by a patterning process, the second passivation layer 57 having a signal guiding region via.
  • the cross-sectional structure after the sixth patterning process is shown in FIG. 16a, FIG. 16b, and FIG. 16c (FIG. 16a, FIG. 16b, and FIG. 16c are cross-sectional structures of one sensing unit, and therefore the signal guiding area via the periphery of the substrate is not formed. Shown in the figure).
  • This step 106 is optional because the purpose of the present invention can be achieved without performing step 106.
  • the method for fabricating a sensor may include only steps 101-105 described above.
  • the manufacturing method of the sensor of this embodiment can use five or six patterning processes in total, and the number of masks used is reduced, the manufacturing cost is reduced, and the production process is simplified compared with the prior art. , greatly improving the equipment capacity and product yield.

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Abstract

提供一种传感器及其制造方法，其中传感器包括：衬底基板（32）、呈交叉排列的一组栅线（30）和一组数据线（31），以及由一组栅线（30）和一组数据线（31）所限定的多个呈阵列状排布的感测单元，每个感测单元包括薄膜晶体管和光电二极管传感器件，其中薄膜晶体管器件为顶栅极结构。光电二极管传感器件包括：与源极（33）连接的接收电极（39），位于接收电极（39）之上的光电二极管（40）、位于光电二极管之上的透明电极（41），以及在透明电极（41）的上方与透明电极（41）连接的偏压线（42），偏压线（42）平行于栅线（30）设置。与现有技术相比减少了掩模板的使用数量，降低了制造成本，简化了生产工艺，提升了设备产能及产片的良率。

Description

传感器及其制造方法 技术领域
本发明涉及一种传感器及其制造方法。 背景技术
由于保健的需要， 各种无损伤医疗检测方法逐渐受到人们的青睐。 在诸 多的无损伤检测方法中， 计算机断层扫描技术（ CT ) 已经得到广泛的应用。 在计算机断层扫描设备中必不可缺的一个部分就是传感器。
一种传感器的基本结构如图 1所示， 该传感器 12包括多条扫描线 15、 多条数据线 16以及多个感测单元， 每个感测单元包括一个光电二极管 13和 一个场效应晶体管 (Field Effect Transistor, FET) 14, 场效应晶体管 14的栅极 与传感器 12中相应的扫描线 (Scan Line) 15连接， 场效应晶体管 14的漏极与 传感器 12中相应的数据线 (Data Line) 16连接， 光电二极管 13与场效应晶体 管 14的源极连接。这些数据线 16的一端通过连接引脚 17连接数据读出电路 18。
上述传感器的工作原理为： 传感器 12通过扫描线 15施加驱动扫描信号 来控制每个感测单元的场效应晶体管 14的开关状态。 当场效应晶体管 14被 打开时， 光电二极管 13产生的光电流信号依次通过与场效应晶体管 14连接 的数据线 16、 数据读出电路 18而输出， 通过控制扫描线 15与数据线 16上 的信号时序来实现光电流信号的釆集功能，即通过控制场效应管 14的开关状 态来实现对光电二极管 13产生的光电流信号釆集的控制作用。
目前， 传感器通常釆用薄膜晶体管（ Thin Film Transistor, TFT )平板结 构， 这种传感器在断面上可具有多层， 例如， 每个感测单元内包括： 基板、 栅极层、 栅极绝缘层、 有源层、 源极与漏极层、 钝化层、 PIN光电传感器的 PIN结和透明电极窗口层， 以及偏压线层和挡光条层等。 当然， 不同传感器 由于具体结构的差异， 在断面上的具体图层也不完全相同。
传感器的各个图层一般通过构图工艺形成， 而每一次构图工艺通常包括 掩模、 曝光、 显影、 刻蚀和剥离等步骤。 也就是说， 为了实现传感器的多个 图层， 需要釆用多次构图工艺。 例如， 上述具有多层的传感器在制造时通常 需要釆用 9至 11次构图工艺， 这样就对应的需要 9至 11张光罩掩模板， 由 此， 使传感器的制造成本较高， 制造工艺较为复杂， 且产能较难提升。 发明内容
本发明的目的是提供一种传感器及其制造方法， 用以解决现有技术中存 在的传感器的制造成本较高， 且制造工艺较为复杂， 产能较难提升的技术问 题。
根据本发明的第一方面， 提供一种传感器， 包括：
一种传感器， 包括： 衬底基板、 呈交叉排列的一组栅线和一组数据线， 以及由所述一组栅线和一组数据线所限定的呈阵列状排布的多个感测单元， 每个感测单元包括薄膜晶体管器件和光电二极管传感器件， 其中，
所述薄膜晶体管器件包括： 相对而置形成沟道的源极和漏极， 所述漏极 与相邻的数据线连接， 以及位于所述源极和所述漏极之上的欧姆层、 位于所 述欧姆层之上并覆盖所述沟道的有源层、 位于所述有源层之上的栅极绝缘层 和位于所述栅极绝缘层之上、 所述沟道上方并与相邻的栅线连接的栅极； 所述光电二极管传感器件包括： 与所述源极连接的接收电极、 位于所述 接收电极之上的光电二极管、 位于所述光电二极管之上的透明电极， 以及在 所述透明电极的上方与所述透明电极连接的偏压线， 所述偏压线平行于栅线 设置。
根据本发明的第二方面， 提供一种传感器的制造方法， 包括： 在衬底基板上通过第一次构图工艺形成源极和漏极的图形， 与所述漏极 连接的数据线的图形， 以及与所述源极连接的接收电极的图形， 其中， 所述 源极和漏极相对而置形成沟道；
通过第二次构图工艺形成位于所述接收电极之上的光电二极管的图形， 以及位于所述光电二极管之上的透明电极的图形；
通过第三次构图工艺形成位于所述源极和漏极之上的欧姆层的图形； 通过第四次构图工艺形成位于所述欧姆层之上并覆盖所述沟道的有源层 的图形；
通过第五次构图工艺形成栅极绝缘层的图形， 所述栅极绝缘层在所述透 明电极的上方具有通孔；
通过第六次构图工艺形成位于所述栅极绝缘层之上、 所述沟道上方的栅 极的图形， 与所述栅极连接的栅线的图形， 以及在所述透明电极的上方通过 通孔与所述透明电极连接的偏压线的图形。
根据本发明的第三方面， 还提供一种传感器的制造方法， 包括： 在衬底基板上通过第一次构图工艺形成偏压电极的图形、 与所述偏压电 极连接的偏压电极引脚的图形、位于所述偏压电极之上的光电二极管的图形， 以及位于所述光电二极管之上的透明电极的图形；
通过第二次构图工艺形成位于所述透明电极和所述偏压电极引脚之上、 并覆盖所述衬底基板的第一钝化层的图形；
通过第三次构图工艺形成源极、 漏极和数据线的图形， 以及位于所述源 极和漏极之上的欧姆层的图形， 其中， 所述源极和漏极相对而置形成沟道， 所述漏极与所述数据线连接， 所述源极与所述透明电极连接；
通过第四次构图工艺形成位于所述欧姆层之上并覆盖所述沟道的有源层 的图形；
通过第五次构图工艺形成位于所述有源层之上的栅极绝缘层的图形、 位 于所述栅极绝缘层之上、 所述沟道上方的栅极的图形， 以及与所述栅极连接 的栅线的图形。
根据本发明实施例的传感器的薄膜晶体管器件为顶栅型， 对比于现有技 术， 本发明实施例中制作传感器的方法减少了掩模板的使用数量， 降低了制 造成本， 简化了生产工艺， 大大提升了设备产能及产品的良品率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有传感器的立体结构示意图；
图 2为根据本发明实施例的传感器的其中一个感测单元的俯视图； 图 3a为本发明实施例的感测单元在第一次构图工艺后沿图 2的 A-A，线 的截面视图； 图 3b为本发明实施例的感测单元在第一次构图工艺后沿图 2的 B-B，线 的截面视图；
图 4a为本发明实施例的感测单元在第二次构图工艺后沿图 2的 A-A，线 的截面视图；
图 4b为本发明实施例的感测单元在第二次构图工艺后沿图 2的 B-B，线 的截面视图；
图 5a为本发明实施例的感测单元在第三次构图工艺后沿图 2的 A-A，线 的截面视图；
图 5b为本发明实施例的感测单元在第三次构图工艺后沿图 2的 B-B，线 的截面视图；
图 6a为本发明实施例的感测单元在第四次构图工艺后沿图 2的 A-A，线 的截面视图；
图 6b为本发明实施例的感测单元在第四次构图工艺后沿图 2的 B-B，线 的截面视图；
图 7a为本发明实施例的感测单元在第五次构图工艺后沿图 2的 A-A，线 的截面视图；
图 7b为本发明实施例的感测单元在第五次构图工艺后沿图 2的 B-B，线 的截面视图；
图 8a为本发明实施例的感测单元在第六次构图工艺后沿图 2的 A-A，线 的截面视图；
图 8b为本发明实施例的感测单元在第六次构图工艺后沿图 2的 B-B，线 的截面视图；
图 9a为本发明实施例的感测单元在第七次构图工艺后沿图 2的 A-A，线 的截面视图；
图 9b为本发明实施例的感测单元在第七次构图工艺后沿图 2的 B-B，线 的截面视图；
图 10为根据本发明另一实施例的传感器的其中一个感测单元的俯视图； 图 11a为本发明另一实施例的感测单元在第一次构图工艺后沿图 10的 A-A' 线的截面视图；
图 l ib为本发明另一实施例的感测单元在第一次构图工艺后沿图 10的 B-B， 线的截面视图；
图 11c为本发明另 实施例的感测单元在第一次构图工艺后沿图 10的 C-C 线的截面视图；
图 12a为本发明另 实施例的感测单元在第二次构图工艺后沿图 10的 A-A' 线的截面视图；
图 12b为本发明另 实施例的感测单元在第二次构图工艺后沿图 10的 B-B' 线的截面视图；
图 12c为本发明另 实施例的感测单元在第二次构图工艺后沿图 10的 C-C 线的截面视图；
图 13a为本发明另 实施例的感测单元在第三次构图工艺后沿图 10的
A-A' 线的截面视图；
图 13b为本发明另 实施例的感测单元在第三次构图工艺后沿图 10的 B-B' 线的截面视图；
图 13c为本发明另 实施例的感测单元在第三次构图工艺后沿图 10的 C-C 线的截面视图；
图 14a为本发明另 实施例的感测单元在第四次构图工艺后沿图 10的 A-A' 线的截面视图；
图 14b为本发明另 实施例的感测单元在第四次构图工艺后沿图 10的 B-B' 线的截面视图；
图 14c为本发明另 实施例的感测单元在第四次构图工艺后沿图 10的
C-C 线的截面视图；
图 15a为本发明另 实施例的感测单元在第五次构图工艺后沿图 10的 A-A' 线的截面视图；
图 15b为本发明另 实施例的感测单元在第五次构图工艺后沿图 10的 B-B' 线的截面视图；
图 15c为本发明另 实施例的感测单元在第五次构图工艺后沿图 10的 C-C 线的截面视图；
图 16a为本发明另 实施例的感测单元在第六次构图工艺后沿图 10的 A-A' 线的截面视图；
图 16b为本发明另 实施例的感测单元在第六次构图工艺后沿图 10的 B-B， 线的截面视图； 以及
图 16c为本发明另一实施例的感测单元在第六次构图工艺后沿图 10的 C-C 线的截面视图。
附图标记：
12-传感器 13-光电二极管 14-场效应晶体管
15-扫描线 16-数据线 17-连接引脚
18-数据读出电路 30-栅线 31-数据线
32-衬底基板 33-源极 34-漏极
35-欧姆层 36-有源层 37-栅极绝缘层
38-栅极 57-第二钝化层 40-光电二极管
41-透明电极 42a-偏压电极 40a-N型半导体
40b-I型半导体 40c-P型半导体 43-第一钝化层
42b-偏压电极引脚 42-偏压线 39-接收电极
44-钝化层 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的术语 "连接" 并非限定于物理的或者机械的连接， 而是可 以包括电性的连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该 相对位置关系也相应地改变。
在本发明以下实施例中， 传感器可以是 X射线传感器， 也可以是其他类 型的传感器， 例如通过光电转换进行传输的传感器。 在下面的描述和图示中 针对单个感测单元进行， 其他感测单元可以同样地形成。 针对现有技术中存在的传感器的制造成本较高， 且制造工艺较为复杂的 技术问题， 本发明的实施例提供了一种传感器及其制造方法。
图 2示出了根据本发明一个实施例的传感器的其中一个感测单元的俯视 图。 图 9a和图 9b是图 2的感测单元沿 A-A， 线和 B-B， 线的截面图。 如图 2、 9a和图 9b所示， 该传感器， 包括： 衬底基板 32、 呈交叉排列的一组栅线 30和一组数据线 31、由所述一组栅线 30和一组数据线 31所限定的呈阵列状 排布的多个感测单元， 每个感测单元包括薄膜晶体管器件和光电二极管传感 器件， 其中，
所述薄膜晶体管器件包括： 相对而置形成沟道的源极 33和漏极 34, 所 述漏极 34与相邻的数据线 31连接， 以及位于源极 33和漏极 34之上的欧姆 层 35、位于欧姆层 35之上并覆盖沟道的有源层 36、位于有源层 36之上的栅 极绝缘层 37和位于栅极绝缘层 37之上、沟道上方并与相邻的栅线 30连接的 栅极 38;
所述光电二极管传感器件包括： 与源极 33连接的接收电极 39、 位于接 收电极 39之上的光电二极管 40、位于光电二极管 40之上的透明电极 41 , 以 及在透明电极 41的上方与透明电极 41连接的偏压线 42, 所述偏压线 42平 行于栅线 30设置。
本发明的实施例中，所述衬底基板 32可以为玻璃基板、塑料基板或其他 材料的基板； 所述栅线 30、 栅极 38、 数据线 31、 源极 33、 漏极 34、 接收电 极 39和偏压线 42 (以及下文中的偏压电极 42a和偏压电极引脚 42b )的材质 可以是相同的，例如可以为铝钕合金（AlNd )、铝（Al )、铜（Cu )、钼（Mo )、 钼钨合金 ( MoW )或铬（Cr )的单层膜， 也可以为这些金属单质或合金材料 任意组合所构成的复合膜。 这些单层或复合膜的厚度例如在 150纳米至 450 纳米之间。
本发明的实施例中，欧姆层 35的材质例如可以为掺杂质半导体 ( n+a-Si ); 有源层 36 的材质可以为半导体材料， 例如非晶硅（a-Si ) , 厚度例如在 30 纳米至 250纳米之间； 栅极绝缘层 37的材质可以为氮化硅， 厚度例如在 300 纳米至 500纳米之间； 透明电极 41的材质可以为诸如氧化铟锡（ ITO )或氧 化铟辞（IZO )等的透明导电材料。
本发明实施例中， 所述光电二极管 40为 PIN型光电二极管， 包括： 位 于接收电极 39之上的 N型半导体（n+a-Si ) 40a, 位于 N型半导体 40a之上 的 I型半导体（ a-Si )40b,以及位于 I型半导体 40b之上的 P型半导体( p+a-Si ) 40c。 PIN型光电二极管具有结电容小、 渡越时间短、 灵敏度高等优点， 因此 为优选。 然而， 在本发明的其它实施例中， 光电二极管还可以釆用诸如 MIS 型光电二极管的其他类型光电二极管。
继续参照图 2、 图 9a和图 9b所示， 在一个实施例中， 所述栅极绝缘层 37覆盖基板， 并在透明电极 41的上方具有连接透明电极 41和偏压线 42的 通孔。 在一个实施例中， 所述传感器还包括： 位于偏压线 42、 栅线 30和栅 极 38之上并覆盖基板的钝化层 44, 所述钝化层 44具有信号引导区过孔 (图 9a和图 9b为一个感测单元的截面结构， 因此位于基板周边的信号引导区过 孔未在图中示出） 。 钝化层 44 (以及下文中的第一钝化层 43和第二钝化层 57 )可以釆用无机绝缘膜（例如氮化硅等）或有机绝缘膜（例如感光树脂材 料或者非感光树脂材料等 ) , 厚度例如在 150纳米至 1500纳米之间。
该实施例的传感器的薄膜晶体管器件为顶栅型， 传感器可共釆用七次构 图工艺制作形成， 对比于现有技术， 可减少制造过程中掩模板的使用数量， 降低了制造成本， 简化了生产工艺， 大大提升了设备产能及产品的良品率。
根据本发明一个实施例， 上述传感器的制造方法包括：
步骤 101、在衬底基板 32上通过一次构图工艺形成源极 33和漏极 34的 图形， 与漏极 34连接的数据线 31的图形， 以及与源极 33连接的接收电极 39的图形， 其中， 所述源极 33和漏极 34相对而置形成沟道。 第一次构图工 艺后的截面结构请参照图 3a和图 3b所示。
图 3a和图 3b为衬底基板在第一次构图工艺后的截面图。 图 2和图 9a、 图 9b分别是最终经过七次工艺后得到的感测单元的俯视图和剖面图。 因此， 图 3a和图 3b的衬底基板只是按图 2示出的 A-A， 线及 B-B， 线的方向被切 开， 其并不代表图 2的衬底基板的剖面图。 同样， 图 4a至图 8b也是按相同 方式示出。
一次构图工艺依次通常包括基板清洗、 成膜、 光刻胶涂覆、 曝光、 显影、 刻蚀、 光刻胶去除等步骤。 基板清洗包括使用去离子水、 有机清洗液进行清 洗等。 成膜工艺用于形成将被构图的结构层。 例如， 对于金属层通常釆用物 理气相沉积方式（例如磁控溅射法）成膜， 并通过湿法刻蚀形成图形； 而对 于非金属层通常釆用化学气相沉积方式成膜， 并通过干法刻蚀形成图形。 以 下步骤中的构图工艺与此道理相同， 不再赘述。
步骤 102、通过一次构图工艺形成位于接收电极 39之上的光电二极管 40 的图形， 以及位于光电二极管 40之上的透明电极 41的图形。 第二次构图工 艺后的截面结构请参照图 4a和图 4b所示。
在一个示例中， 当光电二极管 40为 PIN型光电二极管时， 该步骤 102 可包括：
依次沉积 N型半导体层、 I型半导体层、 P型半导体层和透明电极层， 通过一次构图工艺形成光电二极管 40的图形和透明电极 41的图形。
其中在该次构图工艺中， 透明电极 41图形可以单独釆用湿法刻蚀形成， 也可以与光电二极管 40的图形同时通过干法刻蚀形成。
步骤 103、 通过一次构图工艺形成位于源极 33和漏极 34之上的欧姆层 35的图形。 第三次构图工艺后的截面结构请参照图 5a和图 5b所示。
步骤 104、通过一次构图工艺形成位于欧姆层 35之上并覆盖沟道的有源 层 36的图形。 第四次构图工艺后的截面结构请参照图 6a和图 6b所示。
步骤 105、 通过一次构图工艺形成栅极绝缘层 37的图形， 所述栅极绝缘 层 37在透明电极 41的上方具有通孔。 第五次构图工艺后的截面结构请参照 图 7a和图 7b所示。
步骤 106、 通过一次构图工艺形成位于栅极绝缘层 37之上、 沟道上方的 栅极 38的图形， 与栅极 38连接的栅线 30的图形， 以及在透明电极 41的上 方通过通孔与透明电极 41连接的偏压线 42的图形。 第六次构图工艺后的截 面结构请参照图 8a和图 8b所示。
此外， 在步骤 106之后， 该实施例的方法还可进一步包括：
步骤 107、 通过一次构图工艺形成覆盖基板的钝化层 44的图形， 所述钝 化层 44具有信号引导区过孔。 第七次构图工艺后的截面结构请参照图 9a和 图 9b所示（图 9a和图 9b为一个感测单元的截面结构， 因此位于基板周边的 信号引导区过孔未在图中示出） 。
该步骤 107为可选的， 因为在不执行步骤 107的情况下， 同样可以实现 本发明的目的。 因此， 在一个实施例中， 用于制造传感器的方法可仅包括上 述步骤 101~106。 从以上内容可以看出， 本发明实施例的传感器的制造方法可共釆用六次 或七次构图工艺， 对比于现有技术， 减少了掩模板的使用数量， 降低了制造 成本， 简化了生产工艺， 大大提升了设备产能及产品的良品率。
根据本发明的另一个实施例，还提供了另外一种传感器，如图 10、图 16a、 图 16b和图 16c所示， 该传感器包括： 衬底基板 32、 呈交叉排列的一组栅线 30和一组数据线 31 ,以及由所述一组栅线 30和一组数据线 31所限定的呈阵 列状排布的多个感测单元， 每个感测单元包括薄膜晶体管器件和光电二极管 传感器件， 其中，
所述薄膜晶体管器件包括： 相对而置形成沟道的源极 33和漏极 34, 所 述漏极 34与相邻的数据线 31连接， 以及位于源极 33和漏极 34之上的欧姆 层 35、位于欧姆层 35之上并覆盖沟道的有源层 36、位于有源层 36之上的栅 极绝缘层 37和位于栅极绝缘层 37之上、沟道上方并与相邻的栅线 30连接的 栅极 38;
所述光电二极管传感器件包括： 位于衬底基板 32之上的偏压电极 42a 和与偏压电极 42a连接的偏压电极引脚 42b、 位于偏压电极 42a之上的光电 二极管 40、 位于光电二极管 40之上并与源极 33连接的透明电极 41。
在一个实施例中， 所述光电二极管为 PIN型光电二极管， 包括： 位于偏 压电极 42a之上的 N型半导体（n+a-Si ) 40a, 位于 N型半导体 40a之上的 I 型半导体（ a-Si ) 40b, 以及位于 I型半导体 40b之上的 P型半导体（ p+a-Si ) 40c。
在一个实施例中， 所述传感器， 还可包括：
位于每个光电二极管传感器件的透明电极 41和偏压电极引脚 42b之上、 并覆盖基板的第一钝化层 43 ,所述第一钝化层 43具有容纳源极 33、漏极 34、 数据线 31和欧姆层 35的凹槽， 以及连接源极 33和透明电极 41的通孔， 所 述源极 33、 漏极 34和数据线 31位于所述第一钝化层 43之上。
在一个实施例中，所述传感器还可包括：位于栅线 30和每个薄膜晶体管 器件的栅极 38之上、 并覆盖基板的第二钝化层 57, 所述第二钝化层 57具有 信号引导区过孔（图 16a和图 16b为一个感测单元的截面结构， 因此位于基 板周边的信号引导区过孔未在图中示出） 。
根据本发明一个实施例， 上述传感器的制造方法包括： 步骤 101、在衬底基板 32上通过一次构图工艺形成偏压电极 42a的图形、 与偏压电极 42a连接的偏压电极引脚 42b的图形、 位于偏压电极 42a之上的 光电二极管 40的图形， 以及位于光电二极管 40之上的透明电极 41的图形。 第一次构图工艺后的截面结构请参照图 lla、 图 lib和图 11c所示。
图 l la、 图 l lb、 图 11c的衬底基板只是按图 10示出的 A-A， 线、 B-B， 线及 C-C 线的方向被切开， 其并不代表图 10的衬底基板的剖面图。 同样， 图 12a至图 15c也是按相同方式示出。
在一个示例中， 当光电二极管 40为 PIN型光电二极管时， 该步骤 101 可包括：
101a. 在衬底基板上依次沉积偏压电极层、 N型半导体层、 I型半导体层、
P型半导体层和透明电极层， 并在透明电极层之上涂覆光刻胶；
101b. 釆用具有全透光区、 半透光区和不透光区的掩模板对基板上的光 刻胶进行曝光、 显影， 得到具有光刻胶完全去除区、 光刻胶部分去除区和光 刻胶完全保留区的光刻胶图形；
101c. 对基板上的光刻胶完全去除区进行刻蚀， 形成偏压电极 42a的图 形、 光电二极管 40的图形和透明电极 41的图形；
101d. 对基板上的光刻胶部分去除区进行灰化、 去除光刻胶部分去除区 中的光刻胶并且保留光刻胶完全保留区的光刻胶，刻蚀且然后将光刻胶去除， 形成偏压电极引脚 42b的图形。
上述描述中以正性光刻胶为例进行说明， 掩模板的完全透光区、 半透光 区和不透光区用于对光刻胶进行完全曝光、 部分曝光和非曝光操作， 显影后 得到光刻胶完全去除区、 光刻胶部分去除区和光刻胶完全保留区。 光刻胶完 全保留区中光刻胶基本全部保留。
在上述步骤 101b中， 不透光区对应形成偏压电极 42a、 PIN光电二极管 40和透明电极 41的区域； 半透光区对应形成偏压电极引脚 42b的区域。 另 夕卜， 该步骤中所釆用的掩模板可以具体为双色调掩模板（例如灰色调掩模板 或者半色调掩模板等） 。
步骤 102、 通过一次构图工艺形成位于透明电极 41和偏压电极引脚 42b 之上、并覆盖基板的第一钝化层 43的图形。第二次构图工艺后的截面结构请 参照图 12a、 图 12b和图 12c所示。 步骤 103、通过一次构图工艺形成源极 33、漏极 34和数据线 31的图形， 以及位于源极 33和漏极 34之上的欧姆层 35的图形， 其中， 所述源极 33和 漏极 34相对而置形成沟道， 所述漏极 34与数据线 31连接， 所述源极 33与 透明电极 41连接。 第三次构图工艺后的截面结构请参照图 13a、 图 13b和图 13c所示。
步骤 104、通过一次构图工艺形成位于欧姆层 35之上并覆盖沟道的有源 层 36的图形。 第四次构图工艺后的截面结构请参照图 14a、 图 14b和图 14c 所示。
步骤 105、 通过一次构图工艺形成位于有源层 36之上的栅极绝缘层 37 的图形、 位于栅极绝缘层 37之上、 沟道上方的栅极 38的图形， 以及与栅极 38连接的栅线 30的图形。 第五次构图工艺后的截面结构请参照图 15a、 图 15b和图 15c所示。
此外， 在步骤 105之后， 该实施例方法还可进一步包括：
步骤 106、 通过一次构图工艺形成覆盖基板的第二钝化层 57的图形， 所 述第二钝化层 57具有信号引导区过孔。第六次构图工艺后的截面结构请参照 图 16a、 图 16b和图 16c所示（图 16a、 图 16b和图 16c为一个感测单元的截 面结构， 因此位于基板周边的信号引导区过孔未在图中示出） 。 该步骤 106 为可选的， 因为在不执行步骤 106的情况下， 同样可以实现本发明的目的。 因此， 在一个实施例中， 用于制造传感器的方法可仅包括上述步骤 101~105。
从以上内容可以看出， 该实施例的传感器的制造方法可共釆用五次或六 次构图工艺，对比于现有技术， 减少了掩模板的使用数量， 降低了制造成本， 简化了生产工艺， 大大提升了设备产能及产品的良品率。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种传感器， 包括：衬底基板、呈交叉排列的一组栅线和一组数据线， 以及由所述一组栅线和一组数据线所限定的呈阵列状排布的多个感测单元， 每个感测单元包括薄膜晶体管器件和光电二极管传感器件， 其中，
所述薄膜晶体管器件包括： 相对而置形成沟道的源极和漏极， 所述漏极 与相邻的数据线连接， 以及位于所述源极和所述漏极之上的欧姆层、 位于所 述欧姆层之上并覆盖所述沟道的有源层、 位于所述有源层之上的栅极绝缘层 和位于所述栅极绝缘层之上、 所述沟道上方并与相邻的栅线连接的栅极； 所述光电二极管传感器件包括： 与所述源极连接的接收电极、 位于所述 接收电极之上的光电二极管、 位于所述光电二极管之上的透明电极， 以及在 所述透明电极的上方与所述透明电极连接的偏压线， 所述偏压线平行于栅线 设置。
2、 如权利要求 1所述的传感器， 还包括： 位于偏压线、 栅线和栅极之上 并覆盖衬底基板的钝化层， 所述钝化层具有信号引导区过孔。
3、如权利要求 1或 2所述的传感器， 其中， 所述栅极绝缘层覆盖衬底基 板， 并在透明电极的上方具有连接透明电极和偏压线的通孔。
4、 如权利要求 1-3 中任一项所述的传感器， 其中， 所述光电二极管为 PIN型光电二极管， 包括： 位于接收电极之上的 N型半导体， 位于 N型半导 体之上的 I型半导体， 以及位于 I型半导体之上的 P型半导体。
5、 一种传感器的制造方法， 包括：
在衬底基板上通过第一次构图工艺形成源极和漏极的图形， 与所述漏极 连接的数据线的图形， 以及与所述源极连接的接收电极的图形， 其中， 所述 源极和漏极相对而置形成沟道；
通过第二次构图工艺形成位于所述接收电极之上的光电二极管的图形， 以及位于所述光电二极管之上的透明电极的图形；
通过第三次构图工艺形成位于所述源极和漏极之上的欧姆层的图形； 通过第四次构图工艺形成位于所述欧姆层之上并覆盖所述沟道的有源层 的图形；
通过第五次构图工艺形成栅极绝缘层的图形， 所述栅极绝缘层在所述透 明电极的上方具有通孔；
通过第六次构图工艺形成位于所述栅极绝缘层之上、 所述沟道上方的栅 极的图形， 与所述栅极连接的栅线的图形， 以及在所述透明电极的上方通过 通孔与所述透明电极连接的偏压线的图形。
6、 如权利要求 5所述的制造方法， 进一步包括：
通过第七次构图工艺形成覆盖衬底基板的钝化层的图形， 所述钝化层具 有信号引导区过孔。
7、如权利要求 5或 6所述的制造方法， 其中， 所述通过第二次构图工艺 形成光电二极管的图形， 以及透明电极的图形的步骤包括：
依次沉积 N型半导体层、 I型半导体层、 P型半导体层和透明电极层， 然后通过一次构图工艺形成光电二极管的图形和透明电极的图形。
8、 一种传感器的制造方法， 包括：
在衬底基板上通过第一次构图工艺形成偏压电极的图形、 与所述偏压电 极连接的偏压电极引脚的图形、位于所述偏压电极之上的光电二极管的图形， 以及位于所述光电二极管之上的透明电极的图形；
通过第二次构图工艺形成位于所述透明电极和所述偏压电极引脚之上、 并覆盖所述衬底基板的第一钝化层的图形；
通过第三次构图工艺形成源极、 漏极和数据线的图形， 以及位于所述源 极和漏极之上的欧姆层的图形， 其中， 所述源极和漏极相对而置形成沟道， 所述漏极与所述数据线连接， 所述源极与所述透明电极连接；
通过第四次构图工艺形成位于所述欧姆层之上并覆盖所述沟道的有源层 的图形；
通过第五次构图工艺形成位于所述有源层之上的栅极绝缘层的图形、 位 于所述栅极绝缘层之上、 所述沟道上方的栅极的图形， 以及与所述栅极连接 的栅线的图形。
9、 如权利要求 8所述的制造方法， 进一步包括：
通过第六次构图工艺形成覆盖衬底基板的第二钝化层的图形， 所述第二 钝化层具有信号引导区过孔。
10、 如权利要求 8或 9所述的制造方法， 其中， 所述通过第一次构图工 艺形成偏压电极的图形、 偏压电极引脚的图形、 光电二极管的图形， 以及透 明电极的图形， 包括：
在衬底基板上依次沉积偏压电极层、 N型半导体层、 I型半导体层、 P型 半导体层和透明电极层， 并在透明电极层之上涂覆光刻胶；
釆用具有全透光区、 半透光区和不透光区的掩模板对衬底基板上的光刻 胶进行曝光、 显影， 得到具有光刻胶完全去除区、 光刻胶部分去除区和光刻 胶完全保留区的光刻胶图形；
对衬底基板上的光刻胶完全去除区进行刻蚀， 形成偏压电极的图形、 光 电二极管的图形和透明电极的图形；
对衬底基板上的光刻胶部分去除区进行灰化、 去除光刻胶部分去除区中 的光刻胶并且保留光刻胶完全保留区的光刻胶， 刻蚀且然后将光刻胶去除， 形成偏压电极引脚的图形。
11、如权利要求 10所述的制造方法， 其中， 所述掩模板的不透光区对应 形成偏压电极、 光电二极管和透明电极的区域； 所述掩模板的半透光区对应 形成偏压电极引脚的区域。
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