WO2014013848A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2014013848A1
WO2014013848A1 PCT/JP2013/067450 JP2013067450W WO2014013848A1 WO 2014013848 A1 WO2014013848 A1 WO 2014013848A1 JP 2013067450 W JP2013067450 W JP 2013067450W WO 2014013848 A1 WO2014013848 A1 WO 2014013848A1
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WIPO (PCT)
Prior art keywords
semiconductor
chip
semiconductor device
semiconductor element
mounting
Prior art date
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PCT/JP2013/067450
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English (en)
French (fr)
Inventor
伸一 寳木
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日産自動車株式会社
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Publication of WO2014013848A1 publication Critical patent/WO2014013848A1/ja

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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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Definitions

  • the present invention relates to a semiconductor device in which a semiconductor element is mounted on a member to be mounted.
  • JP 2008-166680A A semiconductor device in which a semiconductor element is mounted on a mounting member such as a bus bar using solder is known (JP 2008-166680A).
  • An object of the present invention is to provide a technique for preventing a mounted member from warping during cooling after mounting a semiconductor element.
  • a semiconductor device is disposed between a semiconductor element, a mounted member on which the semiconductor element is mounted by surface bonding, and the semiconductor element and the mounted member for bonding the semiconductor element to the mounted member.
  • a low elastic body. The low elastic body has a lower elastic modulus than the semiconductor element and the mounted member.
  • FIG. 1 is a circuit diagram of a three-phase inverter for driving a motor including the semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of one power module.
  • FIG. 3 is a diagram for explaining a method of mounting a semiconductor chip on a chip mounting electrode which is a mounted member in the semiconductor device according to the first embodiment.
  • FIG. 4 is a diagram for explaining the configuration of the semiconductor device according to the second embodiment.
  • FIG. 5 is a diagram for explaining the configuration of the semiconductor device according to the third embodiment.
  • FIG. 6 is a diagram for explaining the configuration of the semiconductor device according to the fourth embodiment.
  • FIG. 1 is a circuit diagram of a three-phase inverter 14 for driving a motor provided with the semiconductor device according to the first embodiment.
  • one power module 10 has a plurality of power semiconductors 11 (semiconductor elements) and a plurality of free-wheeling diodes 12 (semiconductor elements). Each freewheeling diode 12 is connected in antiparallel with each power semiconductor 11.
  • the power semiconductor 11 is configured by a semiconductor element such as a thyristor, GTO, or IGBT.
  • This one power module 10 is for one phase of a three-phase inverter 14 for driving the AC motor 13.
  • the power of the DC power supply 15 is converted into three-phase AC power for driving the AC motor 13 by the smoothing capacitor 16 and the three power modules 10.
  • the AC motor 13 is used, for example, for driving an electric vehicle (EV) or a hybrid vehicle (HEV).
  • the inverter 14 includes an external bus bar (output side) 21 connecting the AC motor 13 and the inverter 14, an external bus bar (P side) 22 and an external bus bar (N side) 23 connecting the DC power supply 15 and the inverter 14. Is connected.
  • One power module 10 includes an output electrode 24 connected to an external bus bar (output side) 21, a P-type electrode 25 connected to an external bus bar (P side) 22, and an N-type electrode 26 connected to an external bus bar (N side) 23. It has.
  • FIG. 2 is a cross-sectional view of one power module 10. Although three power modules 10 are shown in FIG. 1, all three have the same configuration. In the circuit diagram of FIG. 1, only two power semiconductors and two freewheeling diodes are shown for one power module 10. However, in the mounted state, four power semiconductors and four freewheeling diodes are used for one power module 10, and two power semiconductors and two freewheeling diodes are connected in parallel.
  • the power module 10 includes a chip mounting electrode 41 (a member to be mounted) integrally formed with the case 31 and a plurality of semiconductor chips (mounted) arranged (mounted) vertically above the chip mounting electrode 41 inside the case 31.
  • Semiconductor device) 51 and a cooler 61 provided for the purpose of cooling the semiconductor chip 51.
  • the cooler 61 is a base that fixes the chip mounting electrode 41 together with the case 31 in an electrically insulated state. If one of the two semiconductor chips 51 on the left and right is the power semiconductor 11, the other is the free wheel diode 12.
  • the left and right two semiconductor chips 51 are joined by a low elastic body 52 so as to be electrically conductive vertically above the chip mounting electrode 41.
  • the semiconductor chip 51 is connected to a high voltage electrode terminal 53 fixed to the case 31 by bonding wires 54 to 56 and a current-carrying metal electrode 57.
  • the electrode terminal 53 in the center is electrically connected to the external bus bar by screws.
  • the external bus bar is any one of an external bus bar (P side), an external bus bar (N side), and an external bus bar (output side).
  • the cooler 61 is fixed vertically below the power module 10.
  • An insulating sheet 62 is interposed between the cooler 61 and the chip mounting electrode 41 to electrically insulate them.
  • the insulating sheet 62 is coated or impregnated with grease for enhancing thermal conductivity while ensuring insulation.
  • the case 31 and the cooler 61 are fixed by bolts 63 and nuts 64 that are mounting members. That is, the chip mounting electrode 41 and the insulating sheet 62 are sandwiched between the case 31 and the cooler 61 and are fastened together with the bolt 63 and the nut 64. Thereby, each component of the power module 10 is fixed.
  • the inside of the case 31 is sealed with a sealing material 65 so that the surface of the semiconductor chip 51 (semiconductor element) does not oxidize or corrode due to contact with moisture or oxygen in the air. That is, the sealing material 65 covers the semiconductor chip 51 and the chip mounting electrode 41 from vertically above.
  • a gel-like resin is used as the sealing material 65.
  • FIG. 3 is a diagram for explaining a method of mounting the semiconductor chip 51 on the chip mounting electrode 41 which is a mounted member.
  • the semiconductor chip 51 is mounted on the chip mounting electrode 41 by surface bonding using the low elastic body 52 having a lower elastic modulus than the semiconductor chip 51 and the chip mounting electrode 41.
  • the low elastic body 52 has an elastic modulus lower than that of solder conventionally used when the semiconductor chip 51 is mounted.
  • a resin obtained by adding a silver filler, a copper filler, a nickel filler, or the like to a resin such as a silicon resin, an epoxy resin, or an acrylic resin can be used.
  • these materials are examples, and the low elastic body 52 is not limited to these materials.
  • the chip mounting electrode 41 mounted with the semiconductor chip 51 is referred to as a semiconductor device.
  • the mounted device Since the warpage of the chip mounting electrode 41 which is a member can be suppressed, the problem that the heat of the semiconductor chip 51 becomes difficult to escape does not occur.
  • the thickness of the chip mounting electrode 41 is increased in order to prevent the warpage of the chip mounting electrode 41.
  • the warping of the chip mounting electrode 41 is reduced. Since it can suppress, the thickness of the chip
  • tip mounting electrode 41 can be made thinner than the conventional one, and a semiconductor device can be reduced in size.
  • FIG. 4 is a diagram for explaining the configuration of the semiconductor device according to the second embodiment.
  • the thickness of the mounting region 71 of the semiconductor chip 51 is thinner than the thickness of the non-mounting region 72 of the semiconductor chip 51 out of the thickness of the chip mounting electrode 41 that is the mounted member.
  • the chip mounting electrode 41 has a recessed shape in which the mounting area 71 of the semiconductor chip 51 is thinner than the non-mounting area 72, and the semiconductor chip 51 is mounted in this recessed area.
  • the thickness of the chip mounting electrode 41 means the thickness of the semiconductor chip 51 in the mounting direction.
  • the mounting area of the semiconductor chip 51 includes not only the area where the low elastic body 52 and the chip mounting electrode 41 are in contact but also the peripheral area. However, the region where the low elastic body 52 and the chip mounting electrode 41 are in contact with each other may be the mounting region of the semiconductor chip 51.
  • the height of the non-mounting region 72 of the semiconductor chip 51 is set to the height of the mounting region 71. Since the height is higher than the height, the low elastic body 52 can be prevented from flowing out of the mounting region of the semiconductor chip 51.
  • FIG. 5 is a diagram for explaining the configuration of the semiconductor device according to the third embodiment.
  • the chip mounting electrode 41 which is a mounted member has a protrusion 81 provided on the outer periphery of the mounting region of the semiconductor chip 51.
  • the protrusion 81 has a shape protruding in the mounting direction of the semiconductor chip 51 so as to surround the outer periphery of the mounting region of the semiconductor chip 51.
  • the thickness of the chip mounting electrode 41 can be reduced as compared with the semiconductor device in the second embodiment.
  • the protrusions 81 provided on the chip mounting electrode 41 serve as ribs, the same rigidity as the chip mounting electrode 41 in the second embodiment can be ensured, and warping of the chip mounting electrode 41 is suppressed. can do. Further, the protrusion 81 can prevent the low elastic body 52 from flowing out of the mounting area of the semiconductor chip 51.
  • FIG. 6 is a diagram for explaining the configuration of the semiconductor device according to the fourth embodiment.
  • the chip mounting electrode 41 which is a member to be mounted, is provided on the outer periphery of the mounting area of the semiconductor chip 51, and a space 92 is provided on the side opposite to the side on which the semiconductor chip 51 is mounted.
  • It has the protrusion part 91 which has. More specifically, the protruding portion 91 has a shape protruding in the mounting direction of the semiconductor chip 51 so as to surround the outer periphery of the mounting region of the semiconductor chip 51, and is opposite to the mounting direction of the semiconductor chip 51. Has a cavity 92.
  • the thickness of the chip mounting electrode 41 can be reduced as compared with the semiconductor device in the second embodiment.
  • the projecting portion 91 on the chip mounting electrode 41 it is possible to prevent the low elastic body 52 from flowing out of the mounting area of the semiconductor chip 51.
  • the protrusion 91 since the protrusion 91 has the space 92 inside, it has a deformable structure. Thereby, the expansion / contraction deformation of the chip mounting electrode 41 due to the environmental change or the like during use of the semiconductor device can be absorbed by the deformation of the protruding portion 91.
  • the space 92 may have any structure as long as the expansion / contraction deformation of the chip mounting electrode 41 can be absorbed by the deformation of the projecting portion 91.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

　半導体装置は、半導体素子と、半導体素子が面接合により実装される被実装部材と、半導体素子を被実装部材に接合するために半導体素子と被実装部材との間に配置され、半導体素子および被実装部材より弾性率が低い低弾性体とを備える。

Description

半導体装置
　本発明は、半導体素子を被実装部材に実装した半導体装置に関する。
　半導体素子を、バスバーのような被実装部材に半田を用いて実装した半導体装置が知られている（ＪＰ２００８－１６６６８０Ａ）。
　しかしながら、ダイボンド時に熱膨張した被実装部材が半導体素子の実装後の冷却時に、半田固化収縮による歪みによって実装部材側に反るという問題が生じる。
　本発明は、半導体素子の実装後の冷却時に被実装部材が反るのを防ぐ技術を提供することを目的とする。
　一実施形態における半導体装置は、半導体素子と、半導体素子が面接合により実装される被実装部材と、半導体素子を被実装部材に接合するために半導体素子と被実装部材との間に配置される低弾性体とを備える。低弾性体は、半導体素子および被実装部材より弾性率が低い。
　本発明の実施形態、本発明の利点については、添付された図面とともに以下に詳細に説明される。
図１は、第１の実施形態に係る半導体装置を備えたモータ駆動用三相インバータの回路図である。 図２は、１つのパワーモジュールの断面図である。 図３は、第１の実施形態における半導体装置において、半導体チップを被実装部材であるチップ実装電極に実装する方法を説明するための図である。 図４は、第２の実施形態における半導体装置の構成を説明するための図である。 図５は、第３の実施形態における半導体装置の構成を説明するための図である。 図６は、第４の実施形態における半導体装置の構成を説明するための図である。
　（第１の実施形態）
　図１は、第１の実施形態に係る半導体装置を備えたモータ駆動用三相インバータ１４の回路図である。図１に示すように、１つのパワーモジュール１０は、複数のパワー半導体１１（半導体素子）及び複数の還流ダイオード１２（半導体素子）を有している。各還流ダイオード１２は、各パワー半導体１１と逆並列に接続されている。
　パワー半導体１１は、例えば、サイリスタ、ＧＴＯ、ＩＧＢＴ等の半導体素子によって構成される。この１つのパワーモジュール１０は、交流モータ１３を駆動するための３相インバータ１４の１相分である。直流電源１５の電力は、平滑用のコンデンサ１６と３個のパワーモジュール１０により、交流モータ１３を駆動する３相交流電力に変換される。交流モータ１３は、例えば、電気自動車（ＥＶ）やハイブリッド自動車（ＨＥＶ）の駆動に用いられる。
　詳細には、インバータ１４には、交流モータ１３とインバータ１４を接続する外部バスバー（出力側）２１、直流電源１５とインバータ１４を接続する外部バスバー（Ｐ側）２２及び外部バスバー（Ｎ側）２３が接続されている。１つのパワーモジュール１０は、外部バスバー（出力側）２１と接続する出力電極２４、外部バスバー（Ｐ側）２２と接続するＰ型電極２５及び外部バスバー（Ｎ側）２３と接続するＮ型電極２６を備えている。
　図２は、１つのパワーモジュール１０の断面図である。図１には、３つのパワーモジュール１０が示されているが、３つとも同じ構成である。なお、図１の回路図においては、１つのパワーモジュール１０についてパワー半導体が２つ、還流ダイオードが２つしか示していない。しかし、実装状態では、１つのパワーモジュール１０についてパワー半導体が４つ、還流ダイオードが４つ用いられ、２つのパワー半導体、２つの還流ダイオードがそれぞれ並列接続されている。
　パワーモジュール１０は、ケース３１の内部に、このケース３１と一体成形されたチップ実装電極４１（被実装部材）と、このチップ実装電極４１の鉛直上部に配置（実装）される複数の半導体チップ（半導体素子）５１と、半導体チップ５１を冷却する目的で備えられる冷却器６１とを有する。なお、冷却器６１は、ケース３１とともに、チップ実装電極４１を電気的に絶縁した状態で固定する基部である。左右に２つある半導体チップ５１は、その一方がパワー半導体１１であれば、他方は還流ダイオード１２である。
　左右２つの半導体チップ５１は、後述するように、低弾性体５２によって、チップ実装電極４１の鉛直上方に電気的に導通可能に接合される。半導体チップ５１は、ケース３１に固定される強電電極端子５３と、ボンディングワイヤ５４～５６や通電用金属電極５７により接続されている。中央にある電極端子５３は、ネジにより外部バスバーと電気的に接続される。なお、外部バスバーは、外部バスバー（Ｐ側）、外部バスバー（Ｎ側）、外部バスバー（出力側）のいずれかである。
　パワーモジュール１０の鉛直下方では、冷却器６１が固定される。冷却器６１とチップ実装電極４１との間には、これらを電気的に絶縁するための絶縁シート６２が挟み込まれている。絶縁シート６２は、絶縁を確保しつつ、熱導電性を高めるためのグリースが塗布又は含浸されている。
　ケース３１と冷却器６１とは、取付部材であるボルト６３及びナット６４によって固定される。すなわち、ケース３１と冷却器６１とによって、チップ実装電極４１及び絶縁シート６２を挟持し、これをボルト６３及びナット６４によって共締めする。これによりパワーモジュール１０の各部品が固定される。
　半導体チップ５１（半導体素子）の表面が空気中の湿気や酸素に触れて酸化したり腐食したりしないように、封止材６５によってケース３１内部が封止される。すなわち、封止材６５は、半導体チップ５１及びチップ実装電極４１を鉛直上方から被覆するものである。封止材６５としては、ゲル状の樹脂を用いている。
　図３は、半導体チップ５１を被実装部材であるチップ実装電極４１に実装する方法を説明するための図である。本実施形態では、半導体チップ５１およびチップ実装電極４１よりも弾性率が低い低弾性体５２を用いて、半導体チップ５１をチップ実装電極４１に面接合により実装する。この低弾性体５２は、半導体チップ５１を実装する際に従来用いられている半田よりも弾性率が低い。低弾性体５２としては、例えば、シリコン樹脂、エポキシ樹脂やアクリル樹脂などの樹脂に銀フィラー、銅フィラー、ニッケルフィラーなどを添加したものを用いることができる。ただし、これらの素材は例示であって、低弾性体５２がこれらのものに限定されることはない。
　なお、ここでは便宜上、チップ実装電極４１に半導体チップ５１を実装したものを半導体装置と呼ぶ。
　以上、第１の実施形態における半導体装置によれば、半導体素子５１と、半導体素子５１が面接合により実装されるチップ実装電極４１と、半導体素子５１をチップ実装電極４１に接合するために半導体素子５１とチップ実装電極４１との間に配置され、半導体素子５１およびチップ実装電極４１より弾性率が低い低弾性体５２とを備える。これにより、半導体素子５１の実装後の冷却時における固化収縮の歪みを低弾性体自身の弾性変形によって吸収することができるので、被実装部材であるチップ実装電極４１の反りを抑制することができる。被実装部材の反りが生じる従来の半導体装置では、反った部分が空間となって、半導体素子の熱が逃げにくくなるという問題が生じるが、第１の実施形態における半導体装置によれば、被実装部材であるチップ実装電極４１の反りを抑制することができるので、半導体チップ５１の熱が逃げにくくなるという問題も生じない。
　また、従来の半導体装置では、チップ実装電極４１の反りを防ぐためにチップ実装電極４１の厚さを厚くしていたが、第１の実施形態における半導体装置によれば、チップ実装電極４１の反りを抑制することができるため、チップ実装電極４１の厚さを従来のものよりも薄くすることができ、半導体装置を小型化することができる。
　－第２の実施形態－
　図４は、第２の実施形態における半導体装置の構成を説明するための図である。第２の実施形態における半導体装置では、被実装部材であるチップ実装電極４１の厚さのうち、半導体チップ５１の実装領域７１の厚さは、半導体チップ５１の非実装領域７２の厚さよりも薄い。すなわち、チップ実装電極４１は、半導体チップ５１の実装領域７１が非実装領域７２よりも厚さが薄い凹み形状となっており、このくぼんだ領域に半導体チップ５１が実装される。ここで、チップ実装電極４１の厚さとは、半導体チップ５１の実装方向の厚さを意味する。
　なお、半導体チップ５１の実装領域とは、図４に示すように、低弾性体５２とチップ実装電極４１とが接している部分の領域だけでなく、その周辺領域を含む。ただし、低弾性体５２とチップ実装電極４１とが接している部分の領域を半導体チップ５１の実装領域としてもよい。
　上述したように、半導体チップ５１の実装領域７１の厚さを、半導体チップ５１の非実装領域７２の厚さよりも薄くすることにより、半導体チップ５１の非実装領域７２の高さが実装領域７１の高さよりも高くなるので、低弾性体５２が半導体チップ５１の実装領域より外側に流出するのを防止することができる。
　－第３の実施形態－
　図５は、第３の実施形態における半導体装置の構成を説明するための図である。第３の実施形態における半導体装置では、被実装部材であるチップ実装電極４１は、半導体チップ５１の実装領域の外周に設けられた突起８１を有する。突起８１は、半導体チップ５１の実装領域の外周を取り囲むように、半導体チップ５１の実装方向に突出した形状をしている。
　第３の実施形態における半導体装置によれば、第２の実施形態における半導体装置と比べて、チップ実装電極４１の厚さ、特に、半導体チップ５１の非実装領域の厚さを薄くすることができる。また、チップ実装電極４１に設けられた突起８１がリブとしての役割を果たすので、第２の実施形態におけるチップ実装電極４１と同等の剛性を確保することができ、チップ実装電極４１の反りを抑制することができる。さらに、突起８１によって、低弾性体５２が半導体チップ５１の実装領域より外側に流出するのを防止することができる。
　－第４の実施形態－
　図６は、第４の実施形態における半導体装置の構成を説明するための図である。第４の実施形態における半導体装置では、被実装部材であるチップ実装電極４１は、半導体チップ５１の実装領域の外周に設けられ、半導体チップ５１が実装されている側とは逆側に空間９２を有する突状部９１を有する。より具体的には、突状部９１は、半導体チップ５１の実装領域の外周を取り囲むように、半導体チップ５１の実装方向に突出した形状をしており、半導体チップ５１の実装方向とは逆側に空洞９２を有する。
　第４の実施形態における半導体装置によれば、第２の実施形態における半導体装置と比べて、チップ実装電極４１の厚さ、特に、半導体チップ５１の非実装領域の厚さを薄くすることができる。また、チップ実装電極４１に突状部９１を設けることにより、低弾性体５２が半導体チップ５１の実装領域より外側に流出するのを防止することができる。さらに、突状部９１は内部に空間９２を有するので、変形可能な構造となっている。これにより、半導体装置の使用時における環境変化等に起因するチップ実装電極４１の膨張・収縮変形を、突状部９１の変形により吸収することができる。
　なお、空間９２は、チップ実装電極４１の膨張・収縮変形を突状部９１の変形により吸収できるのであればどのような構造でもよい。
　本発明は、上述した実施形態に限定されることはなく、本発明の要旨を逸脱しない範囲内で様々な変形や応用が可能である。
　本願は、２０１２年７月１９日に日本国特許庁に出願された特願２０１２－１６０７５３に基づく優先権を主張し、この出願の全ての内容は参照により本明細書に組み込まれる。

Claims (4)

  1. 　半導体素子と、
    　前記半導体素子が面接合により実装される被実装部材と、
    　前記半導体素子を前記被実装部材に接合するために前記半導体素子と前記被実装部材との間に配置され、前記半導体素子および前記被実装部材より弾性率が低い低弾性体と、
    を備える半導体装置。
  2. 　請求項１に記載の半導体装置において、
    　前記被実装部材の厚さのうち、前記半導体素子の実装領域の厚さは、前記半導体素子の非実装領域の厚さよりも薄い、
    半導体装置。
  3. 　請求項１に記載の半導体装置において、
    　前記被実装部材は、前記半導体素子の実装領域の外周に設けられ、前記半導体素子の実装方向に突出した突起を有する、
    半導体装置。
  4. 　請求項１に記載の半導体装置において、
    　前記被実装部材は、前記半導体素子の実装領域の外周に設けられ、前記半導体素子の実装方向に突出するとともに内部に空間を有する突状部を有する、
    半導体装置。
PCT/JP2013/067450 2012-07-19 2013-06-26 半導体装置 WO2014013848A1 (ja)

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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5067574A (ja) * 1973-10-15 1975-06-06
JPS57118658A (en) * 1981-12-07 1982-07-23 Hitachi Ltd Lead frame
JPS5844858U (ja) * 1981-09-21 1983-03-25 日本電気株式会社 リ−ドフレ−ム
JPS59125835U (ja) * 1983-02-09 1984-08-24 日本電気ホームエレクトロニクス株式会社 半導体装置
JPS59201433A (ja) * 1983-04-30 1984-11-15 Fujitsu Ltd 半導体装置の製造方法
JPH0344040A (ja) * 1989-07-12 1991-02-25 Hitachi Ltd 半導体装置及びその製造方法
JPH0817995A (ja) * 1994-06-27 1996-01-19 Nec Corp 半導体装置用リードフレーム
JPH11150135A (ja) * 1997-11-17 1999-06-02 Nec Corp 熱伝導性が良好な導電性ペースト及び電子部品
JPH11312764A (ja) * 1997-12-04 1999-11-09 Lg Semicon Co Ltd エリアアレイ型半導体パッケージ及びその製造方法
JP2001127234A (ja) * 1999-10-25 2001-05-11 Matsushita Electronics Industry Corp リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5067574A (ja) * 1973-10-15 1975-06-06
JPS5844858U (ja) * 1981-09-21 1983-03-25 日本電気株式会社 リ−ドフレ−ム
JPS57118658A (en) * 1981-12-07 1982-07-23 Hitachi Ltd Lead frame
JPS59125835U (ja) * 1983-02-09 1984-08-24 日本電気ホームエレクトロニクス株式会社 半導体装置
JPS59201433A (ja) * 1983-04-30 1984-11-15 Fujitsu Ltd 半導体装置の製造方法
JPH0344040A (ja) * 1989-07-12 1991-02-25 Hitachi Ltd 半導体装置及びその製造方法
JPH0817995A (ja) * 1994-06-27 1996-01-19 Nec Corp 半導体装置用リードフレーム
JPH11150135A (ja) * 1997-11-17 1999-06-02 Nec Corp 熱伝導性が良好な導電性ペースト及び電子部品
JPH11312764A (ja) * 1997-12-04 1999-11-09 Lg Semicon Co Ltd エリアアレイ型半導体パッケージ及びその製造方法
JP2001127234A (ja) * 1999-10-25 2001-05-11 Matsushita Electronics Industry Corp リードフレームとそれを用いた樹脂封止型半導体装置およびその製造方法

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