WO2013183101A1 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- WO2013183101A1 WO2013183101A1 PCT/JP2012/064368 JP2012064368W WO2013183101A1 WO 2013183101 A1 WO2013183101 A1 WO 2013183101A1 JP 2012064368 W JP2012064368 W JP 2012064368W WO 2013183101 A1 WO2013183101 A1 WO 2013183101A1
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- G11C13/004—Reading or sensing circuits or methods
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/10—Phase change RAM [PCRAM, PRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
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Definitions
- the present invention relates to a semiconductor memory device.
- phase change memories using chalcogenide materials as recording materials have been actively studied.
- a phase change memory is a type of resistance change memory that stores information using the fact that recording materials between electrodes have different resistance states.
- the phase change memory stores information using the fact that the resistance value of a phase change material such as Ge 2 Sb 2 Te 5 is different between an amorphous state and a crystalline state.
- the resistance is high in the amorphous state and low in the crystalline state. Therefore, information is read from the memory by applying a potential difference to both ends of the element, measuring the current flowing through the element, and determining the high resistance state / low resistance state of the element.
- phase change memory data is rewritten by changing the electrical resistance of the phase change film to different states by Joule heat generated by current.
- the reset operation that is, the operation of changing to the high resistance amorphous state is performed by flowing a large current for a short time to dissolve the phase change material, and then rapidly decreasing the current and quenching.
- the set operation that is, the operation of changing to a low-resistance crystal state is performed by flowing a current sufficient to maintain the phase change material at the crystallization temperature for a long time.
- this phase change memory is suitable for miniaturization because the current required to change the state of the phase change film decreases as the miniaturization progresses. For this reason, research is actively conducted.
- Patent Document 1 as a method for highly integrating a phase change memory, a plurality of through-holes penetrating all layers are collectively formed in a stacked structure in which a plurality of gate electrode materials and insulating films are alternately stacked.
- a configuration is disclosed in which a gate insulating film, a channel layer, and a phase change film are formed and processed inside a through hole.
- Each memory cell includes a transistor and a phase change element connected in parallel, and a plurality of memory cells are connected in series in a vertical direction, that is, a normal direction to the semiconductor substrate, to form a phase change memory chain.
- individual phase change memory chains are selected by vertical selection transistors.
- the channel semiconductor layer of each select transistor has a structure separated for each phase change memory chain.
- JP 2008-160004 A WO2011 / 0774545 gazette
- Patent Document 1 has the following problems. In order to reduce the bit cost, it is desirable to stack as many memory cells as possible. However, when many memory cells are stacked, the number of cells connected in series increases, so that the voltage across the chain increases when a current necessary for the rewrite operation of the phase change memory flows. On the other hand, since the voltage necessary for rewriting the selected chain is simultaneously applied to the non-selected chain, it is necessary to prevent the current from flowing through the non-selected chain by turning off the selection transistor.
- the selection transistor In order to stack as many cells as possible, it is necessary to suppress the voltage drop by reducing the ON resistance of the selection transistor for the selection chain and to secure a voltage applied to the phase change memory chain. On the other hand, for the non-selected chain, it is necessary to suppress the OFF leakage current of the selection transistor. Therefore, the selection transistor is required to reduce both the resistance in the ON state and the source / drain leakage current in the OFF state.
- the technique described in Patent Document 1 is considered to be difficult to achieve both of these. For example, in order to reduce the resistance in the ON state, the channel length of the selection transistor may be shortened. On the other hand, the leakage current between the source and drain in the OFF state increases due to the short channel effect.
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device using a select transistor having a small resistance in an ON state, a small leakage current in an OFF state, and a small size. To do.
- the channel of the first selection transistor for selecting the memory cell array is electrically connected to each adjacent memory cell array.
- a suitable memory cell array can be manufactured by increasing the density, and the capacity of the semiconductor memory device and the bit cost can be reduced.
- FIG. 2 is a diagram illustrating a configuration of a memory cell array unit of the semiconductor memory device according to the first embodiment.
- FIG. FIG. 2 is an equivalent circuit diagram of the semiconductor memory device of FIG. 1.
- Select transistor STTr It is a three-dimensional schematic diagram.
- FIG. 4 is a YZ sectional view of FIG. 3.
- 6 is a diagram illustrating a state in which a current flows through a channel semiconductor layer 50p in Embodiment 1.
- FIG. FIG. 6 is a diagram illustrating a configuration of a memory cell array unit of a semiconductor memory device according to a second embodiment.
- FIG. 7 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 6.
- the selection transistor STTr It is a figure which shows the characteristic.
- FIG. 4 is a three-dimensional schematic diagram illustrating a part of a memory cell array portion of a semiconductor memory device according to a third embodiment.
- FIG. 10 is an equivalent circuit diagram of the semiconductor memory device shown in FIG.
- FIG. 10 is a diagram illustrating a configuration of a memory cell array unit of a semiconductor memory device according to a fourth embodiment.
- FIG. 12 is an equivalent circuit diagram of the semiconductor memory device of FIG. 11.
- FIG. 10 is a diagram illustrating a configuration of a memory cell array unit of a semiconductor memory device according to a fifth embodiment.
- FIG. 14 is an equivalent circuit diagram of the semiconductor memory device shown in FIG. 13.
- FIG. 10 is a three-dimensional schematic diagram of a part of a memory cell array portion of a semiconductor memory device according to a sixth embodiment.
- FIG. 16 is an equivalent circuit diagram of the semiconductor memory device of FIG. 15.
- 12 is a partial cross-sectional view of a memory cell array portion of a semiconductor memory device according to a seventh embodiment.
- FIG. 18 is an equivalent circuit diagram of the semiconductor memory device of FIG. 17.
- 10 is a partial cross-sectional view of a memory cell array portion of a semiconductor memory device according to an eighth embodiment.
- FIG. 20 is a three-dimensional schematic diagram of the semiconductor memory device shown in FIG. 19.
- FIG. 21 is an equivalent circuit diagram of the semiconductor memory device of FIG. 20.
- FIG. 22 is a diagram showing a modification of FIGS.
- FIG. 1 is a diagram showing a configuration of a memory cell array portion of a semiconductor memory device according to Embodiment 1 of the present invention.
- FIG. 1A is a three-dimensional schematic diagram of a part of the semiconductor memory device, and
- FIG. 1B is an XZ sectional view of FIG.
- the electrode 3 extends in the X direction and operates as a bit line (selection electrode) for selecting the phase change memory chain PCMCHAIN in the Y direction.
- a stacked body in which gate polysilicon layers 21 p, 22 p, 23 p, and 24 p to be cell gate electrodes and insulating films 11, 12, 13, 14, and 15 are alternately stacked is disposed below the electrode 3, a stacked body in which gate polysilicon layers 21 p, 22 p, 23 p, and 24 p to be cell gate electrodes and insulating films 11, 12, 13, 14, and 15 are alternately stacked is disposed.
- a phase change memory chain PCMCHAIN is formed in a hole in the Z direction formed in the stacked body.
- Select transistor STTr Has a gate electrode 81p, a gate insulating film 10, and a channel semiconductor layer 50p. Select transistor STTr. Insulating films 71, 72, and 31 are disposed around the periphery.
- the plate-like electrode 2 is connected to the selection transistor STTr. It is arranged at the bottom of.
- the N-type semiconductor layer 38p electrically connects the electrode 3 and PCMCHIAN.
- the insulating film 92 is formed between the electrode 3 and PCMCHIAN.
- the N-type semiconductor layer 60p electrically connects the electrode 2 and the channel semiconductor layer 50p.
- PCMCHAIN formed in the hole of the stacked body includes a gate insulating film 9, a channel semiconductor layer 8p, a phase change material layer 7, and an insulating film 91.
- the gate electrodes 81p can be formed at a 2F pitch and a 3F pitch, respectively, where F is the minimum processing dimension. That is, a memory cell having a projected area 6F 2 in the XY plane can be formed.
- phase change material layer 7 for example, a material that stores information by utilizing the difference between the resistance value in the amorphous state and the resistance value in the crystalline state, such as Ge 2 Sb 2 Te 5, can be used.
- the phase change material in the amorphous state is heated above the crystallization temperature and held for about 10 ⁇ 6 seconds or longer. It implements by making it into a crystalline state.
- the phase change material in the crystalline state can be brought into an amorphous state by heating it to a temperature equal to or higher than the melting point to make it into a liquid state and then rapidly cooling it.
- FIG. 2 is an equivalent circuit diagram of the semiconductor memory device of FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG.
- Each memory cell includes a cell transistor and a phase change memory connected in parallel.
- PCMCHAIN is configured by connecting memory cells in series.
- the potential application circuit is a circuit that applies a potential to each electrode, and is appropriately provided in the embodiments described below.
- the reset operation / set operation is performed using Joule heat of current flowing through the phase change material layer 7 of the SMC.
- the read operation is performed by detecting the current flowing through the phase change material layer 7 of the SMC and determining the resistance state.
- Select transistor STTr Is used to select PCMCHAIN.
- Select transistor STTr Connected to PCMCHAIN including SMC.
- An ON voltage is applied to the gate of the other transistors, and other selection transistors STTr.
- An OFF voltage is applied to the gate.
- a voltage (VRESET / VSET / VREAD) corresponding to the reset / set / read operation is applied to the bit line 3 connected to the PCMCHAIN including the SMC, and the other bit lines 3 (non-selected bit lines)
- the same 0 V as that of the wiring (word line WL) formed by the lower electrode 2 is applied.
- FIG. 3 shows the selection transistor STTr. It is a three-dimensional schematic diagram. For comparison, FIG. 3A shows a conventional selection transistor STTr. FIG. 3B shows the configuration of the select transistor STTr. The configuration of was shown.
- the select transistor STTr In the conventional configuration shown in FIG. 3A, the select transistor STTr.
- the channel semiconductor layers 50p are separated for each PCMCHAIN in the Y direction.
- the channel semiconductor layer 50p is shared by PCMCHAIN adjacent in the Y direction. That is, a select transistor STTr. For selecting a certain PCMCHAIN.
- Channel transistor layer 50p and select transistor STTr For selecting PCMCHAIN adjacent to PCMCHAIN in the Y direction.
- the channel semiconductor layer 50p is electrically connected.
- FIG. 4 is a YZ sectional view of FIG. 4A and 4B correspond to FIGS. 3A and 3B, respectively.
- the conventional selection transistor STTr the selection transistor STTr.
- the difference in configuration will be described more specifically.
- Select transistor STTr As one of the characteristics required for this, there is a source / drain breakdown voltage that is equal to or greater than the potential difference between the selected bit line potential (VRESET / VSET / VREAD) and the word line potential (0 V) during the OFF operation. STTr.
- the source / drain breakdown voltage can be secured by increasing the channel length. However, since the resistance between the source and the drain during the ON operation is increased at the same time, the voltage drop is increased, and the voltage applied to both ends of the selected chain SPCMCHAIN is decreased.
- the number of memory cells connected in series in the chain cell increases, the number of non-selected cells connected in series with the SMC increases, so that the voltage drop in the non-selected cells increases.
- the channel length needs to be equal to or greater than the minimum value LCHMIN that can ensure the source-drain breakdown voltage. Therefore, in the first embodiment, the selection transistor STTr.
- the configuration shown in FIG. 1 In order to reduce the resistance between the source and drain during N operation while securing the channel length of LCHMIN to be equal to or longer than LCHMIN, the configuration shown in FIG.
- the select transistor STTr In the conventional configuration shown in FIG. 4A, the select transistor STTr. However, the resistance increases because current flows through the channel semiconductor layer 50p having the width F.
- a recess is provided between the channel semiconductor layers 50p connected to the adjacent PCMCHAIN.
- the selection transistor STTr. can be ensured to be equal to or longer than LCHMIN.
- the interval between adjacent PCMCHAIN is F, if the depth of the recess is (LCHMIN ⁇ F) / 2 or more, the length of the leakage current path (LEAKPATH) becomes LCHMIN or more. This is equivalent to securing a channel length equal to or greater than LCHMIN.
- FIG. 5 is a diagram for explaining how a current flows through the channel semiconductor layer 50p in the first embodiment.
- the current density of the portion of the channel semiconductor layer 50p whose width in the Y direction is F is the same as that of the conventional configuration, but the current is shared in the Y direction in the portion shared by the Y direction. It can be considered that resistance is low.
- the channel semiconductor layer 50p in the first embodiment can be regarded as having a low resistance as compared with the conventional structure.
- the effect shown in FIG. 5A is exhibited when PCMCHAIN is sparsely selected in the Y direction.
- the current flowing through the SPCMCHAIN spreads in the Y direction in the channel semiconductor layer 50p and can be regarded as having a low resistance.
- PCMCHAIN is selected densely in the Y direction as shown in FIG. 5B, there is not much room for the current flowing through each SPCMCHAIN to spread in the Y direction in the channel semiconductor layer 50p, so the resistance is reduced. The effect of becomes smaller.
- FIG. 6 is a diagram showing a configuration of a memory cell array unit of the semiconductor memory device according to the second embodiment.
- 6A is a three-dimensional schematic diagram of a part of the semiconductor memory device
- FIG. 6B is an XZ sectional view of FIG. 6A.
- some parts such as a cell gate and a gate insulating film are omitted from the illustration.
- the difference of the first embodiment from FIG. 1 is that the selection transistor STTr.
- the gate electrode 81p does not have a groove for separation in the X direction, that is, a space of the dimension F in which the insulating film 31 is embedded. Therefore, STTr.
- the channel semiconductor layer 50p is formed on both surfaces of the gate electrode 81p in the X direction via the gate insulating film 10. With this configuration, STTr. Pitch in the X direction and STTr. The pitch in the X direction of PCMCHAIN formed on the upper part by connecting to can be set to 2F. However, as will be described later, since the insulating film 31 is omitted, it should be noted that when an ON potential is applied to one gate electrode 81p, the channel semiconductor layers 50p on both sides thereof are turned on.
- the channel semiconductor layer 50p is formed to be connected in the Y direction, and a recess similar to that shown in FIG. 4 is formed on the upper surface of the channel semiconductor layer 50p. Thereby, the leakage current between SPCMCHAIN and USPCMCHAIN adjacent in the Y direction can be suppressed.
- the selection transistor STTr The problem is that when an ON voltage is applied to one gate electrode 81p, the channel semiconductor layers 50p on both sides in the X direction of the gate electrode 81p are turned on, and two X-direction selections are made simultaneously. . In the second embodiment, this problem is dealt with as follows.
- the channel semiconductor layer 50p When the thickness of the channel semiconductor layer 50p, that is, the dimension TSi in the X direction is sufficiently small, even if an ON voltage is applied to one of the gate electrodes 81p on both sides of the channel semiconductor layer 50p, a strong OFF voltage is applied to the other Thus, the channel semiconductor layer 50p can be turned off.
- an ON voltage (5 V in FIG. 6B) was applied to the gate electrodes 81p on both sides of the channel semiconductor layer 50p (rightmost) to be turned on, and 5 V was applied.
- the OFF voltage higher than the normal OFF voltage is applied to the gate electrode 81p on the opposite side (FIG. 6 ( In b), ⁇ 10V) is applied.
- the channel semiconductor layer 50p to which 5V is applied to both gates is turned on, and the channel semiconductor layer 50p to which 5V and ⁇ 10V are applied is turned off.
- the channel semiconductor layers 50p whose gates on both sides are 0V and the channel semiconductor layers 50p whose gates on both sides are 0V and ⁇ 10V are turned off. Therefore, only the channel semiconductor layer 50p in which 5 V is applied to both gates can be turned on. That is, PCMCHAIN can be selected in the X direction.
- FIG. 7 is an equivalent circuit diagram of the semiconductor memory device shown in FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG. Since the method for selecting a cell in PCMCHAIN and the method for reading / writing information from / to a memory cell are the same as in the first embodiment, a method for selecting PCMCHAIN will be described.
- STTr Connected to PCMCHAIN including SMC.
- An ON voltage for example, 5 V
- An OFF voltage for example, 0 V
- STTr Connected to the gate of STTr.
- An OFF voltage for example, ⁇ 10 V
- stronger than the normal OFF voltage is applied to the gates of No. 1 and No. 2.
- a voltage (VRESET / VSET / VREA) corresponding to the reset / set / read operation is applied to the bit line 3 connected to the PCMCHAIN including the SMC, and the other bit lines 3 (unselected bit lines) The same 0 V as that of the wiring (word line WL) formed by the lower electrode 2 is applied.
- FIG. 8 shows the selection transistor STTr. It is a figure which shows the characteristic.
- FIG. 8A shows STTr.
- the thickness TSi of the channel semiconductor layer 50p are shown in FIG. Shows the drain current-drain voltage (VD) dependence.
- the characteristics when the voltages of the two gates are both 5V are indicated by (5V, 5V), and the characteristics when the voltages are 5V and -10V are indicated by (5V, -10V).
- the select transistor STTr As described above, in the semiconductor memory device according to the second embodiment, the select transistor STTr. It is possible to reduce the channel resistance during the ON operation while securing the channel length for ensuring the source / drain breakdown voltage during the OFF operation.
- the semiconductor memory device according to the second embodiment can increase the capacity and bit cost of the semiconductor memory device in that the same effect as that of the first embodiment can be exhibited while the projected area on the XY plane of the memory cell is 4F 2. This is advantageous from the viewpoint of reducing.
- a plurality of wirings formed by the upper electrode 3 are formed at a pitch 2F in the Y direction as bit lines extending in the X direction.
- the third embodiment a configuration example in which the upper electrode 3 is formed in a plate shape like the lower electrode 2 will be described. Even in the case of using the configuration according to the third embodiment, the pitch in the X direction / direction of the memory cell to 2F, the projected area in the XY plane of the memory cell can be 4F 2.
- FIG. 9 is a three-dimensional schematic diagram showing a part of the memory cell array portion of the semiconductor memory device according to the third embodiment. For ease of understanding, some parts such as a cell gate and a gate insulating film are omitted from the illustration.
- the difference between the second embodiment and FIG. 6 is that the bit line 3 has a plate shape, and that the selection transistor is on the lower side of STDTr. And the upper STUTr. It is composed of two stages. STUTr. Is provided to select PCMCHAIN in the Y direction in view of the bit line 3 being formed in a plate shape.
- the gate electrodes 81p are formed at a 2F pitch so as to extend in the Y direction as in the second embodiment, and the upper selection transistors STUTr.
- the gate electrodes 82p are formed at a 2F pitch so as to extend in the X direction orthogonal to 81p. STDTr.
- the channel semiconductor layer 50p is formed to be connected in the Y direction.
- STUTr The channel semiconductor layer 51p is formed to be connected in the X direction.
- STDTr Has a structure similar to that shown in FIG. 8A, that is, a structure in which gate electrodes 81p are formed on both sides of one channel semiconductor layer 50p via a gate insulating film. STUTr. Similarly, the gate electrode 82p is formed on both sides of one channel semiconductor layer 51p via a gate insulating film. STDTr. In the channel semiconductor layer 50p, a recess is formed in the same manner as in the first and second embodiments in order to suppress a leakage current between the selected chain and the non-selected chain. STUTr. It is not necessary to form such a recess in the channel semiconductor layer 51p. The reason will be described with reference to FIG.
- PCMCHAIN is selected.
- the leakage current path is (a) STUTr. Is ON and STDTr. Is OFF, USPCMCHAIN, (b) STUTr. STDTr. Is in the OFF state USPCMCHAIN, (c) STUTr. STDTr. Flows between the upper electrode 3 and the lower electrode 2 via the USPCMCHAIN in the ON state. The current path is shown as sneak path in FIG.
- Sneak path leakage current is always STDTr.
- the channel semiconductor layer 50p in the OFF state flows in the Y direction. Therefore, STDTr. If a recess as shown in FIG. 9A is formed only in the channel semiconductor layer 50p, the leakage current can be suppressed. As can be seen from the symmetry, STDTr. No recess is formed in the channel semiconductor layer 50p of STUTr. Even when a recess is formed in the channel semiconductor layer 50p, leakage current can be suppressed. That is, STDTr. And STUTr. Leakage current can be suppressed by forming a recess in either one of the above.
- FIG. 10 is an equivalent circuit diagram of the semiconductor memory device shown in FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG. Since a method for selecting a cell in PCMCHAIN and a method for reading / writing information from / to a memory cell are the same as those in the first and second embodiments, a method for selecting PCMCHAIN will be described.
- the third embodiment when selecting PCMCHAIN, STDTr. And STUTr. Both are used.
- STDTr Connected to PCMCHAIN including SMC.
- An ON voltage for example, 5 V
- An OFF voltage for example, 0 V
- STTr. Is connected to the gate electrode 81p of the STTr.
- An OFF voltage for example, ⁇ 10 V
- stronger than the normal OFF voltage is applied to the gate electrode 81p.
- STUTr Connected to PCMCHAIN including SMC. ON voltage (for example, 5V) is applied to the two gate electrodes 81p of STUTr. An OFF voltage (for example, 0 V) is applied to the gate electrode 82p.
- ON voltage for example, 5V
- An OFF voltage for example, 0 V
- An OFF voltage for example, ⁇ 10 V
- VRESET / VSET / VREAD The voltage (VRESET / VSET / VREAD) corresponding to the reset / set / read operation is applied to the bit line 3 (plate electrode), and 0 V is applied to the wiring (word line WL) by the lower electrode 2.
- the semiconductor memory device is similar to the first and second embodiments in that the selection transistor STTr. It is possible to reduce the channel resistance during the ON operation while securing the channel length for ensuring the source / drain breakdown voltage during the OFF operation.
- the semiconductor memory device since the number of bit lines 3 for passing a current required for driving PCMCHAIN, particularly during a reset operation / set operation, is reduced as compared with the first and second embodiments.
- the peripheral circuit area for driving 3 can be reduced. Furthermore, it is advantageous from the viewpoint of increasing the capacity of the semiconductor memory device and reducing the bit cost in that the same effect as in the first embodiment can be exhibited while the projected area on the XY plane of the memory cell is 4F 2 .
- Embodiments 1 to 3 PCMCHAIN was formed in the hole formed in the laminated body of the cell gate and the insulating film.
- One PCMCHAIN is formed in one hole.
- Embodiment 4 of the present invention a configuration example will be described in which a stacked body of cell gates and insulating films is formed in a stripe shape extending in the Y direction, and a pair of PCMCHAIN is formed in a groove of the stacked body.
- FIG. 11 is a diagram showing a configuration of a memory cell array unit of the semiconductor memory device according to the fourth embodiment.
- FIG. 11A is a three-dimensional schematic diagram of a part of the semiconductor memory device, and
- FIG. 11B is an XZ sectional view of FIG.
- some parts such as a cell gate and a gate insulating film are omitted from the illustration.
- a groove extending in the Y direction is formed in a laminated body in which cell gate electrodes 21p to 24p and insulating films 11 to 15 are alternately laminated.
- a phase change memory chain PCMCHAIN is formed in the groove. Below the PCMCHAIN, the selection transistor STTr. Is arranged.
- PCMCHAIN formed in the trench of the stacked body has a gate insulating film 9, a channel semiconductor layer 8p, a phase change material layer 7, and an insulating film 91.
- the PCMCHAIN are separated from each other at a 2F pitch in the Y direction in the groove of the laminate.
- the insulating film 91 disposed in the trench of the stacked body separates the individual PCMCHAIN in the X direction, thereby forming a pair of PCMCHAIN facing in the X direction in each PCMCHAIN.
- the channel semiconductor layer 50p is formed so as to be connected in the Y direction as in the first to third embodiments.
- a recess is formed in the same manner as in the first to third embodiments in order to suppress a leakage current between SPCMCHAIN and USPCMCHAIN adjacent in the Y direction.
- the gate electrode 81p of each 2F pitch the minimum feature size is F can be formed in 3F pitch, it is possible to form a unit structure of the projected area 6F 2 in the XY plane. Since a pair of PCMCHAIN separated by the insulating film 91 is formed in the unit structure, the projected area in the XY plane of PCMCHAIN can be 3F 2 .
- FIG. 12 is an equivalent circuit diagram of the semiconductor memory device of FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG.
- the method for selecting a cell in PCMCHAIN and the method for reading / writing information from / to a memory cell are the same as in the first to third embodiments.
- the method for selecting PCMCHAIN is the same as in the first embodiment.
- the semiconductor memory device is similar to the first to third embodiments in that the select transistor STTr. It is possible to reduce the channel resistance during the ON operation while securing the channel length for ensuring the source / drain breakdown voltage during the OFF operation.
- the semiconductor memory device while the projected area in the XY plane of the memory cell to 3F 2, in that it has the same effect as Embodiment 1, capacity and cost per bit of the semiconductor memory device This is advantageous from the viewpoint of reducing.
- FIG. 13 is a diagram showing a configuration of a memory cell array unit of the semiconductor memory device according to the fifth embodiment.
- FIG. 13A is a three-dimensional schematic diagram of a part of the semiconductor memory device, and
- FIG. 13B is an XZ sectional view of FIG.
- some parts such as a cell gate and a gate insulating film are omitted from the illustration.
- FIG. 11 is different from FIG. 11 in the fourth embodiment in that the select transistor is located on the lower side of STDTr. And the upper STUTr. It is composed of two stages. Another difference is that the lower selection transistor STDTr.
- the gate electrode 81p has no groove for separation in the X direction, that is, a space of the dimension F in which the insulating film 31 is embedded. Therefore, STDTr.
- the channel semiconductor layer 50p is formed on both surfaces of the gate electrode 81p in the X direction via the gate insulating film 10. With this configuration, STDTr. X-direction pitch and STDTr.
- the pitch in the X direction of PCMCHAIN formed on the upper part by connecting to can be set to 2F.
- FIG. 6 of the second embodiment it should be noted that when an ON potential is applied to one gate electrode 81p, the channel semiconductor layers 50p on both sides thereof are turned on.
- the STDTr The channel semiconductor layer 50p of the STTr.
- a recess is formed on the upper surface of the channel semiconductor layer 50p as in the first to fourth embodiments, thereby suppressing leakage current between SPCMCHAIN and USPCMCHAIN adjacent in the Y direction.
- an ON voltage is applied to the gate electrodes 81p on both sides of the channel semiconductor layer 50p to be turned on, and an OFF voltage is applied to the gate electrodes 81p on both sides of the channel semiconductor layer 50p to be turned off.
- an OFF voltage is applied to the gate electrodes 81p on both sides of the channel semiconductor layer 50p to be turned off.
- the gate electrodes 82p are extended in the Y direction and formed at a 2F pitch.
- Channel semiconductor layers 8p are formed on both sides in the X direction of the gate electrode 82p.
- the channel semiconductor layer 8p is the same layer as the channel semiconductor layer 8p of the PCMCHAIN cell transistor and is also electrically connected.
- Two channel semiconductor layers 8p are formed between the gate electrodes 82p adjacent in the X direction, and are connected to the two PCMCHAINs, respectively.
- STUTr The channel semiconductor layers 8p are separated without being connected in the Y direction.
- Every other gate electrode 82p is electrically bundled so that power can be supplied from a peripheral circuit.
- Two lines of STUTr By applying an ON voltage to one of the gate electrodes 82p and an OFF voltage to the other, only one of the two PCMCHAINs can be brought into conduction with the bit line 3.
- STUTr instead of the channel semiconductor layer 8p of STDTr. It is also conceivable to separate the channel semiconductor layer 50p in the Y direction. In this case, however, STDTr.
- the channel length for securing the source / drain breakdown voltage during the OFF operation cannot be secured. In other words, a recess for securing the channel length between adjacent PCMCHAINs must be provided on the channel semiconductor layer of the selection transistor for selecting PCMCHAIN.
- FIG. 14 is an equivalent circuit diagram of the semiconductor memory device shown in FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG. Since a method for selecting a cell in PCMCHAIN and a method for reading / writing information from / to a memory cell are the same as in the first to fourth embodiments, a method for selecting PCMCHAIN will be described.
- the fifth embodiment when selecting PCMCHAIN, STDTr. And STUTr. Both are used.
- the semiconductor memory device is similar to the first to third embodiments in that the select transistor STTr. It is possible to reduce the channel resistance during the ON operation while securing the channel length for ensuring the source / drain breakdown voltage during the OFF operation.
- the semiconductor memory device STUTr. Since the channel semiconductor layer 8p is separated in the Y direction, the ON resistance is large, and the number of cells that can be stacked in PCMCHAIN is reduced accordingly. However, since the projected area of PCMCHAIN onto the XY plane is as small as 2F 2 , it is advantageous for high integration in the semiconductor substrate surface.
- a plurality of wirings with the upper electrode 3 are formed at a pitch 2F so as to extend in the X direction.
- the sixth embodiment of the present invention a configuration example in which the upper electrode 3 is formed in a plate shape like the lower electrode 2 will be described.
- the semiconductor memory device according to the present embodiment 6 the pitch of the X-direction / Y-direction of the memory cell to 2F, the projected area in the XY plane of the unit structures can be 4F 2.
- the projected area of the PCMCHAIN in the XY plane can be 2F 2 .
- FIG. 15 is a three-dimensional schematic diagram of a part of the memory cell array portion of the semiconductor memory device according to the sixth embodiment. For ease of understanding, some parts such as a cell gate and a gate insulating film are omitted from the illustration.
- the difference from FIG. 14 of the fifth embodiment is that the bit line 3 has a plate shape, and that the upper selection transistors (STO, STE) and STUTr. Of two stages, STDTr. And the gate electrode of the upper selection transistor are orthogonal to each other.
- STDTr Has a gate electrode (not shown in FIG. 15) extending in the X direction and a channel semiconductor layer 50p extending in the X direction, and a leak current between the selected chain and the non-selected chain is formed on the channel semiconductor layer 50p.
- a recess is formed as in the first to fifth embodiments. STUTr. It is not necessary to form a recess in the channel semiconductor layer 51p. The reason is the same as the description of the sneak path of the third embodiment.
- FIG. 16 is an equivalent circuit diagram of the semiconductor memory device of FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG. Since a method for selecting a cell in PCMCHAIN and a method for reading / writing information from / to a memory cell are the same as in the first to fifth embodiments, a method for selecting PCMCHAIN will be described. In the sixth embodiment, when selecting PCMCHAIN, STDTr. And STUTr. Both are used.
- STDTr Connected to PCMCHAIN including SMC. ON voltage is applied to the two gate electrodes 81p of the other STDTr. An OFF voltage is applied to the gate electrode 81p. However, STDTr. STDTr. Is connected to the gate electrode 81p of the STDTr. An OFF voltage stronger than a normal OFF voltage is applied to the gate electrode 81p.
- STUTr Connected to PCMCHAIN including SMC. ON voltage is applied to the two gate electrodes 8p of the other STUTr. An OFF voltage is applied to the gate electrode 8p. However, STUTr. Connected to the gate electrode 8p of the STUTr. A strong OFF voltage is applied to the other gate electrode 8p.
- the ON voltage is applied to the side connected to the PCMCHAIN including the SMC, and the OFF voltage is applied to the other side.
- a voltage (VRESET / VSET / VREAD) corresponding to the reset / set / read operation is applied to the bit line 3 (plate electrode), and 0 V is applied to the wiring (word line WL) formed by the lower electrode 2.
- the semiconductor memory device has a smaller number of bit lines 3 for passing a current required for driving PCMCHAIN, particularly during a reset operation / set operation, as compared with the fourth to fifth embodiments.
- the peripheral circuit area for driving the bit line 3 can be reduced. Further, since the projected area on the XY plane of PCMCHAIN is 2F 2 , it is advantageous for high integration in the semiconductor substrate surface.
- the semiconductor memory device of the sixth embodiment can also achieve an effect of increasing the capacity and reducing the bit cost.
- the selection transistor is formed in multiple stages in order to form and selectively operate the PCMCHIAN having a projected area of 2F 2 in the XY plane.
- Embodiment 7 of the present invention a configuration example will be described in which a PCMCHIAN having a projected area in the XY plane of 2F 2 is formed and selectively operated with a single selection transistor.
- FIG. 17 is a partial cross-sectional view of the memory cell array portion of the semiconductor memory device according to the seventh embodiment.
- the selection transistor is formed in one stage, the selection transistor STTr.
- the selection transistor STTr Are formed with a pitch F.
- Select transistor STTr Each channel semiconductor layer 50p is connected to only one PCMCHAIN in the X direction.
- the channel semiconductor layer 50p is connected in the Y direction, and a recess is formed in the upper portion in the same manner as in the first to sixth embodiments.
- FIG. 18 is an equivalent circuit diagram of the semiconductor memory device of FIG.
- the voltage conditions for the read operation / set operation / reset operation are also shown in FIG. Since a method for selecting a cell in PCMCHAIN and a method for reading / writing information from / to a memory cell are the same as in the first to sixth embodiments, a method for selecting PCMCHAIN will be described.
- STTr. when selecting PCMCHAIN, STTr. Is used.
- STTr Connected to PCMCHAIN including SMC. ON voltage is applied to two gate electrodes (one is 81p and the other is 82p), and the other STTr. An OFF voltage is applied to the gate electrode. However, STTr. Connected to the gate electrode of the STTr. The other gate electrode is applied with an OFF voltage (for example, ⁇ 10 V) stronger than the normal OFF voltage.
- a voltage (VRESET / VSET / VREAD) corresponding to the reset / set / read operation is applied to the bit line 3 (SBL) connected to the PCMCHAIN including the SMC, and the other bit line 3 (USBL) and the lower electrode 0V is applied to the wiring (word line WL) by 2.
- the semiconductor memory device of the seventh embodiment is advantageous for high integration in the semiconductor substrate surface because the projected area of the PCMCHAIN on the XY plane is 2F 2 .
- STTr STTr.
- Channel semiconductor layer 50p is shared by adjacent PCMCHAINs, the select transistor STTr. It is possible to reduce the channel resistance during the ON operation while securing the channel length for ensuring the source-drain breakdown voltage during the OFF operation. As a result, the number of cells that can be stacked in PCMCHAIN can be increased. As a result, the capacity of the semiconductor memory device and the bit cost reduction effect can be obtained even in the semiconductor memory device of the seventh embodiment.
- FIG. 19 is a partial cross-sectional view of the memory cell array portion of the semiconductor memory device according to the eighth embodiment.
- the layer selection transistor LSTTr. Is placed below the PCMCHAIN array of the semiconductor memory device described in the first embodiment.
- An example of a structure in which two layers of the structure in which the film is formed is laminated is illustrated. Each layered structure has the same configuration, but the upper layered body is given a number in the 200s for distinction.
- FIG. 20 is a three-dimensional schematic diagram of the semiconductor memory device shown in FIG. For ease of understanding, some parts such as a cell gate and a gate insulating film are omitted from the illustration.
- LSTTr The channel semiconductor layer 51p extends in the Y direction similarly to the gate electrode 82p. STTr. Channel semiconductor layer 50p and LSTTr. The channel semiconductor layers 51p are connected to each other one by one.
- FIG. 21 is an equivalent circuit diagram of the semiconductor memory device of FIG. The voltage conditions for the read operation / set operation / reset operation are also shown in FIG. LSTTr. Is added to form a PCMCHAIN array, and as shown in the equivalent circuit diagram of FIG. 21, at least one of bit line 3 / word line 2 / cell gate / selection transistor gate is provided between the PCMCHAIN arrays formed in a plurality of layers. Can be shared. As a result, an increase in the peripheral circuit area required for driving the bit line 3 / word line 2 / cell gate / selection transistor gate can be suppressed, and a reduction in bit cost can be promoted.
- the semiconductor memory device includes a layer selection transistor LSTTr. Since the channel semiconductor layers 51p are connected in the Y direction, the ON resistance can be reduced. Also, the LSTTr. All the gate electrodes can be bound and operated. Also, the leakage current between PCMCHAIN is STTr. Of the channel semiconductor layer 50p of the LSTTr. It is not necessary to form a recess in the channel semiconductor layer 51p.
- the layer selection transistor LSTTr In the operation of the memory cell, the layer selection transistor LSTTr. Of the PCMCHAIN array including the SMC is included. An ON voltage is applied to the gate (LST1 in FIG. 21), and the other layer selection transistors LSTTr. An OFF voltage is applied to the gate (LST2 in FIG. 21).
- the selection of PCMCHAIN and the method of selecting the memory cell therein are the same as in the first embodiment.
- FIG. 22 is a diagram showing a modification of FIGS. 19 to 21, the layer selection transistor LSTTr.
- the gate electrode 82p and the channel semiconductor layer 51p of STTr. are formed in a pattern extending in the Y direction parallel to the STTr. It can also be formed by a pattern extending in the X direction perpendicular to the line.
- LSTTr. The role of the lower electrode 2 and STTr. ON / OFF switching between the channel semiconductor layers 50p of LSTTr. STTr. Even if they are orthogonal to each other, the same function can be exhibited. Also, LSTTr. In FIG. 5, the ON resistance can be reduced by connecting the channel semiconductor layer 51p in the X direction.
- LSTTr Is compared with PCMCHAIN of the semiconductor memory device of the first embodiment.
- PCMCHAIN was added to the structure, but LSTTr.
- PCMCHAIN arrays can also be stacked by adding.
- at least one of bit line 3 / word line 2 / cell gate / selection transistor gate can be shared among the PCMCHAIN arrays formed in a plurality of layers. For this reason, it is possible to suppress an increase in peripheral circuit area necessary for driving the bit line 3 / word line 2 / cell gate / selection transistor gate, and to promote a reduction in bit cost.
- the layer selection transistor LSTTr Since the channel semiconductor layer 51p can be extended in the X direction or the Y direction, the ON resistance can be reduced.
- the semiconductor memory device can share the bit line, the word line, the cell gate, and the selection transistor gate in each layer of the PCMCHAIN array formed in a plurality of layers. For this reason, an increase in the peripheral circuit area necessary for driving the bit line, the word line, the cell gate, and the selection transistor gate can be suppressed, and a reduction in bit cost can be promoted. Since the channel of the layer selection transistor can be shared and the ON resistance can be reduced, a decrease in the number of stacked cells in the PCMCHAIN due to the addition of the layer selection transistor can be suppressed. As a result, the semiconductor memory device of the sixth embodiment can also achieve an effect of increasing the capacity and reducing the bit cost.
- the present invention is not limited to the above-described embodiment, and includes various modifications.
- the above embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to the one having all the configurations described.
- a part of the configuration of one embodiment can be replaced with the configuration of another embodiment.
- the configuration of another embodiment can be added to the configuration of a certain embodiment. Further, with respect to a part of the configuration of each embodiment, another configuration can be added, deleted, or replaced.
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Abstract
Description
図1は、本発明の実施形態1に係る半導体記憶装置のメモリセルアレイ部の構成を示す図である。図1(a)は半導体記憶装置の一部の立体模式図、図1(b)は図1(a)のXZ断面図である。
以上のように、本実施形態1に係る半導体記憶装置によれば、OFF動作時のソース/ドレイン間耐圧を確保するためのチャネル長を確保しつつ、ON動作時のチャネル抵抗を低減することができる。これにより、PCMCHAIN内の積層可能なセル数を増加させることができる。その結果、半導体記憶装置の大容量化とビットコストを低減する効果が得られる。
実施形態1の半導体記憶装置においては、X方向のメモリセルのピッチが3Fであるため、Y方向のピッチ2Fと合せてメモリセルのXY面における投影面積は6F2となっている。本発明の実施形態2では、X方向のメモリセルのピッチを2Fにし、メモリセルのXY面における投影面積を4F2にした構成例を説明する。
以上のように、本実施形態2に係る半導体記憶装置は、実施形態1と同様に、選択トランジスタSTTr.のOFF動作時におけるソース/ドレイン間耐圧を確保するためのチャネル長を確保しつつ、ON動作時のチャネル抵抗を低減することができる。
実施形態2において、上部電極3による配線は、X方向に延伸するビット線としてY方向のピッチ2Fで複数形成されている。本実施形態3では、上部電極3も下部電極2と同様にプレート状に形成した構成例を説明する。本実施形態3に係る構成を用いる場合においても、X方向/方向のメモリセルのピッチを2Fにし、メモリセルのXY面における投影面積を4F2にすることができる。
以上のように、本実施形態3の半導体記憶装置は、実施形態1~2と同様に、選択トランジスタSTTr.のOFF動作時におけるソース/ドレイン間耐圧を確保するためのチャネル長を確保しつつ、ON動作時のチャネル抵抗を低減することができる。
実施形態1~3では、セルゲートと絶縁膜の積層体に形成した孔内にPCMCHAINを形成した。1つの孔内には1つのPCMCHAINが形成されている。本発明の実施形態4では、セルゲートと絶縁膜の積層体をY方向に延伸するストライプ状にし、積層体の溝内に1対のPCMCHAINを形成した構成例を説明する。
以上のように、本実施形態4に係る半導体記憶装置は、実施形態1~3と同様に、選択トランジスタSTTr.のOFF動作時におけるソース/ドレイン間耐圧を確保するためのチャネル長を確保しつつ、ON動作時のチャネル抵抗を低減することができる。
実施形態4の半導体記憶装置は、X方向のメモリセルのピッチが3Fであるため、Y方向のピッチ2Fと合せて単位構造のXY面内における投影面積は6F2となる。単位構造にPCMCHAINが2つあるので、PCMCHAIN1つあたりのXY面内における投影面積は3F2となる。本発明の実施形態5では、X方向のメモリセルのピッチを2Fにし、PCMCHAINのXY面内における投影面積を2F2にした構成例を説明する。
以上のように、本実施形態5に係る半導体記憶装置は、実施形態1~3と同様に、選択トランジスタSTTr.のOFF動作時におけるソース/ドレイン間耐圧を確保するためのチャネル長を確保しつつ、ON動作時のチャネル抵抗を低減することができる。
実施形態5の半導体記憶装置では、上部電極3による配線がX方向に延伸するようにピッチ2Fで複数形成されている。本発明の実施形態6では、上部電極3も下部電極2と同様にプレート状に形成した構成例を説明する。本実施形態6に係る半導体記憶装置は、X方向/Y方向のメモリセルのピッチを2Fにし、単位構造のXY面内における投影面積を4F2にすることができる。また実施形態4~5に係る半導体記憶装置と同様に、単位構造内に2つのPCMCHAINが形成されるので、PCMCHAINのXY面内における投影面積を2F2にすることができる。
以上のように、本実施形態6の半導体記憶装置は、実施形態4~5と比較して、PCMCHAINの駆動、特にリセット動作/セット動作時に必要な電流を流すビット線3の数が減るので、ビット線3を駆動するための周辺回路面積を低減できる。またPCMCHAINのXY面における投影面積が2F2となるので、半導体基板面内の高集積化にとって有利である。
実施形態5~6の半導体記憶装置は、XY面内における投影面積が2F2であるPCMCHIANを形成し選択的に動作させるため、選択トランジスタを多段で形成していた。本発明の実施形態7では、1段の選択トランジスタで、XY面内における投影面積が2F2であるPCMCHIANを形成し選択的に動作させる構成例を説明する。
以上のように、本実施形態7の半導体記憶装置は、PCMCHAINのXY面における投影面積が2F2となるので、半導体基板面内の高集積化にとって有利である。また、STTr.のチャネル半導体層50pが隣接PCMCHAINどうしで共有されているので、実施形態1~6と同様に、選択トランジスタSTTr.のOFF動作時のソース/ドレイン間耐圧を確保するためのチャネル長を確保しつつON動作時のチャネル抵抗を低減することができる。これにより、PCMCHAIN内の積層可能なセル数を増加させることができる。その結果、本実施形態7の半導体記憶装置でも大容量化とビットコスト低減効果が得られる。
実施形態1~7の半導体記憶装置を更に大容量化するため、PCMCHAINアレイをさらに積層することもできる。本発明の実施形態8では、PCMCHAINアレイを積層した構成例を説明する。
以上のように、本実施形態8の半導体記憶装置は、複数層形成するPCMCHAINアレイの各層でビット線、ワード線、セルゲート、選択トランジスタゲートを共有化することができる。このため、ビット線、ワード線、セルゲート、選択トランジスタゲートを駆動するために必要な周辺回路面積の増加を抑制し、低ビットコスト化が推進できる。層選択トランジスタのチャネルを共有化しON抵抗を低減できるので、層選択トランジスタを追加したことによるPCMCHAIN内のセル積層数減少は抑制できる。その結果、本実施形態6の半導体記憶装置でも大容量化とビットコスト低減効果が得られる。
3、203:下部電極
21p、22p、23p、24p:ゲートポリシリコン層
81p、82p:ゲート電極
7、207:相変化材料層
8p、50p、51p、208p、250p、251p:チャネル半導体層
9、10、20、209、210、220:ゲート絶縁膜層
60p、61p、62p、260p、38p、238p:N型半導体層
11、12、13、14、15、71、72、73、74:絶縁膜層
211、212、213、214、215、271、272、273、274:絶縁膜層
31、32、91、92、231、232、291、292:絶縁膜層
PCMCHAIN:相変化メモリチェイン
SPCMCHAIN:選択相変化チェイン
USPCMCHAIN:非選択相変化チェイン
STTr.:選択トランジスタ
STUTr.:上部選択トランジスタ
STDTr.:下部選択トランジスタ
STO、STE:選択トランジスタ
LSTTr.:層選択トランジスタ
LST1、LST2:層選択トランジスタのゲート電極
GATE1、GATE2、GATE3、GATE4:トランジスタのゲート電極
GATE21、GATE22、GATE23、GATE24:トランジスタのゲート電極
GL1、GL2、GL3、GL4:ゲートに給電する端子
STm-2、STm-1、STm、STm+1、STm+2、STm+3、STm+4、STm+5:選択トランジスタゲート
BL、BLn-1、BLn、BLn+1、BLn+2:ビット線
SBL:選択ビット線
USBL:非選択ビット線
SMC:選択メモリセル
WL:ワード線
VREAD:読出し電圧
VSET:セット電圧
VRESET:リセット電圧
Tsi:チャネルシリコン膜厚
Claims (13)
- 下部電極上に配置され、第1方向に延伸する複数の第1選択トランジスタと、
前記下部電極の法線方向に直列接続された1以上のメモリセルを含み、前記第2方向に沿って複数設けられたメモリセルアレイと、
前記第2方向に沿って複数設けられたメモリセルアレイのうちいずれかを選択する選択部と、
を備え、
前記法線方向における前記メモリセルアレイの一端は前記第1選択トランジスタと電気的に接続され、他端は前記選択部と電気的に接続され、
前記第1選択トランジスタは、前記第2方向に沿って複数設けられており、
各前記第1選択トランジスタのチャネルは、前記第2方向に沿って隣接する各前記メモリセルアレイと電気的に接続されている
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記第1選択トランジスタのチャネルのうち、前記第2方向に沿って隣接する前記メモリセルアレイ間の部分において、前記チャネルを前記法線方向に陥没させた凹部が形成されている
ことを特徴とする半導体記憶装置。 - 請求項2において、
前記凹部の深さは、前記第1選択トランジスタのソース-ドレイン間の耐圧を確保できる最小距離の半分から、前記第2方向に沿って隣接する前記メモリセルアレイ間の間隔の半分を減算した距離以上である
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記選択部は、前記第2方向に延伸し前記第1方向に複数配置された選択線として構成されており、
前記メモリセルアレイの前記他端は、前記メモリセルアレイの上方に位置する前記選択線と直接接続されている
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記半導体記憶装置は、前記第1選択トランジスタのゲート電極に電位を印加する電位印加回路を備え、
前記第1選択トランジスタのゲート電極は、前記第2方向に隣接する各前記第1選択トランジスタのチャネルそれぞれと、ゲート絶縁膜を介して接続されており、
前記電位印加回路は、
ON状態にする前記第1選択トランジスタのチャネルに接続された前記ゲート電極には前記第1選択トランジスタをON状態にする所定のON電位を印加し、
OFF状態にする前記第1選択トランジスタのチャネルであって前記ON電位が印加される前記ゲート電極に接続された前記チャネルに、前記ON電位が印加される前記ゲート電極の反対側において接続された前記ゲート電極には、前記第1選択トランジスタをOFF状態にする所定のOFF電位よりも小さい第2OFF電位を印加し、
OFF状態にする前記第1選択トランジスタのチャネルであって前記第2OFF電位が印加される前記ゲート電極に接続された前記チャネルに、前記第2OFF電位が印加される前記ゲート電極の反対側において接続された前記ゲート電極には、前記OFF電位を印加する
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記選択部は、
前記第1方向と前記第2方向によって形成される平面上に形成された平面状の選択プレートと、
前記選択プレートと前記メモリセルアレイの間に配置され、前記第2方向に延伸し、各前記メモリセルアレイに対応して前記第1方向に沿って複数設けられた第2選択トランジスタと、
を備えていることを特徴とする半導体記憶装置。 - 請求項1において、
前記メモリセルアレイは、
前記第2方向に沿って対向して配置された1対のメモリセルを有し、
前記第1選択トランジスタは、
前記1対のメモリセルそれぞれを個別に選択することができるように構成されている
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記メモリセルアレイは、
前記第2方向に沿って対向して配置された1対のメモリセルを有し、
前記第1選択トランジスタのゲート電極は、
前記第2方向に隣接する各前記第1選択トランジスタのチャネルそれぞれと、ゲート絶縁膜を介して接続されており、
前記半導体記憶装置は、
前記選択部と前記メモリセルアレイの間に配置され、前記1対のメモリセルそれぞれを個別に選択する第3選択トランジスタと、
前記第1選択トランジスタのゲート電極に電位を印加する電位印加回路と、
を備え、
前記電位印加回路は、
ON状態にする前記第1選択トランジスタのチャネルに接続された前記ゲート電極には前記第1選択トランジスタをON状態にする所定のON電位を印加し、
OFF状態にする前記第1選択トランジスタのチャネルであって前記ON電位が印加される前記ゲート電極に接続された前記チャネルに、前記ON電位が印加される前記ゲート電極の反対側において接続された前記ゲート電極には、前記第1選択トランジスタをOFF状態にする所定のOFF電位よりも小さい第2OFF電位を印加し、
OFF状態にする前記第1選択トランジスタのチャネルであって前記第2OFF電位が印加される前記ゲート電極に接続された前記チャネルに、前記第2OFF電位が印加される前記ゲート電極の反対側において接続された前記ゲート電極には、前記OFF電位を印加する
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記選択部は、前記第1方向と前記第2方向によって形成される平面上に形成された平面状の選択プレートとして構成されており、
前記メモリセルアレイは、
前記第2方向に沿って対向して配置された1対のメモリセルを有し、
前記第1選択トランジスタのゲート電極は、
前記第2方向に隣接する各前記第1選択トランジスタのチャネルそれぞれと、ゲート絶縁膜を介して接続されており、
前記半導体記憶装置は、
前記選択部と前記メモリセルアレイの間に配置され、前記第2方向に延伸し、各前記メモリセルアレイに接続された第4選択トランジスタと、
前記第4選択トランジスタと前記メモリセルアレイの間に配置され、前記1対のメモリセルそれぞれを個別に選択する第5選択トランジスタと、
を備えたことを特徴とする半導体記憶装置。 - 請求項1において、
前記メモリセルアレイは、
前記第2方向に沿って対向して配置された1対のメモリセルを有し、
前記第1選択トランジスタは、
前記メモリセルアレイが有する前記1対のメモリセルのうち一方と、前記一方のメモリセルを有する前記メモリセルアレイに隣接する前記メモリセルアレイが有する前記1対のメモリセルのうち一方とに接続された第1ゲート電極と、
前記メモリセルアレイが有する前記1対のメモリセルそれぞれに接続された第2ゲート電極と、
が絶縁膜を介して組になって接続されて構成されており、
前記半導体記憶装置は、
前記第1および第2ゲート電極に電位を印加する電位印加回路を備え、
前記電位印加回路は、
選択する前記メモリセルに接続された前記第1および第2ゲート電極には前記第1選択トランジスタをON状態にする所定のON電位を印加し、
選択しない前記メモリセルに接続された前記第2ゲート電極であって前記ON電位が印加される前記第1ゲート電極に隣接する前記第2ゲート電極と、選択しない前記メモリセルに接続された前記第1ゲート電極であって前記ON電位が印加される前記第2ゲート電極に隣接する前記第1ゲート電極には、前記第1選択トランジスタをOFF状態にする所定のOFF電位よりも小さい第2OFF電位を印加し、
選択しない前記メモリセルに接続された前記第2ゲート電極であって前記ON電位が印加される前記第1ゲート電極に隣接していない前記第2ゲート電極と、選択しない前記メモリセルに接続された前記第1ゲート電極であって前記ON電位が印加される前記第2ゲート電極に隣接していない前記第1ゲート電極には、前記OFF電位を印加する
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記半導体記憶装置は、
前記第1選択トランジスタと、
前記選択部と、
前記メモリセルアレイと、
を有する積層体を複数積層して形成され、
前記積層体はさらに、
前記第1選択トランジスタと前記下部電極の間に配置され、前記積層体を選択する層選択トランジスタを備える
ことを特徴とする半導体記憶装置。 - 請求項11において、
前記積層体が有する前記第1選択トランジスタのゲート電極、前記選択部、前記下部電極、および前記メモリセルアレイ内の前記メモリセルのセルゲート電極のうち少なくともいずれかは、他の前記積層体が有する対応する部位と等電位となるように構成され、
前記層選択トランジスタのゲート電極は、各前記積層体間で電気的に独立している
ことを特徴とする半導体記憶装置。 - 請求項1において、
前記メモリセルは抵抗変化型メモリであることを特徴とする半導体記憶装置。
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