WO2015186164A1 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- WO2015186164A1 WO2015186164A1 PCT/JP2014/064571 JP2014064571W WO2015186164A1 WO 2015186164 A1 WO2015186164 A1 WO 2015186164A1 JP 2014064571 W JP2014064571 W JP 2014064571W WO 2015186164 A1 WO2015186164 A1 WO 2015186164A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
- H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
- H10B63/34—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the vertical channel field-effect transistor type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/823—Device geometry adapted for essentially horizontal current flow, e.g. bridge type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa or cup type devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
Definitions
- the present invention relates to a rewritable nonvolatile memory, for example, a phase change memory, a ReRAM, an STT-MRAM, a memory having a charge storage layer, a semiconductor storage device including a memory having an antifuse layer, or a storage system including the semiconductor storage device It is related to technology effective when applied to.
- a rewritable nonvolatile memory for example, a phase change memory, a ReRAM, an STT-MRAM, a memory having a charge storage layer, a semiconductor storage device including a memory having an antifuse layer, or a storage system including the semiconductor storage device It is related to technology effective when applied to.
- Patent Document 1 describes a technique for manufacturing a large-capacity semiconductor memory device by using a phase change memory as a nonvolatile memory and connecting a plurality of bits in series in a chain. Further, it is described that “in a semiconductor memory in which a diode and a transistor are connected in series, there is a problem that the characteristics of the transistor deteriorate due to carriers entering from the diode to the transistor” (see summary). Further, paragraph [0044] states that “the following operation is performed in a cell in which a memory cell in which such a transistor and a phase change element are connected in parallel, ie, a chain cell, is connected”. Has been.
- each word line 59 is formed with control electrodes 15, 25, 35, 45 on the staircase at the end of the memory array of each layer, and connected to the control electrodes having different depths.
- the word line contact plugs 55, 56, 57, and 58 are connected to each other ”(see paragraph [0016]).
- Patent Document 3 This publication states that “contact 349 provides electrical connection to select lines 241, 242, 243 and select line 244” (see paragraph [0022]).
- Patent Document 4 This publication describes that “the M2 wiring in the multilayer wiring is used as the word line shunt wiring WLSi” (see paragraph [0026]).
- JP 2012-69830 A JP 2008-140912 A Special table 2013-533628 gazette JP 2011-060397 A
- the read bit line is extended in a direction parallel to the silicon substrate, and the first selection is performed in the same direction as the read bit line.
- a line hereinafter referred to as a Y selection line
- the second selection line is extended in a direction parallel to the silicon substrate and in a direction perpendicular to the read bit line.
- the X selection line and the Y selection line used for the memory selection operation are connected to the silicon substrate via contacts. In order to increase the read speed and the write speed, it is necessary to drive the Y selection line at a high speed. For this reason, the number of base wiring lines extending in the same direction as the Y selection line increases.
- the present application includes a plurality of means for solving the above-described problems.
- a plurality of contacts that connect the signal line for selecting the address in the second direction and the semiconductor substrate are arranged in a region that does not interfere with the bit line extended in the first direction.
- 1 is an example showing a partial planar configuration of a memory array of a semiconductor memory device according to Embodiment 1 of the present invention
- 1 is an example showing a partial planar configuration of a memory array of a semiconductor memory device according to Embodiment 1 of the present invention
- 2 is an example showing a partial cross-sectional configuration of a memory array compared with the semiconductor memory device of Example 1 of the present invention.
- 2 is an example showing a partial cross-sectional configuration of a memory array compared with the semiconductor memory device of Example 1 of the present invention.
- 2 is an example showing a partial cross-sectional configuration of a memory array compared with the semiconductor memory device of Example 1 of the present invention.
- 2 is an example showing a partial planar configuration of a memory array compared with the semiconductor memory device of Example 1 of the present invention.
- 1 is an example showing a circuit configuration of a part of a memory array of a semiconductor memory device according to Embodiment 1 of the present invention
- 2 is an example showing a circuit configuration of a read bit line selector of the semiconductor memory device according to the first embodiment of the present invention.
- 2 is an example showing a circuit configuration including a global read bit line of the semiconductor memory device according to the first embodiment of the present invention
- 1 is an example showing a circuit configuration of a sense amplifier of a semiconductor memory device according to Example 1 of the present invention. It is an example which shows the cross-sectional structure of a part of memory array of the semiconductor memory device of Example 1 of this invention.
- FIG. 1 is an example showing a partial planar configuration of a memory array of a semiconductor memory device according to Embodiment 1 of the present invention; It is an example which shows the one part planar structure of the memory array of the semiconductor memory device of Example 2 of this invention. It is an example which shows the one part planar structure of the memory array of the semiconductor memory device of Example 3 of this invention. It is an example which shows the one part planar structure of the memory array of the semiconductor memory device of Example 4 of this invention. It is an example which shows the one part planar structure of the memory array of the semiconductor memory device of Example 4 of this invention. It is an example which shows the cross-sectional structure of a part of memory array of the semiconductor memory device of Example 5 of this invention.
- FIG. 10 is an example of a circuit configuration of a part of the memory array MA of the semiconductor memory device 1201 of this embodiment.
- the memory array MA is composed of a plurality of memory chains MC.
- the memory chain MC is configured by connecting a plurality of memory cells CELL in series.
- Memory cell CELL is configured by connecting one phase change element PCM and one Z selection element ZMOS in parallel.
- one phase change element PCM and a plurality of Z selection elements ZMOS are connected in parallel.
- the Z direction is a direction orthogonal to the silicon substrate, and the X direction and the Y direction are preferably orthogonal to the Z direction and orthogonal to each other. In this way, a plurality of memory cells existing in the Z direction can be collectively formed by a single drilling process, and the manufacturing cost can be reduced.
- the read bit line is preferably extended in the X direction or the Y direction. In this embodiment, the description will be made assuming that the read bit line is extended in the X direction and parallel to the Y selection line.
- the memory chain is stacked in four layers. It goes without saying that it is possible to stack more than four layers or to have a number of layers less than four. There is an advantage that the memory capacity can be increased by increasing the number of stacked layers. There is an advantage that manufacturing is facilitated by reducing the number of stacked layers.
- FIG. 1 A schematic plan view of the second layer of the memory chain will be described with reference to FIG.
- a plurality of memory chains MC exist in the second-layer memory array 2.
- the memory chain of the X address I and Y address J of the H layer is denoted MC (H)-(I)-(J).
- a plurality of read bit lines RBL are extended in the X direction.
- the read bit line of the Y address C of the A layer is shown as RBL (H)-(J).
- the read bit line RBL is shared by a plurality of memory arrays MA. By sharing, it is possible to reduce the contact area of the read bit line, and the chip area can be reduced and can be manufactured at low cost.
- a plurality of Y selection lines Y are extended in the X direction.
- FIG. 1 shows a schematic cross-sectional view of A-A ′ shown in FIG.
- the Y selection line Y is connected to the L-shaped wiring L via the sub-contact SCONT.
- the L-shaped wiring L is connected to the base contact wiring 201 via the contact CONT. Further, it is connected to the base MOS 102 through a connection not shown.
- the selection operation is, for example, when the memory chain MC-2-0-0 is selected and the memory chain MC-2-0-0 is selected from the state where the memory chain MC-2-0-1 is not selected. Instead, the memory chain MC-2-0-1 is changed to a selected state, that is, the selected state of the memory cell CELL is changed.
- the third-layer read bit line RBL3, for example, RBL3-0 or RBL3-1 does not exist in the vicinity of the contact, for example, within a distance within 2F (F is the minimum processing dimension). Further, the underlying wiring 101 does not exist in the vicinity of the contact.
- the read bit line is a wiring used in the memory array MA and extends in the X direction.
- the base wiring 101 has many wirings extending in the X direction, and if there is a contact CONT continuously in the Y direction, the layout must be such that the base wiring 101 exists in the vicinity of the contact CONT.
- a layout in which the base wiring 101 is not provided near the contact CONT Is possible.
- the base MOS 102 is a MOS fabricated on the silicon substrate 103, and the base wiring 101 means a wiring for a signal line, a power supply line, or the like that drives the base MOS 102.
- a signal driven by the base MOS is used for a memory array selection operation or the like.
- it is used for driving the Y selection line Y.
- the transition speed of the Y selection line can be improved, the selection operation regarding the Y address can be performed at high speed, and a high-speed write operation can be realized.
- the reason why the number of wirings extending in the X direction is larger than the wiring extending in the Y direction with respect to the base wiring will be described.
- the number of selection operations when one page is written is expressed by the following mathematical formula (Formula 1).
- Number of selection operations page size / number of simultaneous write bits Since the phase change memory has a relatively large write current of, for example, 40 ⁇ A, the number of simultaneous write bits is as small as 32 bits, for example, and the number of selection operations is increased. For example, when the page size is 8832B in the 8 KB + spare area 640B, the number of selection operations is 2,208.
- the page area which is a unit of reading and writing, has a length in the Y direction orthogonal to the read bit line longer than the length in the X direction.
- a description will be given by taking as an example a case where a page area extends over four memory chains MC in the X direction.
- the number of operations for selecting the Y selection line is 2208, and the number of operations for selecting the X selection line is 4.
- the number of selection operations for the Y selection line is 552 times, the number of selection operations for the X selection line is 2208 times, and the total number of selection operations for the X selection line and the Y selection line increases. .
- the number of signal lines for controlling it increases and the width of the signal line increases. Therefore, with respect to the base wiring, the number of wirings extending in the X direction is larger than the wiring extending in the Y direction.
- the Y selection line has both the role of designating the write target address and the role of designating whether or not to write.
- the X selection line and the Z selection line have a role of designating a write target address.
- the length of the Y selection line is preferably about twice the length of the X selection line.
- the left half of the memory array MA (the side with the smaller Y address) is wired upward ( ⁇ X direction) from the sub-contact SCONT, and then bent in the left direction ( ⁇ Y direction). Connect to contact CONT on the left of array MA.
- the right half (the Y address larger side) of the memory array MA is wired upward ( ⁇ X direction) from the sub-contact SCONT and then bent rightward (Y direction) to the contact CONT on the right side of the memory array MA. Connecting.
- the length of the memory array MA in the X direction is substantially equal to the length of the Y selection line, and the length in the Y direction is substantially equal to the length of the X selection line.
- the number of memory chains in the X direction is preferably a multiple of two. By doing so, it is possible to simplify the control circuit, reduce the chip area, and reduce the manufacturing cost. It goes without saying that redundant rows can be added to the number of memory chains MC in the X direction. In this case, there is an effect that the loss rate of the product due to manufacturing failure can be reduced.
- a case where the number of memory chains in the X direction is 512 will be described as an example.
- the number of memory chains in the Y direction is preferably slightly larger than a multiple of two.
- ECC error correction information
- redundant columns can be further added to the number of memory chains MC in the Y direction.
- the loss rate of the product due to manufacturing failure can be reduced.
- the size of the additional data is preferably about 8% of the size of the main body data. It goes without saying that it can be made 2% to 30%.
- 552 KB of data is recorded in one memory array layer.
- the X address is 0 to 511
- the Y address is 0 to 1103
- the Z address is 0 to 7.
- the main body data is 512 KB
- the additional data is 40 KB. It goes without saying that the data size of the memory array is different from the page size, the block size which is the unit of erasure, and the super block size which is the unit of defect management.
- interlayer insulating film is not shown.
- FIG. 3 shows eight Z selection lines Z for four layers.
- the memory cell CELL in the memory chain MC is selected using the Z selection line Z.
- the contact CONT connected to the Y selection line Y for specifying the Y address, the base contact wiring 201, and the L-shaped wiring L in parallel with the read bit line extended in the X direction. Are arranged in the X direction.
- the L-shaped wiring L is preferably L-shaped.
- the layout can be performed with standard process rules, the development period can be shortened.
- it is not necessarily L-shaped.
- wiring using an arc corresponding to 1 ⁇ 4 of a circle is possible.
- the bent portion does not exist, the reliability of the semiconductor memory device 1201 is improved.
- an arc corresponding to 1 ⁇ 4 of a circle satisfies the following equation (Equation 2) with respect to the radius r of the arc with the chord length g of the arc.
- double-gate NMOSFETs for the X selection element XMOS and the Y selection element YMOS.
- the gate width of the MOSFET can be increased compared to the case of using a planar MOSFET, so that it is easy to secure a current necessary for writing the phase change element PCM. Become. Therefore, there is an advantage that the yield of the semiconductor memory device 1201 can be improved. Further, since the driving power of the MOSFET is improved, the number of memory cells CELL included in the memory chain MC can be increased.
- the double gate NMOSFET has two gate electrodes, and when an on voltage is applied to both gate electrodes, the MOS is turned on (becomes a low resistance state). When an on voltage is applied only to one of the gate electrodes, or when an off voltage is applied to all the gate electrodes, the MOS is turned off (becomes a high resistance state).
- Ti, TiN, W, Al, Cu or the like can be used as a material for wiring and contacts. It goes without saying that a plurality of materials are formed into a laminated structure as necessary.
- the current at the time of writing can flow from the source electrode SL toward the write electrode WR.
- the current at the time of erasing can be flowed from the write electrode WR toward the source electrode SL.
- a Z selection line Z is used to select a Z address of a memory cell in the memory chain. A case where one memory chain includes eight memory cells will be described as an example.
- Fig. 9 shows a schematic plan view of the comparison method.
- a contact CONT connecting the Y selection line and the base contact wiring 201 is located at the same Y address as the Y selection line Y.
- the second layer contact CONT passes through the lower layer, in this case, the vicinity of the third layer read bit line.
- an electrical short circuit short circuit
- the contact CONT passes in the vicinity of the base wiring 101, there is a possibility that a short circuit occurs in the short circuit danger portion 602 with the lower layer wiring, resulting in defective products.
- the comparison method does not include the L-shaped wiring L that connects the sub-contact SCONT and the contact CONT, and the sub-contact SCONT that connects the Y selection line Y and the L-shaped wiring L.
- the contact CONT connects the Y selection line Y and the base contact wiring 201.
- FIG. 10 shows a schematic circuit diagram of a part of the memory array and the Y selection line drive circuit Local Y driver.
- a plurality of Y selection layers for example, the 0th layer Y selection line Y0-0 and the first layer Y selection line Y1-0 are connected to each other, and are connected to the Local Y driver.
- the Local Y driver is driven by an intermediate Y selection line signal Medium Y, a power supply voltage line (not shown), and a GND line.
- the circuit area of the Y selection line drive circuit Local Y driver it is possible to reduce the circuit area of the Y selection line drive circuit Local Y driver to be less than the circuit area of the memory array in which the corresponding Y selection line is used. It has become. If not driven at the same time, the area of the Y selection line drive circuit Local Y driver is larger than that of the memory array, and the ratio of the area occupied by the memory array to the chip area is reduced, resulting in an increase in manufacturing cost.
- FIG. 11 shows a schematic circuit diagram of the read bit line selector RBLS.
- the read bit line selector RBLS By using the read bit line selector RBLS, the number of read bit line contacts that connect the read bit line and the underlying wiring is reduced, and the degree of freedom of wiring due to the contact is prevented, and the semiconductor memory device 1201 having a high write data transfer rate is provided. Can be realized.
- a plurality of read bit lines RBL are connected to the global read bit line via a read bit line selection element RBLMOS.
- description will be made using an example in which the number of layers is four and four from each layer, a total of 16 read bit lines RBL are connected to one global read bit line GRBL.
- Each read bit line selection line RBLSEL is connected to a plurality of read bit line selection elements RBLMOS.
- one read bit line RBL can be connected to the global read bit line GRBL from the 16 read bit lines RBL.
- the read bit line selection line RBLSEL can be formed simultaneously with the Y selection element YMOS. By forming them simultaneously, it is possible to reduce the manufacturing cost, and a low-cost semiconductor memory device 1201 can be realized.
- FIG. 12 is a schematic circuit diagram showing the relationship between the read bit line selector RBLS and the sense amplifier SA.
- a plurality of read bit line selectors RBLS are connected to one global read bit line GRBL.
- a preamplifier for amplifying the signal of the read bit line RBL to the read bit line selection line RBLSEL. This has the effect of increasing the sensing speed and improving the read data transfer speed, but has the demerit of increasing the circuit area and the manufacturing cost.
- the amplifier circuit a method of amplifying a differential signal with a dummy bit line by a current mirror type circuit can be used.
- Fig. 13 shows a schematic circuit diagram of the sense amplifier.
- the precharge voltage VPRE is applied to the bit line. For example, a voltage of 0.5V is applied. Thereafter, the memory cell CELL to be read is selected. If the value of the memory cell CELL is “1”, the resistance of the phase change element PCM included in the memory cell CELL is low, the charge moves through the phase change element PCM, and the voltage of the bit line is, for example, The voltage drops to 0.1V. On the other hand, if the value of the memory cell CELL is “0”, the resistance of the phase change element PCM included in the memory cell CELL is high, the electric charge moving through the phase change element PCM is small, and the voltage of the bit line is almost equal. Maintained at 0.5V.
- a difference between the voltage of the bit line voltage and the reference voltage VREF is amplified using a differential amplifier circuit, and the result is output to the sense amplifier output SAO.
- the result of the sense amplifier output SAO is output to the outside of the semiconductor memory device 1201 via a data input / output pad (not shown).
- the discharge circuit operates by inputting a discharge signal DIS, and can set the read bit line RBL to 0V. By setting the voltage to 0 V after the end of reading, noise generation due to the read bit line can be reduced, and a highly reliable semiconductor memory device 1201 can be realized.
- SAN and SAP are sense amplifier operation signals.
- the power supply voltage VDD and the ground voltage GND are supplied to the sense amplifiers, respectively.
- the differential amplifier circuit enabler TG is a signal line that enables the input of the differential amplifier circuit.
- FIG. 1 A part of the memory array MA is shown in FIG.
- the memory chain MC is arranged at 2F intervals.
- the X selection destination is extended in the Y direction.
- FIG. 14 shows a schematic cross-sectional view of the cross section D-D ′ of FIG. A part of the memory chain MC is shown.
- the Z selection element ZMOS and the phase change element PCM include a silicon oxide film 1406, a gate oxide film 1403, a silicon channel 1404, a phase change material 1405, a Z selection transistor gate electrode 1401, and an interlayer insulating film 1402.
- a vertical GAA-NMOSFET Gate All Around n-channel MOSFET
- NMOSFET Gate All Around n-channel MOSFET
- the number of phase change elements PCM included in the memory chain MC can be increased, and a large-capacity semiconductor memory device 1201 can be realized.
- PMOS can be used. Since the size of the transistor can be reduced by using the vertical MOSFET as compared with the case of using 4F2 and a planar MOS, the capacity can be increased.
- the GAA structure By using the GAA structure, it becomes possible to widen the gate width as compared with the case of using a planar MOS, improving the driving power of the MOS, and increasing the number of memory cells CELL included in the phase change chain MC.
- the capacity can be increased.
- the voltage applied to the gate electrode of the non-selected Z selection transistor can be made lower than when the NMOS is used. Therefore, the gate breakdown voltage of the Z selection MOS can be reduced, and the reliability of the semiconductor memory device 1201 can be reduced. Has the effect of improving.
- a chalcogenide material particularly a GeSbTe alloy (germanium-antimony-tellurium alloy) can be used.
- the chalcogenide material can take two metastable states, an amorphous state (amorphous state) and a crystalline state, and the electric resistance value in each state is different. That is, the resistance is high in the case of amorphous and low resistance in the crystalline state.
- the values “0” and “1” can be stored.
- the amorphous case is ‘0’ and the crystalline state is ‘1’.
- Rewriting from '0' to '1' is erasing, and rewriting from '1' to '0' is writing.
- Rewriting is performed by causing a current to flow through the phase change element PCM and generating Joule heat.
- the phase change element is crystallized by holding at a temperature equal to or higher than the crystallization temperature for a certain time.
- it is made amorphous (vitrified) by heating above the melting point and rapidly cooling.
- the phase change element PCM can take a value of three or more.
- the phase change element is described by taking a crystal-amorphous phase change as an example.
- a crystal A-crystal B phase change can be used.
- the crystal A and the crystal B are crystals having different crystal structures.
- a case where a phase change element is used as a storage element will be described as an example.
- ReRAM Spin injection type MRAM
- a charge storage type memory for example, a floating gate type memory is used.
- a charge trap memory can be used.
- ReRAM ReRAM with a small rewrite current
- the number of memory elements included in one memory chain MU can be increased, and there is an effect that a large-capacity semiconductor memory device 1201 can be realized.
- the semiconductor memory device 1201 having a high write data rate can be realized by using the STT-MRAM having a high rewrite speed.
- the semiconductor memory device 1201 with low power consumption can be realized by using a charge storage type memory with a small write current.
- a phase change element is used as a memory element is described.
- Write and erase are performed by generating Joule heat by supplying a write current to the phase change element PCM.
- the write current is 40 ⁇ A, for example, and the erase current is 20 uA, for example. Note that it is logically possible to perform writing or erasing by generating Joule heat by passing a current through an adjacent Z selection MOS.
- a write current for example, 40 ⁇ A flows through the selected memory chain MC.
- almost no current flows through the non-selected memory chain MC.
- the bundle erase is to erase all bits included in the memory chain MC at the same time for a plurality of memory chains MC, and to cause a current to flow mainly through the Z selection MOS. This is because if an attempt is made to erase only a part of the memory chain, the memory cell adjacent to the erase region is likely to be mistakenly erased. Furthermore, when a plurality of memory chains are erased at once, it becomes possible to heat adjacent memory chains using heat generated from one memory chain or reduce heat escape, and the electrical energy required for erasure Thus, a semiconductor memory device 1201 that can be erased at high speed can be realized.
- the reason why the heat escape can be reduced is that the memory chain adjacent to a certain memory chain is heated so that the temperature difference between the memory chains is reduced and the heat flux density is proportional to the temperature difference. This is because the heat flux between the chains is reduced. Furthermore, by causing the current to flow mainly through the Z selection element ZMOS, even if the phase change element has a high resistance and a high voltage is required to cause the phase change element itself to generate heat, by causing the Z selection element ZMOS to generate heat, The voltage required for erasing can be reduced, and more stable heat generation during erasing can be realized.
- phase change element PCM In order to select the phase change element PCM, by turning off the Z selection element ZMOS of the same memory cell CELL, a current flows through the phase change element instead of the Z selection element.
- FIG. 16 is an example of a configuration diagram illustrating the semiconductor memory device 1201 according to the second embodiment.
- the present embodiment is characterized in that the length of the read bit line RBL is substantially equal to or shorter than the length of the Y selection line Y. Specifically, when the length of the Y selection line Y is LY and the length of the read bit line RBL is LRBL, the following equation (Equation 4) is established.
- Equation 4 LRBL ⁇ 1.5 ⁇ LY
- the length of the memory array in the X direction is shorter than the length of RBL and shorter than the length of the Y selection line Y. Therefore, when the length of the RBL is shorter than 0.75 ⁇ LY, the RBL is shortened, so the memory array is also shortened, the ratio of the memory array to the whole chip is reduced, and the memory capacity is reduced. Arise.
- the global read bit line shown in FIG. 11 is formed of a base wiring layer.
- the read bit line RBL is connected to the underlying wiring through the read bit line contact RBLCONT. Needless to say, it can be connected to the underlying wiring via the read bit line selector RBLS formed simultaneously with the Y selection line as in the first embodiment.
- the read bit line contact connects the read bit line RBL and the read bit line selection element RBLSEL.
- the read bit line selection element RBLSEL is connected to the global read bit line GRBL formed of the underlying wiring layer via the read bit line selector contact RBLSCONT shown in FIG.
- the L-shaped wiring layer L and the sub-contact SCONT are not necessary. Therefore, the process cost for forming them is unnecessary, and the semiconductor memory device 1201 can be manufactured at low cost.
- the number of read bit line contacts RBLCONT and in some cases the number of read bit line selectors RBLS in the chip increases, and there is a problem that the capacity of the semiconductor memory device 1201 decreases. It is desirable to use it for applications that require a low-cost and low-capacity semiconductor storage device 1201, such as a low-pixel toy camera storage device or a netbook that is a low-cost personal computer connected to the Internet.
- FIG. 17 is an example of a schematic circuit diagram showing a part of the semiconductor memory device 1201 in the third embodiment.
- This embodiment is characterized in that the contacts are not arranged in a straight line but are arranged in an uneven shape.
- every other contact CONT is arranged with a slightly shifted Y address.
- the case where the amount of deviation is 2F is illustrated.
- CONT2-552 and CONT2-550 have the same Y coordinate, but CONT2-551 has a Y coordinate offset of ⁇ 2F compared to the Y coordinate of CONT2-552.
- positioning can be used also about the subcontact SCONT.
- the contact deviation amount (offset amount) OF is 2F, which is appropriate in view of the current manufacturing technology, but the range of the following equation (Equation 5) can be used. (Equation 5) 0.5F ⁇ OF ⁇ 5F Although the contact CONT is shown as a square in FIG. 17, the effect of improving the reliability can be obtained even if the contact CONT is actually a shape close to a circle and the shift amount is 1F.
- the distance between the contacts is 1F when the deviation amount OF is 0F, but the deviation amount OF is
- the distance d between the contacts is d> 1F as shown in the following formula (Formula 6) from the three-square theorem. That is, the distance d between contacts can be made larger than F.
- both the contact formation region CONTAREA has the same X coordinate as the upper half of the memory array and the contact formation region CONTARE has the same X coordinate as the lower half of the memory array.
- the contact formation region CONTAREA2-0-0 and the contact formation region CONTAREA2-0-2 are formed at the same X coordinate as the upper half of the memory array MA
- the contact formation region CONTAREA2-0-1 is the contact formation region CONTAAREA2- It is formed at an X coordinate different from 0-0, and is formed at the same X coordinate as the lower half of the memory array MA. That is, the contact formation regions CONTAARE are arranged in a staggered manner.
- the wiring shape of the L-shaped wiring L also changes as the coordinates of the contact CONT are changed with respect to the first embodiment.
- the wiring shape of the L-shaped wiring L is different depending on the memory array.
- the shape of the L-shaped wiring of the memory array MA2-0-1 and the shape of the memory array MA-2-0-2 are different.
- every other memory array has L-shaped wiring in the same shape.
- the shape of the L-shaped wiring of the memory array MA2-0-1 and the shape of the memory array MA-2-0-3 are the same.
- the number of sub-contacts SCONT corresponding to the memory array MA is illustrated as eight. Needless to say, the number of sub-contacts SCONT and contacts CONT is actually more than eight.
- a plurality of layers of Y selection lines Y are electrically connected, and the contact CONT connecting the memory chain 0th layer and the first layer and the contact CONT connecting the memory chain first layer and the second layer are It is characterized by having the same X coordinate.
- the area consumed by the contact CONT can be reduced, and the manufacturing cost of the semiconductor memory device 1201 can be reduced.
- the layer selection at the time of writing and erasing is performed using the write electrode WR. Selection of a layer at the time of reading is performed using the read bit line RBL.
- the contact CONT connecting the memory chain 0th layer and the first layer and the contact CONT connecting the memory chain first layer and the second layer can have the same Y coordinate. By doing so, the area consumed by the contact CONT can be further reduced. However, there is a problem that the unevenness in the Z direction at the place where the contacts overlap increases, making lithography (exposure process) in the manufacturing process difficult.
- the Y selection line Y is preferably connected to the L-shaped wiring L via the contact CONT.
- the contact CONT for each layer instead of forming the contact CONT for each layer, after forming the L-shaped wiring L for three layers, after forming the contact CONT in four layers at a time, the L-shaped wiring L of the 0th layer is formed. be able to. In this case, the manufacturing cost can be reduced. However, there is a problem that the difficulty of the manufacturing process increases.
- drilling for connecting four layers can be performed by one dry etching using the L-shaped wiring L as a stopper. This is because the X coordinate of the L-shaped wiring is made the same, the Y coordinate is shifted by, for example, 1F, and the lower-layer L-shaped wiring L slightly protrudes, for example, 1F2 (F2) from the upper-layer L-shaped wiring L. An L-shaped wiring is formed on. Thereafter, dry etching is performed so that a part of each of the four layers is exposed. In this way, all four layers of the L-shaped wiring L can be connected to the base contact wiring 201 in a single drilling process and contact forming process.
- SYMBOLS 101 Base wiring, 102 ... Base MOS, 103 ... Silicon substrate, 201 ... Base contact wiring, 601 ... Short-circuit danger part with lower layer read bit line, 602 ... Short-circuit danger part with lower layer wiring, 1401 ... Z selection transistor gate electrode , 1402 ... interlayer insulating film, 1403 ... gate oxide film, 1404 ... silicon channel, 1405 ... phase change material, 1406 ... silicon oxide film, 1901 ... Y-direction signal wiring possible area, CELL ... memory cell, CONTAAREA ... contact formation area, DIS: Discharge signal, F: Minimum processing dimension, GND: Ground voltage, GRBL: Global read bit line, L ...
Abstract
Description
もう一つは、前記コンタクトが下地配線の近傍を通過するため、そこにおいて電気的に短絡(ショート)する可能性がある課題である。下地配線のY選択線と同一方向に延伸される下地配線の本数が多いため、下地配線を避けてコンタクト電極を通過させることは困難である。
前記半導体基板と平行な第1の方向に複数の第1記憶部からなる第2記憶部を備え、
第1の方向と直交し、かつ、半導体基板と平行な第2の方向に複数の前記第2記憶部からなる第3記憶部を備え、
半導体基板と直交する第3の方向に複数の前記第3記憶部からなる第4記憶部を備える半導体記憶装置において、
前記第2の方向のアドレスを選択する信号線と半導体基板を接続する複数のコンタクトを前記第1の方向に延伸されたビット線に干渉しない領域に配置すること」を特徴とする。
下地配線に関して、X方向に延伸される配線がY方向に延伸される配線よりも多くなる理由を説明する。1ページをライトするときの選択動作の回数は、下記の数式(数1)で表される。
選択動作の回数=ページサイズ/同時ライトビット数
相変化メモリはライト電流が例えば40μAと比較的大きいために、同時ライトビット数は例えば32bitと少なく、選択動作の回数が多くなる。例えばページサイズが8KB+spare領域640Bの8832Bの場合、選択動作の回数は2208回となる。
もちろん、円弧は厳密に円の1/4である必要がないのは言うまでもない。円弧の弦長gが下記の数式(数3)式を満たす範囲であれば、追加で要求されるチップ面積は少なく、安価な半導体記憶装置1201を製造することができる。
また、Y方向に対して斜め45度の配線が可能であることは言うまでもない。この場合、L字配線Lの長さが短くなるために、高速なY選択線の駆動が可能であり、ライト動作速度が向上する効果がある。
LRBL < 1.5×LY
メモリアレイのX方向の長さはRBLの長さより短く、Y選択線Yの長さより短い。そのため、RBLの長さが0.75×LYよりも短い場合には、RBLが短くなるため、メモリアレイも短くなり、メモリアレイがチップ全体に占める割合が低下し、メモリ容量が低下する課題が生じる。
(数5)
0.5F ≦ OF ≦ 5F
コンタクトCONTを図17に正方形で示したが、実際には円形に近い形状であり、ずれ量が1Fであっても、信頼性向上の効果は得られる。例えば、コンタクト形状が真円であると仮定した場合、X方向に2F間隔で直径1Fのコンタクトを配置すると、ずれ量OFが0Fの場合、コンタクト間の距離は1Fになるが、ずれ量OFが例えば,0.5Fの場合、コンタクト間の距離dは三平方の定理から下記の数式(数6)式に示される通り、d>1Fとなる。すなわち、コントタクト間の距離dをFよりも大きくすることができる。
一方、ずれ量OFを5Fよりも大きくすると、コンタクト面積の増大がチップ面積の増加に与える影響が大きくなり、チップ製造コストが上昇する。
Claims (15)
- 半導体基板と、
第1記憶部と、
前記半導体基板と平行な第1の方向に形成された複数の前記第1記憶部からなる第2記憶部と、
前記第1の方向と直交し、かつ、前記半導体基板と平行な第2の方向に形成された複数の前記第2記憶部からなる第3記憶部と、
前記半導体基板と直交する第3の方向に複数の前記第3記憶部からなる第4記憶部とを備え、
前記第2の方向のアドレスを選択する信号線と前記半導体基板を接続する複数のコンタクトを前記第1の方向に延伸されたビット線に干渉しない領域に配置することを特徴とする半導体記憶装置。 - 前記ビット線に干渉しない方向が前記第1の方向であることを特徴とする請求項1に記載の半導体記憶装置。
- 前記ビット線がリードビット線であることを特徴とする請求項1に記載の半導体記憶装置。
- 前記第1記憶部が相変化メモリであることを特徴とする請求項1に記載の半導体記憶装置。
- 前記コンタクトと前記第2の方向のアドレスを選択する信号線が配線により接続されていることを特徴とする請求項1に記載の半導体記憶装置。
- 前記配線が角度90度の折り返しを行うことを特徴とする請求項5に記載の半導体記憶装置。
- 前記配線がL字型であることを特徴とする請求項5に記載の半導体記憶装置。
- 前記配線が前記第1の方向と45度の角をなし、半導体基板と平行であることを特徴とする請求項5に記載の半導体記憶装置。
- 前記複数のビット線の1つをセンスアンプに接続する選択回路を特徴とする請求項1に記載の半導体記憶装置。
- 半導体基板と、
第1記憶部と、
前記半導体基板と平行な第1の方向に形成された複数の前記第1記憶部からなる第2記憶部と、
前記第1の方向と直交し、かつ、前記半導体基板と平行な第2の方向に形成された複数の前記第2記憶部からなる第3記憶部と、
前記半導体基板と直交する第3の方向に形成された複数の前記第3記憶部からなる第4記憶部とを備え、
前記第2の方向のアドレスを選択する信号線を前記第3の方向の複数の記憶部を制御するアレイ回路で共有し同時に駆動することを特徴とする半導体記憶装置。 - 前記第3の方向のアドレスの選択をライトプレート電極で行うことを特徴とする請求項11に記載の半導体記憶装置。
- 前記第2の方向のアドレスを選択する信号線と半導体基板を接続する複数のコンタクトを備え、
前記第1の方向と前記第2の方向に関して同一の座標に複数のコンタクトが配線を介して積層されていることを特徴とする請求項11に記載の半導体記憶装置。 - 半導体基板と、
第1記憶部と、
前記半導体基板と平行な第1の方向に形成された複数の前記第1記憶部からなる第2記憶部と、
第1の方向と直交し、かつ、前記半導体基板と平行な第2の方向に形成された複数の前記第2記憶部からなる第3記憶部と、
前記半導体基板と直交する第3の方向に形成された複数の前記第3記憶部からなる第4記憶部とを備え、
前記第2の方向のアドレスを選択する信号線と前記半導体基板を接続する複数のコンタクトが列を形成し、
前記列が一直線に並んでおらず、ずれOFが形成されており、前記ずれOFの量が0.5F≦OF≦5F(ここで、Fは最小加工寸法である。)であることを特徴とする半導体記憶装置。 - 半導体基板と、
第1記憶部と、
前記半導体基板と平行な第1の方向に形成された複数の前記第1記憶部からなる第2記憶部と、
第1の方向と直交し、かつ、前記半導体基板と平行な第2の方向に形成された複数の前記第2記憶部からなる第3記憶部と、
半導体基板と直交する第3の方向に形成された複数の前記第3記憶部からなる第4記憶部とを備え、
前記第2の方向のアドレスを選択する信号線と前記半導体基板を接続する複数のコンタクトが密集したコンタクト形成領域を備え、
前記コンタクト形成領域が第2の方向に対して、千鳥状に配置されていることを特徴とする半導体記憶装置。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP2012238348A (ja) * | 2011-05-10 | 2012-12-06 | Hitachi Ltd | 半導体記憶装置 |
JP2013065707A (ja) * | 2011-09-16 | 2013-04-11 | Toshiba Corp | 不揮発性記憶装置およびその製造方法 |
JP5283805B1 (ja) * | 2011-11-22 | 2013-09-04 | パナソニック株式会社 | 抵抗変化型不揮発性記憶装置、および抵抗変化型不揮発性記憶装置のアクセス方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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JP5283805B1 (ja) * | 2011-11-22 | 2013-09-04 | パナソニック株式会社 | 抵抗変化型不揮発性記憶装置、および抵抗変化型不揮発性記憶装置のアクセス方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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