WO2013179638A1 - 半導体モジュール及びその製造方法 - Google Patents

半導体モジュール及びその製造方法 Download PDF

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Publication number
WO2013179638A1
WO2013179638A1 PCT/JP2013/003332 JP2013003332W WO2013179638A1 WO 2013179638 A1 WO2013179638 A1 WO 2013179638A1 JP 2013003332 W JP2013003332 W JP 2013003332W WO 2013179638 A1 WO2013179638 A1 WO 2013179638A1
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Prior art keywords
source electrode
bare chip
copper connector
copper
semiconductor module
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PCT/JP2013/003332
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English (en)
French (fr)
Inventor
崇 須永
昇 金子
修 三好
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日本精工株式会社
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Publication date
Application filed by 日本精工株式会社 filed Critical 日本精工株式会社
Priority to JP2014518275A priority Critical patent/JP5871064B2/ja
Priority to CN201380003744.2A priority patent/CN103918067B/zh
Priority to EP13797985.2A priority patent/EP2858100B1/en
Priority to US14/127,187 priority patent/US9312234B2/en
Publication of WO2013179638A1 publication Critical patent/WO2013179638A1/ja

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Definitions

  • the present invention relates to a semiconductor module such as a power module to be incorporated into an automotive electrical device and a method of manufacturing the same.
  • a motor drive unit is provided in a housing in which an electric motor involved in steering of a vehicle is accommodated, and the electronic apparatus is mounted on the motor drive unit.
  • the electronic device is incorporated into a motor drive as a power module.
  • the power module is equipped with power elements such as FET (Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), etc. that are suitable for controlling electric devices driven by relatively large currents such as electric power steering devices. It is configured as a so-called semiconductor module. Since this type of power module is mounted in a vehicle, it is also called an in-vehicle module.
  • FET Field Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • FIG. 14 is a schematic cross-sectional view of an example of a conventional semiconductor module.
  • the semiconductor module 100 shown in FIG. 14 includes a metal substrate 101, a resin 102 provided on a flat surface of the bottom of a recess of the substrate 101, and a plurality of copper foils (wiring patterns) 103a formed on the resin 102, And 103b, 103c, and 103d.
  • a groove 109 is formed between the copper foil 103a and the copper foil 103c and the copper foil 103d.
  • the heat buffer plates 104a and 104b are respectively formed on the copper foils 103a and 103b among the plurality of copper foils 103a, 103b, 103c and 103d, and the IGBTs 105a and 105b are formed on the heat buffer plates 104a and 104b. Each is formed.
  • Each IGBT 105a, 105b is a bare chip IGBT (bare chip transistor).
  • the emitter of the IGBT 105a and the copper foil 103b are connected by a wire 106a constituted by a wire, and the emitter of the IGBT 105b and the copper foil 103c are connected by a wire 106b similarly constituted by a wire.
  • the resin 102, the copper foils 103a, 103b and 103c, the thermal buffer plates 104a and 104b, the IGBTs 105a and 105b, and the wirings 106a and 106b are sealed by a gel 107. Further, a lid 108 covering the concave portion of the substrate 101 is fixed to the upper portion of the substrate 101.
  • FIG. 15 is a schematic plan view showing another example of the conventional semiconductor module.
  • a plurality of conductive pads 201 and 202 are formed on a substrate (not shown).
  • the MOS chip 203 is soldered on one of the plurality of conductive pads 201 and 202.
  • a plurality of source electrodes 205 and a single gate electrode 204 are formed on the top surface of the MOS chip 203, and a drain electrode (not shown) is formed on the bottom surface of the MOS chip 203.
  • the source electrode 205 of the MOS chip 203 and the other conductive pad 202 of the plurality of conductive pads 201 and 202 formed on the substrate are interconnected by the lead 210.
  • the lead 210 is formed by punching and bending a metal plate, and extends in the X direction and the Y direction with a rectangular flat source electrode connection portion 211 extending in the X direction and the Y direction (horizontal direction) shown in FIG.
  • a flat electrode connection portion 212 and a connection portion 213 which is inclined in the Z direction (vertical direction) and connects the source electrode connection portion 211 and the electrode connection portion 212 are provided.
  • the source electrode connection portion 211 is soldered to the source electrode 205 of the MOS chip 203, and the electrode connection portion 212 is soldered to the other conductive pad 202 of the plurality of conductive pads 201 and 202 on the substrate. It is supposed to be connected.
  • the width a of the source electrode connection portion 211 in the X direction is equal to or greater than the width b of the plurality of source electrodes 205 in the X direction.
  • the conventional semiconductor module 100 shown in FIG. 14 and the semiconductor module 200 shown in FIG. 15 have the following problems. That is, in the case of the semiconductor module 100 shown in FIG. 14, the connection between the emitter of the IGBT 105a and the copper foil 103b and the connection of the emitter of the IGBT 105b and the copper foil 103c are connected using the wires 106a and 106b formed of wires. ing. Since connection using this wire is performed using a wire bonding apparatus (not shown), the work of mounting the wires 106a and 106b is performed on the wiring pattern on the substrate with the IGBTs 105a and 105b and other surface mounted components.
  • the lead-out direction of the lead 210 connected to the source electrode 205 is only the Y direction shown in FIG. Not listed.
  • the lead-out direction of the lead 210 connected to the source electrode 205 is only one direction, there is no freedom in the arrangement of the MOS chip 203 mounted on the substrate, and no freedom in the design of the wiring on the substrate. .
  • the layout of the semiconductor module on the substrate can not be made compact because there is no design freedom of the wiring on the substrate.
  • the present invention has been made to solve the above-mentioned problems, and its object is to make the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate by the solder mounting operation. It is an object of the present invention to provide a semiconductor module that can be performed in the same process as a solder mounting operation performed when mounting other surface mounting components on a wiring pattern on a substrate, and a method of manufacturing the same.
  • Another object of the present invention is to provide flexibility in the arrangement of bare chip transistors mounted on a substrate and the design of wiring on the substrate, and to make the layout of the semiconductor module on the substrate compact. It is an object of the present invention to provide a semiconductor module and a method of manufacturing the same that can easily make the lengths of the paths of the three-phase motor on the substrate the same.
  • a semiconductor module comprises a metal substrate, an insulating layer formed on the substrate, and a plurality of wiring patterns formed on the insulating layer.
  • a bare chip transistor mounted via solder on one of the plurality of wiring patterns, an electrode formed on the upper surface of the bare chip transistor, and the other wiring pattern of the plurality of wiring patterns are soldered.
  • a copper connector composed of a copper plate for connection.
  • the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed by a solder mounting operation. Therefore, the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed in the same process as the solder mounting operation performed when mounting the bare chip transistor or other surface mounting components on the wiring pattern on the substrate. it can.
  • the manufacturing tact of the semiconductor module can be shortened, and no dedicated equipment for wire bonding becomes necessary, and the manufacturing cost of the semiconductor module can be reduced. That is, since the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can also be performed by the facility for the solder mounting operation, the equipment investment can be suppressed. Furthermore, it is possible to simultaneously carry out the process of mounting bare chip transistors and other surface mounted components on the wiring patterns on the substrate and the process of connecting the electrodes of the bare chip transistors and the wiring patterns on the substrate.
  • the copper plate and the copper connector may be a plate-like member made of a material having the same electrical and mechanical properties as copper, or a connector having a material having the same electrical and mechanical properties as copper. It is preferable to use a copper plate or a copper connector since it is easy to obtain industrially stable quality at a relatively low cost.
  • the bare chip transistor is a bare chip FET having a source electrode and a gate electrode formed on the upper surface
  • the copper connector includes a copper connector for a source electrode and a copper connector for a gate electrode.
  • the source electrode on the FET and the other wiring pattern of the plurality of wiring patterns are connected via the solder with the copper connector for the source electrode, and the gate electrode on the bare chip FET and the plurality of wiring patterns are further connected. It is preferable to connect with the other wiring pattern top with the said copper connector for gate electrodes via solder.
  • the connection between the source electrode of the bare chip FET and the wiring pattern on the substrate is made using a copper connector for the source electrode, and the connection between the gate electrode of the bare chip FET and another wiring pattern on the substrate is made for the gate electrode
  • solder mounting can be performed. Therefore, the connection between the source electrode of the bare chip FET and the wiring pattern on the substrate and the connection between the gate electrode of the bare chip FET and another wiring pattern on the substrate are bare chip FET and others Can be performed in the same process as the solder mounting operation performed when mounting the surface mounting component on the wiring pattern on the substrate.
  • the copper connector for the gate electrode is of one type
  • the copper connector for the source electrode is a first copper connector for the source electrode in which the copper connector for the gate electrode is disposed 180 ° straight.
  • Two types of copper connectors for the second source electrode which are disposed 90 ° at right angles to the copper connector for the gate electrode, and in one bare chip FET, the copper connector for the one type of gate electrode and the two types It is good to use combining with the copper connector for any one of source electrodes selected from the copper connector for a 1st source electrode, and the copper connector for a 2nd source electrode.
  • this semiconductor module a degree of freedom is created in the arrangement of bare chip transistors mounted on the substrate, the degree of freedom in the design of the wiring on the substrate is increased, and the layout of the semiconductor module on the substrate can be made compact.
  • the gate electrode and the source electrode formed on the upper surface of the bare chip FET may be arranged in series in a straight manner, and the source electrode may be formed in a rectangular shape. Furthermore, in this semiconductor module, the copper connector for the first source electrode is drawn out along the direction in which the short side of the rectangular-shaped source electrode extends, and along the short side and the long side of the source electrode. It is preferable to provide a connection portion having a short side and a long side and having an area of a connection surface connected to the source electrode that is substantially the same as that of the source electrode.
  • the copper connector for the second source electrode is drawn out along the direction in which the long side of the rectangular shaped source electrode extends, and is along the long side and the short side of the source electrode. It is preferable to provide a connection portion having a long side and a short side and having an area of a connection surface connected to the source electrode that is substantially the same area as the source electrode. According to this semiconductor module, it is possible to ensure the connection reliability between the second source electrode copper connector disposed at 90 ° right angle to the gate electrode copper connector and the source electrode formed on the upper surface of the bare chip FET.
  • a step of forming an insulating layer on a metal substrate, a step of forming a plurality of wiring patterns on the insulating layer, and a plurality of wiring patterns A step of applying a solder paste thereon; a step of mounting a bare chip transistor on the solder paste applied on one of the plurality of wiring patterns; and an electrode formed on the upper surface of the bare chip transistor
  • a copper connector comprising a copper plate on the step of applying a solder paste, on the solder paste applied on the electrode of the bare chip transistor and on the other paste of the plurality of wiring patterns.
  • the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed by a solder mounting operation by using a copper connector composed of a copper plate. Therefore, the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed in the same process as the solder mounting operation performed when mounting the bare chip transistor or other surface mounted components on the wiring pattern on the substrate. . For this reason, while being able to shorten the manufacture tact of a semiconductor module, a dedicated facility for wire bonding becomes unnecessary, and the manufacturing cost of the semiconductor module can be reduced.
  • the bare chip transistor is a bare chip FET having a source electrode and a gate electrode formed on the upper surface
  • the copper connector includes a copper connector for source electrode and a copper connector for gate electrode.
  • connection between the source electrode of the bare chip FET and the wiring pattern on the substrate is performed using the copper connector for the source electrode, and the gate electrode of the bare chip FET and the substrate Since connection with another wiring pattern can be performed by a solder mounting operation by using a copper connector for gate electrode, the connection between the source electrode of the bare chip FET and the wiring pattern on the substrate and the gate electrode of the bare chip FET and another on the substrate.
  • the connection with the wiring pattern can be performed in the same process as the solder mounting operation performed when mounting a bare chip FET or other surface mounted components on the wiring pattern on the substrate.
  • the copper electrode connector for gate electrode is one type, and the copper connector for source electrode is disposed at a 180 ° straight arrangement with respect to the copper connector for gate electrode.
  • the copper connector for source electrode is disposed at a 180 ° straight arrangement with respect to the copper connector for gate electrode.
  • a semiconductor module like the above-described semiconductor module, freedom in the arrangement of bare chip transistors mounted on the substrate is created, and the freedom of wiring on the substrate is increased, and thus, on the substrate
  • the layout of the semiconductor module can be made compact, and the lengths of the paths of the respective phases of the three-phase motor on the substrate can be easily made the same. This makes it possible to easily match the phase characteristics of the three-phase motor, in particular the impedance characteristics of the respective phases, and to improve the ripple accuracy such as torque and speed.
  • the semiconductor module according to another aspect of the present invention is characterized in that the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate is performed in a solder mounting operation by using a copper connector formed of a copper plate. Do. In the semiconductor module according to still another aspect of the present invention, freedom in the arrangement of bare chip transistors mounted on the substrate is created, and the freedom of design of the wiring on the substrate is increased.
  • a copper connector for one type of gate electrode and a copper connector for first source electrode arranged in a 180 ° straight arrangement with respect to the copper connector for gate electrode; Any one selected from two types of copper connectors for the first source electrode and copper connectors for the second source electrode with the copper connector for the second source electrode arranged at 90 ° right angle to the copper connector for the gate electrode It is characterized in that it is used in combination with one of the copper connectors for source electrodes.
  • the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed by the solder mounting operation by using the copper connector made of copper plate.
  • the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed in the same process as the solder mounting operation performed when mounting the bare chip transistor and other surface mounted components on the wiring pattern on the substrate. For this reason, while being able to shorten the manufacture tact of a semiconductor module, a dedicated facility for wire bonding becomes unnecessary, and the manufacturing cost of the semiconductor module can be reduced.
  • one of a copper connector for a gate electrode, a copper connector for a first source electrode, and a copper connector for a second source electrode is selected.
  • the degree of freedom in the arrangement of bare chip transistors mounted on the substrate there is a degree of freedom in the arrangement of bare chip transistors mounted on the substrate, and the degree of freedom in the design of the wiring on the substrate is increased.
  • the layout of the semiconductor module on the substrate can be made compact, and the length of the path of each phase of the three-phase motor on the substrate can be easily made the same. This makes it possible to easily match the phase characteristics of the three-phase motor, in particular the impedance characteristics of the respective phases, and to improve the ripple accuracy such as torque and speed.
  • FIG. 6 is a schematic diagram for explaining a connection state of an electrode of a bare chip FET constituting a bare chip transistor and a wiring pattern on a substrate in the semiconductor module shown in FIGS.
  • the copper connector for gate electrodes is shown, (A) is a perspective view of the state which looked at the copper connector for gate electrodes from diagonally upward left side, (B) is the perspective view of the copper connector for gate electrodes seen from diagonally upper right side.
  • FIG. The copper connector for gate electrodes is shown, (A) is a top view, (B) is a front view, (C) is a right side view, (D) is a left side view. It is the perspective view of the state which looked at the copper connector for 1st source electrodes from diagonally upward left side.
  • the copper connector for 1st source electrodes is shown, (A) is a top view, (B) is a front view, (C) is a right side view, (D) is a left side view.
  • FIG. 1 It is the perspective view of the state which looked at the copper connector for 2nd source electrodes from diagonally upward left side.
  • the copper connector for 2nd source electrodes is shown, (A) is a top view, (B) is a front view, (C) is a right side view, (D) is a left side view.
  • FIG. 1 is a view showing the basic structure of an electric power steering apparatus in which a semiconductor module according to the present invention is used.
  • FIG. 2 is a block diagram showing a control system of a controller of the electric power steering apparatus shown in FIG.
  • FIG. 3 is an exploded perspective view of a controller including the semiconductor module of the electric power steering apparatus shown in FIG.
  • FIG. 4 is a plan view of the semiconductor module shown in FIG.
  • FIG. 5 is a schematic diagram for explaining the connection between the electrodes of the bare chip FET constituting the bare chip transistor and the wiring pattern on the substrate in the semiconductor module shown in FIGS. 3 and 4.
  • FIG. 1 is a view showing the basic structure of an electric power steering apparatus in which a semiconductor module according to the present invention is used.
  • FIG. 2 is a block diagram showing a control system of a controller of the electric power steering apparatus shown in FIG.
  • FIG. 3 is an exploded perspective view of a controller including the semiconductor module of the electric power steering apparatus shown in FIG.
  • FIG. 4
  • FIG. 6 is a plan view for explaining the connection state between the electrode of the bare chip FET and the copper connector.
  • FIG. 6 (A) shows that the gate electrode copper connector is connected to the gate electrode of the bare chip FET and (1) A plan view for explaining a state in which a copper connector for source electrode is connected, (B) is connected to a copper connector for gate electrode to the gate electrode of bare chip FET, and a copper connector for second source electrode to the source electrode. It is a top view for demonstrating the connected state.
  • FIG. 7 is a schematic plan view of the bare chip FET.
  • FIG. 1 shows the basic structure of an electric power steering apparatus in which the semiconductor module according to the present invention is used.
  • the column shaft 2 of the steering handle 1 is a reduction gear 3 and a universal joint 4A. And 4B, through the pinion rack mechanism 5, it is connected to the tight rod 6 of the steering wheel.
  • a torque sensor 7 for detecting the steering torque of the steering wheel 1 is provided on the column shaft 2, and an electric motor 8 assisting the steering force of the steering wheel 1 is connected to the column shaft 2 via the reduction gear 3. It is done.
  • Electric power is supplied from a battery (not shown) to the controller 10 for controlling the electric power steering apparatus, and an ignition key signal IGN (see FIG. 2) is input through an ignition key (not shown).
  • the controller 10 calculates a steering assist command value to be an assist (steering assist) command based on the steering torque Ts detected by the torque sensor 7 and the vehicle speed V detected by the vehicle speed sensor 9, and the calculated steering
  • the current supplied to the electric motor 8 is controlled based on the auxiliary command value.
  • the controller 10 is mainly composed of a microcomputer, and the mechanism and configuration of its control device are as shown in FIG.
  • the steering torque Ts detected by the torque sensor 7 and the vehicle speed V detected by the vehicle speed sensor 9 are input to the control arithmetic unit 11 as a control arithmetic unit, and the current command value calculated by the control arithmetic unit 11 is gate drive circuit 12 Enter in
  • the gate drive signal formed based on the current command value or the like in the gate drive circuit 12 is input to the motor drive unit 13 having a bridge configuration of FET, and the motor drive unit 13 passes through the interruption device 14 for emergency stop and three phases
  • An electric motor 8 configured of a brushless motor is driven.
  • the respective phase currents of the three-phase brushless motor are detected by the current detection circuit 15, and the detected three-phase motor currents ia to ic are inputted to the control arithmetic unit 11 as feedback currents.
  • a rotation sensor 16 such as a Hall sensor is attached to the three-phase brushless motor, the rotation signal RT from the rotation sensor 16 is input to the rotor position detection circuit 17, and the detected rotation position ⁇ is a control arithmetic device It is input to 11.
  • the ignition signal IGN from the ignition key is input to the ignition voltage monitor unit 18 and the power supply circuit unit 19, and the power supply voltage Vdd from the power supply circuit unit 19 is input to the control arithmetic device 11, and a reset signal for stopping the device. Rs is input to the control arithmetic device 11.
  • blocking apparatus 14 is comprised by the relay contacts 141 and 142 which interrupt
  • FET Tr1 and Tr2, FET Tr3 and Tr4, and FET Tr5 and Tr6 connected in series are connected in parallel to the power supply line 81.
  • the FET Tr1 and Tr2, FET Tr3 and Tr4, and FET Tr5 and Tr6 connected in parallel to the power supply line 81 are connected to the ground line 82.
  • the source electrode S of the FETTr1 and the drain electrode D of the FETTr2 are connected in series to form a c-phase arm of a three-phase motor, and a current is output through a c-phase output line 91c.
  • the source electrode S of the FETTr3 and the drain electrode D of the FETTr4 are connected in series to form an a-phase arm of a three-phase motor, and a current is output through an a-phase output line 91a.
  • the source electrode S of the FETTr5 and the drain electrode D of the FETTr6 are connected in series to form a b-phase arm of a three-phase motor, and a current is output through the b-phase output line 91b.
  • FIG. 3 is an exploded perspective view of the controller 10 including the semiconductor module of the electric power steering apparatus shown in FIG. 1.
  • the controller 10 is a semiconductor module 30 as a power module including the case 20 and the motor drive unit 13. And a control circuit board 40 including the heat dissipation sheet 39, the control arithmetic device 11 and the gate drive circuit 12, a power and signal connector 50, a three-phase output connector 60, and a cover 70.
  • the case 20 is formed in a substantially rectangular shape, and provided at the longitudinal direction end of the semiconductor module placement portion 21 for placing the semiconductor module 30 and the semiconductor module placement portion 21.
  • a plurality of screw holes 21 a into which mounting screws 38 for mounting the semiconductor module 30 are screwed are formed in the semiconductor module mounting portion 21. Further, a plurality of mounting posts 24 for mounting the control circuit board 40 are erected on the semiconductor module mounting portion 21 and the power and signal connector mounting portion 22, and the control circuit board 40 is mounted on each mounting post 24. A screw hole 24a into which a mounting screw 41 for mounting is screwed is formed. Furthermore, in the three-phase output connector mounting portion 23, a plurality of screw holes 23a into which mounting screws 61 for mounting the three-phase output connector 60 are screwed are formed.
  • the semiconductor module 30 has the circuit configuration of the motor drive unit 13 described above, and as shown in FIG. 4, six FETs Tr1 to Tr6 and a positive electrode terminal 81a connected to the power supply line 81 on the substrate 31; A negative terminal 82a connected to the ground line 82 is mounted.
  • the substrate 31 also includes an a-phase output terminal 92a connected to the a-phase output line 91a, a b-phase output terminal 92b connected to the b-phase output line 91b, and a c-phase output connected to the c phase output line 91c.
  • a three-phase output unit 90 including a terminal 92c is mounted.
  • other surface mounting components 37 including a capacitor are mounted on the substrate 31.
  • the substrate 31 of the semiconductor module 30 is provided with a plurality of through holes 31 a through which mounting screws 38 for mounting the semiconductor module 30 are inserted.
  • Each of the FETs Tr1 to Tr6 is configured by a bare chip FET (bare chip transistor) 35, and as shown in FIG. 7, a source electrode S and a gate electrode G are provided on the bare chip FET 35. It has an electrode.
  • the gate electrode G and the source electrode S formed on the upper surface of the bare chip FET 35 are arranged in series in the vertical direction in FIG. 7 as shown in FIG.
  • the gate electrode G is formed in a rectangular shape having a short side extending in the vertical direction in FIG. 7 and a long side orthogonal to the short side.
  • the source electrode S is formed in a rectangular shape having a short side extending in the vertical direction in FIG. 7 and a long side orthogonal to the short side.
  • the short side and the long side of the source electrode S are larger than the short side and the long side of the gate electrode G, and the area of the source electrode S is larger than the area of the gate electrode G.
  • the semiconductor module 30 includes a substrate 31 made of metal, and an insulating layer 32 is formed on the substrate 31.
  • the substrate 31 is made of metal such as aluminum.
  • a plurality of wiring patterns 33a to 33d are formed on the insulating layer 32.
  • Each of the wiring patterns 33a to 33d is made of a metal such as copper or aluminum or an alloy containing the metal.
  • a bare chip FET 35 constituting each of the FETs Tr1 to Tr6 is mounted on the wiring pattern 33a among the plurality of wiring patterns 33a to 33d via the solder 34a.
  • the drain electrode formed on the lower surface of the bare chip FET 35 is connected to the wiring pattern 33a via the solder 34a.
  • the source electrode S of the bare chip FET 35 and the other wiring pattern 33b among the plurality of wiring patterns 33a to 33d are connected to each other via the solder 34e and 34b by the copper connector 36a for the source electrode.
  • the gate electrode G of the bare chip FET 35 and the other wiring pattern 33c among the plurality of wiring patterns 33a to 33d are connected by the gate electrode copper connector 36b through the solder 34f and 34c, respectively.
  • the gate electrode copper connector 36b is of one type, and all the FETs Tr1 to Tr6 in FIG. 4 are drawn out and connected in the arrow A direction shown in FIG. This situation is shown in FIGS. 6 (A) and 6 (B).
  • the copper connector 36a for the source electrode is a first copper connector 36a1 for the source electrode, which is disposed 180 ° straight with respect to the copper connector 36b for the gate electrode, and FIG.
  • the first source electrode copper connector 36a1 is drawn out and connected in the direction of the arrow A ′ shown in FIG.
  • the second source electrode copper connector 36a2 is drawn out and connected in the direction of arrow B shown in FIG. 7 in the FETTr1 in FIG. 4, and drawn out in the direction of arrow B 'shown in FIG. 7 in the FETTr3 and Tr5 in FIG. Connected
  • the degree of freedom in the arrangement of the bare chip FET 35 mounted on the substrate 31 is created, the degree of freedom in the design of the wiring on the substrate 31 is increased, and the layout of the semiconductor module 30 on the substrate 31 can be made compact.
  • the lengths of the paths of the three-phase motor on the substrate 31 are made the same. You can do it easily. This makes it possible to easily match the phase characteristics of the three-phase motor, in particular, the impedance characteristics, and to improve the ripple accuracy such as torque and speed.
  • the gate electrode copper connector 36b is formed by punching and bending a copper plate, extends from the flat plate portion 36ba and one end of the flat plate portion 36ba, and is connected to the gate electrode G of the bare chip FET 35 through the solder 34f. And a connection portion 36bc extending from the other end of the flat portion 36ba and connected to the wiring pattern 33c via the solder 34c.
  • the flat plate portion ba of the copper connector 36b for gate electrode constitutes the suction surface of the suction device by air. For this reason, adsorption by air can be performed using the flat plate portion ba.
  • the connection portion 36bb of the gate electrode copper connector 36b is formed to extend outward at the lower end of the connection piece 36bd which extends obliquely downward from one end of the flat plate portion 36ba.
  • the connection portion 36 bb has short sides and long sides along the short sides and the long sides of the gate electrode G, and the area of the connection surface connected to the gate electrode G has substantially the same area as the area of the gate electrode G.
  • connection reliability between the gate electrode copper connector 36b and the gate electrode G can be secured.
  • connection portion 36bc of the gate electrode copper connector 36b is formed to extend outward at the lower end of the connection piece 36be extending obliquely downward from the other end of the flat plate portion 36ba.
  • the connection portion 36 bc is located below the connection portion 36 bb.
  • the area of the connection surface of the connection portion 36bc to the wiring pattern 33c is larger than the area of the connection surface of the connection portion 36bb to the gate electrode G.
  • the gate electrode copper connector 36b is substantially coplanar when viewed from the front having the flat plate portion 36ba, the connection piece 36bd, the connection portion 36bb, the connection piece 36be, and the connection portion 36bc. Since it is formed in the shape of a letter, it is possible to perform the reflow connection described later in the solder connection, and to effectively relieve the thermal stress when the semiconductor module 30 becomes high temperature due to heat generation.
  • the first source electrode copper connector 36a1 is formed by punching and bending a copper plate, extends from the flat plate portion 36aa and one end of the flat plate portion 36aa, and the source electrode S of the bare chip FET 35 via the solder 34e. And a connection portion 36 ac extending from the other end of the flat portion 36 aa and connected to the wiring pattern 33 b via the solder 34 b.
  • the flat plate portion 36aa of the first source electrode copper connector 36a1 constitutes the suction surface of the suction device using air. For this reason, adsorption by air can be performed using the flat plate portion aa.
  • an identification hole 36af for identifying the second source electrode copper connector 36a2 is formed in the flat plate portion 36aa.
  • the first source electrode copper connector 36a1 is drawn out along the direction (arrow A 'direction in FIG. 7) in which the short side of the source electrode S formed in a rectangular shape extends.
  • the contact portion 36ab of the first source electrode copper connector 36a1 is formed to extend outward at the lower end of the connection piece 36ad which extends obliquely downward from one end of the flat plate portion 36aa.
  • the contact portion 36ab has a short side and a long side along the short side and the long side of the source electrode S, and the area of the connection surface connected to the source electrode S has substantially the same area as the source electrode S. There is.
  • the first source is disposed 180 ° straight with respect to the gate electrode copper connector 36 b
  • the connection reliability between the electrode copper connector 36a1 and the source electrode S formed on the upper surface of the bare chip FET 35 can be secured.
  • connection portion 36ac of the first source electrode copper connector 36a1 is formed so as to extend outward at the lower end of the connection piece 36ae extending obliquely downward from the other end of the flat plate portion 36aa.
  • the connection portion 36ac is located below the connection portion 36ab.
  • the area of the connection surface of the connection portion 36ac to the wiring pattern 33b is substantially the same as the area of the connection surface of the connection portion 36ab to the source electrode S.
  • the first source electrode copper connector 36a1 has a flat portion 36aa, a connection piece 36ad, a connection portion 36ab, a connection piece 36ae, and a connection portion 36ac. Since it is formed in a substantially U-shape, it is possible to perform the reflow connection described later in the solder connection, and to effectively relieve the thermal stress when the semiconductor module 30 becomes high temperature due to heat generation.
  • the second source electrode copper connector 36a2 is formed by punching and bending a copper plate, and extends from the flat plate portion 36aa and one end of the flat plate portion 36aa, and the source electrode S of the bare chip FET 35 via the solder 34e. And a connection portion 36 ac extending from the other end of the flat portion 36 aa and connected to the wiring pattern 33 b via the solder 34 b.
  • the flat plate portion 36aa of the second source electrode copper connector 36a2 constitutes the suction surface of the suction device using air. For this reason, adsorption by air can be performed using the flat plate portion aa.
  • the second source electrode copper connector 36a2 is drawn along the direction in which the long side of the source electrode S formed in a rectangular shape extends (the arrow B or B direction in FIG. 7).
  • the connection portion 36ab of the second source electrode copper connector 36a2 is formed to extend outward at the lower end of the connection piece 36ad extending obliquely downward from one end of the flat plate portion 36aa.
  • the connection portion ab has a short side and a long side along the long side and the short side of the source electrode S, and the area of the connection surface connected to the source electrode S is substantially the same as the area of the source electrode S.
  • the second source is disposed at 90 ° perpendicular to the gate electrode copper connector 36 b
  • the connection reliability between the electrode copper connector 36a2 and the source electrode S formed on the top surface of the bare chip FET 35 can be secured.
  • connection portion 36ac of the second source electrode copper connector 36a2 is formed so as to extend outward at the lower end of the connection piece 36ae extending obliquely downward from the other end of the flat plate portion 36aa.
  • the connection portion 36ac is located below the connection portion 36ab.
  • the area of the connection surface of the connection portion 36ac to the wiring pattern 33b is substantially the same as the area of the connection surface of the connection portion 36ab to the source electrode S.
  • the second source electrode copper connector 36a2 has the flat portion 36aa, the connection piece 36ad, the connection portion 36ab, the connection piece 36ae, and the connection portion 36ac. Since it is formed in a substantially U-shape, it is possible to perform the reflow connection described later in the solder connection, and to effectively relieve the thermal stress when the semiconductor module 30 becomes high temperature due to heat generation.
  • another wiring pattern 33d of the plurality of wiring patterns 33a to 33d formed on the insulating layer 32 is another wiring pattern 33d via a solder 34d.
  • the surface mounting component 37 is mounted.
  • the semiconductor module 30 configured in this way is mounted on the semiconductor module mounting portion 21 of the case 20 by a plurality of mounting screws 38, as shown in FIG.
  • the substrate 31 of the semiconductor module 30 is formed with a plurality of through holes 31 a through which the mounting screws 38 are inserted.
  • the heat dissipation sheet 39 is mounted on the semiconductor module mounting portion 21, and the semiconductor module 30 is mounted on the heat dissipation sheet 39.
  • the heat generated by the semiconductor module 30 is dissipated to the case 20 through the heat dissipating sheet 39 by the heat dissipating sheet 39.
  • control circuit board 40 mounts a plurality of electronic components on the substrate to constitute a control circuit including the control arithmetic device 11 and the gate drive circuit 12.
  • the control circuit board 40 After mounting the semiconductor module 30 on the semiconductor module mounting portion 21, the control circuit board 40 is provided with a plurality of standing on the semiconductor module mounting portion 21 and the power and signal connector mounting portion 22 from above the semiconductor module 30.
  • a plurality of mounting screws 41 are mounted on the mounting post 24.
  • the control circuit board 40 is formed with a plurality of through holes 40 a through which the mounting screws 41 are inserted.
  • the power and signal connector 50 inputs DC power from a battery (not shown) to the semiconductor module 30 and various signals including signals from the torque sensor 12 and the vehicle speed sensor 9 to the control circuit board 40. Used.
  • the power and signal connector 50 is attached to the power and signal connector mounting portion 22 provided in the semiconductor module mounting portion 21 by a plurality of mounting screws 51.
  • the three-phase output connector 60 is used to output the current from the a-phase output terminal 92a, the b-phase output terminal 92b, and the c-phase output terminal 92c.
  • the three-phase connector 60 is attached to the three-phase output connector mounting portion 23 provided at the width direction end of the semiconductor module mounting portion 21 by a plurality of mounting screws 61.
  • the three-phase output connector 60 is formed with a plurality of through holes 60 a through which the mounting screws 61 are inserted.
  • the cover 70 covers the control circuit board 40 from above the control circuit board 40 with respect to the case 20 to which the semiconductor module 30, the control circuit board 40, the power and signal connector 50, and the three-phase output connector 60 are attached. Attached to cover the
  • the semiconductor module 30 First, the insulating layer 32 is formed on one main surface of the metal substrate 31 (insulating layer forming step). Next, a plurality of wiring patterns 33a to 33d are formed on the insulating layer 32 (wiring pattern formation step). Thereafter, solder paste (solders 34a to 34d) is applied onto the plurality of wiring patterns 33a to 33d, respectively (solder paste application step).
  • solder paste solders 34a to 34d
  • one of the bare chip FETs 35 is mounted on a solder paste (solder 33a) applied on one of the plurality of wiring patterns 33a to 33d (a bare chip FET mounting step), and another wiring pattern 33d is formed.
  • Other surface mounting components 37 are mounted on the solder paste (solder 34 d) applied on top.
  • the other bare chip FETs 35 are also mounted on the same or separate wiring pattern as the wiring pattern 33a.
  • solder paste (solder 34 e, 34 f) is applied onto the source electrode S and the gate electrode G formed on the upper surface of the bare chip FET 35 (solder paste application step). Thereafter, the solder paste (solder 34e) applied on the source electrode S of the bare chip FET 35 and the wiring pattern 33b other than the wiring pattern 33a on which the bare chip FET 35 is mounted among the plurality of wiring patterns 33a to 33d are applied.
  • the copper connector 36a for source electrode (the copper connector for source electrode selected from the copper connector 36a1 for the first source electrode and the copper connector 36a2 for the second source electrode) is mounted ( Process for mounting copper connector for source electrode).
  • the wiring pattern 33a on which the bare chip FET 35 is mounted and the copper connector 36a for the source electrode among the plurality of wiring patterns 33a to 33d are mounted on the solder paste (solder 34f) applied on the gate electrode G of the bare chip FET 35.
  • the copper connector 36b for gate electrode is mounted on the solder paste (solder 34c) applied on the other wiring pattern 33c other than the above wiring pattern 33b (mounting step of copper connector for gate electrode).
  • the semiconductor module intermediate assembly configured by the above steps is placed in a reflow furnace (not shown), and one of the plurality of wiring patterns 33a to 33d is soldered through the solder 34a of the wiring pattern 33a and the bare chip FET 35. Bonding, bonding between the wiring pattern 33 d and the other surface mounting component 37 via solder 34 d, and bonding between the source electrode S formed on the upper surface of the bare chip FET 35 and the copper connector 36 a for source electrode via solder 34 e.
  • the semiconductor module 30 is completed.
  • the connection between the source electrode S of the bare chip FET 35 and the wiring pattern 33b on the substrate 31 is performed using the copper connector 36a for the source electrode, and the connection between the gate electrode G of the bare chip FET 35 and another wiring pattern 33c on the substrate 31
  • the solder mounting operation can be performed.
  • connection between the source electrode S of the bare chip FET 35 and the wiring pattern 33b on the substrate 31 and the other electrode on the gate electrode G of the bare chip FET 35 and the substrate 31 The connection with the pattern 33 c can be performed in the same process as the solder mounting operation performed when mounting the bare chip FET 35 and the other surface mounted components 37 on the wiring patterns 33 a and 33 d on the substrate 31. Therefore, the manufacturing tact of the semiconductor module 30 can be shortened, and no dedicated equipment for wire bonding is required, and the manufacturing cost of the semiconductor module 30 can be reduced.
  • this invention can perform a various change and improvement, without being limited to this.
  • the bare chip FET 35 is used in the semiconductor module 30, the present invention is not limited to the bare chip FET 35, and another bare chip transistor such as a bare chip IGBT may be used.
  • copper connectors are used on the electrodes formed on the upper surface of the bare chip transistors and on other wiring patterns other than the wiring patterns to which the bare chip transistors are connected among the plurality of wiring patterns. It may be connected via solder. Thereby, the connection between the electrode of the bare chip transistor and the wiring pattern on the substrate can be performed in the same process as the solder mounting operation performed when mounting the bare chip transistor or other surface mounted components on the wiring pattern on the substrate it can.
  • a bare chip IGBT When a bare chip IGBT is used as a bare chip transistor, it is preferable to connect the emitter electrode and the gate electrode formed on the bare chip IGBT to the wiring pattern on the substrate using a copper connector via solder. As described above, when using the bare chip IGBT to connect the emitter electrode and the gate electrode formed on the bare chip IGBT to the wiring pattern on the substrate using the copper connector, the emitter of the bare chip IGBT is used. The connection between the electrode and the wiring pattern on the substrate and the connection between the gate electrode of the bare chip IGBT and another wiring pattern on the substrate are performed when mounting the bare chip IGBT or other surface mounted components on the wiring pattern on the substrate It can be performed in the same process as the solder mounting operation.
  • the source electrode S formed on the upper surface of the bare chip FET 35 is formed in a rectangular shape, it may be formed in a square shape.
  • the shapes of the first source electrode connector 36a1 and the second source electrode copper connector 36a2 connected to the source electrode S can be made identical and made common.
  • a common copper connector 36c is used as a jumper wire for the a-phase output line 91a, the b-phase output line 91b, and the c-phase output line 91c.
  • the lengths of the paths of the a-phase output line 91a, the b-phase output line 91b, and the c-phase output line 91c can be made the same.

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Abstract

　ベアチップトランジスタの電極と基板上の配線パターンとの接続を半田実装作業で行うようにして、ベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で行うことを可能とする半導体モジュール及びその製造方法を提供する。半導体モジュール（３０）は、絶縁層（３２）上に形成された複数の配線パターン（３３ａ）～（３３ｄ）と、複数の配線パターン（３３ａ）～（３３ｄ）のうち一つの配線パターン（３３ａ）上に半田（３４ａ）を介して実装されるベアチップトランジスタ（３５）と、ベアチップトランジスタ（３５）の上面に形成された電極（Ｓ），（Ｇ）と複数の配線パターン（３３ａ）～（３３ｄ）のうち他の配線パターン（３３ｂ），（３３ｃ）とを半田（３４ｂ），（３４ｃ）を介して接続するための、銅板で構成される銅コネクタ（３６ａ），（３６ｂ）とを備えている。

Description

半導体モジュール及びその製造方法
　本発明は、自動車用電気機器に組み込まれるパワーモジュール等の半導体モジュール及びその製造方法に関する。
　昨今、自動車等の車両における種々の電気機器の制御に電子装置が導入されてきた。電子装置が組み込まれた電気機器の一例として電動パワーステアリング装置では、自動車の操舵に係る電動モータが収容される筐体にモータ駆動部が設けられ、このモータ駆動部に電子装置が搭載される。この電子装置は、パワーモジュールとして、モータ駆動部に組み込まれる。
　パワーモジュールは、電動パワーステアリング装置のような比較的大きな電流で駆動される電気機器の制御に適した、例えば、ＦＥＴ（Field Effect Transistor）、ＩＧＢＴ（Insulated Gate Bipolar Transistor）等のパワー素子を搭載したいわゆる半導体モジュールとして構成される。この種のパワーモジュールは、車両に搭載されることから車載モジュール（In-vehicle Module）とも呼ばれる。
　従来、この種の半導体モジュールとして、例えば、図１４に示すものが知られている（特許文献１参照）。図１４は、従来の半導体モジュールの一例の断面模式図である。
　図１４に示す半導体モジュール１００は、金属製の基板１０１と、基板１０１の凹部の底部平坦面上に設けられた樹脂１０２と、樹脂１０２上に形成された複数の銅箔（配線パターン）１０３ａ，１０３ｂ，１０３ｃ，１０３ｄとを備えている。銅箔１０３ａ及び銅箔１０３ｃと銅箔１０３ｄとの間には、溝１０９が形成されている。そして、複数の銅箔１０３ａ，１０３ｂ，１０３ｃ，１０３ｄのうち銅箔１０３ａ，１０３ｂの上には、熱緩衝板１０４ａ，１０４ｂがそれぞれ形成され、熱緩衝板１０４ａ，１０４ｂ上には、ＩＧＢＴ１０５ａ，１０５ｂがそれぞれ形成されている。各ＩＧＢＴ１０５ａ，１０５ｂは、ベアチップＩＧＢT（ベアチップトランジスタ）である。
　そして、ＩＧＢＴ１０５ａのエミッタと銅箔１０３ｂとがワイヤで構成される配線１０６ａで接続され、また、ＩＧＢＴ１０５ｂのエミッタと銅箔１０３ｃとが同じくワイヤで構成される配線１０６ｂで接続されている。
　また、樹脂１０２、銅箔１０３ａ，１０３ｂ，１０３ｃ、熱緩衝板１０４ａ，１０４ｂ、ＩＧＢＴ１０５ａ，１０５ｂ、及び配線１０６ａ，１０６ｂは、ゲル１０７によって封入されている。また、基板１０１の凹部を覆う蓋１０８が基板１０１の上部に固定されている。
　また、従来の半導体モジュールの他の例として、例えば、図１５に示すものも知られている（特許文献２参照）。図１５は、従来の半導体モジュールの他の例を示す平面模式図である。
　図１５に示す半導体モジュール２００において、基板（図示せず）上には複数の導電パッド２０１，２０２が形成されている。そして、複数の導電パッド２０１，２０２のうちの一つの導電パッド２０１上にはＭＯＳチップ２０３が半田接続されている。また、ＭＯＳチップ２０３の上面には、複数のソース電極２０５及び単一のゲート電極２０４が形成され、ＭＯＳチップ２０３の下面には図示しないドレイン電極が形成されている。
　そして、ＭＯＳチップ２０３のソース電極２０５と、基板上に形成された複数の導電パッド２０１，２０２のうちの他の導電パッド２０２とがリード２１０によって相互接続されている。リード２１０は、金属板を打抜き及び曲げ加工することによって形成され、図１５に示すＸ方向及びＹ方向（水平方向）に延びる矩形平板状のソース電極接続部２１１と、Ｘ方向及びＹ方向に延びる平板状の電極接続部２１２と、ソース電極接続部２１１と電極接続部２１２とを繋ぐＺ方向（上下方向）に傾斜した連結部２１３とを備えている。ここで、ソース電極接続部２１１は、ＭＯＳチップ２０３のソース電極２０５に半田接続され、また、電極接続部２１２は、基板上の複数の導電パッド２０１，２０２のうちの他の導電パッド２０２に半田接続されるようになっている。
　そして、ソース電極接続部２１１のＸ方向の幅ａは複数のソース電極２０５のＸ方向の幅ｂ以上になっている。これにより、ソース電極２０５における不均一なはんだ濡れと当該半田のリフローによる当該ソース電極２０５に対する位置ずれを防止することができる。
特開２００４－３３５７２５号公報 特開２００７－９５９８４号公報
　しかしながら、これら従来の図１４に示した半導体モジュール１００及び図１５に示した半導体モジュール２００にあっては、以下の問題点があった。
　即ち、図１４に示した半導体モジュール１００の場合、ＩＧＢＴ１０５ａのエミッタと銅箔１０３ｂとの接続及びＩＧＢＴ１０５ｂのエミッタと銅箔１０３ｃとの接続につき、ワイヤで構成される配線１０６ａ，１０６ｂを用いて接続している。このワイヤを用いた接続は、ワイヤボンディング装置（図示せず）を使用して行われるため、配線１０６ａ，１０６ｂを実装する作業が、ＩＧＢＴ１０５ａ，１０５ｂやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と異なり、製造工程が別になってしまうという問題があった。ワイヤボンディングによる実装作業が、半田実装作業と異なり、別の製造工程を要すると、製造タクトが長くなるとともに、ワイヤボンディングの専用設備が必要になり、製造コストが高くなってしまうという問題があった。
　また、図１５に示した半導体モジュール２００の場合、ソース電極２０５に接続されたリード２１０の引き出し方向は、図１５に示すＹ方向のみであり、一方、ゲート電極２０４に接続されるリードについては何ら記載されていない。ここで、ソース電極２０５に接続されたリード２１０の引き出し方向が一方向のみであると、基板上に実装されるＭＯＳチップ２０３の配置の自由度がなく、基板上の配線の設計自由度がない。この基板上の配線の設計自由度がないことにより、基板上における半導体モジュールのレイアウトをコンパクトにすることができない、という問題があった。また、ソース電極２０５に接続されたリード２１０の引き出し方向が一方向のみであると、基板上における３相モータの各相の径路の長さを同一にすることが困難で、各相のインピーダンス特性が異なり、３相モータの各相特性を一致させることが困難となる、という問題があった。
　従って、本発明は上述の問題点を解決するためになされたものであり、その目的は、ベアチップトランジスタの電極と基板上の配線パターンとの接続を半田実装作業で行うようにして、ベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で行うことを可能とする半導体モジュール及びその製造方法を提供することにある。
　また、本発明の他の目的は、基板上に実装されるベアチップトランジスタの配置及び基板上の配線の設計に自由度を持たせ、基板上における半導体モジュールのレイアウトをコンパクトにすることができるとともに、基板上における３相モータの各相の径路の長さを同一にすることを容易に行える半導体モジュール及びその製造方法を提供することにある。
　上記課題を解決するため、本発明のある態様に係る半導体モジュールは、金属製の基板と、該基板の上に形成された絶縁層と、該絶縁層上に形成された複数の配線パターンと、該複数の配線パターンのうち一つの配線パターン上に半田を介して実装されるベアチップトランジスタと、該ベアチップトランジスタの上面に形成された電極と前記複数の配線パターンのうち他の配線パターンとを半田を介して接続するための、銅板で構成される銅コネクタとを備えたことを特徴としている。
　この半導体モジュールによれば、銅板で構成される銅コネクタを用いることにより、ベアチップトランジスタの電極と基板上の配線パターンとの接続を半田実装作業で行える。そのため、ベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で、ベアチップトランジスタの電極と基板上の配線パターンとの接続を行うことができる。これにより、半導体モジュールの製造タクトを短くすることができるとともに、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。即ち、ベアチップトランジスタの電極と基板上の配線パターンとの接続も半田実装作業用の設備にて行うことが可能であるため、設備投資を抑制することができる。更に、ベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する工程と、ベアチップトランジスタの電極と基板上の配線パターンとの接続を行う工程とを同時に行うことも可能となる。
　なお、銅板及び銅コネクタは、それぞれ、銅と同様の電気的・機械的特性を有する材質の板状部材、銅と同様の電気的・機械的特性を有する材質のコネクタであってもよいが、工業的に安定した品質のものが比較的安価に得やすいため、銅板、銅コネクタを用いることが好ましい。
　また、この半導体モジュールにおいて、前記ベアチップトランジスタが、上面にソース電極及びゲート電極を形成したベアチップＦＥＴであり、前記銅コネクタが、ソース電極用銅コネクタと、ゲート電極用銅コネクタとを備え、前記ベアチップＦＥＴのソース電極上と前記複数の配線パターンのうち他の配線パターン上とを前記ソース電極用銅コネクタで半田を介して接続し、前記ベアチップＦＥＴのゲート電極上と前記複数の配線パターンのうち更に他の配線パターン上とを前記ゲート電極用銅コネクタで半田を介して接続することが好ましい。
　この半導体モジュールによれば、ベアチップＦＥＴのソース電極と基板上の配線パターンとの接続をソース電極用銅コネクタを用い、ベアチップＦＥＴのゲート電極と基板上の別の配線パターンとの接続をゲート電極用銅コネクタを用いることにより、半田実装作業で行えるので、ベアチップＦＥＴのソース電極と基板上の配線パターンとの接続及びベアチップＦＥＴのゲート電極と基板上の別の配線パターンとの接続をベアチップＦＥＴやその他の表面実装部品を基板上の配線パターン上に実装する際に行われるはんだ実装作業と同一の工程で行うことができる。
　また、この半導体モジュールにおいて、前記ゲート電極用銅コネクタは１種類であり、前記ソース電極用銅コネクタは、前記ゲート電極用銅コネクタに対して１８０°ストレート配置とする第１ソース電極用銅コネクタと、前記ゲート電極用銅コネクタに対して９０°直角配置とする第２ソース電極用銅コネクタとの２種類であり、１つのベアチップＦＥＴにおいて、前記１種類のゲート電極用銅コネクタと前記２種類の第１ソース電極用銅コネクタ及び第２ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用するとよい。
　この半導体モジュールによれば、基板上に実装されるベアチップトランジスタの配置に自由度が生まれ、基板上の配線の設計の自由度が増大し、基板上における半導体モジュールのレイアウトをコンパクトにすることができるとともに、基板上における３相モータの各相の径路の長さを同一にすることを容易に行うことができる。これにより、３相モータの各相特性、特に各相のインピーダンス特性を容易に一致させることができ、トルクや速度等のリップル精度を向上することが可能になる。
　また、この半導体モジュールにおいて、前記ベアチップＦＥＴの上面に形成された前記ゲート電極と前記ソース電極とが直列にストレート配置され、前記ソース電極は長方形状に形成されていてもよい。
　更に、この半導体モジュールにおいて、前記第１ソース電極用銅コネクタは、前記長方形状に形成されたソース電極の短辺が延びる方向に沿って引き出されるとともに、当該ソース電極の短辺及び長辺に沿う短辺及び長辺を有する、前記ソース電極に接続する接続面の面積が前記ソース電極とほぼ同一の面積である接続部を備えることが好ましい。
　この半導体モジュールによれば、ゲート電極用銅コネクタに対して１８０°ストレート配置とする第１ソース電極用銅コネクタとベアチップＦＥＴの上面に形成されたソース電極との接続信頼性を確保できる。
　また、この半導体モジュールにおいて、前記第２ソース電極用銅コネクタは、前記長方形状に形成されたソース電極の長辺が延びる方向に沿って引き出されるとともに、当該ソース電極の長辺及び短辺に沿う長辺及び短辺を有する、前記ソース電極に接続する接続面の面積が前記ソース電極とほぼ同一の面積である接続部を備えることが好ましい。
　この半導体モジュールによれば、ゲート電極用銅コネクタに対して９０°直角配置とする第２ソース電極用銅コネクタとベアチップＦＥＴの上面に形成されたソース電極との接続信頼性を確保できる。
　更に、本発明のある態様に係る半導体モジュールの製造方法は、金属製の基板上に絶縁層を形成する工程と、該絶縁層上に複数の配線パターンを形成する工程と、該複数の配線パターン上に半田ペーストを塗布する工程と、前記複数の配線パターンのうち一つの配線パターン上に塗布された半田ペースト上にベアチップトランジスタを搭載する工程と、前記ベアチップトランジスタの上面に形成された電極上に半田ペーストを塗布する工程と、前記ベアチップトランジスタの電極上に塗布された半田ペースト上及び前記複数の配線パターンのうち他の配線パターン上に塗布された半田ペースト上に、銅板で構成される銅コネクタを搭載して半導体モジュール中間組立体を構成する工程と、該半導体モジュール中間組立体をリフロー炉に入れて、前記複数の配線パターンのうち一つの配線パターンと前記ベアチップトランジスタとの半田を介しての接合、前記ベアチップトランジスタの上面に形成された電極と前記銅コネクタとの半田を介しての接合、及び前記複数の配線パターンのうち他の配線パターンと前記銅コネクタとの半田を介しての接合を行う工程とを含むことを特徴としている。
　この半導体モジュールの製造方法によれば、前述の半導体モジュールと同様に、ベアチップトランジスタの電極と基板上の配線パターンとの接続を、銅板で構成される銅コネクタを用いることにより、半田実装作業で行えるので、ベアチップトランジスタの電極と基板上の配線パターンとの接続をベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で行うことができる。このため、半導体モジュールの製造タクトを短くすることができるとともに、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。
　また、この半導体モジュールの製造方法において、前記ベアチップトランジスタが、上面にソース電極及びゲート電極を形成したベアチップＦＥＴであり、前記銅コネクタが、ソース電極用銅コネクタと、ゲート電極用銅コネクタとを備えており、金属製の前記基板上に前記絶縁層を形成する工程と、該絶縁層上に複数の配線パターンを形成する工程と、該複数の配線パターン上に半田ペーストを塗布する工程と、前記複数の配線パターンのうち一つの配線パターン上に塗布された半田ペースト上に前記ベアチップＦＥＴを搭載する工程と、前記ベアチップＦＥＴの上面に形成されたソース電極及びゲート電極上に半田ペーストを塗布する工程と、前記ベアチップＦＥＴのソース電極上に塗布された半田ペースト上及び前記複数の配線パターンのうち他の配線パターン上に塗布された半田ペースト上に、前記ソース電極用銅コネクタを搭載する工程と、前記ベアチップＦＥＴのゲート電極上に塗布された半田ペースト上及び前記複数の配線パターンのうち更に他の配線パターン上に塗布された半田ペースト上に、前記ゲート電極用銅コネクタを搭載して半導体モジュール中間組立体を構成する工程と、該半導体モジュール中間組立体をリフロー炉に入れて、前記複数の配線パターンのうち一つの配線パターンと前記ベアチップＦＥＴとの半田を介しての接合、前記ベアチップＦＥＴの上面に形成されたソース電極と前記ソース電極用銅コネクタとの半田を介しての接合、前記複数の配線パターンのうち他の配線パターンと前記ソース電極用銅コネクタとの半田を介しての接合、前記ベアチップＦＥＴの上面に形成されたゲート電極と前記ゲート電極用銅コネクタとの半田を介しての接合、及び前記複数の配線パターンのうち更に他の配線パターンと前記ゲート電極用銅コネクタとの半田を介しての接合を行う工程とを含むことが好ましい。
　この半導体モジュールの製造方法によれば、前述の半導体モジュールと同様に、ベアチップＦＥＴのソース電極と基板上の配線パターンとの接続をソース電極用銅コネクタを用い、ベアチップＦＥＴのゲート電極と基板上の別の配線パターンとの接続をゲート電極用銅コネクタを用いることにより、半田実装作業で行えるので、ベアチップＦＥＴのソース電極と基板上の配線パターンとの接続及びベアチップＦＥＴのゲート電極と基板上の別の配線パターンとの接続をベアチップＦＥＴやその他の表面実装部品を基板上の配線パターン上に実装する際に行われるはんだ実装作業と同一の工程で行うことができる。
　更に、この半導体モジュールの製造方法において、前記ゲート電極用銅コネクタは１種類であり、前記ソース電極用銅コネクタは、前記ゲート電極用銅コネクタに対して１８０°ストレート配置とする第１ソース電極用銅コネクタと、前記ゲート電極用銅コネクタに対して９０°直角配置とする第２ソース電極用銅コネクタとの２種類であり、１つのベアチップＦＥＴにおいて、前記１種類のゲート電極用銅コネクタと前記２種類の第１ソース電極用銅コネクタ及び第２ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用するとよい。
　この半導体モジュールの製造方法によれば、前述の半導体モジュールと同様に、基板上に実装されるベアチップトランジスタの配置に自由度が生まれ、基板上の配線の設計の自由度が増大し、基板上における半導体モジュールのレイアウトをコンパクトにすることができるとともに、基板上における３相モータの各相の径路の長さを同一にすることを容易に行うことができる。これにより、３相モータの各相特性、特に各相のインピーダンス特性を容易に一致させることができ、トルクや速度等のリップル精度を向上することが可能になる。
　また、本発明の別の態様に係る半導体モジュールは、ベアチップトランジスタの電極と基板上の配線パターンとの接続を、銅板で構成される銅コネクタを用いることにより、半田実装作業で行うことを特徴とする。
　また、本発明の更に別の態様に係る半導体モジュールは、基板上に実装されるベアチップトランジスタの配置に自由度が生まれ、基板上の配線の設計の自由度が増大し、基板上における半導体モジュールのレイアウトをコンパクトにすることができるように、１つのベアチップＦＥＴにおいて、１種類のゲート電極用銅コネクタと、ゲート電極用銅コネクタに対して１８０°ストレート配置とする第１ソース電極用銅コネクタと、前記ゲート電極用銅コネクタに対して９０°直角配置とする第２ソース電極用銅コネクタとの２種類の第１ソース電極用銅コネクタ及び第２ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用することを特徴とする。
　本発明に係る半導体モジュール及び半導体モジュールの製造方法によれば、ベアチップトランジスタの電極と基板上の配線パターンとの接続を、銅板で構成される銅コネクタを用いることにより、半田実装作業で行えるので、ベアチップトランジスタの電極と基板上の配線パターンとの接続をベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で行うことができる。このため、半導体モジュールの製造タクトを短くすることができるとともに、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。
　また、この半導体モジュール及び半導体モジュールの製造方法において、１つのベアチップＦＥＴにおいて、１種類のゲート電極用銅コネクタと２種類の第１ソース電極用銅コネクタ及び第２ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用した場合には、基板上に実装されるベアチップトランジスタの配置に自由度が生まれ、基板上の配線の設計の自由度が増大し、基板上における半導体モジュールのレイアウトをコンパクトにすることができるとともに、基板上における３相モータの各相の径路の長さを同一にすることを容易に行うことができる。これにより、３相モータの各相特性、特に各相のインピーダンス特性を容易に一致させることができ、トルクや速度等のリップル精度を向上することが可能になる。
本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造を示す図である。 図１に示す電動パワーステアリング装置のコントローラの制御系を示すブロック図である。 図１に示す電動パワーステアリング装置の半導体モジュールを含むコントローラの分解斜視図である。 図３に示す半導体モジュールの平面図である。 図３及び図４に示す半導体モジュールにおいて、ベアチップトランジスタを構成するベアチップＦＥＴの電極と基板上の配線パターンとの接続状態を説明するための模式図である。 ベアチップＦＥＴの電極と銅コネクタとの接続状態を説明するための平面図であり、（Ａ）は、ベアチップＦＥＴのゲート電極にゲート電極用銅コネクタを接続するとともに、ソース電極に第１ソース電極用銅コネクタを接続した状態を説明するための平面図、（Ｂ）は、ベアチップＦＥＴのゲート電極にゲート電極用銅コネクタを接続するとともに、ソース電極に第２ソース電極用銅コネクタを接続した状態を説明するための平面図である。 ベアチップＦＥＴの概略平面図である。 ゲート電極用銅コネクタを示し、（Ａ）はゲート電極用銅コネクタを左側面斜め上方から見た状態の斜視図、（Ｂ）はゲート電極用銅コネクタを右側面斜め上方から見た状態の斜視図である。 ゲート電極用銅コネクタを示し、（Ａ）は平面図、（Ｂ）は正面図、（Ｃ）は右側面図、（Ｄ）は左側面図である。 第１ソース電極用銅コネクタを左側面斜め上方から見た状態の斜視図である。 第１ソース電極用銅コネクタを示し、（Ａ）は平面図、（Ｂ）は正面図、（Ｃ）は右側面図、（Ｄ）は左側面図である。 第２ソース電極用銅コネクタを左側面斜め上方から見た状態の斜視図である。 第２ソース電極用銅コネクタを示し、（Ａ）は平面図、（Ｂ）は正面図、（Ｃ）は右側面図、（Ｄ）は左側面図である。 従来の半導体モジュールの一例の断面模式図である。 従来の半導体モジュールの他の例を示す平面模式図である。
　以下、本発明の実施の形態を図面を参照して説明する。図１は、本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造を示す図である。図２は、図１に示す電動パワーステアリング装置のコントローラの制御系を示すブロック図である。図３は、図１に示す電動パワーステアリング装置の半導体モジュールを含むコントローラの分解斜視図である。図４は、図３に示す半導体モジュールの平面図である。図５は、図３及び図４に示す半導体モジュールにおいて、ベアチップトランジスタを構成するベアチップＦＥＴの電極と基板上の配線パターンとの接続状態を説明するための模式図である。図６は、ベアチップＦＥＴの電極と銅コネクタとの接続状態を説明するための平面図であり、（Ａ）は、ベアチップＦＥＴのゲート電極にゲート電極用銅コネクタを接続するとともに、ソース電極に第１ソース電極用銅コネクタを接続した状態を説明するための平面図、（Ｂ）は、ベアチップＦＥＴのゲート電極にゲート電極用銅コネクタを接続するとともに、ソース電極に第２ソース電極用銅コネクタを接続した状態を説明するための平面図である。図７は、ベアチップＦＥＴの概略平面図である。
　図１には、本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造が示されており、電動パワーステアリング装置において、操向ハンドル１のコラム軸２は、減速ギア３、ユニバーサルジョイント４Ａ及び４Ｂ、ピニオンラック機構５を経て操向車輪のタイトロッド６に連結されている。コラム軸２には、操向ハンドル１の操舵トルクを検出するトルクセンサ７が設けられており、操向ハンドル１の操舵力を補助する電動モータ８が減速ギア３を介してコラム軸２に連結されている。電動パワーステアリング装置を制御するコントローラ１０には、バッテリー（図示せず）から電力が供給されるとともに、イグニションキー（図示せず）を経てイグニションキー信号ＩＧＮ（図２参照）が入力される。コントローラ１０は、トルクセンサ７で検出された操舵トルクＴｓと車速センサ９で検出された車速Ｖとに基づいて、アシスト（操舵補助）指令となる操舵補助指令値の演算を行い、演算された操舵補助指令値に基づいて電動モータ８に供給する電流を制御する。
　コントローラ１０は、主としてマイクロコンピュータで構成されるが、その制御装置の機構及び構成を示すと図２に示すようになる。
　トルクセンサ７で検出された操舵トルクＴｓ及び車速センサ９で検出された車速Ｖは制御演算部としての制御演算装置１１に入力され、制御演算装置１１で演算された電流指令値をゲート駆動回路１２に入力する。ゲート駆動回路１２で、電流指令値等に基づいて形成されたゲート駆動信号はＦＥＴのブリッジ構成で成るモータ駆動部１３に入力され、モータ駆動部１３は非常停止用の遮断装置１４を経て３相ブラシレスモータで構成される電動モータ８を駆動する。３相ブラシレスモータの各相電流は電流検出回路１５で検出され、検出された３相のモータ電流ｉａ～ｉｃは制御演算装置１１にフィードバック電流として入力される。また、３相ブラシレスモータには、ホールセンサ等の回転センサ１６が取り付けられており、回転センサ１６からの回転信号ＲＴがロータ位置検出回路１７に入力され、検出された回転位置θが制御演算装置１１に入力される。
　また、イグニションキーからのイグニション信号ＩＧＮはイグニション電圧モニタ部１８及び電源回路部１９に入力され、電源回路部１９から電源電圧Ｖｄｄが制御演算装置１１に入力されるとともに、装置停止用となるリセット信号Ｒｓが制御演算装置１１に入力される。そして、遮断装置１４は、２相を遮断するリレー接点１４１及び１４２で構成されている。
　また、モータ駆動部１３の回路構成について説明すると、電源ライン８１に対し、直列に接続されたＦＥＴＴｒ１及びＴｒ２、ＦＥＴＴｒ３及びＴｒ４、及びＦＥＴＴｒ５及びＴｒ６が並列に接続されている。そして、電源ライン８１に対して、並列に接続されたＦＥＴＴｒ１及びＴｒ２、ＦＥＴＴｒ３及びＴｒ４、及びＦＥＴＴｒ５及びＴｒ６が接地ライン８２に接続されている。これにより、インバータを構成する。ここで、ＦＥＴＴｒ１及びＴｒ２は、ＦＥＴＴｒ１のソース電極ＳとＦＥＴＴｒ２のドレイン電極Ｄとが直列に接続され、３相モータのｃ相アームを構成し、ｃ相出力ライン９１ｃにて電流が出力される。また、ＦＥＴＴｒ３及びＴｒ４は、ＦＥＴＴｒ３のソース電極ＳとＦＥＴＴｒ４のドレイン電極Ｄとが直列に接続され、３相モータのａ相アームを構成し、ａ相出力ライン９１ａにて電流が出力される。更に、ＦＥＴＴｒ５及びＴｒ６は、ＦＥＴＴｒ５のソース電極ＳとＦＥＴＴｒ６のドレイン電極Ｄとが直列に接続され、３相モータのｂ相アームを構成し、ｂ相出力ライン９１ｂにて電流が出力される。
　次に、図３は、図１に示す電動パワーステアリング装置の半導体モジュールを含むコントローラ１０の分解斜視図であり、コントローラ１０は、ケース２０と、モータ駆動部１３を含むパワーモジュールとしての半導体モジュール３０と、放熱用シート３９と、制御演算装置１１及びゲート駆動回路１２を含む制御回路基板４０と、電力及び信号用コネクタ５０と、３相出力用コネクタ６０と、カバー７０とを備えている。
　ここで、ケース２０は、略矩形状に形成され、半導体モジュール３０を載置するための平板状の半導体モジュール載置部２１と、半導体モジュール載置部２１の長手方向端部に設けられた、電力及び信号用コネクタ５０を実装するための電力及び信号用コネクタ実装部２２と、半導体モジュール載置部２１の幅方向端部に設けられた、３相出力用コネクタ６０を実装するための３相出力用コネクタ実装部２３とを備えている。
　そして、半導体モジュール載置部２１には、半導体モジュール３０を取り付けるための取付けねじ３８がねじ込まれる複数のねじ孔２１ａが形成されている。また、半導体モジュール載置部２１及び電力及び信号用コネクタ実装部２２には、制御回路基板４０を取り付けるための複数の取付けポスト２４が立設され、各取付けポスト２４には、制御回路基板４０を取り付けるための取付けねじ４１がねじ込まれるねじ孔２４ａが形成されている。更に、３相出力用コネクタ実装部２３には、３相出力用コネクタ６０を取り付けるための取付けねじ６１がねじ込まれる複数のねじ孔２３ａが形成されている。
　また、半導体モジュール３０は、前述したモータ駆動部１３の回路構成を有し、図４に示すように、基板３１に、６個のＦＥＴＴｒ１～Ｔｒ６、電源ライン８１に接続された正極端子８１ａ、及び接地ライン８２に接続された負極端子８２ａが実装されている。また、基板３１には、ａ相出力ライン９１ａに接続されたａ相出力端子９２ａ、ｂ相出力ライン９１ｂに接続されたｂ相出力端子９２ｂ、及びｃ相出力ライン９１ｃに接続されたｃ相出力端子９２ｃを含む３相出力部９０が実装されている。また、基板３１上には、コンデンサを含むその他の表面実装部品３７が実装されている。更に、半導体モジュール３０の基板３１には、半導体モジュール３０を取り付けるための取付けねじ３８が挿通する複数の貫通孔３１ａが設けられている。
　ここで、この半導体モジュール３０において、６個のＦＥＴＴｒ１～Ｔｒ６の基板３１上への実装について説明する。各ＦＥＴＴｒ１～Ｔｒ６は、ベアチップＦＥＴ（ベアチップトランジスタ）３５で構成され、図７に示すように、ベアチップＦＥＴ３５上にソース電極Ｓとゲート電極Ｇとを備え、また、ベアチップＦＥＴ３５の下面には図示しないドレイン電極を備えている。
　このベアチップＦＥＴ３５の上面に形成されたゲート電極Ｇとソース電極Ｓとは、図７に示すように、図７における上下方向に沿って直列にストレート配置されている。ゲート電極Ｇは、図７における上下方向に沿って延びる短辺及びこの短辺と直交する長辺を有する長方形状に形成されている。また、ソース電極Ｓは、図７における上下方向に沿って延びる短辺及びこの短辺と直交する長辺を有する長方形状に形成されている。ソース電極Ｓの短辺及び長辺は、ゲート電極Ｇの短辺及び長辺よりも大きく、ソース電極Ｓの面積はゲート電極Ｇの面積よりも大きくなってる。
　半導体モジュール３０は、図５に示すように、金属製の基板３１を備え、基板３１の上には、絶縁層３２が形成されている。基板３１は、アルミニウムなどの金属製である。また、この絶縁層３２上には、複数の配線パターン３３ａ～３３ｄが形成されている。各配線パターン３３ａ～３３ｄは、銅やアルミニウムなどの金属、又はこの金属を含む合金で構成される。そして、複数の配線パターン３３ａ～３３ｄのうち一つの配線パターン３３ａ上には半田３４ａを介して各ＦＥＴＴｒ１～Ｔｒ６を構成するベアチップＦＥＴ３５が実装されている。ベアチップＦＥＴ３５の下面に形成されたドレイン電極が半田３４ａを介して配線パターン３３ａに接続される。そして、ベアチップＦＥＴ３５のソース電極Ｓ上と複数の配線パターン３３ａ～３３ｄのうち他の配線パターン３３ｂ上とがソース電極用銅コネクタ３６ａでそれぞれ半田３４ｅ，３４ｂを介して接続される。また、ベアチップＦＥＴ３５のゲート電極Ｇ上と複数の配線パターン３３ａ～３３ｄのうち更に他の配線パターン３３ｃ上とがゲート電極用銅コネクタ３６ｂでそれぞれ半田３４ｆ，３４ｃを介して接続される。
　ここで、ゲート電極用銅コネクタ３６ｂは１種類であり、図４におけるＦＥＴＴｒ１～Ｔｒ６のすべてにおいて図７に示す矢印Ａ方向に引き出されて接続される。この様子は、図６（Ａ）,（Ｂ）に示される。
　また、ソース電極用銅コネクタ３６ａは、図６（Ａ）に示すように、ゲート電極用銅コネクタ３６ｂに対して１８０°ストレート配置とする第１ソース電極用銅コネクタ３６ａ１と、図６（Ｂ）に示すようにゲート電極用銅コネクタ３６ｂに対して９０°直角配置とする第２ソース電極用銅コネクタ３６ａ２との２種類ある。そして、第１ソース電極用銅コネクタ３６ａ１は、図４におけるＦＥＴＴｒ２、Ｔｒ４、及びＴｒ６において図７に示す矢印Ａ’方向に引き出されて接続される。また、第２ソース電極用銅コネクタ３６ａ２は、図４におけるＦＥＴＴｒ１において図７に示す矢印Ｂ方向に引き出されて接続され、図４におけるＦＥＴＴｒ３及びＴｒ５において図７に示す矢印Ｂ’方向に引き出されて接続される。
　このように、１つのベアチップＦＥＴ３５において、１種類のゲート電極用銅コネクタ３６ｂと２種類の第１ソース電極用銅コネクタ３６ａ１及び第２ソース電極用銅コネクタ３６ａ２のうちから選択されたいずれか一方のソース電極用銅コネクタとが組み合わせて使用される。
　これにより、基板３１上に実装されるベアチップＦＥＴ３５の配置に自由度が生まれ、基板３１上の配線の設計の自由度が増大し、基板３１上における半導体モジュール３０のレイアウトをコンパクトにすることができる。また、基板３１上における３相モータの各相の径路の長さ（ａ相出力ライン９１ａの長さ、ｂ相出力ライン９１ｂの長さ、及びｃ相出力ライン９１ｃの長さ）を同一にすることを容易に行うことができる。これにより、３相モータの各相特性、特に、インピーダンス特性を容易に一致させることができ、トルクや速度等のリップル精度を向上することが可能になる。
　ここで、ゲート電極用銅コネクタ３６ｂの形状について、図５、図８（Ａ）,（Ｂ）、及び図９（Ａ）,(Ｂ)，（Ｃ），（Ｄ）を参照して具体的に説明する。
　ゲート電極用銅コネクタ３６ｂは、銅板を打抜き及び曲げ加工することによって形成されるものであり、平板部３６ｂａと、平板部３６ｂａの一端から延び、半田３４ｆを介してベアチップＦＥＴ３５のゲート電極Ｇに接続される接続部３６ｂｂと、平板部３６ｂａの他端から延び、半田３４ｃを介して配線パターン３３ｃに接続される接続部３６ｂｃとを備えている。
　ゲート電極用銅コネクタ３６ｂの平板部ｂａは、エアーによる吸着装置の吸着面を構成する。このため、平板部ｂａを利用してエアーによる吸着を行うことができる。
　また、ゲート電極用銅コネクタ３６ｂの接続部３６ｂｂは、平板部３６ｂａの一端から斜め下方に延びる連結片３６ｂｄの下端に外方に延びるように形成されている。この接続部３６ｂｂは、ゲート電極Ｇの短辺及び長辺に沿う短辺及び長辺を有し、ゲート電極Ｇに接続する接続面の面積がゲート電極Ｇの面積とほぼ同一の面積を有する。接続部３６ｂｂのゲート電極Ｇに接続する接続面の面積がゲート電極Ｇとほぼ同じとすることにより、ゲート電極用銅コネクタ３６ｂとゲート電極Ｇとの接続信頼性を確保することができる。
　更に、ゲート電極用銅コネクタ３６ｂの接続部３６ｂｃは、平板部３６ｂａの他端から斜め下方に延びる連結片３６ｂｅの下端に外方に延びるように形成されている。接続部３６ｂｃは、接続部３６ｂｂよりも下方に位置する。接続部３６ｂｃの配線パターン３３ｃに対する接続面の面積は、接続部３６ｂｂのゲート電極Ｇに対する接続面の面積よりも大きくなっている。
　このように、ゲート電極用銅コネクタ３６ｂは、図９（Ｂ）に示すように、平板部３６ｂａ、連結片３６ｂｄ、接続部３６ｂｂ、連結片３６ｂｅ、及び接続部３６ｂｃを有する正面から見て略コ字形に形成されているため、半田接続の際に後に述べるリフロー接続を行い、また、半導体モジュール３０が稼働した際に発熱により高温になった際に、熱応力を効果的に緩和できる。
　また、ソース電極用銅コネクタ３６ａのうち、ゲート電極用銅コネクタ３６ｂに対して１８０°ストレート配置とする第１ソース電極用銅コネクタ３６ａ１の形状について、図５、図１０（Ａ）,（Ｂ）、及び図１１（Ａ）,(Ｂ)，（Ｃ），（Ｄ）を参照して具体的に説明する。
　第１ソース電極用銅コネクタ３６ａ１は、銅板を打抜き及び曲げ加工することによって形成されるものであり、平板部３６ａａと、平板部３６ａａの一端から延び、半田３４ｅを介してベアチップＦＥＴ３５のソース電極Ｓに接続される接続部３６ａｂと、平板部３６ａａの他端から延び、半田３４ｂを介して配線パターン３３ｂに接続される接続部３６ａｃとを備えている。
　第１ソース電極用銅コネクタ３６ａ１の平板部３６ａａは、エアーによる吸着装置の吸着面を構成する。このため、平板部ａａを利用してエアーによる吸着を行うことができる。この平板部３６ａａには、第２ソース電極用銅コネクタ３６ａ２との識別のための識別用孔３６ａｆが形成されている。
　また、第１ソース電極用銅コネクタ３６ａ１は、長方形状に形成されたソース電極Ｓの短辺が延びる方向（図７における矢印Ａ’方向）に沿って引き出される。そして、第１ソース電極用銅コネクタ３６ａ１の接点部３６ａｂは、平板部３６ａａの一端から斜め下方に延びる連結片３６ａｄの下端に外方に延びるように形成される。この接点部３６ａｂは当該ソース電極Ｓの短辺及び長辺に沿う短辺及び長辺を有し、ソース電極Ｓに接続する接続面の面積が、ソース電極Ｓとほぼ同一の面積を有している。接続部３６ａｂのソース電極Ｓに接続する接続面の面積を、長方形状のソース電極Ｓとほぼ同一の面積とすることにより、ゲート電極用銅コネクタ３６ｂに対して１８０°ストレート配置とする第１ソース電極用銅コネクタ３６ａ１とベアチップＦＥＴ３５の上面に形成されたソース電極Ｓとの接続信頼性を確保できる。
　更に、第１ソース電極用銅コネクタ３６ａ１の接続部３６ａｃは、平板部３６ａａの他端から斜め下方に延びる連結片３６ａｅの下端に外方に延びるように形成されている。接続部３６ａｃは、接続部３６ａｂよりも下方に位置する。接続部３６ａｃの配線パターン３３ｂに対する接続面の面積は、接続部３６ａｂのソース電極Ｓに対する接続面の面積とほぼ同一となっている。
　このように、第１ソース電極用銅コネクタ３６ａ１は、図１１（Ｂ）に示すように、平板部３６ａａ、連結片３６ａｄ、接続部３６ａｂ、連結片３６ａｅ、及び接続部３６ａｃを有する正面から見て略コ字形に形成されているため、半田接続の際に後に述べるリフロー接続を行い、また、半導体モジュール３０が稼働した際に発熱により高温になった際に、熱応力を効果的に緩和できる。
　また、ソース電極用銅コネクタ３６ａのうち、ゲート電極用銅コネクタ３６ｂに対して９０°直角配置とする第２ソース電極用銅コネクタ３６ａ２の形状について、図５、図１２（Ａ）,（Ｂ）、及び図１３（Ａ）,(Ｂ)，（Ｃ），（Ｄ）を参照して具体的に説明する。
　第２ソース電極用銅コネクタ３６ａ２は、銅板を打抜き及び曲げ加工することによって形成されるものであり、平板部３６ａａと、平板部３６ａａの一端から延び、半田３４ｅを介してベアチップＦＥＴ３５のソース電極Ｓに接続される接続部３６ａｂと、平板部３６ａａの他端から延び、半田３４ｂを介して配線パターン３３ｂに接続される接続部３６ａｃとを備えている。
　第２ソース電極用銅コネクタ３６ａ２の平板部３６ａａは、エアーによる吸着装置の吸着面を構成する。このため、平板部ａａを利用してエアーによる吸着を行うことができる。
　また、第２ソース電極用銅コネクタ３６ａ２は、長方形状に形成されたソース電極Ｓの長辺が延びる方向（図７における矢印ＢあるいはＢ‘方向）に沿って引き出される。そして、第２ソース電極用銅コネクタ３６ａ２の接続部３６ａｂは、平板部３６ａａの一端から斜め下方に延びる連結片３６ａｄの下端に外方に延びるように形成される。この接続部ａｂは、当該ソース電極Ｓの長辺及び短辺に沿う短辺及び長辺を有し、ソース電極Ｓに接続する接続面の面積がソース電極Ｓとほぼ同一の面積を有する。接続部３６ａｂのソース電極Ｓに接続する接続面の面積を、長方形状のソース電極Ｓとほぼ同一の面積とすることにより、ゲート電極用銅コネクタ３６ｂに対して９０°直角配置とする第２ソース電極用銅コネクタ３６ａ２とベアチップＦＥＴ３５の上面に形成されたソース電極Ｓとの接続信頼性を確保できる。
　更に、第２ソース電極用銅コネクタ３６ａ２の接続部３６ａｃは、平板部３６ａａの他端から斜め下方に延びる連結片３６ａｅの下端に外方に延びるように形成されている。接続部３６ａｃは、接続部３６ａｂよりも下方に位置する。接続部３６ａｃの配線パターン３３ｂに対する接続面の面積は、接続部３６ａｂのソース電極Ｓに対する接続面の面積とほぼ同一である。
　このように、第２ソース電極用銅コネクタ３６ａ２は、図１３（Ｂ）に示すように、平板部３６ａａ、連結片３６ａｄ、接続部３６ａｂ、連結片３６ａｅ、及び接続部３６ａｃを有する正面から見て略コ字形に形成されているため、半田接続の際に後に述べるリフロー接続を行い、また、半導体モジュール３０が稼働した際に発熱により高温になった際に、熱応力を効果的に緩和できる。
　なお、図５に示す半導体モジュール３０において、絶縁層３２上に形成された複数の配線パターン３３ａ～３３ｄのうち更にもう一つ他の配線パターン３３ｄ上には半田３４ｄを介してコンデンサなどの他の表面実装部品３７が実装される。
　このように構成された半導体モジュール３０は、図３に示すように、ケース２０の半導体モジュール載置部２１上に複数の取付けねじ３８により取り付けられる。半導体モジュール３０の基板３１には、取付けねじ３８が挿通する複数の貫通孔３１ａが形成されている。
　なお、半導体モジュール３０を半導体モジュール載置部２１上に取り付けるに際しては、放熱用シート３９を半導体モジュール載置部２１上に取付け、その放熱用シート３９の上から半導体モジュール３０を取り付ける。この放熱用シート３９により、半導体モジュール３０で発生した熱が放熱用シート３９を介してケース２０に放熱される。
　また、制御回路基板４０は、基板上に複数の電子部品を実装して制御演算装置１１及びゲート駆動回路１２を含む制御回路を構成するものである。制御回路基板４０は、半導体モジュール３０を半導体モジュール載置部２１上に取り付けた後、半導体モジュール３０の上方から半導体モジュール載置部２１及び電力及び信号用コネクタ実装部２２に立設された複数の取付けポスト２４上に複数の取付けねじ４１により取り付けられる。制御回路基板４０には、取付けねじ４１が挿通する複数の貫通孔４０ａが形成されている。
　また、電力及び信号用コネクタ５０は、バッテリー（図示せず）からの直流電源を半導体モジュール３０に、トルクセンサ１２や車速センサ９からの信号を含む各種信号を制御回路基板４０に入力するために用いられる。電力及び信号用コネクタ５０は、半導体モジュール載置部２１に設けられた電力及び信号用コネクタ実装部２２に複数の取付けねじ５１により取り付けられる。
　そして、３相出力用コネクタ６０は、ａ相出力端子９２ａ、ｂ相出力端子９２ｂ、及びｃ相出力端子９２ｃからの電流を出力するために用いられる。３相出用コネクタ６０は、半導体モジュール載置部２１の幅方向端部に設けられた３相出力用コネクタ実装部２３に複数の取付けねじ６１により取り付けられる。３相出力コネクタ６０には、取付けねじ６１が挿通する複数の貫通孔６０ａが形成されている。
　更に、カバー７０は、半導体モジュール３０、制御回路基板４０、電力及び信号用コネクタ５０、及び３相出力用コネクタ６０が取り付けられたケース２０に対し、制御回路基板４０の上方から当該制御回路基板４０を覆うように取り付けられる。
　次に、半導体モジュール３０の製造方法について図５を参照して説明する。
　半導体モジュール３０の製造に際し、先ず、金属製の基板３１の一方の主面上に絶縁層３２を形成する（絶縁層形成工程）。
　次いで、絶縁層３２上に複数の配線パターン３３ａ～３３ｄを形成する（配線パターン形成工程）。
　その後、複数の配線パターン３３ａ～３３ｄ上にそれぞれ半田ペースト（半田３４ａ～３４ｄ）を塗布する（半田ペースト塗布工程）。
　そして、複数の配線パターン３３ａ～３３ｄのうち一つの配線パターン３３ａ上に塗布された半田ペースト（半田３３ａ）上にベアチップＦＥＴ３５の一つを搭載するとともに（ベアチップＦＥＴ搭載工程）、他の配線パターン３３ｄ上に塗布された半田ペースト（半田３４ｄ）上にその他の表面実装部品３７を搭載する。その他のベアチップＦＥＴ３５についても、配線パターン３３ａと同一あるいは別個の配線パターン上に搭載する。
　次いで、ベアチップＦＥＴ３５の上面に形成されたソース電極Ｓ及びゲート電極Ｇ上に半田ペースト（半田３４ｅ，３４ｆ）を塗布する（半田ペースト塗布工程）。
　その後、ベアチップＦＥＴ３５のソース電極Ｓ上に塗布された半田ペースト（半田３４ｅ）上及び複数の配線パターン３３ａ～３３ｄのうちベアチップＦＥＴ３５が搭載された配線パターン３３ａ以外の他の配線パターン３３ｂ上に塗布された半田ペースト（半田３４ｂ）上に、ソース電極用銅コネクタ３６ａ（第１ソース電極用銅コネクタ３６ａ１及び第２ソース電極用銅コネクタ３６ａ２のうちから選択されたソース電極用銅コネクタ）を搭載する（ソース電極用銅コネクタ搭載工程）。
　また、ベアチップＦＥＴ３５のゲート電極Ｇ上に塗布された半田ペースト（半田３４ｆ）上、及び複数の配線パターン３３ａ～３３ｄのうちベアチップＦＥＴ３５が搭載された配線パターン３３ａ及びソース電極用銅コネクタ３６ａが搭載された配線パターン３３ｂ以外の更に他の配線パターン３３ｃ上に塗布された半田ペースト（半田３４ｃ）上に、ゲート電極用銅コネクタ３６ｂを搭載する（ゲート電極用銅コネクタ搭載工程）。これにより、半導体モジュール中間組立体が構成される。
　そして、以上の工程により構成された半導体モジュール中間組立体をリフロー炉（図示せず）に入れて、複数の配線パターン３３ａ～３３ｄのうち一つの配線パターン３３ａとベアチップＦＥＴ３５との半田３４ａを介しての接合、配線パターン３３ｄとその他の表面実装部品３７との半田３４ｄを介しての接合、ベアチップＦＥＴ３５の上面に形成されたソース電極Ｓとソース電極用銅コネクタ３６ａとの半田３４ｅを介しての接合、複数の配線パターン３３ａ～３３ｄのうち他の配線パターン３３ｂとソース電極用銅コネクタ３６ａとの接合、ベアチップＦＥＴ３５の上面に形成されたゲート電極Ｇとゲート電極用銅コネクタ３６ｂとの半田３４ｆを介しての接合、及び複数の配線パターン３３ａ～３３ｄのうち更に他の配線パターン３３ｃとゲート電極用銅コネクタ２６ｂとの半田３４ｃを介しての接合を一括して行う（接合工程）。
　これにより、半導体モジュール３０は完成する。
　ここで、ベアチップＦＥＴ３５のソース電極Ｓと基板３１上の配線パターン３３ｂとの接続をソース電極用銅コネクタ３６ａを用い、ベアチップＦＥＴ３５のゲート電極Ｇと基板３１上の別の配線パターン３３ｃとの接続をゲート電極用銅コネクタ３６ｂを用いることにより、半田実装作業で行えるので、ベアチップＦＥＴ３５のソース電極Ｓと基板３１上の配線パターン３３ｂとの接続及びベアチップＦＥＴ３５のゲート電極Ｇと基板３１上の別の配線パターン３３ｃとの接続を、ベアチップＦＥＴ３５やその他の表面実装部品３７を基板３１上の配線パターン３３ａ，３３ｄ上に実装する際に行われる半田実装作業と同一の工程で行うことができる。このため、半導体モジュール３０の製造タクトを短くすることができるとともに、ワイヤボンディングの専用設備が不要になり、半導体モジュール３０の製造コストを安価にすることができる。
　以上、本発明の実施形態について説明してきたが、本発明はこれに限定されずに種々の変更、改良を行うことができる。
　例えば、半導体モジュール３０においてベアチップＦＥＴ３５を用いているが、ベアチップＦＥＴ３５に限らず、ベアチップＩＧＢTなどの他のベアチップトランジスタを用いてもよい。そして、その他のベアチップトランジスタを用いる場合には、銅コネクタにより、ベアチップトランジスタの上面に形成された電極上と複数の配線パターンのうちベアチップトランジスタが接続された配線パターン以外の他の配線パターン上とを半田を介して接続すればよい。これにより、ベアチップトランジスタの電極と基板上の配線パターンとの接続をベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で行うことができる。
　そして、ベアチップトランジスタとしてベアチップＩＧＢＴを用いる場合、ベアチップＩＧＢＴ上に形成されたエミッタ電極及びゲート電極を、それぞれ、銅コネクタを用いて基板上の配線パターンに半田を介して接続することが好ましい。
　このように、ベアチップＩＧＢＴを用い、ベアチップＩＧＢＴ上に形成されたエミッタ電極及びゲート電極を、それぞれ、銅コネクタを用いて基板上の配線パターンに半田を介して接続する場合には、ベアチップＩＧＢＴのエミッタ電極と基板上の配線パターンとの接続及びベアチップＩＧＢＴのゲート電極と基板上の別の配線パターンとの接続をベアチップＩＧＢＴやその他の表面実装部品を基板上の配線パターン上に実装する際に行われる半田実装作業と同一の工程で行うことができる。
　また、ベアチップＦＥＴ３５の上面に形成されたソース電極Ｓは、長方形状に形成されているが、正方形状で形成してもよい。この場合、ソース電極Ｓに接続される第１ソース電極用コネクタ３６ａ１及び第２ソース電極用銅コネクタ３６ａ２の形状を同一にして共通化することができる。
　なお、図４に示す半導体モジュール３０において、ａ相出力ライン９１ａ、ｂ相出力ライン９１ｂ、及びｃ相出力ライン９１ｃには、ジャンパー線として共通の銅コネクタ３６ｃが用いられている。これにより、ａ相出力ライン９１ａ、ｂ相出力ライン９１ｂ、及びｃ相出力ライン９１ｃの径路の長さを同一にすることができる。
　１　操向ハンドル
　２　コラム軸
　３　減速ギア３
　４Ａ，４Ｂ　ユニバーサルジョイント
　５　ピニオンラック機構
　６　タイトロッド
　７　トルクセンサ
　８　電動モータ
　９　車速センサ
　１０　コントローラ
　１１　制御演算装置
　１２　ゲート駆動回路
　１３　モータ駆動部
　１４　非常停止用の遮断装置
　１５　電流検出回路
　１６　回転センサ
　１７　ロータ位置検出回路
　１８　ＩＧＮ電圧モニタ部
　１９　電源回路部
　２０　ケース
　２１　半導体モジュール載置部
　２１ａ　ねじ孔
　２２　電力及び信号用コネクタ実装部
　２３　３相出力用コネクタ実装部
　２３ａ　ねじ孔
　２４　取付けポスト
　２４ａ　ねじ孔
　３０　半導体モジュール
　３１　基板
　３１ａ　貫通孔
　３２　絶縁層
　３３ａ～３３ｄ　配線パターン
　３４ａ～３４ｄ　半田
　３５　ベアチップＦＥＴ（ベアチップトランジスタ）
　３６ａ　ソース電極用銅コネクタ
　３６ａ１　第１ソース電極用銅コネクタ
　３６ａ２　第２ソース電極用コネクタ
　３６ｃ　銅コネクタ
　３６ａａ　平板部
　３６ａｂ　接続部
　３６ａｃ　接続部
　３６ａｄ　連結部
　３６ａｅ　連結部
　３６ａｆ　識別用孔
　３６ｂ　ゲート電極用銅コネクタ
　３６ｂａ　平板部
　３６ｂｂ　接続部
　３６ｂｃ　接続部
　３６ｂｄ　連結部
　３６ｂｅ　連結部
　３７　表面実装部品
　３８　取付けねじ
　３９　放熱用シート
　４０　制御回路基板
　４０ａ　貫通孔
　４１　取付けねじ
　５０　電力及び信号用コネクタ
　５１　取付けねじ
　６０　３相出力用コネクタ
　６０ａ　貫通孔
　６１　取付けねじ
　７０　カバー
　８１電源ライン
　８１ａ　正極端子
　８２　接地ライン
　８２ａ　負極端子
　９０　３相出力部
　９１ａ　ａ相出力ライン
　９１ｂ　ｂ相出力ライン
　９１ｃ　ｃ相出力ライン
　Ｇ　ゲート電極（電極）
　Ｓ　ソース電極（電極）

Claims (9)

  1. 　金属製の基板と、該基板の上に形成された絶縁層と、該絶縁層上に形成された複数の配線パターンと、該複数の配線パターンのうち一つの配線パターン上に半田を介して実装されるベアチップトランジスタと、該ベアチップトランジスタの上面に形成された電極と前記複数の配線パターンのうち他の配線パターンとを半田を介して接続するための、銅板で構成される銅コネクタとを備えたことを特徴とする半導体モジュール。
  2. 　前記ベアチップトランジスタが、上面にソース電極及びゲート電極を形成したベアチップＦＥＴであり、前記銅コネクタが、ソース電極用銅コネクタと、ゲート電極用銅コネクタとを備え、前記ベアチップＦＥＴのソース電極上と前記複数の配線パターンのうち他の配線パターン上とを前記ソース電極用銅コネクタで半田を介して接続し、前記ベアチップＦＥＴのゲート電極上と前記複数の配線パターンのうち更に他の配線パターン上とを前記ゲート電極用銅コネクタで半田を介して接続することを特徴とする請求項１記載の半導体モジュール。
  3. 　前記ゲート電極用銅コネクタは１種類であり、前記ソース電極用銅コネクタは、前記ゲート電極用銅コネクタに対して１８０°ストレート配置とする第１ソース電極用銅コネクタと、前記ゲート電極用銅コネクタに対して９０°直角配置とする第２ソース電極用銅コネクタとの２種類であり、１つのベアチップＦＥＴにおいて、前記１種類のゲート電極用銅コネクタと前記２種類の第１ソース電極用銅コネクタ及び第２ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用することを特徴とする請求項２記載の半導体モジュール。
  4. 　前記ベアチップＦＥＴの上面に形成された前記ゲート電極と前記ソース電極とが直列にストレート配置され、前記ソース電極は長方形状に形成されていることを特徴とする請求項３記載の半導体モジュール。
  5. 　前記第１ソース電極用銅コネクタは、前記長方形状に形成されたソース電極の短辺が延びる方向に沿って引き出されるとともに、当該ソース電極の短辺及び長辺に沿う短辺及び長辺を有する、前記ソース電極に接続する接続面の面積が前記ソース電極とほぼ同一の面積である接続部を備えたことを特徴とする請求項４記載の半導体モジュール。
  6. 　前記第２ソース電極用銅コネクタは、前記長方形状に形成されたソース電極の長辺が延びる方向に沿って引き出されるとともに、当該ソース電極の長辺及び短辺に沿う長辺及び短辺を有する、前記ソース電極に接続する接続面の面積が前記ソース電極とほぼ同一の面積である接続部を備えたことを特徴とする請求項４又は５記載の半導体モジュール。
  7. 　金属製の基板上に絶縁層を形成する工程と、
    　該絶縁層上に複数の配線パターンを形成する工程と、
    　該複数の配線パターン上に半田ペーストを塗布する工程と、
    　前記複数の配線パターンのうち一つの配線パターン上に塗布された半田ペースト上にベアチップトランジスタを搭載する工程と、
    　前記ベアチップトランジスタの上面に形成された電極上に半田ペーストを塗布する工程と、
    　前記ベアチップトランジスタの電極上に塗布された半田ペースト上及び前記複数の配線パターンのうち他の配線パターン上に塗布された半田ペースト上に、銅板で構成される銅コネクタを搭載して半導体モジュール中間組立体を構成する工程と、
    　該半導体モジュール中間組立体をリフロー炉に入れて、前記複数の配線パターンのうち一つの配線パターンと前記ベアチップトランジスタとの半田を介しての接合、前記ベアチップトランジスタの上面に形成された電極と前記銅コネクタとの半田を介しての接合、及び前記複数の配線パターンのうち他の配線パターンと前記銅コネクタとの半田を介しての接合を行う工程とを含むことを特徴とする半導体モジュールの製造方法。
  8. 　前記ベアチップトランジスタが、上面にソース電極及びゲート電極を形成したベアチップＦＥＴであり、前記銅コネクタが、ソース電極用銅コネクタと、ゲート電極用銅コネクタとを備えており、
    　金属製の前記基板上に前記絶縁層を形成する工程と、
    　該絶縁層上に複数の配線パターンを形成する工程と、
    　該複数の配線パターン上に半田ペーストを塗布する工程と、
    　前記複数の配線パターンのうち一つの配線パターン上に塗布された半田ペースト上に前記ベアチップＦＥＴを搭載する工程と、
    　前記ベアチップＦＥＴの上面に形成されたソース電極及びゲート電極上に半田ペーストを塗布する工程と、
    　前記ベアチップＦＥＴのソース電極上に塗布された半田ペースト上及び前記複数の配線パターンのうち他の配線パターン上に塗布された半田ペースト上に、前記ソース電極用銅コネクタを搭載する工程と、
    　前記ベアチップＦＥＴのゲート電極上に塗布された半田ペースト上及び前記複数の配線パターンのうち更に他の配線パターン上に塗布された半田ペースト上に、前記ゲート電極用銅コネクタを搭載して半導体モジュール中間組立体を構成する工程と、
    　該半導体モジュール中間組立体をリフロー炉に入れて、前記複数の配線パターンのうち一つの配線パターンと前記ベアチップＦＥＴとの半田を介しての接合、前記ベアチップＦＥＴの上面に形成されたソース電極と前記ソース電極用銅コネクタとの半田を介しての接合、前記複数の配線パターンのうち他の配線パターンと前記ソース電極用銅コネクタとの半田を介しての接合、前記ベアチップＦＥＴの上面に形成されたゲート電極と前記ゲート電極用銅コネクタとの半田を介しての接合、及び前記複数の配線パターンのうち更に他の配線パターンと前記ゲート電極用銅コネクタとの半田を介しての接合を行う工程とを含むことを特徴とする請求項７記載の半導体モジュールの製造方法。
  9. 　前記ゲート電極用銅コネクタは１種類であり、前記ソース電極用銅コネクタは、前記ゲート電極用銅コネクタに対して１８０°ストレート配置とする第１ソース電極用銅コネクタと、前記ゲート電極用銅コネクタに対して９０°直角配置とする第２ソース電極用銅コネクタとの２種類であり、１つのベアチップＦＥＴにおいて、前記１種類のゲート電極用銅コネクタと前記２種類の第１ソース電極用銅コネクタ及び第２ソース電極用銅コネクタのうちから選択されたいずれか一方のソース電極用銅コネクタとを組み合わせて使用することを特徴とする請求項８記載の半導体モジュールの製造方法。
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