WO2013174177A1 - 高压bcd工艺中高压器件的隔离结构及其制造方法 - Google Patents

高压bcd工艺中高压器件的隔离结构及其制造方法 Download PDF

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WO2013174177A1
WO2013174177A1 PCT/CN2013/073437 CN2013073437W WO2013174177A1 WO 2013174177 A1 WO2013174177 A1 WO 2013174177A1 CN 2013073437 W CN2013073437 W CN 2013073437W WO 2013174177 A1 WO2013174177 A1 WO 2013174177A1
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Prior art keywords
voltage
isolation
epitaxial layer
layer
type
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PCT/CN2013/073437
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English (en)
French (fr)
Inventor
闻永祥
张邵华
江宇雷
孙样慧
俞国强
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杭州士兰集成电路有限公司
杭州士兰微电子股份有限公司
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Priority to US14/403,405 priority Critical patent/US9824913B2/en
Publication of WO2013174177A1 publication Critical patent/WO2013174177A1/zh
Priority to US15/726,854 priority patent/US10770340B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology

Definitions

  • the present invention relates to an isolation structure of a high voltage device in a high voltage BCD process and a method of fabricating the same, and more particularly to an isolation structure of a high voltage device in a high voltage BCD process of the order of 1200V and a method of fabricating the same.
  • the BCD process is a monolithic integrated process technology that enables Bipolar, CMOS, and DMOS devices to be fabricated on the same chip, referred to as the BCD process. Since the BCD process combines the advantages of each of the above three devices, this makes the BCD process the mainstream process technology for integrated circuits. BCD process technology has been developed for many years and there are many mature process solutions. The BCD process can select different devices for different circuits to optimize the corresponding electronic circuit devices, achieving low power consumption, high integration, high speed, and high drive capability of the entire circuit. The BCD process is an excellent choice for IC manufacturing processes such as power management, display drivers, automotive electronics, etc., and has broad market prospects.
  • the high-voltage integrated circuit used in the three-phase AC 380V or 440V, 480V power supply variable frequency motor drive circuit is the 1200V high voltage BCD process product.
  • the technical problem to be solved by the present invention is to provide an isolation structure of a high voltage device in a high voltage BCD process and a manufacturing method thereof, so that an epitaxial island of a BCD high voltage device can be effectively isolated, and a device such as an LDM0S transistor in a BCD process can be improved.
  • Breakdown voltage, and at the minimum field oxide thickness, the parasitic turn-on voltage of the high-voltage device aluminum wiring and silicon surface can reach 1200V or more, thereby improving the entire high-voltage BCD
  • the flatness of the step of the oxide surface of the process silicon improves the reliability of the product.
  • the present invention provides an isolation structure of a high voltage device in a high voltage BCD process, including:
  • a field oxide layer is located on the isolation region.
  • the high voltage device is completely depleted of the epitaxial island charge of the isolation region and the high voltage device during breakdown, and the epitaxial island refers to an epitaxial layer between adjacent isolation regions.
  • the field oxide layer has a thickness of 600 (Tl 8000 A).
  • the epitaxial layer is a stacked structure.
  • the epitaxial layer is a two-layer stacked structure including a first epitaxial layer and a second epitaxial layer.
  • the thickness of the first epitaxial layer 3. ( ⁇ 5 0 ⁇ , resistance was 1. ( ⁇ 10 ⁇ ⁇ ( ⁇ ;. .
  • the thickness of the second epitaxial layer 3. (T15 ⁇ , the resistivity of 1. 0 ⁇ 4. 0 ⁇ ⁇ .
  • the first miscellaneous type is a ⁇ type
  • the second miscellaneous type is a ⁇ type
  • the isolation structure further includes:
  • the present invention also provides a method of fabricating an isolation structure for a high voltage device in a high voltage BCD process, comprising: providing a semiconductor substrate having a first miscellaneous type;
  • an epitaxial layer having a second miscellaneous type on the semiconductor layer Forming an epitaxial layer having a second miscellaneous type on the semiconductor layer, and forming an isolation region having a first impurity type in the epitaxial layer, the isolation layer penetrating through the epitaxial layer and extending to the semiconductor In the substrate, the impurity concentration of the isolation region is of the same order of magnitude as the impurity concentration of the epitaxial layer, and the first miscellaneous type is opposite to the second miscellaneous type;
  • a field oxide layer is formed on the isolation region.
  • the field oxide layer has a thickness of 600 (Tl 8000 A).
  • the epitaxial layer is a stacked structure.
  • the epitaxial layer is a two-layer stacked structure, and the forming process of the epitaxial layer and the isolation region includes:
  • the ions implanted in the first buried layer are boron ions, and the implantation energy is 6 (T100KeV, and the dose is lE12 ⁇ lE14/cm 2 ) .
  • the implanted ions in the first isolation region are boron ions, and the implantation energy is 6 (T100KeV, and the dose is 1E12 ⁇ 1E14/cm 2 ) .
  • the implanted ions in the second isolation region are boron ions, and the implantation energy is 6 (T100KeV, and the dose is 1E12 ⁇ 1E14/cm 2 ) .
  • the thickness of the first epitaxial layer is 3. ( ⁇ 5. 0 ⁇ , the resistivity is 1. ( ⁇ 10 ⁇ ( ⁇ ; the thickness of the second epitaxial layer is 3. (T15. ⁇ , resistivity is 1. 0 to 4. 0 ⁇ ⁇ .
  • the first miscellaneous type is a ⁇ type
  • the second miscellaneous type is a ⁇ type
  • the method further includes: before forming the field oxide layer:
  • a first cryptic type of ions is positioned using a mask and implanted on the surface of the epitaxial layer to form an isolated surface region, the field oxide layer being located on the isolated surface region.
  • the ions implanted in the isolation surface region are boron ions, the implantation energy is 25 to 50 KeV, and the dose is 5E13 5E14/cm 2 .
  • the present invention has the following advantages:
  • the isolation The impurity concentration of the region is of the same order of magnitude as that of the epitaxial layer, so that the concentration of the epitaxial island between the isolation regions is close to the equilibrium state, and the epitaxial island charge of the isolation region and the high voltage device is close to the high voltage breakdown of the device.
  • the impurity concentration of the isolation region in the embodiment of the present invention is lower than that of the conventional isolation junction, and the carrier concentration is correspondingly lower, and the charge in the isolation region is nearly depleted when the device is under high voltage breakdown, by the MOS capacitor.
  • the thickness of the oxide layer of the MOS capacitor is thinner at the same turn-on voltage.
  • the isolation structure can still withstand the parasitic breakdown voltage of 1200V, thereby improving the flatness of the silicon oxide surface step of the high-voltage BCD process and improving the reliability of the product.
  • the isolation structure in the embodiment of the present invention is formed in a plurality of times in the longitudinal direction, and is formed by a buried layer in the semiconductor substrate and an isolation region in the plurality of epitaxial layers, which can reduce the lateral diffusion size of the isolation region. Save layout area.
  • a P-type impurity isolation surface region may be formed under the field oxide layer to prevent the boron absorption during the formation of the field oxide layer, thereby reducing the surface impurity concentration of the isolation structure and causing the isolation structure. Leakage phenomenon. DRAWINGS
  • FIG. 1 is a flow chart showing a method of manufacturing an isolation structure of a high voltage device in a high voltage BCD process according to an embodiment of the present invention
  • 2 to 8 are schematic cross-sectional structural views corresponding to respective steps in the manufacturing method of the isolation structure of the high voltage device in the high voltage BCD process according to the embodiment of the present invention. detailed description
  • FIG. 1 is a flow chart showing a method of manufacturing an isolation structure of a high voltage device in the high voltage BCD process of the present embodiment, including:
  • Step S l l providing a semiconductor substrate having a first miscellaneous type
  • Step S12 forming an epitaxial layer having a second miscellaneous type on the semiconductor layer, and in the An isolation region having a first miscellaneous type is formed in the epitaxial layer, the isolation layer penetrating through the epitaxial layer and extending into the semiconductor substrate, the impurity concentration of the isolation region and the impurity concentration of the epitaxial layer
  • the first miscellaneous type is opposite to the second miscellaneous type
  • Step S13 forming a field oxide layer on the isolation region.
  • the first miscellaneous type is one of P type and N type miscellaneous
  • the second miscellaneous type is another one of P type and N type.
  • the first miscellaneous type is P type
  • the first type The second type is N type, but those skilled in the art should understand that the above two types of miscellaneous types can be interchanged.
  • a P-type semiconductor substrate 10 is provided in which a P-type first buried layer 12 and an N-type second buried layer 11 are formed.
  • the thickness of the oxide layer of the initial oxidation is 0. 2 ⁇ 0. 6 ⁇ m is optional, for example, the semiconductor substrate 10 may be a ⁇ 100> crystal orientation silicon substrate, a resistivity of ⁇ ⁇ -cm.
  • the forming process of the first buried layer 12 and the second buried layer 11 may include: locating a region of the second buried layer 11 of the ruthenium type with a photolithographic plate, and then performing ion implantation, and the implanted ions may be, for example, erbium ions, implanted
  • the implanted ions may be, for example, erbium ions, implanted
  • the energy is 60 keV
  • the dose is selected between lE15 and 2E15/cm 2
  • the annealing temperature is 120 (optional between Tl 250 ° C, the time is between 0. 5 ⁇ 2H
  • the region of the P-type first buried layer 12 is located, and then ion implantation is performed.
  • the implanted ions may be, for example, boron ions, and the implantation energy is 6 (Tl00KeV, and the dose is selected between lE12 and lE14/cm 2 , and then performed.
  • Annealing, annealing temperature is 100 (optional between Tl l00 ° C, time between 0. 5 ⁇ 2H optional.
  • P type miscellaneous first buried layer 12 as the first layer of the isolation zone.
  • an N-type impurity first epitaxial layer 13 is grown on the semiconductor substrate 10 to cover the first buried layer 12 and the second buried layer 11. Specifically, before the first epitaxial layer 13 is formed, it can be cleaned with 1:1 (Tl: 20 HF acid, and then the first epitaxial layer 13 is grown to have a thickness of 3. ( ⁇ 5. 0 ⁇ , resistivity is 1 ⁇ )
  • the first epitaxial layer 13 is ion-implanted to form a first impurity-type first isolation region 14 as a second layer of the isolation region.
  • the method comprises the following steps: growing a thin oxide layer and selecting a thickness between 300 ⁇ and 600 ; then, using the photolithography plate to position the first isolation region 14 and performing ion implantation, the implanted ions may be, for example, boron ions, and the implantation energy is 6 (T ⁇ 100KeV, the dose is lE12 ⁇ lE14/cm 2 , after which The annealing temperature is 100 (optional between Tll00 °C, and the time is between 0. 5 ⁇ 2H).
  • an N-type impurity second epitaxial layer 15 is grown on the first epitaxial layer 13. Specifically, the thickness of the second epitaxial layer 15 is increased by a method of epitaxial growth or the like, and the thickness is 3. ( ⁇ 5. 0 ⁇ , The resistivity is 1. 0 ⁇ 4. ⁇ -cm o
  • the second epitaxial layer 15 is ion-implanted, and a second impurity-type isolation region 16 is formed therein as a third layer of the isolation region.
  • the method may include: growing a thin oxide layer and selecting a thickness between 300 ⁇ and 600 ;; then locating the region of the second isolation region 16 with a lithography plate and performing ion implantation, and the implanted ions may be, for example, boron ions, and the implanted ions may be, for example, boron ions, and the implantation energy is 6 (Tl00KeV, the dose is lE12 ⁇ lE14/cm 2 optional, after annealing, the annealing temperature is 100 (optional between Tll00 °C, the time is between 0.
  • the annealed and quarantined isolation region (including the first isolation)
  • the doping concentration of the region 14 and the second isolation region 16 is the same order of magnitude as the first epitaxial layer 13 and the second epitaxial layer 15.
  • a pad oxide layer (the material of which may be S i0 2 ) 101 is grown on the second epitaxial layer 15, and a selective oxidizing dielectric layer (the material may be SiN) 102 is formed on the pad oxide layer 101, and the pad oxide layer 101 is formed.
  • the thickness of the layer is selected between 25CT400A, and the thickness of the oxidized dielectric layer 102 is selected to be 100 ( ⁇ 50 ⁇ ); then the active region lithography plate is used to locate the oxidation region, and the selective oxidation region is etched by dry etching or the like. .
  • the isolation mask is ion-implanted by using the photoresist and the selective oxide dielectric layer 102 as a masking layer to form a germanium-type isolation surface region 17, and the implanted ions may be boron.
  • the ion, the implantation energy is 25 to 50 KeV, and the dose is 5E13 to 5E14/cm 2 .
  • the isolation surface region 17 can serve as the fourth layer of the isolation region.
  • a field oxide layer 18 is formed on the isolation surface region 17, which may be formed by selective oxidation of silicon (L0C0S) having a thickness of 600 (Tl8000A) and also annealing of the implantation of the isolation surface region 17.
  • the first isolation region 14 and the second isolation region 16 are all cumbersome, and the surface impurity concentration of the isolation structure is reduced in order to prevent the boron absorbing effect of the field oxide layer 18 from being formed.
  • An isolation surface region 17 may be formed under the field oxide layer 18 to increase its cumbersome concentration. If the first If the isolation region 14 and the second isolation region 16 are N-type, the isolation surface region 17 is not required to be formed, and the field oxide layer 18 is directly formed on the second isolation region 16.
  • the isolation structure formed in this embodiment is as shown in FIG. 8, and includes: a P-type impurity substrate; an N-type impurity epitaxial layer (in this embodiment, the first epitaxial layer 13 and the first layer are stacked)
  • the second epitaxial layer 15) is located on the semiconductor substrate 10; the P-type impurity isolation region (including the isolation surface region 17, the second isolation region 16, the first isolation region 14, and the first buried layer 12 in this embodiment), Throughout the entire epitaxial layer and extending into the semiconductor substrate 10, the impurity concentration of the isolation region is of the same order of magnitude as the impurity concentration of the epitaxial layer; the field oxide layer 18 is located on the isolation region, specifically in the isolation surface region in this embodiment. Above 17.
  • the epitaxial island charge where the isolation region and the high voltage device are located is completely depleted, and the epitaxial island refers to the epitaxial layer between adjacent isolation regions. It should be noted that the complete depletion of charge includes a near-depletion condition within the error tolerance.
  • the first epitaxial layer 13 and the second epitaxial layer 15 together constitute a stacked epitaxial layer, and a first buried layer 12 is formed in the semiconductor substrate, and is formed therein after forming each epitaxial layer.
  • the ion implantation forms a corresponding isolation region, and then is annealed and pushed to diffuse, so that the isolation region in each epitaxial layer and the first buried layer 12 are connected to form a complete isolation region.
  • the number of laminates in the epitaxial layer is not limited to two layers, and may be, for example, one layer, three layers, or the like.
  • the technical solution of the embodiment can realize the LDM0S transistor of the order of 1200V and the isolation structure of the high voltage to the integrated level of 1200V, and is suitable for the high voltage BCD process of 1200V or more.
  • the isolation region is formed by two epitaxy and two ion implantations, which can reduce the lateral diffusion size and save the layout area.
  • the formation of the isolation surface region can prevent the boron absorption during the growth of the field oxide layer, so that the impurity concentration on the surface of the isolation region is changed. The light leakage caused by the isolation structure.
  • the impurity concentration of the isolation region and the impurity concentration of the epitaxial island can be adjusted to be close to equilibrium by the process.
  • the isolation region and the epitaxial island charge of the high voltage device are nearly completely depleted, so that the high voltage device on the epitaxial island
  • the breakdown point occurs on the longitudinal epitaxial junction, thus increasing the breakdown voltage of the 1200V high voltage LDM0S transistor.
  • the impurity concentration of the entire isolation region is smaller than that of the conventional isolation structure, the carrier concentration is also small, and the charge in the isolation region is nearly exhausted when the device is under high voltage breakdown. It is known from the M0S capacitor CV theory that when the current is carried When the sub-concentration is small, the oxide thickness of the MOS capacitor can be made at the same turn-on voltage. Thinner, on the 1200V high-voltage BCD isolation structure, that is, the thickness of the field oxide layer under the aluminum wiring of the high-voltage device can be small, the isolation region can still withstand the parasitic breakdown withstand voltage of 1200V, thereby improving the oxidation of the silicon surface of the entire high-voltage BCD process. The flattening of the steps improves the reliability of the product.

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Abstract

一种高压BCD工艺中高压器件的隔离结构及其制造方法，所述隔离结构包括：具有第一掺杂类型的半导体衬底（10）；具有第二掺杂类型的外延层（13，15），所述第一掺杂类型和第二掺杂类型相反；具有第一掺杂类型的隔离区，贯穿所述外延层并延伸至所述半导体衬底内，所述隔离区的掺杂浓度与所述外延层的掺杂浓度为同一数量级；场氧化层（18），位于所述隔离区上。该结构能使BCD高压器件所在外延岛得到有效隔离，提高BCD工艺中高压器件的击穿电压，而且在最小场氧化层的厚度下，使高压器件铝布线和硅表面的寄生开启电压可以达到1200V以上，从而改善整个高压BCD工艺硅表面氧化层台阶的平坦度，提高产品的可靠性。

Description

高压 BCD工艺中高压器件的隔离结构及其制造方法 技术领域
本发明涉及一种高压 BCD工艺中高压器件的隔离结构及其制造方法， 尤其涉 及一种 1200V量级的高压 BCD工艺中高压器件的隔离结构及其制造方法。 背景技术
BCD工艺是一种单片集成工艺技术，这种技术能够在同一芯片上制作 Bipolar、 CMOS和 DMOS器件， 简称为 BCD工艺。 由于 BCD工艺综合了以上三种器件各自的优 点， 这使 BCD工艺成为集成电路的主流工艺技术。 BCD工艺技术已经发展了多年， 有许多成熟的工艺方案。 BCD工艺可以对于不同的电路选择不同的器件来达到相应 电子电路器件的最优化， 实现整个电路的低功耗、 高集成度、 高速度、 高驱动能力 的要求。 BCD工艺是电源管理、 显示驱动、 汽车电子等 IC制造工艺的上佳选择， 具有广阔的市场前景。
随着国家节能降耗力度的加大， 大功率半导体分立器件产业保持着持续、 快 速、稳定的发展， 产业规模不断壮大， 以高压集成电路为核心高压功率开关器件的 电力电子功率模块和组件获得了越来越广泛的应用， 现正沿着高电压、 高功率、 高 密度三个不同研究方向发展。其中应用于三相交流 380V或 440V、 480V供电的变频 电机驱动回路中的高压集成电路， 就是采用 1200V高压 BCD工艺产品。 对于 1200V 高电压 BCD工艺， 除了关键的 1200V高压 LDM0S器件的开发外，还必须开发具有能 使这些高压器件所在外延岛能得到有效隔离的隔离结构， 同时，还必须考虑到这些 高压器件铝布线上的高压对硅表面所引起的寄生效应，如 1200V器件铝布线和硅表 面的寄生开启电压也必须大于 1200V。 发明内容
本发明要解决的技术问题是提供一种高压 BCD工艺中高压器件的隔离结构及 其制造方法，使 BCD高压器件所在外延岛能得到有效隔离， 并提高 BCD工艺中高压 器件如 LDM0S晶体管等器件的击穿电压，而且在最小场氧化层的厚度下，使高压器 件铝布线和硅表面的寄生开启电压可以达到 1200V 以上， 从而改善整个高压 BCD 工艺硅表面氧化层台阶的平坦度， 提高产品的可靠性。
为解决上述技术问题， 本发明提供了一种高压 BCD工艺中高压器件的隔离结 构， 包括：
具有第一惨杂类型的半导体衬底；
具有第二惨杂类型的外延层， 位于所述半导体衬底上， 所述第一惨杂类型和 第二惨杂类型相反；
具有第一惨杂类型的隔离区， 贯穿所述外延层并延伸至所述半导体衬底内， 所述隔离区的惨杂浓度与所述外延层的惨杂浓度为同一数量级；
场氧化层， 位于所述隔离区上。
可选地， 所述高压器件在击穿时所述隔离区和所述高压器件所在的外延岛电 荷完全耗尽， 所述外延岛指的是相邻隔离区之间的外延层。
可选地， 所述场氧化层的厚度为 600(Tl8000A。
可选地， 所述外延层为叠层结构。
可选地， 所述外延层为 2层的叠层结构， 包括相叠的第一外延层和第二外延 层。
可选地， 所述第一外延层的厚度为 3. (Γΐ5. 0μπι， 电阻率为 1. (Γ10Ω·( Π; 所述 第二外延层的厚度为 3. (T15. Ομπι, 电阻率为 1. 0〜4. 0Ω· τι。
可选地， 所述第一惨杂类型为 Ρ型， 第二惨杂类型为 Ν型。
可选地， 所述隔离结构还包括：
具有第一惨杂类型的隔离表面区， 位于所述场氧化层下的外延层表面。
本发明还提供了一种高压 BCD工艺中高压器件的隔离结构的制造方法， 包括： 提供具有第一惨杂类型的半导体衬底；
在所述半导体层上形成具有第二惨杂类型的外延层， 并在所述外延层中形成 具有第一惨杂类型的隔离区，所述隔离层贯穿所述外延层并延伸至所述半导体衬底 内，所述隔离区的惨杂浓度与所述外延层的惨杂浓度为同一数量级，所述第一惨杂 类型与第二惨杂类型相反；
在所述隔离区上形成场氧化层。
可选地， 所述场氧化层的厚度为 600(Tl8000A。
可选地， 所述外延层为叠层结构。 可选地， 所述外延层为 2层的叠层结构， 所述外延层和隔离区的形成过程包 括：
对所述半导体衬底进行离子注入， 在其中形成具有第一惨杂类型的第一埋层 和具有第二惨杂类型的第二埋层；
在所述半导体衬底上生长第一外延层， 覆盖所述第一埋层和第二埋层； 使用光刻版定位并在所述第一外延层中注入第一惨杂类型的离子， 以形成第 一隔离区；
对所述第一隔离区进行退火；
在所述第一外延层上生长第二外延层；
使用光刻版定位并在所述第二外延层中注入第一惨杂类型的离子， 以形成第 二隔离区；
对所述第二个隔离区进行退火， 使所述第二隔离区、 第一隔离区和第一埋层 相接形成所述隔离区。
可选地， 所述第一埋层中注入的离子为硼离子， 注入能量为 6(Tl00KeV， 剂量 为 lE12〜lE14/cm2。
可选地， 所述第一隔离区中注入的离子为硼离子， 注入能量为 6(Tl00KeV， 剂 量为 lE12〜lE14/cm2。
可选地， 所述第二隔离区中注入的离子为硼离子， 注入能量为 6(Tl00KeV， 剂 量为 lE12〜lE14/cm2。
可选地， 第一外延层的厚度为 3. (Γΐ5. 0μπι， 电阻率为 1. (Γ10Ω·( Π; 所述第二 外延层的厚度为 3. (T15. Ομπι, 电阻率为 1. 0〜4. 0Ω· τι。
可选地， 所述第一惨杂类型为 Ρ型， 第二惨杂类型为 Ν型。
可选地， 在形成所述场氧化层之前所述方法还包括：
使用掩模板定位并在所述外延层表面注入第一惨杂类型的离子， 以形成隔离 表面区， 所述场氧化层位于所述隔离表面区上。
可选地， 所述隔离表面区中注入的离子为硼离子， 注入能量为 25〜50KeV， 剂 量为 5E13〜5E14/cm2。
与现有技术相比， 本发明具有以下优点：
本发明实施例的高压 BCD工艺中高压器件的隔离结构及其制造方法中， 隔离 区的惨杂浓度与外延层的惨杂浓度为同一数量级，使得隔离区之间的外延岛的浓度 与隔离区接近平衡状态，在器件高压击穿时隔离区和高压器件所在的外延岛电荷接 近完全耗尽，使得外延岛上的高压器件击穿点发生在纵向外延结面上， 因此可以提 高诸如 LDM0S晶体管等器件的击穿电压。
进一步地， 本发明实施例中的隔离区的惨杂浓度比常规隔离结浓度低， 载流 子浓度相应也较低，而且在器件高压击穿时隔离区中的电荷接近耗尽， 由 M0S电容 CV理论可知， 当载流子浓度较小时， 在相同开启电压下， M0S电容的氧化层厚度较 薄，例如在 1200V量级高压 BCD工艺中， 高压器件铝布线下的场氧化层厚度可以较 小， 隔离结构仍然能够承受 1200V的寄生击穿耐压，从而改善整个高压 BCD工艺硅 表面氧化层台阶的平坦度， 提高产品的可靠性。
另外， 本发明实施例中的隔离结构在纵向分多次形成， 由位于半导体衬底中 的埋层、 多个外延层中的隔离区域相接而成， 可以减小隔离区的横向扩散尺寸， 节 省版图面积。此外， 对于 P型惨杂的隔离区， 在场氧化层下方还可以形成 P型惨杂 的隔离表面区，防止在形成场氧化层时的吸硼作用使得隔离结构的表面杂质浓度降 低而导致隔离结构的漏电现象。 附图说明
图 1是本发明实施例的高压 BCD工艺中高压器件的隔离结构的制造方法的流 程示意图；
图 2至图 8是本发明实施例的高压 BCD工艺中高压器件的隔离结构的制造方 法中各步骤对应的剖面结构示意图。 具体实施方式
下面结合具体实施例和附图对本发明作进一步说明， 但不应以此限制本发 明的保护范围。
图 1示出了本实施例的高压 BCD工艺中高压器件的隔离结构的制造方法的 流程示意图， 包括：
步骤 S l l， 提供具有第一惨杂类型的半导体衬底；
步骤 S 12， 在所述半导体层上形成具有第二惨杂类型的外延层， 并在所述 外延层中形成具有第一惨杂类型的隔离区， 所述隔离层贯穿所述外延层并延伸 至所述半导体衬底内， 所述隔离区的惨杂浓度与所述外延层的惨杂浓度为同一 数量级， 所述第一惨杂类型与第二惨杂类型相反；
步骤 S13， 在所述隔离区上形成场氧化层。
其中第一惨杂类型是 P型和 N型惨杂中的一种， 第二惨杂类型为 P型和 N 型中的另一种， 本实施例中第一惨杂类型为 P型， 第二惨杂类型为 N型， 但本 领域技术人员应当理解， 上述两种惨杂类型可以互换。
下面结合图 1和图 2至图 8对本实施例的高压 BCD工艺中高压器件的隔离 结构的制造方法进行详细说明。
首先参考图 2， 提供 P型惨杂的半导体衬底 10， 在其中形成 P型惨杂的第 一埋层 12和 N型惨杂的第二埋层 11。
其中， 半导体衬底 10 例如可以是 <100>晶向的硅衬底， 电阻率为 ΙΟ^ΟΟΩ-cm, 初始氧化的氧化层厚度为 0. 2〜0. 6μ米之间可选。
第一埋层 12和第二埋层 11的形成过程可以包括： 用光刻版定位出 Ν型惨 杂的第二埋层 11 的区域， 之后进行离子注入， 注入离子例如可以为锑离子， 注入能量为 60KeV， 剂量在 lE15〜2E15/cm2之间可选， 之后进行退火， 退火温度 为 120(Tl250°C之间可选， 时间在 0. 5〜2H之间可选； 用光刻版定位出 P型惨杂 的第一埋层 12 的区域， 之后进行离子注入， 注入离子例如可以是硼离子， 注 入能量为 6(Tl00KeV， 剂量在 lE12〜lE14/cm2之间可选， 之后进行退火， 退火温 度为 100(Tl l00°C之间可选， 时间在 0. 5〜2H之间可选。 其中， P型惨杂的第一 埋层 12作为隔离区的第一层。
参考图 3， 在半导体衬底 10上生长 N型惨杂的第一外延层 13， 覆盖第一 埋层 12和第二埋层 11。具体包括：在形成第一外延层 13之前，可以用 1 : l(Tl : 20的 HF酸进行清洗， 然后生长第一外延层 13， 其厚度为 3. (Γΐ5. 0μπι， 电阻率 为 1·
Figure imgf000007_0001
参考图 4， 对第一外延层 13进行离子注入， 形成 Ρ型惨杂的第一隔离区 14， 作为隔离区的第二层。 具体包括： 生长薄氧化层， 厚度为 300Α至 600Α之 间可选； 之后使用光刻版定位第一隔离区 14 并进行离子注入， 注入的离子例 如可以是硼离子， 注入能量为 6(T〜100KeV， 剂量为 lE12〜lE14/cm2， 之后进行 退火， 退火温度为 100(Tll00°C之间可选， 时间为 0. 5〜2H之间可选。
参考图 5， 在第一外延层 13上生长 N型惨杂的第二外延层 15。 具体可以 包括： 在生长第二外延层 15之前， 使用 1 : l(Tl : 20的 HF酸进行清洗， 然后 使用外延生长等方法生长第二外延层 15， 其厚度为 3. (Γΐ5. 0μπι， 电阻率为 1. 0^4. ΟΩ-cm o
参考图 6， 对第二外延层 15进行离子注入， 在其中形成 Ρ型惨杂的第二隔 离区 16， 作为隔离区的第三层。 具体可以包括： 生长薄氧化层， 厚度为 300Α〜600Α之间可选； 之后用光刻版定位第二隔离区 16 的区域并进行离子注 入， 注入的离子例如可以是硼离子， 注入能量为 6(Tl00KeV， 剂量为 lE12〜lE14/cm2可选， 之后进行退火， 退火温度为 100(Tll00°C之间可选， 时间 在 0. 5〜2H 之间可选， 然后继续在温度为 120CTC的氮气和氧气气氛下各退火 2〜8H， 使得第二隔离区 16、 第一隔离区 14扩散相接形成隔离区并与第一埋层 12接触。 退火推结后的隔离区 （包括第一隔离区 14、 第二隔离区 16 ) 的惨杂 浓度与第一外延层 13和第二外延层 15为同一数量级。
参考图 7， 在第二外延层 15上生长垫氧化层 （其材料可以是 S i02 ) 101， 在垫氧化层 101 上形成选择氧化介质层 （其材料可以是 SiN) 102， 垫氧化层 101的厚度为 25CT400A之间可选， 选择氧化介质层 102的厚度为 100(Γΐ50θΑ 之间可选； 之后使用有源区光刻版定位氧化区， 并用干法刻蚀等方法刻蚀出选 择氧化区。
之后使用隔离掩模板进行光刻， 用光刻胶和选择氧化介质层 102作为掩蔽 层， 对第二外延层 15表面进行离子注入， 形成 Ρ型惨杂的隔离表面区 17， 注 入离子可以是硼离子， 注入能量为 25〜50KeV， 剂量为 5E13〜5E14/cm2。 其中， 隔离表面区 17可以作为隔离区的第四层。
之后参考图 8， 在隔离表面区 17上形成场氧化层 18， 其形成方法可以是 硅的选择氧化 （L0C0S ) ， 其厚度为 600(Tl8000A， 同时也完成隔离表面区 17 的注入的退火。
需要说明的是， 本实施例中， 第一隔离区 14、 第二隔离区 16都是 Ρ型惨 杂的， 为了防止形成场氧化层 18 的吸硼作用使得隔离结构的表面惨杂浓度减 小， 可以在场氧化层 18下方形成隔离表面区 17， 以加大其惨杂浓度。 如果第 一隔离区 14、 第二隔离区 16选用 N型惨杂的， 则无需形成隔离表面区 17， 在 第二隔离区 16上直接形成场氧化层 18即可。
之后， 可以按照常规 BCD工艺流程继续制作器件， 例如 LDM0S晶体管等。 至此， 本实施例中所形成的隔离结构如图 8所示， 包括： P型惨杂的衬底； N型惨杂的外延层 （本实施例中包括相叠的第一外延层 13和第二外延层 15 ) ， 位于半导体衬底 10上； P型惨杂的隔离区 （本实施例中包括隔离表面区 17、 第二隔离区 16、 第一隔离区 14、 第一埋层 12 ) ， 贯穿整个外延层并延伸至半 导体衬底 10 内， 该隔离区的惨杂浓度与外延层的惨杂浓度为同一数量级； 场 氧化层 18， 位于隔离区上， 本实施例中具体位于隔离表面区 17之上。
在高压器件击穿时， 隔离区和高压器件所在的外延岛电荷完全耗尽， 其中 外延岛指的是相邻隔离区之间的外延层。 需要说明的是， 电荷完全耗尽包括在 误差允许范围内的接近耗尽的情况。
在本实施例中，第一外延层 13和第二外延层 15共同组成了叠层的外延层， 并且在半导体衬底内形成了第一埋层 12，在形成每一外延层之后在其中进行离 子注入形成相应的隔离区域， 之后经过退火推结扩散， 使得每一外延层中的隔 离区域以及第一埋层 12 相接后形成完整的隔离区。 但是， 本领域技术人员应 当理解， 外延层中叠层的数量并不限于 2层， 例如也可以是 1层、 3层等。
本实施例的技术方案可以实现 1200V量级的 LDM0S晶体管和 1200V量级高 压到集成的隔离结构， 适用于 1200V以上的高压 BCD工艺。 其中隔离区通过两 次外延、 两次离子注入来形成， 可以减小横向扩散尺寸， 节省版图面积， 同时 隔离表面区的形成可以防止生长场氧化层时的吸硼作用使得隔离区表面杂质 浓度变淡而引起的隔离结构漏电现象。
另外， 隔离区的惨杂浓度与外延岛的惨杂浓度可以通过工艺调节接近平衡 状态， 在器件高压击穿时隔离区和高压器件所在外延岛电荷接近完全耗尽， 使 得外延岛上的高压器件击穿点发生在纵向外延结面上， 因此可以提高 1200V高 压 LDM0S晶体管的击穿电压。
此外， 由于整个隔离区的惨杂浓度比常规的隔离结构小，载流子浓度也小， 而且在器件高压击穿时隔离区中的电荷接近耗尽， 由 M0S 电容 CV理论可知， 当载流子浓度较小时， 在相同的开启电压下， M0S 电容的氧化层厚度可以做得 较薄， 在 1200V高压 BCD隔离结构上， 也即高压器件铝布线下的场氧化层的厚 度可以较小， 隔离区仍然能够承受 1200V的寄生击穿耐压， 从而改善整个高压 BCD工艺硅表面氧化层台阶的平坦化， 提高产品的可靠性。
本发明虽然以较佳实施例公开如上， 但其并不是用来限定本发明， 任何本 领域技术人员在不脱离本发明的精神和范围内， 都可以做出可能的变动和修 改， 因此本发明的保护范围应当以本发明权利要求所界定的范围为准。

Claims

权 利 要 求
1. 一种高压 BCD工艺中高压器件的隔离结构， 其特征在于， 包括： 具有第一惨杂类型的半导体衬底；
具有第二惨杂类型的外延层， 位于所述半导体衬底上， 所述第一惨杂类型 和第二惨杂类型相反；
具有第一惨杂类型的隔离区， 贯穿所述外延层并延伸至所述半导体衬底 内， 所述隔离区的惨杂浓度与所述外延层的惨杂浓度为同一数量级； 场氧化层， 位于所述隔离区上。
2.根据权利要求 1所述的高压 BCD工艺中高压器件的隔离结构， 其特征 在于， 所述高压器件在击穿时所述隔离区和所述高压器件所在的外延岛电荷完 全耗尽， 所述外延岛指的是相邻隔离区之间的外延层。
3.根据权利要求 1所述的高压 BCD工艺中高压器件的隔离结构， 其特征 在于， 所述场氧化层的厚度为 6000〜18000A。
4.根据权利要求 1或 3所述的高压 BCD工艺中高压器件的隔离结构， 其 特征在于， 所述外延层为叠层结构。
5.根据权利要求 4所述的高压 BCD工艺中高压器件的隔离结构， 其特征 在于， 所述外延层为 2层的叠层结构， 包括相叠的第一外延层和第二外延层。
6.根据权利要求 5所述的高压 BCD工艺中高压器件的隔离结构， 其特征 在于， 所述第一外延层的厚度为 3.0〜15.0μιη， 电阻率为 1.0〜10Ω·οιη; 所述第二 外延层的厚度为 3.0〜15.0μιη， 电阻率为 1.0〜4.0Ω·οιη。
7.根据权利要求 1所述的高压 BCD工艺中高压器件的隔离结构， 其特征 在于， 所述第一惨杂类型为 P型， 第二惨杂类型为 N型。
8.根据权利要求 7所述的高压 BCD工艺中高压器件的隔离结构， 其特征 在于， 还包括：
具有第一惨杂类型的隔离表面区， 位于所述场氧化层下的外延层表面。
9.一种高压 BCD工艺中高压器件的隔离结构的制造方法， 其特征在于， 包括：
提供具有第一惨杂类型的半导体衬底；
在所述半导体层上形成具有第二惨杂类型的外延层， 并在所述外延层中形 成具有第一惨杂类型的隔离区， 所述隔离层贯穿所述外延层并延伸至所述半导 体衬底内， 所述隔离区的惨杂浓度与所述外延层的惨杂浓度为同一数量级， 所 述第一惨杂类型与第二惨杂类型相反；
在所述隔离区上形成场氧化层。
10. 根据权利要求 9所述的高压 BCD工艺中高压器件的隔离结构的制造 方法， 其特征在于， 所述场氧化层的厚度为 6000〜18000A。
11. 根据权利要求 9或 10所述的高压 BCD工艺中高压器件的隔离结构 的制造方法， 其特征在于， 所述外延层为叠层结构。
12. 根据权利要求 11所述的高压 BCD工艺中高压器件的隔离结构的制 造方法， 其特征在于， 所述外延层为 2层的叠层结构， 所述外延层和隔离区的 形成过程包括：
对所述半导体衬底进行离子注入， 在其中形成具有第一惨杂类型的第一埋 层和具有第二惨杂类型的第二埋层；
在所述半导体衬底上生长第一外延层， 覆盖所述第一埋层和第二埋层； 使用光刻版定位并在所述第一外延层中注入第一惨杂类型的离子， 以形成 第一隔离区；
对所述第一隔离区进行退火； 在所述第一外延层上生长第二外延层；
使用光刻版定位并在所述第二外延层中注入第一惨杂类型的离子， 以形成 第二隔离区；
对所述第二个隔离区进行退火， 使所述第二隔离区、 第一隔离区和第一埋 层相接形成所述隔离区。
13. 根据权利要求 12所述的高压 BCD工艺中高压器件的隔离结构的制 造方法， 其特征在于， 所述第一埋层中注入的离子为硼离子， 注入能量为 60〜100KeV， 剂量为 lE12〜lE14/cm2。
14. 根据权利要求 12所述的高压 BCD工艺中高压器件的隔离结构的制 造方法， 其特征在于， 所述第一隔离区中注入的离子为硼离子， 注入能量为 60〜100KeV， 剂量为 lE12〜lE14/cm2。
15. 根据权利要求 12所述的高压 BCD工艺中高压器件的隔离结构的制 造方法， 其特征在于， 所述第二隔离区中注入的离子为硼离子， 注入能量为 60〜100KeV， 剂量为 lE12〜lE14/cm2。
16. 根据权利要求 12所述的高压 BCD工艺中高压器件的隔离结构的制 造方法，其特征在于，第一外延层的厚度为 3.0〜15.0μιη， 电阻率为 1.0〜10Ω·οιη; 所述第二外延层的厚度为 3.0〜15.0μιη， 电阻率为 1.0〜4.0Ω·οιη。
17. 根据权利要求 9所述的高压 BCD工艺中高压器件的隔离结构的制造 方法， 其特征在于， 所述第一惨杂类型为 P型， 第二惨杂类型为 N型。
18. 根据权利要求 17所述的高压 BCD工艺中高压器件的隔离结构的制 造方法， 其特征在于， 在形成所述场氧化层之前还包括：
使用掩模板定位并在所述外延层表面注入第一惨杂类型的离子， 以形成隔 离表面区， 所述场氧化层位于所述隔离表面区上。
19. 根据权利要求 18所述的高压 BCD工艺中高压器件的隔离结构的制 造方法， 其特征在于， 所述隔离表面区中注入的离子为硼离子， 注入能量为 25〜50KeV， 剂量为 5E13〜5E14/cm2。
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