Classifications

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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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  • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
  • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
  • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
  • H01L25/075—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00
  • H01L25/0753—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10H20/00 the devices being arranged next to each other
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  • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
  • H01L25/162—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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  • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
  • H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
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  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
  • H10F39/018—Manufacture or treatment of image sensors covered by group H10F39/12 of hybrid image sensors
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  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
  • H10F39/024—Manufacture or treatment of image sensors covered by group H10F39/12 of coatings or optical elements
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  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/804—Containers or encapsulations
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/806—Optical elements or arrangements associated with the image sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
  • H10F39/80—Constructional details of image sensors
  • H10F39/809—Constructional details of image sensors of hybrid image sensors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F55/00—Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/80—Constructional details
  • H10H20/85—Packages
  • H10H20/855—Optical field-shaping means, e.g. lenses
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
  • H01L2223/544—Marks applied to semiconductor devices or parts
  • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/42—Wire connectors; Manufacturing methods related thereto
  • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
  • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
  • H01L2224/481—Disposition
  • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/11—Device type
  • H01L2924/12—Passive devices, e.g. 2 terminal devices
  • H01L2924/1204—Optical Diode
  • H01L2924/12044—OLED
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
  • H01L2924/151—Die mounting substrate
  • H01L2924/153—Connection portion
  • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
  • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
  • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
  • H10H20/01—Manufacture or treatment
  • H10H20/036—Manufacture or treatment of packages
  • H10H20/0363—Manufacture or treatment of packages of optical field-shaping means

Definitions

• This disclosure relates to the manufacture and assembly of wafer stacks, such as those used, for example, to fabricate opto-electronic modules.
• Optical devices such as cameras and integrated camera optics are sometimes integrated into electronic devices such as mobile phones and computers, among others. Manufacturing active and passive optical and electronic components for such devices on a wafer scale is becoming more attractive. One reason is the ongoing trend to reduce the cost of such devices.
• a wafer scale package, or wafer stack can include multiple wafers stacked along the smallest wafer dimension (i.e., the axial direction) and attached to one another.
• the wafer stack can include substantially identical optical or opto-electronic devices arranged side-by-side.
• various individual components may need to be aligned with one another, and any required alignment may need to be maintained during the assembly process so that the resulting devices operate properly.
• this disclosure describes a method of forming a stack of wafers.
• the method includes providing a sub-stack comprising a first wafer and a second wafer, each of which has a respective upper surface and lower surface.
• the sub-stack includes a first thermally-curable adhesive at an interface between the upper surface of the first wafer and the lower surface of the second wafer.
• the method includes placing a third wafer on the upper surface of the second wafer, the third wafer having an upper surface and a lower surface.
• a second thermally-curable adhesive is present at an interface between the upper surface of the second wafer and the lower surface of the third wafer.
• the method further includes providing ultra-violet (UV) radiation in a direction of the upper surface of the third wafer to cure a UV-curable adhesive in openings in the second wafer and in contact with portions of the third wafer so as to bond the third wafer to the sub-stack at discrete locations. Subsequently, the third wafer and the sub-stack are heated so to cure the first and second thermally-curable adhesives.
• UV ultra-violet
• a wafer stack includes a first, second and third wafers, each of which has a respective upper surface and lower surface.
• a first thermally-cured adhesive is at an interface between the upper surface of the first wafer and the lower surface of the second wafer, and a second thermally-cured adhesive is at an interface between the upper surface of the second wafer and the lower surface of the third wafer.
• UV-cured adhesive is disposed in the second wafer at discrete locations near the second wafer's periphery and is in contact with portions of the second and third wafers.
• pre-curing the UV-curable adhesive material at selected locations distributed over the surface of the wafers prior to removing the wafer stack from one location can reduce the likelihood that misalignment between the wafers will occur, for example, when the stack subsequently is transferred to a second location (e.g., an oven) for thermal curing.
• the disclosed techniques for forming a wafer stack can, in some implementations, be faster, more accurate and less expensive than forming the wafer stack using a bond aligner.
• FIG 1 is a cross-sectional view of wafers for forming a wafer stack for manufacturing multiple modules.
• FIG 2 is a cross-sectional view of a wafer stack for manufacturing multiple modules.
• FIG 3 is a cross-sectional view of an opto-electronic module.
• FIG 4 is a flow chart of a method of fabricating a wafer stack.
• FIG 5 illustrates a pair of wafers on one another, with a thermally-curing adhesive at the contact interfaces.
• FIG 6 illustrates three wafers on one another, with thermally-curing adhesives at the contact interfaces.
• FIG 7 illustrates a top view of a wafer indicating locations of UV-transparent windows.
• FIGS. 8, 9, 10 and 11 are cross-sectional views illustrating steps of forming a wafer stack using a first local UV curing technique.
• FIGS. 12, 13 and 14 are cross-sectional views illustrating steps of forming a wafer stack using a second local UV curing technique.
• FIGS. 15, 16, 17 and 18 are cross-sectional views illustrating steps of forming another wafer stack using a local UV curing technique.
• FIG. 1 shows a schematic cross-sectional view of wafers for forming a wafer stack 10, as shown in FIG. 2.
• the stacked wafer subsequently can be divided into individual micro-optics structures.
• the stack can be diced into multiple modules 12, an example of which is illustrated in FIG. 3.
• FIG. 3 shows further details of the illustrated module 12 .
• the techniques for forming a wafer stack as described in this disclosure can be used to form wafer stacks for other types of modules as well.
• the module 12 includes at least one active optical component and at least one passive optical component.
• an active optical component include a light sensing or a light emitting component, such as a photodiode, an image sensor, an LED, an OLED or a laser chip.
• a passive optical component include an optical component that redirects light by refraction and/or diffraction and/or reflection such as a lens, a prism, a mirror or an optical system (e.g., a collection of passive optical components that may include mechanical elements such as aperture stops, image screens or holders).
• Module 12 includes several constituents (P, S, O) stacked upon each other in the vertical direction (i.e., the z direction in FIG. 1). Directions in the x-y plane (cf., FIG. 2) that are perpendicular to the vertical (z) direction may be referred to as lateral directions. Module 12 includes a substrate P, a separation member S, and an optics member O stacked upon each other. Some implementations also may include a baffle member over the optics member. Substrate P is, for example, a printed circuit board assembly. The printed circuit board (PCB) of the PCB assembly may be referred to as an interposer.
• PCB printed circuit board
• an emission member E for emitting light e.g., an optical transmitter die including, for example, a light-emitting diode for emitting infrared light or near-infrared light
• a detecting member D e.g., an optical receiver die including, for example, a photo diode for detecting infrared light or near-infrared light
• light refers to electromagnetic radiation and, can include, for example, electromagnetic radiation in the infrared, visible or ultraviolet (UV) portion of the electromagnetic spectrum.
• Electrodes of emission member E and detecting member D are connected electrically to outside the module 12 where solder balls 17 are attached. Some implementations include four electrical contacts: two for the emission member E and two for the detecting member D. Instead of providing solder balls 17, some implementations include contact pads on the PCB which may be provided with solder balls at a later time.
• Module 12 thus can be mounted, for example, on a printed circuit board 1 , e.g., using surface mount technology (SMT), next to other electronic components.
• Printed circuit board 19 may be a constituent of an electronic device such as a hand-held cornmunication or other computing device (e.g., a smart phone or other mobile phone).
• Separation member S has two openings 14, with emission member E arranged in one of them and detecting member D being arranged in the other. This way, emission member E and detecting member D are laterally encircled by separating member S.
• openings are shown as substantially circular, they may have other shapes in some implementations.
• Separation member S may fulfill several tasks. It can ensure a well-defined distance between substrate P and optics member O (through its vertical extension) which helps to achieve well-defmed light paths from emitting member E through optics member O and from the outside of module 12 through optics member O onto detecting member D. Separation member S can also provide protection of detecting member D from light that is not supposed to be detected by detection member D, by being substantially non- transparent to light generally detectable by detecting member D and by forming a portion of the outside walls of module 12.
• Separation member S also can provide protection of detecting member D from light emitted by emitting member E which should not reach detecting member D, so as to reduce optical cross-talk between emission member E and detecting member D, by being substantially non-transparent to light generally detectable by detecting member D and by forming a wall between emission member E and detecting member D. Light reflected inside module 1 and stray light originating from emission member E can be prevented from reaching detecting member D this way.
• separating member S is made of a polymer material, for example, a hardenable (e.g., curable) polymer material, such as an epoxy resin.
• the separating member can be made, for example, of an epoxy containing carbon black or other pigment.
• a close distance between emission member (e.g., LED) E and detecting member (e.g., photodiode) D can be important.
• the emitter situated close to the receiver requires an IR- effective optical insulation by a separating wall or cover.
• the separating member S has a vertical wall dividing portion that separates the emission member E and detecting member D from one another, which can help reduce internal optical crosstalk.
• the active electronic components (such as emission member E and detecting member D in the example of Fig. 1) in module 12 can be packaged or unpackaged electronic components.
• technologies such as wire-bonding or flip chip technology or any other known surface mount technologies may be used, as can conventional through-hole technology.
• Optics member O includes a blocking portion b and two transparent portions t, one for allowing light emitted by emission member E to leave module 12, and another one for allowing light to enter module 12 from the outside of module 12 and reach detecting member D.
• Blocking portion b is substantially non-transparent for light generally detectable by detecting member D, e.g., by being made of a suitable (polymer) material.
• Transparent portions t comprise a passive optical component L or, more particularly and as an example, a lens member L each, for light guidance.
• Lens members L may, e.g., comprise, as shown in FIG. 3, two lens elements 15 in close contact to a transparent element 16.
• Transparent elements 16 can have the same vertical dimension as optics member O where it forms blocking portion b, such that optics member O where it forms blocking portion b together with transparent elements 16 describes a (close-to- perfect) solid plate shape.
• Lens elements 15 (see FIG. 1) redirect light by refraction and/or by diffraction.
• the lens elements may all be of generally convex shape (as shown in FIG. 1), but one or more of lens elements 15 may be differently shaped, e.g., generally or partially concave.
• the module 12 can be used as a proximity sensor.
• Proximity sensor modules can be incorporated, for example, into a mobile phone to detect that the mobile phone is next to the user's ear or face so that the phone's display can be dimmed or deactivated automatically when the display is not being used, thereby extending the life of the phone's battery.
• the stack 10 includes first, second and third wafers PW, SW, OW.
• the first wafer PW is a substrate wafer
• the second wafer SW is a spacer wafer
• the third wafer OW is an optics wafer.
• the wafer stack 10 may include as few as two wafers or may include more than three wafers. Also, the wafers may be of different types than those in the illustrated example.
• a wafer refers to a substantially disk- or plate-like shaped item, its extension in one direction (z-direction or vertical direction) is small with respect to its extension in the other two directions (x- and y-directions or lateral directions).
• a (non-blank) wafer On a (non-blank) wafer, a plurality of similar structures or items can be arranged, or provided therein, for example, on a rectangular grid.
• a wafer can have openings or holes, and in some cases a wafer may be free of material in a predominant portion of its lateral area.
• a wafer may be made, for example, of a
• the wafers may comprise hardenable materials such as a thermally or ultraviolet (UV) curable polymers.
• UV ultraviolet
• the diameter of a wafer is between 5 cm and 40 cm, and can be, for example between 10 cm and 31 cm.
• the wafer may be cylindrical with a diameter, for example, of 2, 4, 6, 8 or 12 inches, one inch being about 2.54 cm.
• the wafer thickness can be, for example, between 0.2 mm and 10 mm, and in some cases, is between 0.4 mm and 6 mm.
• the wafer stack 10 of FIGS. 1 and 2 show provisions for three modules 12, in some implementations there can be, in one wafer stack, provisions for at least ten modules in each lateral direction, and in some cases at least thirty or even fifty or more modules in each lateral direction.
• each of the wafers are: laterally at least 5 cm or 10 cm, and up to 30 cm or 40 cm or even 50 cm; and vertically (measured with no components arranged on substrate wafer PW) at least 0.2 mm or 0.4 mm or even 1 mm, and up to 6 mm or 10 mm or even 20 mm.
• each wafer PW, SW, OW comprises multiple substantially identical members across its surface(s).
• optics wafer OW can include lens elements 15 and lens members L, which can be arranged, for example, on a rectangular lattice, with a little distance from each other to facilitate a subsequent separation step.
• such members can be formed, for example, using a replication process.
• Substrate wafer PW can be, for example, a PCB assembly comprising a PCB of standard PCB materials, provided with solder balls 17 on the one side and with active optical components (e.g., members E and D described above) soldered to the other side.
• the latter can be placed on substrate wafer PW, for example, by pick-and-place using standard pick-and-place machines.
• the spacer wafer SW can help maintain the substrate wafer PW and the optics wafer OW at substantially a constant distance from one another.
• incorporating the spacer wafer SW into the wafer stack can enable higher imaging performance and complexity.
• each of the wafers PW, SW, OW preferably is composed of a material that is substantially non- transparent for light detectable by detecting members D, except for areas specifically designed to be transparent (e.g., transparent portions t and transparent regions 3). Nevertheless, the techniques described in this disclosure can be used with transparent wafers as well.
• the wafers PW, SW and OW are aligned and bonded together.
• Each active optical component (such as detecting members D and emission members E on the substrate wafer PW) should be accurately aligned with a
• a hole may be formed in the substrate wafer PW, where the hole extends through a thickness of the substrate wafer PW, to provide venting during the reflow process in order to release pressure build-up.
• the hole can be formed in the substrate wafer PW through drilling or an etching process.
• two of the wafers that are to form the wafer stack 10 are placed one on the other to form a sub-stack (FIG. 4, block 202).
• the spacer wafer SW is placed on the substrate wafer PW such that the active optical components (e.g., members E and D) on the substrate wafer PW are located within the openings 14 in the spacer wafer SW.
• a thermally curable adhesive 102 is present on one or both of the contacting surfaces at the interface between the spacer wafer SW and the substrate wafer PW.
• the thermally curable adhesive 102 is provided as a thin layer that substantially covers the lower side of the spacer wafer SW.
• the adhesive 102 may be provided as droplets adhering to the lower surface of the spacer wafer SW and/or the upper surface of the substrate wafer PW.
• the adhesive material 102 can be applied, for example, by a jet printing or jet spraying process in which droplets are applied by a jet head that scans over the surface and ejects the droplets at places where the adhesive is to be applied.
• the collection of droplets does not need to cover an entire surface portion of the spacer wafer SW or substrate wafer PW, but may comprise discrete droplets that flow into each other because of capillary forces when the spacer wafer SW and substrate wafer PW are brought together.
• the adhesive material 102 can be applied by a screen printing-like process, by a lithographic process, by another printing process or by other means (e.g., by a squeegee).
• a third wafer e.g., optical wafer OW
• the sub-stack block 204
• the sub-stack block 206
• a thermally curable adhesive 104 is disposed on one or both of the contacting surfaces at the interface between the spacer wafer SW and the optics wafer OW (see FIG. 6).
• aligning the third wafer (e.g., the optics wafer OW) and the sub-stack involves aligning the optics wafer OW and the substrate wafer PW, and can be performed, for example, using a mask aligner.
• the mask aligner has multiple (e.g., four) calibrated microscopes that can be used to align alignment marks on the wafers.
• the substrate wafer PW and the optics OW each may have multiple (e.g., two) alignment marks.
• the first and second wafers are placed on one another outside the mask aligner to form the sub-stack, which then is loaded into the mask aligner where it is held, for example, on a first chuck.
• the third wafer e.g., the optics wafer OW
• blocks 204 and 206 of FIG. 4 are performed in the mask aligner.
• the mask aligner can provide alignment between the alignment marks on the wafers with accuracy on the order of 1-2 microns.
• placement of the first and second wafers also takes place in the mask aligner.
• the thermally curable adhesives 102, 104 can be provided on the surfaces of the wafers prior to loading the wafers into the mask aligner.
• the thermally curable adhesive 104 at the interface between the second and third wafers can be the same as or different from the thermally curable adhesive 102 at the interface between the first and second wafers.
• the thermally curable adhesive 104 can be applied to the wafer surface(s) using the same technique as, or a different technique from, the technique used to apply the thermally curable adhesive 102.
• the adhesives 102, 104 should be selected to provide good adhesion to the surfaces of the wafers on which they are applied and preferably should be substantially non-transparent to the light detectable by the detecting member D.
• the wafers are preferably composed primarily of materials that are substantially non-transparent to the radiation detectable by the detecting member D, which in some applications, includes UV light.
• UV curing techniques cannot readily be used to bond the wafers in the stack 10 when the adhesive 102, 104 is located on the surfaces of the wafers as shown in FIGS. 5 and 6.
• the wafer stack 10 needs to be heated at an elevated temperature.
• One way of accomplishing such thermal curing is to transfer the wafer stack 10 from the mask aligner to an oven (block 212) and perform the thermal cure in the oven (block 214).
• transferring the stack 10 prior to curing the adhesives 102, 104 can cause the wafers to become misaligned with respect to one another.
• the optics wafer OW may become misaligned with respect to the spacer wafer SW and/or the substrate wafer PW.
• the optics wafer OW and spacer wafer SW initially can be bonded to one another using a local (e.g., spot) UV- curing technique at or near the peripheries of the wafers (block 210).
• the local UV- curing can be performed, for example, while the wafer stack 10 is in the mask aligner, prior to being transferred to the oven for the thermal cure (i.e., prior to blocks 212 and 214 of FIG. 4).
• various approaches can be used to accomplish the local UV-curing.
• the optics wafer OW includes UV-transparent windows 120 near its periphery.
• the optics wafer OW has eight transparent windows 120 substantially equally spaced from another near the periphery of the wafer, with each window 120 having a diameter of between 2-4 mm (e.g., about 3 mm).
• the windows 120 are through-holes extending from the front surface to the back surface of the optics wafer OW.
• the windows 120 are partially or completely filled with a UV-transparent material.
• the spacer wafer SW includes openings 122 (see FIG. 8) that correspond to the positions of the windows 120 in the optics wafer OW.
• the openings 122 in the spacer wafer SW can be formed, for example, as through-holes that extend from the front surface to the back surface of the spacer wafer.
• the openings 122 in the spacer wafer SW preferably have substantially the same diameter as the diameter of the windows 120 in the optics wafer OW.
• the optics wafer OW includes windows 120 that are partially or completely filled with a UV-transparent material.
• the openings 122 in the spacer wafer SW are substantially filled with a UV-curable adhesive material 124, such as a UV-curable glue, epoxy or other adhesive (see FIG. 9).
• the optical wafer OW is aligned with the substrate wafer PW (FIG. 4, block 204), and the optics wafer OW is placed on the spacer wafer SW (FIG. 4, block 206) as shown in FIG. 10.
• FIG. 4 the substrate wafer PW
• UV radiation e.g., UV illumination
• a vacuum chuck that holds the optics wafer OW in the mask aligner can include holes located at positions corresponding to positions of the openings 122.
• the wafer stack 10 is transferred from the mask aligner to the oven (block 212) and the stack is heated so as to cure the thermally-curable adhesive materials 102, 104 simultaneously. After removal from the oven, the wafer stack 10 can be separated (e.g., diced) into separate modules 12.
• the windows 120 in the optics wafer OW are through-holes that extend from the front surface to the back surface of the optics wafer.
• the optics wafer OW is aligned with the sub-stack and placed on the spacer wafer SW (FIG. 4, blocks 204, 206). Then, the openings 122 in the spacer wafer SW and the through-holes 120 are substantially filled with a UV-curable adhesive material 124, such as a UV-curable glue, epoxy or other adhesive (see FIG. 13).
• a UV-curable adhesive material 124 such as a UV-curable glue, epoxy or other adhesive
• UV radiation is directed to the adhesive material 124 in the through-holes 120 of the optics wafer OW and the openings 122 in the spacer wafer SW so as to cure the adhesive material 124 and locally bond the wafers to one another (FIG. 4, block 210).
• the foregoing operations, including dispensing of the UV-curable material 124, can be performed, for example, in a mask aligner.
• the wafer stack 10 is transferred from the mask aligner to the oven (block 212) and the stack is heated so as to cure the thermally- curable adhesive materials 102, 104. After removal from the oven, the wafer stack 10 can be separated (e.g., diced) into separate modules 12.
• the local (e.g., spot) UV-cured bonding technique can be used to bond additional wafers to a previously- formed sub-stack of two or more wafers.
• a third wafer e.g., the optics wafer OW
• a fourth wafer e.g., a baffle wafer
• the process can be repeated to add additional wafers, if needed.
• aligning and stacking the additional wafer(s), as well as dispensing the UV-curable adhesive material and performing the UV-curing process can be accomplished in the mask aligner prior to transferring the stack to the oven for the thermal curing process.
• Pre-curing the adhesive material 124 at selected locations distributed over the surface of the wafers prior to removing the wafer stack from the mask aligner reduces the likelihood that misalignment between the wafers will occur, for example, when the stack subsequently is transferred to the oven for thermal curing.
• the disclosed techniques for forming a wafer stack can, in some implementations, be faster, more accurate and less expensive than forming the wafer stack using a bond aligner.
• a sub-stack composed of a substrate wafer PW and a spacer wafer SW is formed, and the optics wafer OW is placed on the sub-stack.
• a sub-stack composed of an optics wafer OW and spacer wafer SW is formed, and subsequently a substrate wafer PW is placed on the sub-stack.
• alignment between the sub-stack and another wafer, as well as the local UV-cure step can take place in a mask aligner prior to moving the wafer stack to an oven for the thermal curing process.
• UV-transparent windows e.g., through-holes that, in some cases, may be partially or completely filled with a UV-transparent material
• UV-transparent windows are provided in the substrate wafer PW instead of in the optics wafer OW.
• FIGS. 15 - 18 illustrate an example of steps in formation of a wafer stack, where a substrate wafer PW is placed onto a sub-stack composed of an optics wafer OW and spacer wafer SW.
• the spacer wafer SW is placed on the optics wafer OW to form a sub-stack.
• Thermally-curing adhesive 104 is present at the contact interfaces.
• the spacer wafer SW includes openings (e.g., through-holes) 122 near its periphery.
• the openings 122 in the spacer wafer SW are substantially filled with a UV-curable adhesive material 124, such as a UV-curable glue, epoxy or other adhesive (FIG. 16).
• the substrate wafer PW then is aligned with the optics wafer OW, and the substrate wafer PW is placed on the spacer wafer SW as shown in FIG. 17.
• the substrate wafer PW includes UV- transparent windows 130 that are partially or completely filled with a UV-transparent material.
• UV radiation e.g., UV illumination
• the wafer stack 10 can be transferred to an oven so as to cure the thermally-curable adhesive materials 102, 104. After removal from the oven, the wafer stack 10 can be separated (e.g., diced) into separate modules 12.
• the UV-transparent windows 130 near the periphery of the substrate wafer SW are through-holes that extend from one surface of the substrate wafer SW to its opposite surface.
• the openings 122 at the periphery of the spacer wafer SW and the corresponding windows 130 near the periphery of the substrate wafer PW can be substantially filled with the UV-curable material 124 after the substrate wafer SW is aligned and placed on the sub-stack.
• UV radiation e.g., UV illumination
• the wafer stack 10 can be transferred to an oven so as to cure the thermally-curable adhesive materials 102, 104. After removal from the oven, the wafer stack 10 can be separated (e.g., diced) into separate modules 12.

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• 2013
  • 2013-05-15 EP EP13790259.9A patent/EP2850654B1/en active Active
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