WO2013147359A1 - Boîtier de semi-conducteur et son procédé de fabrication - Google Patents

Boîtier de semi-conducteur et son procédé de fabrication Download PDF

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Publication number
WO2013147359A1
WO2013147359A1 PCT/KR2012/002626 KR2012002626W WO2013147359A1 WO 2013147359 A1 WO2013147359 A1 WO 2013147359A1 KR 2012002626 W KR2012002626 W KR 2012002626W WO 2013147359 A1 WO2013147359 A1 WO 2013147359A1
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WIPO (PCT)
Prior art keywords
wiring
redistribution pattern
forming
semiconductor chip
pattern layer
Prior art date
Application number
PCT/KR2012/002626
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English (en)
Korean (ko)
Inventor
헤안 소흐세이
지엔 시에우유엔
웨이 웡쳥
분 소흐시에우
첸하우양
Original Assignee
주식회사 네패스
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Publication date
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to CN201280072193.0A priority Critical patent/CN104205327B/zh
Publication of WO2013147359A1 publication Critical patent/WO2013147359A1/fr

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Definitions

  • the technical idea of the present invention relates to a semiconductor package, and more particularly, to a semiconductor package including a through wiring and a manufacturing method thereof.
  • An object of the present invention is to provide a method of manufacturing a semiconductor package including a through wiring with precision and low process defects.
  • a method of manufacturing a semiconductor package including: preparing a conductive member; Removing a portion of the conductive member to form a flat portion and a protrusion protruding from the flat portion; Forming a sealing member for sealing the conductive member; Removing a portion of the sealing member to expose the protrusion of the conductive member from the sealing member to form a through wiring; Forming a redistribution pattern layer electrically connected to the through wiring on the through wiring; Mounting a semiconductor chip on the redistribution pattern layer; And forming an outer connection member electrically connected to the through wiring.
  • a semiconductor package including: a through wiring formed using a protrusion formed by using the manufacturing method described above and removing a partial region of a conductive member; A redistribution pattern layer disposed on the through wiring and electrically connected to the through wiring; A semiconductor chip disposed on the redistribution pattern layer and electrically connected to the redistribution pattern layer; And an external connection member electrically connected to the through wiring.
  • the manufacturing process can be simplified, and the yield and the process cost can be reduced. have.
  • FIG. 1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor package of FIG. 1 taken along line A-A according to an exemplary embodiment.
  • 3 to 22 are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 1 according to an embodiment of the present invention according to process steps.
  • FIG. 23 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
  • 24 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
  • FIG. 1 is a plan view illustrating a semiconductor package 100 according to an embodiment of the present invention.
  • 2 is a cross-sectional view taken along the line A-A of the semiconductor package 100 of FIG. 1 according to an embodiment of the present invention.
  • the semiconductor package 100 may include a through wiring 110, a semiconductor chip 120, a sealing member 130, a redistribution pattern layer 140, an underfill layer 160, and an outer connection member. And 170.
  • the through wire 110 may be positioned to penetrate the sealing member 130.
  • the through wiring 110 may be electrically connected to the semiconductor chip 120 by the redistribution pattern layer 140. That is, the through wire 110 may be electrically connected to the semiconductor chip pad 122 of the semiconductor chip 120 through the redistribution pattern 144 and the semiconductor chip connection member 124.
  • the through wire 110 may be formed using the protrusions 113 (see FIG. 4) formed from the conductive member 111 (see FIG. 4), as described with reference to FIGS. 3 to 22 below.
  • the through wiring 110 exposed from the sealing member 130 may have a recessed surface 115 as compared to the surface 135 of the sealing member 130.
  • the surface of the sealing member 130 and the exposed surface of the through wiring 110 may be located on the same plane.
  • the sealing member 130 may include an insulator and may include, for example, an epoxy mold compound (EMC).
  • EMC epoxy mold compound
  • the redistribution pattern layer 140 may be positioned on the sealing member 130 and the through wiring 110, and may be electrically connected to the through wiring 110.
  • the surface 116 of the through wire 110 connected to the redistribution pattern layer 140 may be coplanar with the surface 136 of the sealing member 130.
  • the redistribution pattern layer 140 may include a first insulating layer 142, a redistribution pattern 144, and a second insulating layer 146.
  • the redistribution pattern 144 may be surrounded by the first insulating layer 142 and the second insulating layer 146.
  • the redistribution pattern 144 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the redistribution pattern 144 may redistribute the through wiring 110 and / or the redistribution of the semiconductor chip 120. Accordingly, the redistribution pattern 144 may reduce the size of the input / output terminals of the semiconductor chip 120 and increase the number of the input / output terminals. In addition, by the redistribution pattern 144, the semiconductor package 100 may have a fan-out structure.
  • the redistribution pattern layer 140 may be formed of a prefabricated structure, and the structure of the redistribution pattern layer 140 is also included in the technical idea of the present invention when the structure is adhered to the sealing member 130 by pressing, bonding, or reflowing.
  • the semiconductor chip 120 may be positioned on the redistribution pattern layer 140 and electrically connected to the redistribution pattern layer 140.
  • the semiconductor chip pad 122 of the semiconductor chip 120 may be electrically connected to the redistribution pattern 144 of the redistribution pattern layer 140 through the semiconductor chip connection member 124.
  • the semiconductor chip 120 may be a memory chip or a logic chip.
  • Such a memory chip may include, for example, DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, or MRAM. have.
  • Such a logic chip may be a controller for controlling the memory chips.
  • the semiconductor chip 120 may be spaced apart from the redistribution pattern layer 140 by the height of the semiconductor chip connection member 124.
  • the semiconductor chip 120 is in contact with the redistribution pattern layer 140 is also included in the technical idea of the present invention.
  • the semiconductor package 100 may not include the underfill layer 160.
  • the underfill layer 160 may be positioned between the semiconductor chip 120 and the redistribution pattern layer 140 to fill a space between the semiconductor chip 120 and the redistribution pattern layer 140.
  • the underfill layer 160 may fill the space between the semiconductor chip connection members 124.
  • Underfill layer 160 may include an insulator and may be, for example, an epoxy molding compound, silica, resin, glassy material, a polymer, or the like.
  • the underfill layer 160 may function to fix the semiconductor chip 120 while being in contact with the redistribution pattern layer 140.
  • the underfill layer 160 may have appropriate toughness to prevent cracking due to external impact. Can have
  • the outer connection member 170 may be electrically connected to the through wiring 110 at a position opposite to the redistribution pattern layer 140, and thus may be electrically connected to the semiconductor chip 120 through the redistribution pattern layer 140. Can be connected. In addition, the outer connection member 170 may electrically connect the semiconductor chip 120 with an external device.
  • the through wiring 110 may have a recessed surface 115, and the outer connecting member 170 may be formed by the sealing member 130. It may be aligned and / or fixed.
  • the outer connection member 170 may be located at the same position perpendicular to the through wire 110.
  • the outer connecting member 170 may include a conductive material, for example, may include a metal.
  • the outer connection member 170 may be a solder ball.
  • the semiconductor chip 120 may be located at a central portion of the semiconductor package 100.
  • this is exemplary and the technical idea of the present invention is not limited thereto, and the case where the semiconductor chip 120 is located at any part of the semiconductor package 100 is also included in the technical idea of the present invention.
  • the outer connection member 170 may be located outside the semiconductor chip 120. In addition, the outer connection member 170 may overlap the semiconductor chip 120.
  • the arrangement of the outer connecting member 170 shown in FIG. 1 is exemplary, and the technical idea of the present invention is not limited thereto, and various arrangements of the outer connecting member 170 are included in the technical idea of the present invention.
  • 3 to 22 are cross-sectional views illustrating a manufacturing method of manufacturing the semiconductor package 100 of FIG. 1 according to an embodiment of the present invention according to the process steps.
  • the conductive member 111 is prepared.
  • the conductive member 111 may have a flat plate shape.
  • the conductive member 111 may include a conductive material, for example, may include a metal.
  • the conductive member 111 may include, for example, copper, a copper alloy, aluminum, or an aluminum alloy.
  • a portion of the conductive member 111 is removed to form the flat portion 112 and the protrusion 113 protruding from the flat portion 112.
  • the process may be referred to as a half etching process, but the height of the protrusion 113 is not limited to the height of the flat part 112.
  • the height of the protrusion 113 may have the same height as the through wiring 110 (refer to FIG. 11) formed in a subsequent process or may have a slightly larger height.
  • the height of the planar portion 112 may vary, and the thinner is preferable for the subsequent removal process, but may have a predetermined thickness to prevent the warping phenomenon of the conductive member 111.
  • the conductive member 111 is attached onto the first carrier substrate 119.
  • the conductive member 111 may be attached onto the first carrier substrate 119 using the first adhesive member 118.
  • the planar portion 112 may face the first carrier substrate 119 and may contact the first adhesive member 118.
  • the first carrier substrate 119 may include silicon, glass, ceramic, plastic, or polymer.
  • the first adhesive member 118 may be a liquid adhesive or an adhesive tape.
  • a sealing member 130 for sealing the conductive member 111 is formed.
  • the sealing member 130 may fill between the protrusions 113 of the conductive member 111.
  • the sealing member 130 may be formed to cover the conductive member 111.
  • the sealing member 130 may include an insulator and may include, for example, an epoxy mold compound (EMC).
  • a portion of the sealing member 130 is removed to expose the protrusion 113 of the conductive member 111 from the sealing member 130.
  • the removal process may be performed using polishing, etch back or mechanical chemical polishing (CMP).
  • the second carrier substrate 139 is attached onto the second adhesive member 138. That is, the second carrier substrate 139 is attached on the exposed protrusion 113 of the conductive member 111. Accordingly, the second carrier substrate 139 is attached in the opposite direction to the first carrier substrate 119 based on the conductive member 111.
  • the second carrier substrate 139 may include silicon, glass, ceramic, plastic, or polymer.
  • the first carrier substrate 119 and the second carrier substrate 139 may include the same material or different materials.
  • the first carrier substrate 119 and the first adhesive member 118 are removed.
  • the flat portion 112 of the conductive member 111 is turned upside down.
  • the through wiring 110 may be through silicon via (TSV) or through substrate via (TSV).
  • the through wiring 110 may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the removal process may be performed using polishing, etch back or mechanical chemical polishing (CMP). After the through wiring 110 is formed, a cleaning process may be further performed to remove unwanted residues.
  • the redistribution pattern layer 140 is formed on the through wiring 110.
  • a first insulating layer 142 is formed on the sealing member 130 and the exposed through wiring 110. Subsequently, a portion of the first insulating layer 142 is removed to form a first opening 141 exposing the through wiring 110.
  • the first insulating layer 142 may include an insulator and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
  • a redistribution pattern 144 electrically connected to the through wire 110 is formed on the first insulating layer 142.
  • the redistribution pattern 144 may fill the first opening 141.
  • the redistribution pattern 144 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the redistribution pattern 144 may be formed using various methods such as deposition, plating, and the like.
  • the redistribution pattern 144 may redistribute the through wiring 110.
  • a second insulating layer 146 is formed on the redistribution pattern 144. Subsequently, a portion of the second insulating layer 146 is removed to form a second opening 143 that exposes a portion of the redistribution pattern 144.
  • the second insulating layer 146 may include an insulator and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
  • the first insulating layer 142 and the second insulating layer 146 may include the same material or different materials.
  • the first insulating layer 142, the redistribution pattern 144, and the second insulating layer 146 may constitute the redistribution pattern layer 140.
  • the redistribution pattern layer 140 may be formed of a prefabricated structure, and the structure of the redistribution pattern layer 140 is also included in the technical idea of the present invention when the structure is adhered to the sealing member 130 by pressing, bonding, or reflowing.
  • the second carrier substrate 139 and the second adhesive member 138 are removed. As a result, the through wire 110 may be exposed. In detail, the surface of the through wiring 110 positioned opposite to the redistribution pattern layer 140 may be exposed.
  • a third carrier substrate 149 is attached onto the redistribution pattern layer 140.
  • the third carrier substrate 149 may be attached onto the redistribution pattern layer 140 using the third adhesive member 148.
  • the third carrier substrate 149 may include silicon, glass, ceramic, plastic, or polymer.
  • the third adhesive member 148 may be a liquid adhesive or an adhesive tape.
  • the third carrier substrate 149 may include the same material as the first carrier substrate 119 and / or the second carrier substrate 139 or may include different materials.
  • the third adhesive member 148 may include the same material as the first adhesive member 118 and / or the second adhesive member 138 or may include different materials.
  • the 15 and 16 may be performed in a reverse order. For example, after attaching the third carrier substrate 149 to the redistribution pattern layer 140, the second carrier substrate 139 and the second adhesive member 138 may be removed.
  • a portion of the exposed through wire 110 is removed to form a through wire 110 having a recessed surface 115 as compared with the surface 135 of the sealing member 130.
  • Removing a part of the through wire 110 may be performed using wet etching. By the wet etching, the surface of the through wire 110 may be cleaned.
  • the third carrier substrate 149 and the third adhesive member 148 are removed. Accordingly, the redistribution pattern 144 of the redistribution pattern layer 140 may be exposed. In addition, the redistribution pattern 144 is exposed by the second opening 143.
  • an independent structure 150 including the through wiring 110 and the redistribution pattern layer 140 may be configured.
  • the structure 150 is a region in which a redistribution pattern 144 of the redistribution pattern layer 140 is exposed and a semiconductor chip 120 (see FIG. 19) electrically connected to the redistribution pattern layer 140 is mounted.
  • Can have The other side opposite to the one side may have a region to which the through wiring 110 is exposed from the sealing member 130 and to which an external connection member 170 (refer to FIG. 22) electrically connected to the through wiring 110 is attached. have.
  • Such structure 150 may function as an interposer.
  • the semiconductor chip 120 is mounted on the structure 150.
  • the semiconductor chip 120 is mounted on the redistribution pattern layer 140.
  • the semiconductor chip 120 may be a memory chip or a logic chip.
  • the semiconductor chip 120 may include one semiconductor chip or may include a plurality of semiconductor chips.
  • the semiconductor chip 120 includes a semiconductor chip pad 122.
  • the semiconductor chip connection member 124 such as solder bumps may be attached to the semiconductor chip pad 122.
  • the semiconductor chip connection members 124 may be in electrical contact with each other by contacting the redistribution pattern 144 exposed by the second opening 143. In this case, a reflow process may be further performed to attach the semiconductor chip connection member 124 to the redistribution pattern 144.
  • the semiconductor chip connection member 124 may be formed in the redistribution pattern 144 exposed by the second opening 143.
  • the semiconductor chip pad 122 and the semiconductor chip connection member of the semiconductor chip 120 may be formed.
  • the semiconductor chip 120 may be mounted on the structure 150 to be electrically connected to the 124.
  • the semiconductor chip 120 may be redistributed by the redistribution pattern 144 of the redistribution pattern layer 140. Accordingly, the redistribution pattern 144 may reduce the size of the input / output terminals of the semiconductor chip 120 and increase the number of the input / output terminals. In addition, by the redistribution pattern 144, the semiconductor package 100 may have a fan-out structure.
  • the result of mounting the semiconductor chip 120 on the structure 150 by the process of FIG. 19 is illustrated.
  • the semiconductor chip 120 is spaced apart from the redistribution pattern layer 140 by the height of the semiconductor chip connection member 124.
  • the semiconductor chip 120 may be in contact with the redistribution pattern layer 140 because the depth of the second opening 143 and the height of the semiconductor chip connection member 124 are the same. do.
  • an underfill layer 160 is formed below the semiconductor chip 120.
  • the underfill layer 160 fills a space between the semiconductor chip 120 and the redistribution pattern layer 140.
  • the underfill layer 160 may have a suitable viscosity to fill between the semiconductor chip connection members 124.
  • Underfill layer 160 may include an insulator and may be, for example, an epoxy molding compound, silica, resin, glassy material, a polymer, or the like.
  • the underfill layer 160 may be formed by filling the space between the semiconductor chip 120 and the redistribution pattern layer 140 using a liquid underfill material and then heating or drying the liquid underfill material to solidify the liquid underfill material. .
  • an outer connection member 170 electrically connected to the through wire 110 is formed.
  • the outer connecting member 170 may include a conductive material, for example, may include a metal.
  • the outer connection member 170 may be a solder ball. Through the reflow process, the outer connection member 170 may be attached to the through wiring 110. Thus, the semiconductor package 100 is completed.
  • FIG. 23 is a cross-sectional view illustrating a semiconductor package 200 according to an embodiment of the present invention.
  • the semiconductor package 200 according to the present embodiments is a modification of some components in the semiconductor package of the above-described embodiment, and thus duplicated description will be omitted.
  • the semiconductor package 200 includes a through wiring 110 positioned through the sealing member 130, a redistribution pattern layer 140 disposed on the through wiring 110, and electrically connected thereto.
  • the first semiconductor chip 220a and the second semiconductor chip 220b, the first semiconductor chip 220a, and the second semiconductor chip 220b are disposed on the layer 140 and electrically connected to the redistribution pattern layer 140.
  • An underfill layer 160 filling a space between the first semiconductor chip 220a and the redistribution pattern layer 140 and a space between the second semiconductor chip 220b and the redistribution pattern layer 140 to be fixed;
  • the outer connecting member 170 may be electrically connected to the through wiring 110 at a position opposite to the redistribution pattern layer 140.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may be electrically connected to the redistribution pattern layer 140 similarly to the semiconductor chip 120 of FIG. 1.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may have the same size or different sizes.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may be memory chips or logic chips.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may be homogeneous products having the same function or heterogeneous products having different functions.
  • the first semiconductor chip 220a may be a logic chip and the second semiconductor chip 220b may be a memory chip, or vice versa.
  • the semiconductor package 200 may configure a system on chip (SOC) or a system in package (SIP).
  • SOC system on chip
  • SIP system in package
  • FIG. 23 illustrates a case in which the first semiconductor chip 220a and the second semiconductor chip 220b are arranged in a planar manner
  • the case in which the first semiconductor chip 220a and the second semiconductor chip 220b are vertically stacked is also included in the technical concept of the present invention.
  • FIG. 24 is a cross-sectional view illustrating a semiconductor package 300 according to an embodiment of the present invention.
  • the semiconductor package 300 according to the present exemplary embodiments is a modification of some components of the semiconductor package of the above-described embodiment, and thus a redundant description thereof will be omitted.
  • the semiconductor package 300 includes a through wiring 110 positioned through the sealing member 130, a redistribution pattern layer 140 disposed on the through wiring 110, and electrically connected thereto.
  • the space between the semiconductor chip 120 and the redistribution pattern layer 140 may be formed to fix the semiconductor chip 120 and the semiconductor chip 120 on the layer 140 and electrically connected to the redistribution pattern layer 140.
  • the underfill layer 160 and the redistribution pattern layer 140 may include an outer connection member 170 electrically connected to the through wire 110 at a position opposite to the filling.
  • the semiconductor device may further include an external sealing member 380 disposed on the redistribution pattern layer 140 and sealing the semiconductor chip 120.
  • the outer seal member 380 may include an insulator and may include, for example, an epoxy mold compound (EMC).
  • EMC epoxy mold compound
  • the outer sealing member 380 may perform a function of protecting the semiconductor chip 120 from the outside and / or discharging heat generated from the semiconductor chip 120 to the outside.
  • the outer sealing member 380 may include the same material as the sealing member 130 or may include different materials.
  • the outer sealing member 380 may include the same material as the underfill layer 160 or may include different materials.

Abstract

La présente invention concerne un procédé de fabrication d'un boîtier de semi-conducteur comprenant un câblage de connexion qui est précis et qui a un faible taux de défaut durant le processus de fabrication. Le procédé de fabrication du boîtier de semi-conducteur, selon un mode de réalisation de la présente invention, comprend les étapes de : préparation d'un élément conducteur ; retrait d'une partie de l'élément conducteur pour former une partie plate et une partie en saillie, qui fait saillie à partir de la partie plate ; formation d'un élément de scellage pour sceller l'élément conducteur ; retrait d'une partie de l'élément de scellage pour exposer la partie en saillie de l'élément conducteur à travers l'élément de scellage, et formation du câblage de connexion ; formation, sur le câblage de connexion, d'une couche de motif de recâblage qui est électriquement connectée au câblage de connexion ; montage de la puce semi-conductrice sur la couche de motif de recâblage ; et formation d'un élément de connexion externe qui est connecté électriquement au câblage de connexion.
PCT/KR2012/002626 2012-03-30 2012-04-06 Boîtier de semi-conducteur et son procédé de fabrication WO2013147359A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201280072193.0A CN104205327B (zh) 2012-03-30 2012-04-06 半导体组件及其制造方法

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KR1020120033167A KR101323925B1 (ko) 2012-03-30 2012-03-30 반도체 패키지 및 그 제조 방법
KR10-2012-0033167 2012-03-30

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KR102517379B1 (ko) 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법

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KR20130110872A (ko) 2013-10-10
CN104205327A (zh) 2014-12-10
KR101323925B1 (ko) 2013-10-31

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