JP2010087309A - 半導体モジュールおよび半導体モジュールを備える携帯機器 - Google Patents
半導体モジュールおよび半導体モジュールを備える携帯機器 Download PDFInfo
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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Abstract
【解決手段】素子搭載用基板100の上に形成された絶縁樹脂層30の上に搭載された半導体素子40が封止樹脂50により封止されている。配線層120には、半導体素子40の側に突出する突起電極122と突起部124とがそれぞれ一体的に形成されている。そして、突起電極122は、絶縁樹脂層30を貫通して半導体素子40の素子電極42と電気的に接続されている。突起部124は、半導体素子40の四辺に沿って半導体素子40を取り囲むように配置され、突起電極122と素子電極42との接合部分よりも上方の位置にまで封止樹脂50内に埋め込まれている。
【選択図】図1
Description
図1は、実施の形態1に係る半導体モジュール10の構成を示す断面図である。図2は、図1のA−A線を切断面とする平面図である。
実施の形態1に係る半導体モジュール10の製造方法について図3乃至図7を参照して説明する。
上述した実施の形態1では、突起部124が半導体素子40の全体を取り囲んでいるが、突起部124は必ずしも半導体素子40の全体を取り囲んでいなくてもよい。
図9は、実施の形態2に係る半導体モジュール10の構成を示す概略断面図である。図10は、図9のB−B線を切断面とする平面図である。実施の形態2に係る半導体モジュール10は、絶縁樹脂層30が半導体素子搭載領域だけでなく基材110の一方の側全体に設けられている点が実施の形態1と相違する。実施の形態2における、その他の構成は実施の形態1と同様であり、実施の形態1と同様な構成については適宜説明を省略する。
図11は、実施の形態3に係る半導体モジュール10の構成を示す概略図である。実施の形態3に係る半導体モジュール10は、封止樹脂50の側方において、突起部124が露出している点、および金属箔280で封止樹脂50が被覆されている点で実施の形態1と相違する。
図12は、実施の形態4に係る半導体モジュール10の構成を示す概略図である。実施の形態4に係る半導体モジュール10は、実施の形態2と同様に基材110の一方の側全体に絶縁樹脂層30が設けられているが、金属箔280で半導体素子40をシールドするという技術思想において実施の形態3と共通し、封止樹脂50の側方において、突起部124が露出している点、および金属箔280で封止樹脂50が被覆されている点で実施の形態2と相違する。
図13は、実施の形態5に係る半導体モジュール10の構成を示す概略図である。図14は、図13のC−C線を切断面とする平面図である。本実施の形態では、半導体素子40がワイヤボンディング接続により基材110に搭載されている点で実施の形態1と相違する。また、本実施の形態の突起部124は、後述するように、実施の形態1で説明した突起部124と異なる構造を有する。
本実施の形態に係る半導体モジュール10の製造方法は、図3(A)乃至図3(C)までは、実施の形態1と同様である。
Claims (8)
- 基材と
前記基材の一方の主表面に設けられた配線層と、
前記配線層と対向する素子電極を有し、前記基材の上に絶縁樹脂層を介して搭載された半導体素子と、
前記配線層の上に設けられ、前記素子電極と電気的に接続された基板電極と、
前記半導体素子を封止する封止樹脂と、
前記半導体素子の少なくとも1辺に沿って配置され、前記配線層から前記半導体素子の側に突出して前記封止樹脂に埋め込まれた突起部と、
を備えることを特徴とする半導体モジュール。 - 前記突起部の先端部が前記基板電極と前記素子電極との接合部分よりも上方に位置していることを特徴とする請求項1に記載の半導体モジュール。
- 前記突起部が前記半導体素子の各辺に沿って設けられていることを特徴とする請求項1または2に記載の半導体モジュール。
- 前記基板電極が、前記半導体素子の側に突出し、前記絶縁樹脂層を貫通して前記素子電極と接続された突起電極であることを特徴とする請求項1乃至3のいずれか1項に記載の記載の半導体モジュール。
- 前記突起部と前記突起電極とが同じ材料で形成されていることを特徴とする請求項4に記載の半導体モジュール。
- 前記封止樹脂を被覆する金属箔をさらに備え、
前記金属箔が前記突起部のうち、接地電位に固定された突起部と電気的に接続されていることを特徴とする請求項1乃至5のいずれか1項に記載の半導体モジュール。 - 前記基材の上に設けられ、突起部形成領域が露出するような開口部を有する保護層をさらに備え、
前記突起部が、前記保護層の前記開口部内に埋め込まれた埋込部と、前記保護層の前記開口部周囲の上面よりも上方に突出した突出部とを有することを特徴とする請求項1乃至6のいずれか1項に記載の半導体モジュール。 - 請求項1乃至7のいずれか1項に記載の半導体モジュールを備える携帯機器。
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JP2008255795A JP5484705B2 (ja) | 2008-09-30 | 2008-09-30 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
PCT/JP2009/003598 WO2010013470A1 (ja) | 2008-07-31 | 2009-07-29 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
US13/056,851 US8373281B2 (en) | 2008-07-31 | 2009-07-29 | Semiconductor module and portable apparatus provided with semiconductor module |
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JP2008255795A JP5484705B2 (ja) | 2008-09-30 | 2008-09-30 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
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JP2010087309A true JP2010087309A (ja) | 2010-04-15 |
JP5484705B2 JP5484705B2 (ja) | 2014-05-07 |
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WO2013147359A1 (ko) * | 2012-03-30 | 2013-10-03 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
JP5466785B1 (ja) * | 2013-08-12 | 2014-04-09 | 太陽誘電株式会社 | 回路モジュール及びその製造方法 |
WO2019159798A1 (ja) * | 2018-02-19 | 2019-08-22 | 富士電機株式会社 | 半導体モジュール及びその製造方法 |
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Cited By (7)
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---|---|---|---|---|
WO2013147359A1 (ko) * | 2012-03-30 | 2013-10-03 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
KR101323925B1 (ko) * | 2012-03-30 | 2013-10-31 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
JP5466785B1 (ja) * | 2013-08-12 | 2014-04-09 | 太陽誘電株式会社 | 回路モジュール及びその製造方法 |
WO2019159798A1 (ja) * | 2018-02-19 | 2019-08-22 | 富士電機株式会社 | 半導体モジュール及びその製造方法 |
JP2019145612A (ja) * | 2018-02-19 | 2019-08-29 | 富士電機株式会社 | 半導体モジュール及びその製造方法 |
JP7083256B2 (ja) | 2018-02-19 | 2022-06-10 | 富士電機株式会社 | 半導体モジュール及びその製造方法 |
US11749581B2 (en) | 2018-02-19 | 2023-09-05 | Fuji Electric Co., Ltd. | Semiconductor module and method for manufacturing same |
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