WO2019159798A1 - 半導体モジュール及びその製造方法 - Google Patents

半導体モジュール及びその製造方法 Download PDF

Info

Publication number
WO2019159798A1
WO2019159798A1 PCT/JP2019/004302 JP2019004302W WO2019159798A1 WO 2019159798 A1 WO2019159798 A1 WO 2019159798A1 JP 2019004302 W JP2019004302 W JP 2019004302W WO 2019159798 A1 WO2019159798 A1 WO 2019159798A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating substrate
width
average roughness
sealing resin
roughness
Prior art date
Application number
PCT/JP2019/004302
Other languages
English (en)
French (fr)
Inventor
祐平 西田
文彦 百瀬
尭 出野
北村　征寛
Original Assignee
富士電機株式会社
Ｄｏｗａメタルテック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士電機株式会社, Ｄｏｗａメタルテック株式会社 filed Critical 富士電機株式会社
Priority to CN201980006691.7A priority Critical patent/CN111512434B/zh
Priority to US16/955,115 priority patent/US11749581B2/en
Priority to EP19753674.1A priority patent/EP3712933A4/en
Priority to KR1020207017893A priority patent/KR102454589B1/ko
Publication of WO2019159798A1 publication Critical patent/WO2019159798A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B37/00—Joining burned ceramic articles with other burned ceramic articles or other articles by heating
    • C04B37/02—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles
    • C04B37/023—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used
    • C04B37/026—Joining burned ceramic articles with other burned ceramic articles or other articles by heating with metallic articles characterised by the interlayer used consisting of metals or metal salts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/4807—Ceramic parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2235/00—Aspects relating to ceramic starting mixtures or sintered ceramic products
    • C04B2235/70—Aspects relating to sintered or melt-casted ceramic products
    • C04B2235/96—Properties of ceramic products, e.g. mechanical properties such as strength, toughness, wear resistance
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/32—Ceramic
    • C04B2237/36—Non-oxidic
    • C04B2237/366—Aluminium nitride
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/30—Composition of layers of ceramic laminates or of ceramic or metallic articles to be joined by heating, e.g. Si substrates
    • C04B2237/40—Metallic
    • C04B2237/407—Copper
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B2237/00—Aspects relating to ceramic laminates or to joining of ceramic articles with other articles by heating
    • C04B2237/50—Processing aspects relating to ceramic laminates or to the joining of ceramic articles with other articles by heating
    • C04B2237/52—Pre-treatment of the joining surfaces, e.g. cleaning, machining
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0503—13th Group
    • H01L2924/05032—AlN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H01L2924/35121—Peeling or delaminating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2072—Anchoring, i.e. one structure gripping into another

Definitions

  • the present invention relates to a semiconductor module having a structure in which a semiconductor element is bonded to an insulating substrate through a circuit pattern, and the insulating substrate, the circuit pattern, and the semiconductor element are sealed with a sealing resin, and a manufacturing method thereof.
  • an insulating substrate, a circuit pattern, and a semiconductor element are provided to provide insulation, heat resistance, and durability.
  • the structure is sealed with a sealing resin.
  • Patent Document 2 listed below discloses a method for manufacturing a ceramic circuit board in which fine irregularities are formed on the surface of crystal grains by ion beam etching in order to improve the adhesion with a metal film.
  • Patent Document 3 discloses a ceramic member in which a plurality of protrusions having a diameter smaller than the crystal particle diameter by the acidic etching treatment is formed on the crystal particle surface in order to improve the anchor effect.
  • Patent Document 4 describes that the anchor effect of the brazing material is enhanced by a ceramic base having a plurality of depressions / projections having irregularities larger than the average crystal grain size.
  • Patent Document 5 describes that the surface of the aluminum nitride substrate is roughened by applying abrasive grains to improve the bonding strength of the metal circuit foil.
  • Patent Document 6 covers a circuit board, a heat sink on which the circuit board is mounted, a lead electrically connected to the circuit board, and a connection portion between the circuit board and the circuit board and the lead. And an encapsulating resin portion in which an encapsulating resin is arranged so that a part of the heat sink and a part of the heat sink are exposed to the outside, and at least one of the surface of the circuit board and the surface of the heat sink In this, at least a part of a portion in contact with the sealing resin portion is roughened.
  • JP 2013-258321 A Japanese Patent Laid-Open No. 5-24959 JP 2002-241187 A JP 2010-30280 A JP 2013-27918 A JP 2008-172172 A
  • Patent Documents 1 to 5 the surface roughness of the insulating substrate for improving the adhesion strength between the insulating substrate and the sealing resin is not examined. Further, Patent Document 6 does not describe details of the conditions for the roughening treatment.
  • an object of the present invention is to provide a semiconductor module having improved adhesion between an insulating substrate and a sealing resin and a method for manufacturing the same.
  • the semiconductor module of the present invention comprises: An insulating substrate; A circuit pattern formed on the insulating substrate; A semiconductor element bonded on the circuit pattern; In the semiconductor module comprising the insulating substrate, the circuit pattern and a sealing resin for sealing the semiconductor element,
  • the surface of the insulating substrate at the part where the insulating substrate and the sealing resin are in close contact with each other has an average roughness obtained in the range of 300 ⁇ m in width measured and calculated by the following method in the cross section of the insulating substrate.
  • the cross section of the insulating substrate is photographed with a scanning electron microscope to prepare an SEM image, the SEM image is binarized to prepare surface shape image data, and the image data is two-dimensionally converted using image digitization software. It converts into coordinate data, and calculates
  • Za represents the average roughness.
  • Zn represents the difference between the two-dimensional coordinate data and the average value at each n.
  • N is a value obtained by dividing the measurement width by the measurement pitch.
  • a portion where the insulating substrate and the sealing resin are in close contact includes a peripheral portion of the insulating substrate.
  • the surface of the insulating substrate at the portion where the insulating substrate and the sealing resin are in close contact with each other may have an average roughness of 2 ⁇ m or less in a range of 300 ⁇ m width in the cross section of the insulating substrate. preferable.
  • the surface of the insulating substrate at the portion where the insulating substrate and the sealing resin are in close contact with each other has an average roughness of 0.7 ⁇ m or more in a width of 300 ⁇ m in the cross section of the insulating substrate. It is preferable.
  • the average roughness of the surface of the insulating substrate at the portion where the insulating substrate and the sealing resin are in close contact with each other is 0.1 ⁇ m or less in a width of 3 ⁇ m.
  • the method for manufacturing a semiconductor module of the present invention includes: A surface treatment process for adjusting the surface roughness of the ceramic insulating substrate; An oxidation treatment step of oxidizing the surface of the insulating substrate by heat-treating the insulating substrate; A brazing material coating step of coating a brazing material on the surface of the insulating substrate; A metal foil joining step for joining a metal foil to the insulating substrate surface via the brazing material; A circuit pattern forming step of forming a circuit pattern by etching the metal foil and the brazing material; A semiconductor element mounting step of bonding a semiconductor element on the circuit pattern; A method of manufacturing a semiconductor module including a sealing step of sealing the insulating substrate, the circuit pattern, and the semiconductor element with a sealing resin, In the surface treatment step, the surface of the insulating substrate is wet blasted to roughen the cross section of the insulating substrate so that the average roughness obtained in the range of 300 ⁇ m width is 0.15 ⁇ m or more.
  • the brazing material coating step is performed not only on the surface of the insulating substrate surface to which the metal foil is bonded, but also on the surface to which the metal foil is not bonded and the sealing resin adheres.
  • Consisting of a process of applying materials In the circuit pattern forming step, the surface to which the sealing resin of the insulating substrate is in close contact is measured by the method described above in the cross section of the insulating substrate by etching the portion coated with the brazing material.
  • the calculated average roughness in the range of 300 ⁇ m in width is 0.15 ⁇ m or more, and the average roughness in the range of 3 ⁇ m in width is 0.02 ⁇ m or more.
  • the insulating substrate is preferably made of ceramics, and more preferably made of aluminum nitride.
  • the insulated circuit board of the present invention includes an insulating substrate, In an insulated circuit board having a circuit pattern formed on the insulating board, The surface of the portion of the insulating substrate where the circuit pattern is not formed has an average roughness of 0.15 ⁇ m or more obtained in the range of 300 ⁇ m in width measured and calculated by the method described above in the cross section of the insulating substrate. The average roughness obtained in the range of 3 ⁇ m width is 0.02 ⁇ m or more.
  • the surface of the insulating substrate at the portion where the insulating substrate and the sealing resin are in close contact with each other has an average roughness of 0.15 ⁇ m in a width of 300 ⁇ m in the cross section of the insulating substrate.
  • the average roughness obtained in the range of 3 ⁇ m in width is 0.02 ⁇ m or more, the adhesion strength between the insulating substrate and the sealing resin is improved, and high adhesion strength is maintained even at high temperatures, Since peeling of the sealing resin is suppressed, the durability of the semiconductor module can be improved.
  • relatively rough irregularities are formed on the surface of the insulating substrate by wet blasting, and the surface to which the metal foil is not bonded and the sealing resin is directly bonded
  • fine irregularities can be further formed on the surface of the relatively rough irregularities, and the rough surface on which the fine irregularities are further formed is sealed.
  • the adhesion strength of the stop resin can be further increased, and the peeling of the sealing resin can be suppressed.
  • the insulated circuit board of the present invention when used as an insulated circuit board of a semiconductor module and sealed with a sealing resin, the adhesion strength between the insulating substrate and the sealing resin is improved, and high adhesion is achieved even at high temperatures. Since the strength is maintained and the peeling of the sealing resin is suppressed, the durability of the semiconductor module can be improved.
  • FIG. 1 shows an embodiment of a semiconductor module to which the present invention is applied.
  • the semiconductor module 50 is a power semiconductor module, and a circuit pattern 24 is formed on the upper surface of the insulating substrate 23, and a metal plate 22 having good thermal conductivity is bonded to the lower surface of the insulating substrate 23.
  • the insulating substrate 23, the circuit pattern 24, and the metal plate 22 constitute an insulating circuit substrate 21.
  • a ceramic substrate mainly composed of aluminum nitride, alumina, silicon nitride, or the like is preferably used, but a metal plate surface such as aluminum coated with an insulating resin layer can also be used.
  • a ceramic substrate made of an aluminum nitride sintered body is particularly preferred.
  • the average crystal grain size of the ceramic of the ceramic substrate is preferably 0.5 to 20 ⁇ m, more preferably 2 to 7 ⁇ m.
  • the aluminum nitride sintered body can be obtained by firing a molded body made of an aluminum nitride raw material powder having an average particle size of 0.1 to 15 ⁇ m.
  • the molded body can be made of a sintering aid, an organic binder, if necessary. Etc. may be included.
  • a pattern obtained by etching a metal foil joined to the insulating substrate 23 via a brazing material is preferably employed.
  • metal foil For example, copper is employ
  • the metal plate 22 is not particularly limited as long as it has good thermal conductivity.
  • a metal plate such as copper, aluminum, a copper alloy, and an aluminum alloy is used.
  • semiconductor elements 25 and 26 are joined via solder 29.
  • the external terminals 12 are erected via solder 29, and the semiconductor elements 25 and 26 and the external terminals 12 are connected by the circuit pattern 24 and bonding wires 27.
  • the semiconductor elements 25 and 26 are, for example, IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Semiconductor Field Effect Transistors).
  • the IGBT may be RB-IGBT (Reverse-Blocking-IGBT) or RC-IGBT (Reverse-Conducting-IGBT).
  • sealing resin 28 an epoxy resin, a maleimide resin, a silicone resin, a liquid crystal polymer etc. are used.
  • the sealing resin 28 is in close contact with each of the insulating substrate 23, the circuit pattern 24, the semiconductor elements 25 and 26, the lower portion of the external terminal 12, and the side surface of the metal plate 22. It has a surface (hereinafter referred to as “sealing resin contact surface”) 23 a that is in close contact (adhesion) with the stop resin 28.
  • the sealing resin adhesion surface 23 a is formed on the peripheral edge of the insulating substrate 23 so as to surround the outer periphery of the circuit pattern 24 and the metal plate 22. In this embodiment, the peripheral edge on the upper surface side of the insulating substrate 23.
  • the outer peripheral side surface of the insulating substrate 23 and the peripheral portion on the lower surface side of the insulating substrate 23 located on the outer periphery of the metal plate 22 also serve as the sealing resin adhesion surface 23a.
  • FIG. 2 shows another embodiment of a semiconductor module to which the present invention is applied.
  • This semiconductor module 50 a is also a power semiconductor module, and a circuit pattern 24 is formed on the upper surface of the insulating substrate 23, and a metal plate 22 having good thermal conductivity is bonded to the lower surface of the insulating substrate 23.
  • the insulating substrate 23, the circuit pattern 24, and the metal plate 22 constitute an insulating circuit substrate 21.
  • a resin frame-like case 13 surrounding the insulating circuit board 21 is provided, and the peripheral edge of the insulating circuit board 21 is fixed to the case 13 via the adhesive 14. Yes.
  • the lower portion of the external terminal 12 bent in an L shape is integrally formed so as to penetrate the case 13 and be exposed in the case 13, thereby constituting the insert case 11.
  • semiconductor elements 25 and 26 are joined via solder 29.
  • the semiconductor elements 25 and 26 and the external terminal 12 are connected by a circuit pattern 24 and a bonding wire 27.
  • the inside of the case 13 is filled with a sealing resin 28, and the insulating substrate 23, the circuit pattern 24, the semiconductor elements 25 and 26, and the lower portions of the external terminals 12 are sealed with the sealing resin 28.
  • the insulating substrate 23 has a sealing resin contact surface 23 a that is in close contact (adhesion) with the sealing resin 28.
  • the sealing resin contact surface 23 a is formed on the peripheral edge of the insulating substrate 23.
  • the feature of the semiconductor module of the present invention is that in the semiconductor modules 50 and 50a as described above, the surface roughness of the insulating resin contact surface 23a of the insulating substrate 23 is set to a specific surface roughness.
  • the average roughness obtained in the range of 300 ⁇ m width of the sealing resin contact surface 23a of the insulating substrate 23 is 0.15 ⁇ m or more, and the average obtained in the range of 3 ⁇ m width.
  • the roughness is 0.02 ⁇ m or more.
  • FIG. 3 illustrates the surface shape of the cross section of the insulating substrate 23 on the sealing resin contact surface 23a.
  • the surface shape is extracted from the cross section of the insulating substrate 23 by taking a cross section perpendicular to the surface of the substrate with a scanning electron microscope to prepare an SEM image, and binarizing the SEM image to obtain image data reflecting the surface shape. This can be done by preparing and converting the image data into two-dimensional coordinate data.
  • the binarization of the SEM image can be created by maximizing the contrast with software having an image processing function, such as “Microsoft PowerPoint” (trade name, manufactured by Microsoft Corporation). Note that software other than the above may be used as software having an image processing function.
  • FIG. 3A shows a shape taken out along the surface of the cross section of the insulating substrate 23 so that the width indicated by the arrow in the drawing becomes 300 ⁇ m
  • 30 shows the surface of the crystal grain.
  • the surface shape of FIG. 3A (width 300 ⁇ m) can be taken out using, for example, an SEM image taken at 1000 times, and FIG.
  • the surface shape of 3 ⁇ m) can be taken out by using, for example, an SEM image obtained by photographing the crystal grain surface at a magnification of 15000 times.
  • the binarized surface shape image is digitized using image digitizing software such as “Graphcel” (trade name, freeware), and spreadsheet software such as “Microsoft Excel” (trade name, manufactured by Microsoft).
  • image digitizing software such as “Graphcel” (trade name, freeware)
  • spreadsheet software such as “Microsoft Excel” (trade name, manufactured by Microsoft).
  • Za represents the average roughness.
  • Zn represents the difference between the two-dimensional coordinate data and the average value at each n.
  • N is a value obtained by dividing the measurement width by the measurement pitch.
  • the average roughness was measured at three or more locations on the surface shape from the cross section, and the average value was taken as the measured value.
  • the width 300 ⁇ m indicated by the arrow in FIG. 3A is set as the reference length L, and the average roughness obtained from the surface shape of the portion by the formula shown in FIG. 4 is 0.15 ⁇ m or more.
  • the average roughness obtained from the surface shape of the portion by the formula shown in FIG. 4 is set to 0.02 ⁇ m or more. .
  • the sealing resin bonding surface 23a of the insulating substrate 23 By making the sealing resin bonding surface 23a of the insulating substrate 23 have the above surface shape, the adhesion strength between the insulating substrate 23 and the sealing resin 28 is improved, and high adhesion strength is maintained even at high temperatures. Since peeling of the sealing resin is suppressed, the durability of the semiconductor module can be improved.
  • the sealing resin bonding surface 23a of the insulating substrate 23 is formed on the periphery of the insulating substrate 23 so as to surround the circuit pattern 24, and the circuit pattern 24 is prevented from being peeled off at that portion.
  • the semiconductor elements 25 and 26 bonded thereto can be more firmly protected, and the reliability can be improved.
  • the average roughness obtained in the range of the width 300 ⁇ m of the sealing resin bonding surface 23 a of the insulating substrate 23 is 0.7 ⁇ m or more in order to further increase the adhesion strength between the insulating substrate 23 and the sealing resin 28. It is preferable that the thickness is 1.1 ⁇ m or more. However, the average roughness obtained in the range of the width of 300 ⁇ m is preferably 2 ⁇ m or less so as not to hinder the formation of the circuit pattern 24 and the like.
  • substrate 23 is 0.1 micrometer or less, when raising the adhesive strength of the insulating board
  • a ceramic substrate is used as the insulating substrate 23.
  • a ceramic substrate made of an aluminum nitride sintered body is preferably used.
  • the surface of the insulating substrate 23 is wet blasted to roughen the cross section of the insulating substrate 23 so that the average roughness obtained in the range of 300 ⁇ m width is 0.15 ⁇ m or more.
  • the wet blast treatment can be performed by using abrasive grains having a hardness higher than that of the ceramic substrate, and spraying the ceramic substrate together with compressed air as a liquid containing the abrasive grains.
  • the value of the average roughness obtained in the range of 300 ⁇ m width can be adjusted by adjusting the size of the abrasive grains and the injection pressure.
  • the insulating substrate 23 is heat-treated, and the surface of the insulating substrate 23 is oxidized.
  • the heat treatment can be performed, for example, at 800 to 1200 ° C., preferably 1000 to 1100 ° C. for 2 to 12 hours.
  • a brazing material is applied to the surface of the insulating substrate 23.
  • the brazing material for example, an active metal brazing material containing at least one active metal selected from Ti, Zr, Hf, Nb and the like in an Ag—Cu brazing material is preferably used. Sn, In, etc. may be included as necessary.
  • a paste-like brazing material can be preferably used.
  • the brazing material can be applied, for example, by screen printing, a roll coater, or the like.
  • the brazing material is usually applied only to the surface of the insulating substrate 23 where the metal foil for forming the circuit pattern 24 is joined.
  • the brazing material is also applied to the portion of the insulating substrate 23 that becomes the sealing resin bonding surface 23a where the metal foil is not bonded.
  • a brazing material is applied to the entire surface of the sealing resin bonding surface 23 a of the insulating substrate 23.
  • Metal foil joining process Next, by installing a metal foil for forming the circuit pattern 24 at a predetermined portion of the portion where the brazing material on the surface of the insulating substrate 23 is applied, and pressing in that state as necessary, heat treatment is performed. The brazing material is melted, and the metal foil is bonded to the surface of the insulating substrate 23 through the brazing material.
  • circuit pattern formation process After joining the metal foils in this way, the metal foil and the brazing material are etched and patterned by a known method such as photoetching to form the circuit pattern 24.
  • the surface of the insulating substrate 23 that appears by etching away the brazing material fixed on the surface of the insulating substrate 23 has an average roughness of 0.15 ⁇ m or more obtained in the range of 300 ⁇ m in the surface treatment step.
  • fine unevenness having an average roughness of 0.02 ⁇ m or more obtained in the range of 3 ⁇ m in width is formed on a relatively large uneven surface formed by roughening.
  • the fine irregularities are formed by etching and removing the brazing material fixed on the surface of the insulating substrate 23. Even if the surface of the insulating substrate 23 is oxidized, the irregularities are not formed. Not formed. For this reason, in the present invention, in the brazing material application step, the brazing material is applied also to the portion of the insulating substrate 23 that becomes the sealing resin bonding surface 23a where the metal foil is not bonded.
  • the semiconductor modules 50 and 50a can be manufactured by sealing the insulating substrate 23, the circuit pattern 24, the semiconductor elements 25 and 26, the lower portions of the external terminals 12, and the like with the sealing resin 28. .
  • the semiconductor modules 50 and 50a obtained in this way have relatively rough irregularities in which the surface roughness on the sealing resin bonding surface 23a of the insulating substrate 23 has an average roughness of 0.15 ⁇ m or more obtained in the range of a width of 300 ⁇ m. On the relatively large uneven surface, fine unevenness having an average roughness of 0.02 ⁇ m or more obtained in the range of 3 ⁇ m in width is formed. Therefore, as described above, the insulating substrate 23 and the sealing resin 28 are formed. The adhesion strength is improved, the high adhesion strength is maintained even at high temperatures, and the peeling of the sealing resin is suppressed, so that the durability of the semiconductor module can be improved.
  • Adhesion strength between insulating substrate and sealing resin using ceramic substrate made of aluminum nitride sintered body as insulating substrate, epoxy resin as sealing resin, changing surface roughness of insulating substrate was measured.
  • a shape and size shown in FIG. 5 are obtained by stacking a mold (not shown) on the insulating substrate 23, injecting a resin into a hole provided in the mold, and curing by heating at 170 ° C. for 60 minutes.
  • a sealing resin 28 having a truncated cone shape with a bottom diameter of 3.57 mm, a top diameter of 3 mm, and a height of 4 mm was molded in a state of being bonded to the insulating substrate 23.
  • This sample is used as a share testing machine (product name "DIGITAL FORCE GAUGE Model ZP-1000N", made by Imada Co., Ltd., product name “FORCE GAUGE STAND Model FGS-50D”, made by Simpo Industry Co., Ltd.) set, pressing the plunger 40 against the molded sealing resin 28, to measure the maximum load (kgf) when the broken by pressing Share speed 0.03 mm / sec, the load at 10 mm 2 The adhesion strength (MPa) was determined by dividing.
  • Test Example 1 Comparative Example 1 Ceramic substrate (hereinafter referred to as “standard product”) made of an aluminum nitride sintered body having a surface roughness of an average roughness of 0.10 ⁇ m obtained in a width of 300 ⁇ m and an average roughness of 0.015 ⁇ m obtained in a range of 3 ⁇ m in width. )), A molded body of the sealing resin 28 was formed by the method described above.
  • the brazing material was removed by immersing in an aqueous solution containing at 30 ° C. for 30 minutes.
  • a ceramic substrate having a surface roughness of an average roughness of 0.10 ⁇ m obtained in the range of 300 ⁇ m in width and 0.025 ⁇ m of average roughness obtained in the range of 3 ⁇ m in width was formed.
  • a molded body of the sealing resin 28 was formed on the surface of the substrate by the method described above.
  • Comparative Example 3 The surface of the standard ceramic substrate was treated with wet blasting manufactured by Fuji Kiko Co., Ltd. with alumina abrasive material No. 320 at a pressure of 0.2 MPa, and then the ceramic substrate was heated in the atmosphere at 1050 ° C. for 2 hours to obtain the surface.
  • a molded body of the sealing resin 28 was formed on the surface of the substrate by the method described above.
  • Example 1 The surface of the standard ceramic substrate was oxidized by wet blasting under the same conditions as in Comparative Example 3, and the average roughness obtained in the range of 300 ⁇ m width was 0.33 ⁇ m, and the average roughness obtained in the range of 3 ⁇ m width was A ceramic substrate having a surface roughness of 0.015 ⁇ m was formed.
  • a brazing material is applied under the same conditions as in Comparative Example 2, a copper foil is laminated, and the brazing material is heated and melted and solidified at 850 ° C. in a vacuum, whereby the copper foil is applied to the ceramic substrate surface via the brazing material. After fixing, the copper foil, the brazing material and the reaction layer were removed by immersion in an etching solution in the same manner as in Comparative Example 2.
  • a ceramic substrate having a surface roughness with an average roughness of 0.33 ⁇ m determined within a width of 300 ⁇ m and an average roughness of 0.025 ⁇ m determined within a width of 3 ⁇ m was formed.
  • a molded body of the sealing resin 28 was formed on the surface of the substrate by the method described above.
  • Example 1 in which the molded body of the sealing resin 28 was formed on the surface of the ceramic substrate subjected to the treatment of Example 1, the adhesion strength was remarkably improved at both room temperature and high temperature. In addition, it was possible to exceed 25 MPa, which is a target value for sufficiently imparting heat resistance and durability of the semiconductor module.
  • Test Example 2 An average roughness obtained in the range of 300 ⁇ m in width by the same manufacturing method as in Example 1 except that a ceramic substrate (standard product) made of an aluminum nitride sintered body was used and the wet brass treatment conditions (treatment time) were changed. I made something different.
  • required in the range of 3 micrometers in width was 0.02 micrometer or more in all except one part.
  • a molded body of the sealing resin 28 was formed on the surface of each ceramic substrate thus obtained, and the adhesion strength was measured at room temperature by the method shown in FIG. The result is shown in FIG.
  • black circles indicate that the average roughness obtained in the range of 3 ⁇ m width is 0.02 ⁇ m or more, and black triangles indicate that the average roughness obtained in the range of 3 ⁇ m width is less than 0.02 ⁇ m.
  • the vertical axis in FIG. 7 represents the average roughness value obtained in the range of 300 ⁇ m width, and the horizontal axis represents the adhesion strength (MPa) value.
  • the average roughness obtained in the range of 300 ⁇ m width is close to 2 ⁇ m, the adhesion strength tends not to be further improved.
  • the average roughness obtained in the range of 300 ⁇ m width is preferably 0.15 to 2.0 ⁇ m, more preferably 0.7 to 2.0 ⁇ m, and most preferably 1.1 to 2.0 ⁇ m.

Abstract

絶縁性基板と封止樹脂との接合性がより向上した半導体モジュール及びその製造方法を提供する。 この半導体モジュール５０は、絶縁性基板２３と、該絶縁性基板上に形成された回路パターン２４と、該回路パターン上に接合された半導体素子２５，２６と、前記絶縁性基板、前記回路パターン及び前記半導体素子を封止する封止樹脂２８とを備えている。そして、前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面２３ａは、前記絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μm以上であることを特徴とする。

Description

半導体モジュール及びその製造方法
　本発明は、絶縁性基板上に回路パターンを介して半導体素子が接合され、絶縁性基板、回路パターン及び半導体素子が封止樹脂で封止された構造の半導体モジュール及びその製造方法に関する。
　例えば下記特許文献１に示されるような、電力変換用のスイッチングデバイスとして用いられるパワー半導体モジュール等では、絶縁性、耐熱性、耐久性を付与するために、絶縁性基板、回路パターン及び半導体素子が封止樹脂で封止された構造をなしている。
　しかしながら、スイッチングデバイスとして作動する際に発生する熱により、繰り返し高温に晒されることにより、絶縁性基板と封止樹脂との接着面が剥離し、剥離が内部に伸展することで、浸水、配線のリフトオフ等の不具合を引き起こす可能性があった。
　これに対して、絶縁性基板表面を粗化してアンカー効果を高めることにより、金属膜や封止樹脂との接着性を高める技術が開示されている。
　例えば下記特許文献２には、金属膜との密着力を向上させるため、イオンビームエッチング処理により結晶粒子表面に微細凹凸を形成するセラミック回路基板の製造方法が開示されている。
　また、下記特許文献３には、アンカー効果を向上するため、結晶粒子表面に酸性エッチング処理による結晶粒子径より小さい径の複数の突起部を形成したセラミックス部材が開示されている。
　また、下記特許文献４には、平均結晶粒径より大きな凹凸を有する窪み・突起を複数備えているセラミック基体により、ろう材のアンカー効果を高めることが記載されている。
　更に、下記特許文献５には、窒化アルミ基板の表面に砥粒を当てることで表面粗化し、金属回路箔の接合強度を向上することが記載されている。
　更に、下記特許文献６には、回路基板と、回路基板が搭載されたヒートシンクと、回路基板と電気的に接続されたリードと、回路基板及び回路基板とリードとの接続部を被覆し、リードの一部及びヒートシンクの一部が外部に露出するように、封止樹脂を配置してなる封止樹脂部と、を備える電子制御装置であって、回路基板の表面及びヒートシンクの表面の少なくとも一方の、封止樹脂部と接する部位の少なくとも一部が、粗化処理されているものが開示されている。
特開２０１３－２５８３２１号公報 特開平５－２４９５９号公報 特開２００２－２４１１８７号公報 特開２０１０－３０２８０号公報 特開２０１３－２７９１８号公報 特開２００８－１７２１７２号公報
　しかしながら、上記特許文献１～５では、絶縁性基板と封止樹脂との密着強度を改善するための絶縁性基板の表面粗さについては検討されていない。また、上記特許文献６には、粗化処理の条件について詳細が記載されていない。
　したがって、上記従来技術に開示された技術では、絶縁性基板と封止樹脂との密着性の改善効果が、未だ十分とは言えなかった。
　したがって、本発明の目的は、絶縁性基板と封止樹脂との密着性がより向上した半導体モジュール及びその製造方法を提供することにある。
　上記目的を達成するため、本発明の半導体モジュールは、
　絶縁性基板と、
　該絶縁性基板上に形成された回路パターンと、
　該回路パターン上に接合された半導体素子と、
　前記絶縁性基板、前記回路パターン及び前記半導体素子を封止する封止樹脂とを備えた半導体モジュールにおいて、
　前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、前記絶縁性基板の断面において、下記方法によって測定し算出した、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μｍ以上であることを特徴とする半導体モジュール。
（平均粗さの測定・算出方法）
前記絶縁性基板の断面を走査電子顕微鏡で撮影してＳＥＭ画像を用意し、前記ＳＥＭ画像を２値化して表面形状の画像データを用意し、前記画像データを画像数値化ソフトを用いて２次元座標データに変換し、下記数式により平均粗さＺａを計算して求める。
Figure JPOXMLDOC01-appb-M000004
　上記数式中、Ｚａは平均粗さを表す。Ｚｎは各ｎにおける前記２次元座標データと平均値との差を表す。Ｎは測定幅を測定ピッチで割った値であり、幅３００μｍの粗さ計算時はピッチ＝０．５μｍ、すなわちＮ＝６００、幅３μｍの粗さ計算時はピッチ＝０．００５μｍ、すなわちＮ＝６００とする。
　本発明の半導体モジュールにおいては、前記絶縁性基板と前記封止樹脂とが密着した部分は、前記絶縁性基板の周縁部を含んでいることが好ましい。
　また、前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、前記絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが２μm以下であることが好ましい。
　更に、前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、前記絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが０．７μm以上であることが好ましい。
　更にまた、前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、幅３μｍの範囲で求めた平均粗さが０．１μm以下であることが好ましい。
　一方、本発明の半導体モジュールの製造方法は、
　セラミックス製の絶縁性基板の表面粗さを調整する表面処理工程と、
　前記絶縁性基板を加熱処理して前記絶縁性基板の表面を酸化する酸化処理工程と、
　前記絶縁性基板の表面にろう材を塗布するろう材塗布工程と、
　前記ろう材を介して金属箔を前記絶縁性基板表面に接合する金属箔接合工程と、
　前記金属箔と前記ろう材とをエッチングして回路パターンを形成する回路パターン形成工程と、
　前記回路パターン上に半導体素子を接合する半導体素子実装工程と、
　前記絶縁性基板、前記回路パターン及び前記半導体素子を、封止樹脂で封止する封止工程とを含む半導体モジュールの製造方法であって、
　前記表面処理工程は、前記絶縁性基板の表面をウェットブラスト処理して、前記絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上となるように粗面化する工程からなり、
　前記ろう材塗布工程は、前記絶縁性基板表面の、前記金属箔が接合される面だけでなく、前記金属箔が接合されない面であって前記封止樹脂が密着する面に対しても、ろう材を塗布する工程からなり、
　前記回路パターン形成工程において、前記ろう材が塗布された部分をエッチングすることによって、前記絶縁性基板の前記封止樹脂が密着する面が、前記絶縁性基板の断面において、前述した方法によって測定し算出した、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μm以上である表面粗さとなることを特徴とする。
　本発明の半導体の製造方法においては、前記絶縁性基板は、セラミックス製であることが好ましく、窒化アルミニウムからなることがより好ましい。
　また、本発明の絶縁回路基板は、絶縁性基板と、
　該絶縁性基板上に形成された回路パターンとを有する絶縁回路基板において、
　前記絶縁性基板の前記回路パターンが形成されていない部分の表面は、前記絶縁性基板の断面において、前述した方法によって測定し算出した、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μｍ以上であることを特徴とする。
　本発明の半導体モジュールによれば、絶縁性基板と封止樹脂とが密着した部分における絶縁性基板の表面は、絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μm以上であることにより、絶縁性基板と封止樹脂との密着強度が向上し、高温下においても高い密着強度が維持され、封止樹脂の剥離が抑制されるので、半導体モジュールの耐久性を向上させることができる。
　本発明の半導体モジュールの製造方法によれば、絶縁性基板表面に、ウェットブラスト処理によって比較的粗い凹凸を形成し、更に、金属箔が接合されない面であって封止樹脂が直接接着される面に対しても、ろう材を塗布しエッチングすることにより、比較的粗い凹凸の表面に微小な凹凸を更に形成することができ、粗い凹凸表面に微小な凹凸が更に形成された粗面によって、封止樹脂の密着強度を更に高めて、封止樹脂の剥離を抑制することができる。
　本発明の絶縁回路基板によれば、半導体モジュールの絶縁回路基板として用い、封止樹脂で封止した際に、絶縁性基板と封止樹脂との密着強度が向上し、高温下においても高い密着強度が維持され、封止樹脂の剥離が抑制されるので、半導体モジュールの耐久性を向上させることができる。
本発明の実施形態に係る半導体モジュールの断面図である。 本発明の別の実施形態に係る半導体モジュールの断面図である。 本発明の半導体モジュールの絶縁性基板表面の粗さを示す模式図である。 平均粗さの計算式や概念を示す説明図である。 絶縁性基板と封止樹脂との剥離強度の測定方法を示す説明図である。 絶縁性基板と封止樹脂との剥離強度の測定結果を示す図表である。 絶縁性基板と封止樹脂との剥離強度の別の測定結果を示す図表である。
　以下、図面を参照しながら本発明の半導体モジュールの実施形態を説明する。
　図１には、本発明が適用される半導体モジュールの一実施形態が示されている。この半導体モジュール５０は、パワー半導体モジュールであって、絶縁性基板２３の上面に、回路パターン２４が形成され、絶縁性基板２３の下面に熱伝導のよい金属板２２が接合されている。絶縁性基板２３と、回路パターン２４と、金属板２２とによって、絶縁回路基板２１が構成されている。
　絶縁性基板２３としては、例えば窒化アルミニウム、アルミナ、窒化ケイ素等を主成分とするセラミックス基板が好ましく用いられるが、アルミニウムなどの金属板表面に絶縁樹脂層を被覆したものなどを用いることもできる。特に好ましくは窒化アルミニウム焼結体からなるセラミックス基板である。セラミックス基板のセラミックスの平均結晶粒径は、０．５～２０μｍが好ましく、２～７μｍがより好ましい。窒化アルミニウム焼結体は、平均粒子径が０．１～１５μｍの窒化アルミニウム原料粉末からなる成形体を焼成することにより得ることができ、成形体は、必要に応じて焼結助剤、有機バインダ等を含んでもよい。
　回路パターン２４としては、絶縁性基板２３にろう材を介して接合された金属箔をエッチングによってパターン化したものが好ましく採用される。金属箔としては、特に限定されないが、例えば銅が好ましく採用される。金属板２２は、熱伝導性のよいものであれば、特に限定されないが、例えば銅、アルミニウム、銅合金、アルミニウム合金などの金属板が用いられる。
　そして、回路パターン２４上には、はんだ２９を介して半導体素子２５、２６が接合されている。また、回路パターン２４上には、はんだ２９を介して外部端子１２が立設され、半導体素子２５、２６と外部端子１２とは、回路パターン２４やボンディングワイヤ２７によって接続されている。
　半導体素子２５、２６は、例えば、ＩＧＢＴ（Insulated Gate Bipolar Transistor）やパワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）である。ＩＧＢＴはＲＢ－ＩＧＢＴ（Reverse Blocking-IGBT）やＲＣ－ＩＧＢＴ（Reverse Conducting-IGBT）であってもよい。
　更に、金属板２２の下面と、外部端子１２の上方部分を残して、絶縁性基板２３、回路パターン２４、半導体素子２５、２６、外部端子１２の下方部分、及び金属板２２の側面が、封止樹脂２８によって封止されている。封止樹脂２８としては、特に限定されないが、例えばエポキシ樹脂、マレイミド樹脂、シリコーン樹脂、液晶ポリマーなどが用いられる。
　封止樹脂２８は、絶縁性基板２３、回路パターン２４、半導体素子２５、２６、外部端子１２の下方部分、及び金属板２２の側面のそれぞれに密着しているが、絶縁性基板２３は、封止樹脂２８と密着（接着）した面（以下「封止樹脂密着面」とする）２３ａを有している。封止樹脂密着面２３ａは、回路パターン２４および金属板２２の外周を囲むように、絶縁性基板２３の周縁部に形成されており、この実施形態では、絶縁性基板２３の上面側の周縁部に加え、絶縁性基板２３の外周側面や、金属板２２の外周に位置する、絶縁性基板２３の下面側の周縁部も、封止樹脂密着面２３ａとなっている。
　図２には、本発明が適用される半導体モジュールの他の実施形態が示されている。この半導体モジュール５０ａも、パワー半導体モジュールであって、絶縁性基板２３の上面に、回路パターン２４が形成され、絶縁性基板２３の下面に熱伝導のよい金属板２２が接合されている。絶縁性基板２３と、回路パターン２４と、金属板２２とによって、絶縁回路基板２１が構成されている。
　ただし、この半導体モジュール５０ａでは、絶縁回路基板２１を囲む、樹脂製の枠状のケース１３が設けられており、絶縁回路基板２１の周縁部が、接着剤１４を介してケース１３に固着されている。ケース１３には、Ｌ字状に折曲された外部端子１２の下方部分が、ケース１３を貫通してケース１３内に露出するように一体成形されて、インサートケース１１を構成している。
　そして、回路パターン２４上には、はんだ２９を介して半導体素子２５、２６が接合されている。半導体素子２５，２６と外部端子１２とは、回路パターン２４やボンディングワイヤ２７によって接続されている。
　更に、ケース１３の内部には、封止樹脂２８が充填され、絶縁性基板２３、回路パターン２４、半導体素子２５、２６、外部端子１２の下方部分が、封止樹脂２８によって封止されている。この実施形態の場合も、絶縁性基板２３は、封止樹脂２８と密着（接着）した封止樹脂密着面２３ａを有している。封止樹脂密着面２３ａは、絶縁性基板２３の周縁部に形成されている。
　本発明の半導体モジュールの特徴は、上記のような半導体モジュール５０，５０ａにおいて、絶縁性基板２３の封止樹脂密着面２３ａにおける表面粗さを、特定の表面粗さとなるようにしたことにある。
　すなわち、本発明の半導体モジュール５０，５０ａは、絶縁性基板２３の封止樹脂密着面２３ａの幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μm以上であることを特徴としている。以下、本発明で採用した上記平均粗さの測定、算出方法について詳しく説明する。
　図３は、封止樹脂密着面２３ａにおいて、絶縁性基板２３の断面における表面形状を図示したものである。絶縁性基板２３の断面からの表面形状の抽出は、基板の表面に直角な断面を走査電子顕微鏡で撮影してＳＥＭ画像を用意し、ＳＥＭ画像を２値化して表面形状を反映する画像データを用意し、画像データを２次元座標データに変換することによって行うことができる。
　ＳＥＭ画像の２値化は、画像処理機能を有するソフトウェア、例えば「Microsoft PowerPoint」（商品名、マイクロソフト社製）で、コントラストを最大にすることで作成することができる。なお、画像処理機能を有するソフトウェアとしては、上記以外のソフトウェアを用いても良い。
　図３（Ａ）は、絶縁性基板２３の断面の表面に沿って、図中矢印で示す幅が３００μｍとなるように取出した形状であり、同図（Ｂ）は、その一部を図中矢印で示す幅が３μｍとなるように取出した形状である。なお、３０は、結晶粒の表面を示している
　図３（Ａ）（幅３００μｍ）の表面形状は、例えば１０００倍で撮影したＳＥＭ画像を用いて取出すことができ、図３（Ｂ）（幅３μｍ）の表面形状は、例えば結晶粒の表面を１５０００倍の倍率で撮影したＳＥＭ画像を用いて取出すことができる。
　こうして２値化した表面形状の画像を、画像数値化ソフト、例えば「Graphcel」（商品名、フリーウェア）を用いて数値化し、表計算ソフト、例えば「Microsoft Excel」（商品名、マイクロソフト社製）で、図４に示した下記数式により平均粗さを計算して求めることができる。
Figure JPOXMLDOC01-appb-M000005
　上記数式中、Ｚａは平均粗さを表す。Ｚｎは各ｎにおける前記２次元座標データと平均値との差を表す。Ｎは測定幅を測定ピッチで割った値であり、幅３００μｍの粗さ計算時はピッチ＝０．５μｍ、すなわちＮ＝６００、幅３μｍの粗さ計算時はピッチ＝０．００５μｍ、すなわちＮ＝６００とする。
　なお、平均粗さの測定は、断面からの表面形状の３箇所以上で行い、その平均値を測定値とした。
　そして、本発明では、例えば図３（Ａ）の矢印で示す幅３００μｍを基準長さＬとして、その部分の表面形状から、図４に示す式により平均粗さを求めた値が０．１５μm以上となるようにする。また、図３（Ｂ）の矢印で示す幅３μｍを基準長さＬとして、その部分の表面形状から、図４に示す式により平均粗さを求めた値が０．０２μm以上となるようにする。
　絶縁性基板２３の封止樹脂接着面２３ａを上記のような表面形状とすることにより、絶縁性基板２３と封止樹脂２８との密着強度が向上し、高温下においても高い密着強度が維持され、封止樹脂の剥離が抑制されるので、半導体モジュールの耐久性を向上させることができる。また、絶縁性基板２３の封止樹脂接着面２３ａが、絶縁性基板２３の周縁に、回路パターン２４を囲むように形成されており、その部分での剥離が抑制されることにより、回路パターン２４やそれに接合された半導体素子２５，２６をより強固に保護することができ、信頼性を高めることができる。
　なお、絶縁性基板２３の封止樹脂接着面２３ａの幅３００μｍの範囲で求めた平均粗さは、絶縁性基板２３と封止樹脂２８との密着強度をより高めるために、０．７μm以上であることが好ましく、１．１μm以上であることが更に好ましい。しかし、回路パターン２４等の形成に支障を与えないように、上記幅３００μｍの範囲で求めた平均粗さは、２μm以下であることが好ましい。
　また、絶縁性基板２３の封止樹脂接着面２３ａの幅３μｍの範囲で求めた平均粗さは、絶縁性基板２３と封止樹脂２８との密着強度を高める上で、０．１μm以下であることが好ましい。
　次に、本発明の半導体モジュールの製造方法について説明する。
　（表面処理工程）
　本発明の半導体モジュールの製造方法においては、絶縁性基板２３として、セラミックス基板を用いる。特には、窒化アルミニウム焼結体からなるセラミックス基板が好ましく用いられる。
　そして、絶縁性基板２３の表面をウェットブラスト処理して、絶縁性基板２３の断面において、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上となるように粗面化する。
　ウェットブラスト処理は、セラミックス基板より高い硬度を有する砥粒を使用し、該砥粒を含む液体として、圧縮空気と共に、セラミックス基板に噴射することによって行うことができる。このとき、砥粒の粒子の大きさや、噴射圧力を調整することによって、幅３００μｍの範囲で求めた平均粗さの値を調整することができる。
　（酸化処理工程）
　次に、絶縁性基板２３を加熱処理して、絶縁性基板２３の表面を酸化処理する。加熱処理は、例えば800～1200℃好ましくは1000℃～1100℃で2～12時間保持して行うことができる。
　（ろう材塗布工程）
　次に、絶縁性基板２３の表面にろう材を塗布する。ろう材としては、例えばAg-Cu系ろう材にTi、Zr、Hf、Nbなどから選ばれる少なくとも１種の活性金属を含む活性金属ろう材を使用するのが好ましい。必要に応じてSn、Inなどを含んでいてもよい。前記活性金属ろう材はペースト状のろう材を好ましく用いることができる。ろう材の塗布は、例えばスクリーン印刷、ロールコーター等によって行うことができる。
　従来、ろう材は、絶縁性基板２３表面の、回路パターン２４を形成するための金属箔を接合する部分にのみ塗布されるのが通常である。しかし、本発明では、絶縁性基板２３の封止樹脂接着面２３ａとなる部分の、金属箔が接合されない部分にもろう材を塗布する。好ましくは、絶縁性基板２３の封止樹脂接着面２３ａ全面にろう材を塗布する。
　（金属箔接合工程）
　次に、絶縁性基板２３表面のろう材を塗布した部分の所定箇所に、回路パターン２４を形成するための金属箔を設置し、その状態で必要により押圧して、加熱処理することにより、上記ろう材を溶融させて、ろう材を介して金属箔を絶縁性基板２３表面に接合する。
　（回路パターン形成工程）
　こうして金属箔を接合した後、フォトエッチング等の周知の方法で、金属箔及びろう材をエッチングしてパターニングし、回路パターン２４を形成する。
　このとき、絶縁性基板２３表面に固着されたろう材を、エッチング除去して現れる絶縁性基板２３の表面は、前記表面処理工程で、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上となるように粗面化して形成された比較的大きな凹凸表面に、幅３μｍの範囲で求めた平均粗さが０．０２μm以上となる微細な凹凸が形成されたものとなる。
　上記微細な凹凸は、絶縁性基板２３表面に固着されたろう材をエッチング除去して形成されるものであり、絶縁性基板２３を酸化処理しただけの表面をエッチングしても、そのような凹凸は形成されない。このため、本発明では、前記ろう材塗布工程において、絶縁性基板２３の封止樹脂接着面２３ａとなる部分の、金属箔が接合されない部分にもろう材を塗布するようにしたのである。
　（半導体素子実装工程）
　こうして回路パターン２４を形成した後、常法に従って、半導体素子２５，２６や、外部端子１２を、はんだ２９を介して接合する。
　（封止工程）
　最後に、絶縁性基板２３、回路パターン２４、半導体素子２５，２６、及び外部端子１２の下方部分等を、封止樹脂２８で封止することにより、半導体モジュール５０、５０ａを製造することができる。
　こうして得られる半導体モジュール５０、５０ａは、絶縁性基板２３の封止樹脂接着面２３ａにおける表面形状が、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上となる比較的粗い凹凸を有すると共に、その比較的大きな凹凸表面に、幅３μｍの範囲で求めた平均粗さが０．０２μm以上となる微細な凹凸が形成されているので、前述したように、絶縁性基板２３と封止樹脂２８との密着強度が向上し、高温下においても高い密着強度が維持され、封止樹脂の剥離が抑制されるので、半導体モジュールの耐久性を向上させることができる。
　絶縁性基板として、窒化アルミニウム焼結体からなるセラミックス基板を用い、封止樹脂として、エポキシ樹脂を用いて、絶縁性基板の表面粗さを変えて、絶縁性基板と封止樹脂との密着強度を測定した。
　（樹脂密着強度の測定方法）
　図５に示すように、絶縁性基板２３上に、図示しない型を重ね、型に設けられた孔に樹脂を注入し、１７０℃で６０分間加熱硬化させることによって、図５に示す形状及び大きさ（底面の直径３．５７ｍｍ、上面の直径３ｍｍ、高さ４ｍｍの円錐台形状）の封止樹脂２８を、絶縁性基板２３に接合された状態で成形した。
　このサンプルをシェア試験機（製品名「DIGITAL FORCE GAUGE Model ZP-1000N」、株式会社イマダ製と、製品名「FORCE GAUGE STAND  Model FGS-50D」、シンポ工業株式会社製とを組み合わせた試験機）にセットし、成形された封止樹脂２８に対してプランジャー４０を押し当て、シェア速度０．０３ｍｍ／ｓｅｃで押圧して破断したときの最大荷重（ｋｇｆ）を測定し、この荷重を１０ｍｍ2で割って密着強度（ＭＰａ）を求めた。
　（試験例１）
　比較例１
　幅３００μｍの範囲で求めた平均粗さが０．１０μm、幅３μｍの範囲で求めた平均粗さが０．０１５μmの表面粗さを有する窒化アルミニウム焼結体からなるセラミックス基板（以下「標準品」とする）の表面に、前述した方法で、封止樹脂２８の成形体を形成した。
　比較例２
　上記標準品のセラミックス基板に活性金属含有ペーストろう材（金属分の重量比としてＡｇ：Ｃｕ：Ｔｉ＝８０：１７：３）を塗布して、該ろう材上に無酸素銅の銅箔を積層し、ろう材を真空中850℃に加熱して溶融、凝固させることにより、ろう材を介して銅箔をセラミックス基板表面に固着させた後、塩化第２銅エッチング液により銅箔を除去し、ついで５％の過酸化水素と３％のアンモニア水と１．６重量％のＥＤＴＡを含む水溶液に２０℃で１５分間浸漬し、水洗した後、２％のＤＴＰＡ・５Ｎａと５％の過酸化水素を含む水溶液に３０℃で３０分間浸漬することにより、ろう材を除去した。こうして、幅３００μｍの範囲で求めた平均粗さが０．１０μm、幅３μｍの範囲で求めた平均粗さが０．０２５μmの表面粗さを有するセラミックス基板を形成した。この基板の表面に、前述した方法で、封止樹脂２８の成形体を形成した。
　比較例３
　上記標準品のセラミックス基板の表面を富士機工製ウェットブラストでアルミナ砥材320番のものを0.2MPaの圧力で処理して、次いで、セラミックス基板を大気中1050℃で2時間加熱処理してその表面を酸化し幅３００μｍの範囲で求めた平均粗さが０．３３μm、幅３μｍの範囲で求めた平均粗さが０．０１５μmの表面粗さを有するセラミックス基板を形成した。この基板の表面に、前述した方法で、封止樹脂２８の成形体を形成した。
　実施例１
　上記標準品のセラミックス基板の表面を比較例3と同じ条件でウェットブラストと酸化処理して、幅３００μｍの範囲で求めた平均粗さが０．３３μm、幅３μｍの範囲で求めた平均粗さが０．０１５μmの表面粗さを有するセラミックス基板を形成した。次いで、比較例2と同じ条件でろう材を塗布して、銅箔を積層し、ろう材を真空中850℃に加熱溶融、凝固させることにより、ろう材を介して銅箔をセラミックス基板表面に固着させた後、比較例２と同様にエッチング液に浸漬して銅箔、ろう材および反応層を除去した。こうして、幅３００μｍの範囲で求めた平均粗さが０．３３μm、幅３μｍの範囲で求めた平均粗さが０．０２５μmの表面粗さを有するセラミックス基板を形成した。この基板の表面に、前述した方法で、封止樹脂２８の成形体を形成した。
　こうして得られた比較例１～３、実施例１のサンプルについて、図５に示した方法により、密着強度（ＭＰａ）を測定した。なお、密着強度の測定は、室温（Ｒ．Ｔ；２５℃）下と、１５０℃の高温下とで行った。その結果を図６に示す。
　図６に示されるように、窒化アルミニウム焼結体からなるセラミックス基板の標準品をそのまま用いた比較例１では、密着強度が極めて低かった。
　また、比較例２の処理を施したセラミックス基板の表面に封止樹脂２８の成形体を形成した比較例２における密着強度の評価では、室温下、高温下のいずれも密着強度が倍近くに向上したが、未だ十分な強度とは言えなかった。
　また、比較例３の処理を施したセラミックス基板の表面に封止樹脂２８の成形体を形成した比較例３における密着強度の評価では、室温下、高温下のいずれも密着強度が向上したが、半導体モジュールの耐熱、耐久性を十分に付与する上での目標値となる２５ＭPａには達しなかった。
　一方、実施例１の処理を施したセラミックス基板の表面に、封止樹脂２８の成形体を形成した実施例１における密着強度の評価では、室温下、高温下のいずれも密着強度が顕著に向上し、半導体モジュールの耐熱、耐久性を十分に付与する上での目標値となる２５ＭPａを超えることができた。
　このように、ウェットブラスト処理によって、比較的大きな凹凸を形成した後、酸化処理し、更に、エッチング処理によって、比較的微細な凹凸を形成し、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上、幅３μｍの範囲で求めた平均粗さが０．０２μm以上となるようにすることにより、絶縁性基板と封止樹脂との密着強度を飛躍的に高めることができることがわかった。
　（試験例２）
　窒化アルミニウム焼結体からなるセラミックス基板（標準品）を用い、ウェットブラス処理の条件（処理時間）を変化させた以外は実施例１と同様の製造方法により、幅３００μｍの範囲で求めた平均粗さを変えたものを作成した。なお、幅３μｍの範囲で求めた平均粗さは、一部を除いて、いずれも０．０２μm以上であった。
　こうして得られたそれぞれのセラミックス基板の表面に、封止樹脂２８の成形体を形成し、室温において、図５に示した方法で密着強度を測定した。その結果を図７に示す。図７において、黒丸は、幅３μｍの範囲で求めた平均粗さが０．０２μm以上のものを示し、黒三角は、幅３μｍの範囲で求めた平均粗さが０．０２μm未満のものを示している。図７の縦軸が、幅３００μｍの範囲で求めた平均粗さの値を表し、横軸が密着強度（ＭＰａ）の値を表している。
　図７に示されるように、幅３００μｍの範囲で求めた平均粗さが高くなるほど、密着強度は向上する傾向があった。しかしながら、幅３００μｍの範囲で求めた平均粗さが２μm近くになると、密着強度はそれ以上には向上しない傾向があった。
　したがって、幅３００μｍの範囲で求めた平均粗さは、０．１５～２．０μmが好ましく、０．７～２．０μmがより好ましく、１．１～２．０μmが最も好ましいことがわかる。
１１　インサートケース
１２　外部端子
１３　ケース
１４　接着剤
２1  絶縁回路基板
２２　金属板
２３　絶縁性基板
２４　回路パターン
２５，２６　半導体素子
２７　ボンディングワイヤ
２８　封止樹脂
２９　はんだ
３０　結晶粒の表面
５０、５０ａ　半導体モジュール

Claims (10)

  1. 　絶縁性基板と、
    　該絶縁性基板上に形成された回路パターンと、
    　該回路パターン上に接合された半導体素子と、
    　前記絶縁性基板、前記回路パターン及び前記半導体素子を封止する封止樹脂とを備えた半導体モジュールにおいて、
    　前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、前記絶縁性基板の断面において、下記方法によって測定し算出した、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μｍ以上であることを特徴とする半導体モジュール。
    　（平均粗さの測定・算出方法）
    　前記絶縁性基板の断面を走査電子顕微鏡で撮影してＳＥＭ画像を用意し、前記ＳＥＭ画像を２値化して表面形状の画像データを用意し、前記画像データを画像数値化ソフトを用いて２次元座標データに変換し、下記数式により平均粗さＺａを計算して求める。
    Figure JPOXMLDOC01-appb-M000001
     　上記数式中、Ｚａは平均粗さを表す。Ｚｎは各ｎにおける前記２次元座標データと平均値との差を表す。Ｎは測定幅を測定ピッチで割った値であり、幅３００μｍの粗さ計算時はピッチ＝０．５μｍ、すなわちＮ＝６００、幅３μｍの粗さ計算時はピッチ＝０．００５μｍ、すなわちＮ＝６００とする。
  2. 　前記絶縁性基板と前記封止樹脂とが密着した部分は、前記絶縁性基板の周縁部を含んでいる、請求項１記載の半導体モジュール。
  3. 　前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、前記絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが２μm以下である、請求項１又は２記載の半導体モジュール。
  4. 　前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、前記絶縁性基板の断面において、幅３００μｍの範囲で求めた平均粗さが０．７μm以上である、請求項１～３のいずれか１項記載の半導体モジュール。
  5. 　前記絶縁性基板と前記封止樹脂とが密着した部分における前記絶縁性基板の表面は、幅３μｍの範囲で求めた平均粗さが０．１μm以下である、請求項１～４のいずれか１項記載の半導体モジュール。
  6. 　セラミックス製の絶縁性基板の表面粗さを調整する表面処理工程と、
    　前記絶縁性基板を加熱処理して前記絶縁性基板の表面を酸化する酸化処理工程と、
    　前記絶縁性基板の表面にろう材を塗布するろう材塗布工程と、
    　前記ろう材を介して金属箔を前記絶縁性基板表面に接合する金属箔接合工程と、
    　前記金属箔と前記ろう材とをエッチングして回路パターンを形成する回路パターン形成工程と、
    　前記回路パターン上に半導体素子を接合する半導体素子実装工程と、
    　前記絶縁性基板、前記回路パターン及び前記半導体素子を、封止樹脂で封止する封止工程とを含む半導体モジュールの製造方法であって、
    　前記表面処理工程は、前記絶縁性基板の表面をウェットブラスト処理して粗面化する工程を含み、
    　前記ろう材塗布工程は、前記絶縁性基板表面の、前記金属箔が接合される面だけでなく、前記金属箔が接合されない面であって前記封止樹脂が密着する面に対しても、ろう材を塗布する工程を含み、
    　前記回路パターン形成工程において、前記ろう材が塗布された部分をエッチングすることによって、前記絶縁性基板の前記封止樹脂が密着する面が、前記絶縁性基板の断面において、下記方法によって測定し算出した、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μm以上である表面粗さとすることを特徴とする半導体モジュールの製造方法。
    　（平均粗さの測定・算出方法）
    　前記絶縁性基板の断面を走査電子顕微鏡で撮影してＳＥＭ画像を用意し、前記ＳＥＭ画像を２値化して表面形状の画像データを用意し、前記画像データを画像数値化ソフトを用いて２次元座標データに変換し、下記数式により平均粗さＺａを計算して求める。
    Figure JPOXMLDOC01-appb-M000002
     　
    　　上記数式中、Ｚａは平均粗さを表す。Ｚｎは各ｎにおける前記２次元座標データと平均値との差を表す。Ｎは測定幅を測定ピッチで割った値であり、幅３００μｍの粗さ計算時はピッチ＝０．５μｍ、すなわちＮ＝６００、幅３μｍの粗さ計算時はピッチ＝０．００５μｍ、すなわちＮ＝６００とする。
  7. 　前記絶縁性基板は、窒化アルミニウムからなる、請求項６記載の半導体モジュールの製造方法。
  8. 前記絶縁性基板は、セラミックス製である、請求項１～５のいずれか１項に記載の半導体モジュール。
  9. 前記絶縁性基板は、窒化アルミニウムからなる、請求項８に記載の半導体モジュール。
  10. 　絶縁性基板と、
    　該絶縁性基板上に形成された回路パターンとを有する絶縁回路基板において、
    　前記絶縁性基板の前記回路パターンが形成されていない部分の表面は、前記絶縁性基板の断面において、下記方法によって測定し算出した、幅３００μｍの範囲で求めた平均粗さが０．１５μm以上であり、幅３μｍの範囲で求めた平均粗さが０．０２μｍ以上であることを特徴とする絶縁回路基板。
    　（平均粗さの測定・算出方法）
    　前記絶縁性基板の断面を走査電子顕微鏡で撮影してＳＥＭ画像を用意し、前記ＳＥＭ画像を２値化して表面形状の画像データを用意し、前記画像データを画像数値化ソフトを用いて２次元座標データに変換し、下記数式により平均粗さＺａを計算して求める。
    Figure JPOXMLDOC01-appb-M000003
     　
    　　上記数式中、Ｚａは平均粗さを表す。Ｚｎは各ｎにおける前記２次元座標データと平均値との差を表す。Ｎは測定幅を測定ピッチで割った値であり、幅３００μｍの粗さ計算時はピッチ＝０．５μｍ、すなわちＮ＝６００、幅３μｍの粗さ計算時はピッチ＝０．００５μｍ、すなわちＮ＝６００とする。
PCT/JP2019/004302 2018-02-19 2019-02-06 半導体モジュール及びその製造方法 WO2019159798A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201980006691.7A CN111512434B (zh) 2018-02-19 2019-02-06 半导体模块及其制造方法
US16/955,115 US11749581B2 (en) 2018-02-19 2019-02-06 Semiconductor module and method for manufacturing same
EP19753674.1A EP3712933A4 (en) 2018-02-19 2019-02-06 SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THEREOF
KR1020207017893A KR102454589B1 (ko) 2018-02-19 2019-02-06 반도체 모듈 및 그 제조 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018027138A JP7083256B2 (ja) 2018-02-19 2018-02-19 半導体モジュール及びその製造方法
JP2018-027138 2018-02-19

Publications (1)

Publication Number Publication Date
WO2019159798A1 true WO2019159798A1 (ja) 2019-08-22

Family

ID=67619347

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/004302 WO2019159798A1 (ja) 2018-02-19 2019-02-06 半導体モジュール及びその製造方法

Country Status (6)

Country Link
US (1) US11749581B2 (ja)
EP (1) EP3712933A4 (ja)
JP (1) JP7083256B2 (ja)
KR (1) KR102454589B1 (ja)
CN (1) CN111512434B (ja)
WO (1) WO2019159798A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11587861B2 (en) * 2020-03-30 2023-02-21 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method thereof

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200315023A1 (en) * 2019-03-25 2020-10-01 Intel Corporation Copper interface features for high speed interconnect applications
JP7198178B2 (ja) * 2019-08-16 2022-12-28 デンカ株式会社 セラミックス基板、回路基板及びその製造方法、並びにパワーモジュール
WO2022163064A1 (ja) 2021-01-28 2022-08-04 日本碍子株式会社 分離膜複合体および分離膜複合体の製造方法
CN112979322B (zh) * 2021-02-20 2023-09-08 北京北方华创微电子装备有限公司 陶瓷件及其制作方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0524959A (ja) 1991-07-25 1993-02-02 Matsushita Electric Works Ltd セラミツク回路基板の製造方法
JPH08222661A (ja) * 1995-02-09 1996-08-30 Kyocera Corp 半導体装置
JP2002241187A (ja) 2001-02-09 2002-08-28 Toshiba Ceramics Co Ltd 表面に微細な突起を形成させたセラミックス部材、及びその製造方法
JP2005225745A (ja) * 2004-01-16 2005-08-25 Toshiba Ceramics Co Ltd 耐プラズマ部材及びその製造方法
JP2008172172A (ja) 2007-01-15 2008-07-24 Denso Corp 電子制御装置及びその製造方法
JP2010030280A (ja) 2008-06-27 2010-02-12 Kyocera Corp セラミック基体、放熱基体および電子装置
JP2010087309A (ja) * 2008-09-30 2010-04-15 Sanyo Electric Co Ltd 半導体モジュールおよび半導体モジュールを備える携帯機器
JP2011052240A (ja) * 2009-08-31 2011-03-17 Denso Corp 溶射絶縁膜が備えられる構造体の製造方法
JP2012054368A (ja) * 2010-08-31 2012-03-15 Fujifilm Corp 多層配線基板の製造方法
JP2013027918A (ja) 2011-07-29 2013-02-07 Tokuyama Corp 窒化アルミニウム−金属接合基板の製造方法
JP2013258321A (ja) 2012-06-13 2013-12-26 Fuji Electric Co Ltd 半導体装置
JP2015132013A (ja) * 2013-12-13 2015-07-23 Jx日鉱日石金属株式会社 スパッタリングターゲット及びその製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100712715B1 (ko) 2001-01-31 2007-05-04 도시바세라믹스가부시키가이샤 표면에 미세한 돌기를 형성시킨 세라믹스부재 및 그제조방법
TWI255001B (en) 2001-12-13 2006-05-11 Matsushita Electric Ind Co Ltd Metal wiring substrate, semiconductor device and the manufacturing method thereof
KR100618630B1 (ko) * 2003-10-24 2006-09-13 도시바세라믹스가부시키가이샤 내플라즈마 부재 및 그 제조방법 및 열분사막 형성방법
US8569142B2 (en) * 2003-11-28 2013-10-29 Blackberry Limited Multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same
EP1588803A1 (en) 2004-04-21 2005-10-26 JSR Corporation Chemical mechanical polishing pad, manufacturing process thereof and chemical mechanical polishing method
JP2006145320A (ja) * 2004-11-18 2006-06-08 Matsushita Electric Works Ltd 半導体装置およびその製造方法
JP5181618B2 (ja) 2007-10-24 2013-04-10 宇部興産株式会社 金属箔積層ポリイミド樹脂基板
JPWO2009154295A1 (ja) * 2008-06-20 2011-12-01 日立金属株式会社 セラミックス集合基板とその製造方法及びセラミックス基板並びにセラミックス回路基板
WO2010013470A1 (ja) 2008-07-31 2010-02-04 三洋電機株式会社 半導体モジュールおよび半導体モジュールを備える携帯機器
JP2010087229A (ja) 2008-09-30 2010-04-15 Sanyo Electric Co Ltd 半導体モジュール、半導体モジュールの製造方法および携帯機器
CN102318452A (zh) 2009-02-12 2012-01-11 住友电木株式会社 布线板用树脂组合物，布线板用树脂片，复合体，复合体的制造方法及半导体装置
KR20120050755A (ko) * 2010-11-11 2012-05-21 삼성전기주식회사 반도체 패키지 기판 및 그 제조방법
JP5896214B2 (ja) 2012-01-23 2016-03-30 日亜化学工業株式会社 半導体装置の製造方法
JP2017011049A (ja) 2015-06-19 2017-01-12 株式会社日立製作所 絶縁回路基板及びそれを用いたパワー半導体装置
CN107563087B (zh) 2017-09-13 2020-12-15 绍兴文理学院 最优采样间距条件下的结构面粗糙度系数统计方法
US10510686B2 (en) * 2018-04-27 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0524959A (ja) 1991-07-25 1993-02-02 Matsushita Electric Works Ltd セラミツク回路基板の製造方法
JPH08222661A (ja) * 1995-02-09 1996-08-30 Kyocera Corp 半導体装置
JP2002241187A (ja) 2001-02-09 2002-08-28 Toshiba Ceramics Co Ltd 表面に微細な突起を形成させたセラミックス部材、及びその製造方法
JP2005225745A (ja) * 2004-01-16 2005-08-25 Toshiba Ceramics Co Ltd 耐プラズマ部材及びその製造方法
JP2008172172A (ja) 2007-01-15 2008-07-24 Denso Corp 電子制御装置及びその製造方法
JP2010030280A (ja) 2008-06-27 2010-02-12 Kyocera Corp セラミック基体、放熱基体および電子装置
JP2010087309A (ja) * 2008-09-30 2010-04-15 Sanyo Electric Co Ltd 半導体モジュールおよび半導体モジュールを備える携帯機器
JP2011052240A (ja) * 2009-08-31 2011-03-17 Denso Corp 溶射絶縁膜が備えられる構造体の製造方法
JP2012054368A (ja) * 2010-08-31 2012-03-15 Fujifilm Corp 多層配線基板の製造方法
JP2013027918A (ja) 2011-07-29 2013-02-07 Tokuyama Corp 窒化アルミニウム−金属接合基板の製造方法
JP2013258321A (ja) 2012-06-13 2013-12-26 Fuji Electric Co Ltd 半導体装置
JP2015132013A (ja) * 2013-12-13 2015-07-23 Jx日鉱日石金属株式会社 スパッタリングターゲット及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11587861B2 (en) * 2020-03-30 2023-02-21 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
EP3712933A4 (en) 2020-12-30
EP3712933A1 (en) 2020-09-23
US11749581B2 (en) 2023-09-05
JP7083256B2 (ja) 2022-06-10
US20200388553A1 (en) 2020-12-10
JP2019145612A (ja) 2019-08-29
CN111512434B (zh) 2023-08-08
CN111512434A (zh) 2020-08-07
KR20200090215A (ko) 2020-07-28
KR102454589B1 (ko) 2022-10-13

Similar Documents

Publication Publication Date Title
WO2019159798A1 (ja) 半導体モジュール及びその製造方法
JP6150938B2 (ja) 半導体装置
JP5485110B2 (ja) 配線基板及びその製造方法、電子装置
US7750443B2 (en) Semiconductor device package
EP0682363A2 (en) Via-structure of a multilayer interconnection ceramic substrate
WO2018225809A1 (ja) セラミックス回路基板
JP4789771B2 (ja) 樹脂外囲器付きリードフレームとその製造方法
JP4220641B2 (ja) 樹脂モールド用回路基板と電子パッケージ
US5760466A (en) Semiconductor device having improved heat resistance
JP4591362B2 (ja) 電子装置の製造方法
JP5336711B2 (ja) 樹脂封止型半導体装置
WO2020001979A1 (en) A wire bonding arrangement and method of manufacturing a wire bonding arrangement
TWI228785B (en) Substrate, wiring board, substrate for semiconductor package, semiconductor device, semiconductor package and its manufacturing method
JP5928324B2 (ja) 電力用半導体装置
JP2001210776A (ja) 半導体装置とその製造方法及びリードフレームとその製造方法
JPH0715129A (ja) 表面実装型半導体装置の実装構造および実装方法
CN218867097U (zh) 半导体结构以及半导体封装件
JP2774180B2 (ja) 実装基板
JP3199193B2 (ja) 半導体搭載用回路基板およびその製造方法
JP3398291B2 (ja) 配線基板
JP2010038887A (ja) 磁気センサおよびその製造方法
CN113451143A (zh) 半导体衬底配置结构
CN117643183A (zh) 布线基板
JPH09181214A (ja) 半導体装置
JPH10335769A (ja) 混成集積回路用基板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19753674

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20207017893

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2019753674

Country of ref document: EP

Effective date: 20200618

NENP Non-entry into the national phase

Ref country code: DE