WO2013147359A1 - Semiconductor package and method for manufacturing same - Google Patents

Semiconductor package and method for manufacturing same Download PDF

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Publication number
WO2013147359A1
WO2013147359A1 PCT/KR2012/002626 KR2012002626W WO2013147359A1 WO 2013147359 A1 WO2013147359 A1 WO 2013147359A1 KR 2012002626 W KR2012002626 W KR 2012002626W WO 2013147359 A1 WO2013147359 A1 WO 2013147359A1
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WO
WIPO (PCT)
Prior art keywords
wiring
redistribution pattern
forming
semiconductor chip
pattern layer
Prior art date
Application number
PCT/KR2012/002626
Other languages
French (fr)
Korean (ko)
Inventor
헤안 소흐세이
지엔 시에우유엔
웨이 웡쳥
분 소흐시에우
첸하우양
Original Assignee
주식회사 네패스
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Publication date
Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to CN201280072193.0A priority Critical patent/CN104205327B/en
Publication of WO2013147359A1 publication Critical patent/WO2013147359A1/en

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Definitions

  • the technical idea of the present invention relates to a semiconductor package, and more particularly, to a semiconductor package including a through wiring and a manufacturing method thereof.
  • An object of the present invention is to provide a method of manufacturing a semiconductor package including a through wiring with precision and low process defects.
  • a method of manufacturing a semiconductor package including: preparing a conductive member; Removing a portion of the conductive member to form a flat portion and a protrusion protruding from the flat portion; Forming a sealing member for sealing the conductive member; Removing a portion of the sealing member to expose the protrusion of the conductive member from the sealing member to form a through wiring; Forming a redistribution pattern layer electrically connected to the through wiring on the through wiring; Mounting a semiconductor chip on the redistribution pattern layer; And forming an outer connection member electrically connected to the through wiring.
  • a semiconductor package including: a through wiring formed using a protrusion formed by using the manufacturing method described above and removing a partial region of a conductive member; A redistribution pattern layer disposed on the through wiring and electrically connected to the through wiring; A semiconductor chip disposed on the redistribution pattern layer and electrically connected to the redistribution pattern layer; And an external connection member electrically connected to the through wiring.
  • the manufacturing process can be simplified, and the yield and the process cost can be reduced. have.
  • FIG. 1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of the semiconductor package of FIG. 1 taken along line A-A according to an exemplary embodiment.
  • 3 to 22 are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 1 according to an embodiment of the present invention according to process steps.
  • FIG. 23 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
  • 24 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
  • FIG. 1 is a plan view illustrating a semiconductor package 100 according to an embodiment of the present invention.
  • 2 is a cross-sectional view taken along the line A-A of the semiconductor package 100 of FIG. 1 according to an embodiment of the present invention.
  • the semiconductor package 100 may include a through wiring 110, a semiconductor chip 120, a sealing member 130, a redistribution pattern layer 140, an underfill layer 160, and an outer connection member. And 170.
  • the through wire 110 may be positioned to penetrate the sealing member 130.
  • the through wiring 110 may be electrically connected to the semiconductor chip 120 by the redistribution pattern layer 140. That is, the through wire 110 may be electrically connected to the semiconductor chip pad 122 of the semiconductor chip 120 through the redistribution pattern 144 and the semiconductor chip connection member 124.
  • the through wire 110 may be formed using the protrusions 113 (see FIG. 4) formed from the conductive member 111 (see FIG. 4), as described with reference to FIGS. 3 to 22 below.
  • the through wiring 110 exposed from the sealing member 130 may have a recessed surface 115 as compared to the surface 135 of the sealing member 130.
  • the surface of the sealing member 130 and the exposed surface of the through wiring 110 may be located on the same plane.
  • the sealing member 130 may include an insulator and may include, for example, an epoxy mold compound (EMC).
  • EMC epoxy mold compound
  • the redistribution pattern layer 140 may be positioned on the sealing member 130 and the through wiring 110, and may be electrically connected to the through wiring 110.
  • the surface 116 of the through wire 110 connected to the redistribution pattern layer 140 may be coplanar with the surface 136 of the sealing member 130.
  • the redistribution pattern layer 140 may include a first insulating layer 142, a redistribution pattern 144, and a second insulating layer 146.
  • the redistribution pattern 144 may be surrounded by the first insulating layer 142 and the second insulating layer 146.
  • the redistribution pattern 144 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the redistribution pattern 144 may redistribute the through wiring 110 and / or the redistribution of the semiconductor chip 120. Accordingly, the redistribution pattern 144 may reduce the size of the input / output terminals of the semiconductor chip 120 and increase the number of the input / output terminals. In addition, by the redistribution pattern 144, the semiconductor package 100 may have a fan-out structure.
  • the redistribution pattern layer 140 may be formed of a prefabricated structure, and the structure of the redistribution pattern layer 140 is also included in the technical idea of the present invention when the structure is adhered to the sealing member 130 by pressing, bonding, or reflowing.
  • the semiconductor chip 120 may be positioned on the redistribution pattern layer 140 and electrically connected to the redistribution pattern layer 140.
  • the semiconductor chip pad 122 of the semiconductor chip 120 may be electrically connected to the redistribution pattern 144 of the redistribution pattern layer 140 through the semiconductor chip connection member 124.
  • the semiconductor chip 120 may be a memory chip or a logic chip.
  • Such a memory chip may include, for example, DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, or MRAM. have.
  • Such a logic chip may be a controller for controlling the memory chips.
  • the semiconductor chip 120 may be spaced apart from the redistribution pattern layer 140 by the height of the semiconductor chip connection member 124.
  • the semiconductor chip 120 is in contact with the redistribution pattern layer 140 is also included in the technical idea of the present invention.
  • the semiconductor package 100 may not include the underfill layer 160.
  • the underfill layer 160 may be positioned between the semiconductor chip 120 and the redistribution pattern layer 140 to fill a space between the semiconductor chip 120 and the redistribution pattern layer 140.
  • the underfill layer 160 may fill the space between the semiconductor chip connection members 124.
  • Underfill layer 160 may include an insulator and may be, for example, an epoxy molding compound, silica, resin, glassy material, a polymer, or the like.
  • the underfill layer 160 may function to fix the semiconductor chip 120 while being in contact with the redistribution pattern layer 140.
  • the underfill layer 160 may have appropriate toughness to prevent cracking due to external impact. Can have
  • the outer connection member 170 may be electrically connected to the through wiring 110 at a position opposite to the redistribution pattern layer 140, and thus may be electrically connected to the semiconductor chip 120 through the redistribution pattern layer 140. Can be connected. In addition, the outer connection member 170 may electrically connect the semiconductor chip 120 with an external device.
  • the through wiring 110 may have a recessed surface 115, and the outer connecting member 170 may be formed by the sealing member 130. It may be aligned and / or fixed.
  • the outer connection member 170 may be located at the same position perpendicular to the through wire 110.
  • the outer connecting member 170 may include a conductive material, for example, may include a metal.
  • the outer connection member 170 may be a solder ball.
  • the semiconductor chip 120 may be located at a central portion of the semiconductor package 100.
  • this is exemplary and the technical idea of the present invention is not limited thereto, and the case where the semiconductor chip 120 is located at any part of the semiconductor package 100 is also included in the technical idea of the present invention.
  • the outer connection member 170 may be located outside the semiconductor chip 120. In addition, the outer connection member 170 may overlap the semiconductor chip 120.
  • the arrangement of the outer connecting member 170 shown in FIG. 1 is exemplary, and the technical idea of the present invention is not limited thereto, and various arrangements of the outer connecting member 170 are included in the technical idea of the present invention.
  • 3 to 22 are cross-sectional views illustrating a manufacturing method of manufacturing the semiconductor package 100 of FIG. 1 according to an embodiment of the present invention according to the process steps.
  • the conductive member 111 is prepared.
  • the conductive member 111 may have a flat plate shape.
  • the conductive member 111 may include a conductive material, for example, may include a metal.
  • the conductive member 111 may include, for example, copper, a copper alloy, aluminum, or an aluminum alloy.
  • a portion of the conductive member 111 is removed to form the flat portion 112 and the protrusion 113 protruding from the flat portion 112.
  • the process may be referred to as a half etching process, but the height of the protrusion 113 is not limited to the height of the flat part 112.
  • the height of the protrusion 113 may have the same height as the through wiring 110 (refer to FIG. 11) formed in a subsequent process or may have a slightly larger height.
  • the height of the planar portion 112 may vary, and the thinner is preferable for the subsequent removal process, but may have a predetermined thickness to prevent the warping phenomenon of the conductive member 111.
  • the conductive member 111 is attached onto the first carrier substrate 119.
  • the conductive member 111 may be attached onto the first carrier substrate 119 using the first adhesive member 118.
  • the planar portion 112 may face the first carrier substrate 119 and may contact the first adhesive member 118.
  • the first carrier substrate 119 may include silicon, glass, ceramic, plastic, or polymer.
  • the first adhesive member 118 may be a liquid adhesive or an adhesive tape.
  • a sealing member 130 for sealing the conductive member 111 is formed.
  • the sealing member 130 may fill between the protrusions 113 of the conductive member 111.
  • the sealing member 130 may be formed to cover the conductive member 111.
  • the sealing member 130 may include an insulator and may include, for example, an epoxy mold compound (EMC).
  • a portion of the sealing member 130 is removed to expose the protrusion 113 of the conductive member 111 from the sealing member 130.
  • the removal process may be performed using polishing, etch back or mechanical chemical polishing (CMP).
  • the second carrier substrate 139 is attached onto the second adhesive member 138. That is, the second carrier substrate 139 is attached on the exposed protrusion 113 of the conductive member 111. Accordingly, the second carrier substrate 139 is attached in the opposite direction to the first carrier substrate 119 based on the conductive member 111.
  • the second carrier substrate 139 may include silicon, glass, ceramic, plastic, or polymer.
  • the first carrier substrate 119 and the second carrier substrate 139 may include the same material or different materials.
  • the first carrier substrate 119 and the first adhesive member 118 are removed.
  • the flat portion 112 of the conductive member 111 is turned upside down.
  • the through wiring 110 may be through silicon via (TSV) or through substrate via (TSV).
  • the through wiring 110 may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the removal process may be performed using polishing, etch back or mechanical chemical polishing (CMP). After the through wiring 110 is formed, a cleaning process may be further performed to remove unwanted residues.
  • the redistribution pattern layer 140 is formed on the through wiring 110.
  • a first insulating layer 142 is formed on the sealing member 130 and the exposed through wiring 110. Subsequently, a portion of the first insulating layer 142 is removed to form a first opening 141 exposing the through wiring 110.
  • the first insulating layer 142 may include an insulator and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
  • a redistribution pattern 144 electrically connected to the through wire 110 is formed on the first insulating layer 142.
  • the redistribution pattern 144 may fill the first opening 141.
  • the redistribution pattern 144 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy.
  • the redistribution pattern 144 may be formed using various methods such as deposition, plating, and the like.
  • the redistribution pattern 144 may redistribute the through wiring 110.
  • a second insulating layer 146 is formed on the redistribution pattern 144. Subsequently, a portion of the second insulating layer 146 is removed to form a second opening 143 that exposes a portion of the redistribution pattern 144.
  • the second insulating layer 146 may include an insulator and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
  • the first insulating layer 142 and the second insulating layer 146 may include the same material or different materials.
  • the first insulating layer 142, the redistribution pattern 144, and the second insulating layer 146 may constitute the redistribution pattern layer 140.
  • the redistribution pattern layer 140 may be formed of a prefabricated structure, and the structure of the redistribution pattern layer 140 is also included in the technical idea of the present invention when the structure is adhered to the sealing member 130 by pressing, bonding, or reflowing.
  • the second carrier substrate 139 and the second adhesive member 138 are removed. As a result, the through wire 110 may be exposed. In detail, the surface of the through wiring 110 positioned opposite to the redistribution pattern layer 140 may be exposed.
  • a third carrier substrate 149 is attached onto the redistribution pattern layer 140.
  • the third carrier substrate 149 may be attached onto the redistribution pattern layer 140 using the third adhesive member 148.
  • the third carrier substrate 149 may include silicon, glass, ceramic, plastic, or polymer.
  • the third adhesive member 148 may be a liquid adhesive or an adhesive tape.
  • the third carrier substrate 149 may include the same material as the first carrier substrate 119 and / or the second carrier substrate 139 or may include different materials.
  • the third adhesive member 148 may include the same material as the first adhesive member 118 and / or the second adhesive member 138 or may include different materials.
  • the 15 and 16 may be performed in a reverse order. For example, after attaching the third carrier substrate 149 to the redistribution pattern layer 140, the second carrier substrate 139 and the second adhesive member 138 may be removed.
  • a portion of the exposed through wire 110 is removed to form a through wire 110 having a recessed surface 115 as compared with the surface 135 of the sealing member 130.
  • Removing a part of the through wire 110 may be performed using wet etching. By the wet etching, the surface of the through wire 110 may be cleaned.
  • the third carrier substrate 149 and the third adhesive member 148 are removed. Accordingly, the redistribution pattern 144 of the redistribution pattern layer 140 may be exposed. In addition, the redistribution pattern 144 is exposed by the second opening 143.
  • an independent structure 150 including the through wiring 110 and the redistribution pattern layer 140 may be configured.
  • the structure 150 is a region in which a redistribution pattern 144 of the redistribution pattern layer 140 is exposed and a semiconductor chip 120 (see FIG. 19) electrically connected to the redistribution pattern layer 140 is mounted.
  • Can have The other side opposite to the one side may have a region to which the through wiring 110 is exposed from the sealing member 130 and to which an external connection member 170 (refer to FIG. 22) electrically connected to the through wiring 110 is attached. have.
  • Such structure 150 may function as an interposer.
  • the semiconductor chip 120 is mounted on the structure 150.
  • the semiconductor chip 120 is mounted on the redistribution pattern layer 140.
  • the semiconductor chip 120 may be a memory chip or a logic chip.
  • the semiconductor chip 120 may include one semiconductor chip or may include a plurality of semiconductor chips.
  • the semiconductor chip 120 includes a semiconductor chip pad 122.
  • the semiconductor chip connection member 124 such as solder bumps may be attached to the semiconductor chip pad 122.
  • the semiconductor chip connection members 124 may be in electrical contact with each other by contacting the redistribution pattern 144 exposed by the second opening 143. In this case, a reflow process may be further performed to attach the semiconductor chip connection member 124 to the redistribution pattern 144.
  • the semiconductor chip connection member 124 may be formed in the redistribution pattern 144 exposed by the second opening 143.
  • the semiconductor chip pad 122 and the semiconductor chip connection member of the semiconductor chip 120 may be formed.
  • the semiconductor chip 120 may be mounted on the structure 150 to be electrically connected to the 124.
  • the semiconductor chip 120 may be redistributed by the redistribution pattern 144 of the redistribution pattern layer 140. Accordingly, the redistribution pattern 144 may reduce the size of the input / output terminals of the semiconductor chip 120 and increase the number of the input / output terminals. In addition, by the redistribution pattern 144, the semiconductor package 100 may have a fan-out structure.
  • the result of mounting the semiconductor chip 120 on the structure 150 by the process of FIG. 19 is illustrated.
  • the semiconductor chip 120 is spaced apart from the redistribution pattern layer 140 by the height of the semiconductor chip connection member 124.
  • the semiconductor chip 120 may be in contact with the redistribution pattern layer 140 because the depth of the second opening 143 and the height of the semiconductor chip connection member 124 are the same. do.
  • an underfill layer 160 is formed below the semiconductor chip 120.
  • the underfill layer 160 fills a space between the semiconductor chip 120 and the redistribution pattern layer 140.
  • the underfill layer 160 may have a suitable viscosity to fill between the semiconductor chip connection members 124.
  • Underfill layer 160 may include an insulator and may be, for example, an epoxy molding compound, silica, resin, glassy material, a polymer, or the like.
  • the underfill layer 160 may be formed by filling the space between the semiconductor chip 120 and the redistribution pattern layer 140 using a liquid underfill material and then heating or drying the liquid underfill material to solidify the liquid underfill material. .
  • an outer connection member 170 electrically connected to the through wire 110 is formed.
  • the outer connecting member 170 may include a conductive material, for example, may include a metal.
  • the outer connection member 170 may be a solder ball. Through the reflow process, the outer connection member 170 may be attached to the through wiring 110. Thus, the semiconductor package 100 is completed.
  • FIG. 23 is a cross-sectional view illustrating a semiconductor package 200 according to an embodiment of the present invention.
  • the semiconductor package 200 according to the present embodiments is a modification of some components in the semiconductor package of the above-described embodiment, and thus duplicated description will be omitted.
  • the semiconductor package 200 includes a through wiring 110 positioned through the sealing member 130, a redistribution pattern layer 140 disposed on the through wiring 110, and electrically connected thereto.
  • the first semiconductor chip 220a and the second semiconductor chip 220b, the first semiconductor chip 220a, and the second semiconductor chip 220b are disposed on the layer 140 and electrically connected to the redistribution pattern layer 140.
  • An underfill layer 160 filling a space between the first semiconductor chip 220a and the redistribution pattern layer 140 and a space between the second semiconductor chip 220b and the redistribution pattern layer 140 to be fixed;
  • the outer connecting member 170 may be electrically connected to the through wiring 110 at a position opposite to the redistribution pattern layer 140.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may be electrically connected to the redistribution pattern layer 140 similarly to the semiconductor chip 120 of FIG. 1.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may have the same size or different sizes.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may be memory chips or logic chips.
  • the first semiconductor chip 220a and the second semiconductor chip 220b may be homogeneous products having the same function or heterogeneous products having different functions.
  • the first semiconductor chip 220a may be a logic chip and the second semiconductor chip 220b may be a memory chip, or vice versa.
  • the semiconductor package 200 may configure a system on chip (SOC) or a system in package (SIP).
  • SOC system on chip
  • SIP system in package
  • FIG. 23 illustrates a case in which the first semiconductor chip 220a and the second semiconductor chip 220b are arranged in a planar manner
  • the case in which the first semiconductor chip 220a and the second semiconductor chip 220b are vertically stacked is also included in the technical concept of the present invention.
  • FIG. 24 is a cross-sectional view illustrating a semiconductor package 300 according to an embodiment of the present invention.
  • the semiconductor package 300 according to the present exemplary embodiments is a modification of some components of the semiconductor package of the above-described embodiment, and thus a redundant description thereof will be omitted.
  • the semiconductor package 300 includes a through wiring 110 positioned through the sealing member 130, a redistribution pattern layer 140 disposed on the through wiring 110, and electrically connected thereto.
  • the space between the semiconductor chip 120 and the redistribution pattern layer 140 may be formed to fix the semiconductor chip 120 and the semiconductor chip 120 on the layer 140 and electrically connected to the redistribution pattern layer 140.
  • the underfill layer 160 and the redistribution pattern layer 140 may include an outer connection member 170 electrically connected to the through wire 110 at a position opposite to the filling.
  • the semiconductor device may further include an external sealing member 380 disposed on the redistribution pattern layer 140 and sealing the semiconductor chip 120.
  • the outer seal member 380 may include an insulator and may include, for example, an epoxy mold compound (EMC).
  • EMC epoxy mold compound
  • the outer sealing member 380 may perform a function of protecting the semiconductor chip 120 from the outside and / or discharging heat generated from the semiconductor chip 120 to the outside.
  • the outer sealing member 380 may include the same material as the sealing member 130 or may include different materials.
  • the outer sealing member 380 may include the same material as the underfill layer 160 or may include different materials.

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Abstract

The present invention provides a method for manufacturing a semiconductor package comprising through wiring which is precise and has a low defect rate in the manufacturing process. The method for manufacturing the semiconductor package, according to one embodiment of the present invention, comprises the steps of: preparing a conductive member; removing one portion of the conductive member to form a flat portion and a protruding portion, which protrudes from the flat portion; forming a sealing member for sealing the conductive member; removing a portion of the sealing member to expose the protruding portion of the conductive member through the sealing member, and forming the through wiring; forming on the through wiring a rewiring pattern layer which is electrically connected to the through wiring; mounting a semiconductor chip on the rewiring pattern layer; and forming an external connection member which is electrically connected to the through wiring.

Description

반도체 패키지 및 그 제조 방법Semiconductor package and manufacturing method thereof
본 발명의 기술적 사상은 반도체 패키지에 관한 것으로서, 더욱 상세하게는, 관통 배선을 포함하는 반도체 패키지 및 그 제조 방법에 관한 것이다.The technical idea of the present invention relates to a semiconductor package, and more particularly, to a semiconductor package including a through wiring and a manufacturing method thereof.
최근 반도체 소자는 공정 기술의 미세화 및 기능의 다양화로 인해 칩 사이즈는 감소하고 입출력 단자들의 갯수는 증가함에 따라 전극 패드 피치는 점점 미세화되고 있으며, 다양한 기능의 융합화가 가속됨에 따라 여러 소자를 하나의 패키지 내에 집적하는 시스템 레벨 패키징 기술이 대두되고 있다. 또한 시스템 레벨 패키징 기술은 동작 간 노이즈를 최소화하고 신호 속도를 향상시키기 위하여 짧은 신호 거리를 유지할 수 있는 3차원 적층 기술 형태로 변화되고 있다. 한편 이러한 기술 개선요구와 더불어 제품 가격 상승을 제어하기 위하여 생산성이 높고 제조 원가를 절감하기 위하여, 복수의 반도체 칩을 포함하여 구성된 반도체 패키지를 도입하고 있다.In recent years, as semiconductor devices become smaller in size due to miniaturization of process technology and diversification of functions, electrode pad pitch is becoming smaller as the number of input / output terminals increases, and as the convergence of various functions is accelerated, several devices are packaged in one package. System level packaging technology is emerging. In addition, system-level packaging technology is changing to a three-dimensional stacking technology that can maintain short signal distances to minimize noise between operations and improve signal speed. On the other hand, in order to control the rise in product prices, along with such technical improvement demands, semiconductor packages including a plurality of semiconductor chips are introduced to reduce productivity and manufacturing costs.
종래의 패키지에 복수의 반도체 칩들을 적층하는 경우에, 상측 반도체 칩과 하측 반도체 칩의 상호 연결을 위하여 하측 반도체 칩의 팬-아웃 패키지를 형성한 후에, 패키지 몰드에 레이저 드릴 등을 통하여 관통홀을 형성하고 상기 관통홀에 도전성 물질의 충전하여 관통 배선을 형성하는 것이 일반적이다. 그러한, 패키지 몰드에 형성되는 관통홀이 정밀하게 형성하기 어렵고, 상기 관통홀에 도전성 물질을 치밀하게 충전하기 어려운 한계가 있다. In the case of stacking a plurality of semiconductor chips in a conventional package, after forming the fan-out package of the lower semiconductor chip for interconnection of the upper semiconductor chip and the lower semiconductor chip, through holes are formed in the package mold through a laser drill or the like. It is common to form and to form a through wiring by filling the through hole with a conductive material. Such a through hole formed in the package mold is difficult to form precisely, and there is a limit in that it is difficult to densely fill the through hole with a conductive material.
본 발명의 기술적 사상이 이루고자 하는 기술적 과제는 정밀하고 공정 결함이 낮은 관통 배선을 포함하는 반도체 패키지의 제조 방법을 제공하는 것이다.An object of the present invention is to provide a method of manufacturing a semiconductor package including a through wiring with precision and low process defects.
상기 기술적 과제를 달성하기 위한 본 발명의 기술적 사상에 따른 반도체 패키지의 제조 방법은, 도전 부재를 준비하는 단계; 상기 도전 부재의 일부 영역을 제거하여 평면부 및 상기 평면부로부터 돌출된 돌출부를 형성하는 단계; 상기 도전 부재를 밀봉하는 밀봉 부재를 형성하는 단계; 상기 밀봉 부재의 일부를 제거하여 상기 밀봉 부재로부터 상기 도전 부재의 상기 돌출부를 노출하여 관통 배선을 형성하는 단계; 상기 관통 배선 상에 상기 관통 배선과 전기적으로 연결되는 재배선 패턴층을 형성하는 단계; 상기 재배선 패턴층 상에 반도체 칩을 실장하는 단계; 및 상기 관통 배선에 전기적으로 연결된 외측 연결 부재를 형성하는 단계;를 포함한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor package, including: preparing a conductive member; Removing a portion of the conductive member to form a flat portion and a protrusion protruding from the flat portion; Forming a sealing member for sealing the conductive member; Removing a portion of the sealing member to expose the protrusion of the conductive member from the sealing member to form a through wiring; Forming a redistribution pattern layer electrically connected to the through wiring on the through wiring; Mounting a semiconductor chip on the redistribution pattern layer; And forming an outer connection member electrically connected to the through wiring.
상기 기술적 과제를 달성하기 위한 본 발명의 기술적 사상에 따른 반도체 패키지는, 상술한 제조 방법을 이용하여 제조하고, 도전 부재의 일부 영역을 제거하여 형성한 돌출부를 이용하여 형성된 관통 배선; 상기 관통 배선 상에 위치하고, 상기 관통 배선과 전기적으로 연결되는 재배선 패턴층; 상기 재배선 패턴층 상에 위치하고, 상기 재배선 패턴층과 전기적으로 연결된 반도체 칩; 및 상기 관통 배선과 전기적으로 연결되는 외부 연결 부재;를 포함한다.According to an aspect of the present invention, there is provided a semiconductor package including: a through wiring formed using a protrusion formed by using the manufacturing method described above and removing a partial region of a conductive member; A redistribution pattern layer disposed on the through wiring and electrically connected to the through wiring; A semiconductor chip disposed on the redistribution pattern layer and electrically connected to the redistribution pattern layer; And an external connection member electrically connected to the through wiring.
본 발명의 기술적 사상에 따른 반도체 패키지는, 종래의 관통홀을 충전하여 관통 배선을 형성하는 경우에 비하여, 미리 도전 부재로부터 돌출부를 형성하고, 상기 돌출부를 이용하여 관통 배선을 형성하므로, 정밀하고 공정 결함이 낮은 관통 배선을 제공할 수 있다.The semiconductor package according to the technical concept of the present invention is more precise and process because the protrusions are formed from the conductive member and the through wires are formed using the protrusions, as compared with the case of filling the through-holes in the related art. It is possible to provide a through wiring having a low defect.
또한, 상기 관통 배선을 형성하기 위하여 밀봉 부재에 관통홀 형성 공정과 상기 관통홀을 도전물로 충전하는 충전 공정을 요구하지 않으므로, 제조 공정이 단순해지고 수율 증가 및 공정 비용 감소의 효과를 제공할 수 있다.In addition, since a through hole forming process and a filling process for filling the through hole with a conductive material are not required in order to form the through wiring, the manufacturing process can be simplified, and the yield and the process cost can be reduced. have.
도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시하는 평면도이다.1 is a plan view illustrating a semiconductor package according to an embodiment of the present invention.
도 2는 본 발명의 일 실시예에 따른 도 1의 반도체 패키지를 선 A-A를 따라 절단한 단면도이다.FIG. 2 is a cross-sectional view of the semiconductor package of FIG. 1 taken along line A-A according to an exemplary embodiment.
도 3 내지 도 22는 본 발명의 일 실시예에 따른 도 1의 반도체 패키지를 제조하는 제조 방법을 공정 단계에 따라 도시하는 단면도들이다.3 to 22 are cross-sectional views illustrating a method of manufacturing the semiconductor package of FIG. 1 according to an embodiment of the present invention according to process steps.
도 23은 본 발명의 일 실시예에 따른 반도체 패키지를 도시하는 단면도이다.23 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
도 24는 본 발명의 일 실시예에 따른 반도체 패키지를 도시하는 단면도이다.24 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다. 본 발명의 실시예들은 당해 기술 분야에서 통상의 지식을 가진 자에게 본 발명의 기술적 사상을 더욱 완전하게 설명하기 위하여 제공되는 것이며, 하기 실시예는 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 기술적 사상의 범위가 하기 실시예에 한정되는 것은 아니다. 오히려, 이들 실시예는 본 개시를 더욱 충실하고 완전하게 하고, 당업자에게 본 발명의 기술적 사상을 완전하게 전달하기 위하여 제공되는 것이다. 본 명세서에서 사용된 바와 같이, 용어 "및/또는"은 해당 열거된 항목 중 어느 하나 및 하나 이상의 모든 조합을 포함한다. 동일한 부호는 시종 동일한 요소를 의미한다. 나아가, 도면에서의 다양한 요소와 영역은 개략적으로 그려진 것이다. 따라서, 본 발명의 기술적 사상은 첨부한 도면에 그려진 상대적인 크기나 간격에 의해 제한되지 않는다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully explain the technical idea of the present invention to those skilled in the art, and the following embodiments may be modified in many different forms, and The scope of the technical idea is not limited to the following examples. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items. Like numbers refer to like elements all the time. Furthermore, various elements and regions in the drawings are schematically drawn. Therefore, the technical idea of the present invention is not limited by the relative size or the distance drawn in the accompanying drawings.
도 1은 본 발명의 일 실시예에 따른 반도체 패키지(100)를 도시하는 평면도이다. 도 2는 본 발명의 일 실시예에 따른 도 1의 반도체 패키지(100)를 선 A-A를 따라 절단한 단면도이다.1 is a plan view illustrating a semiconductor package 100 according to an embodiment of the present invention. 2 is a cross-sectional view taken along the line A-A of the semiconductor package 100 of FIG. 1 according to an embodiment of the present invention.
도 1 및 도 2를 참조하면, 반도체 패키지(100)는 관통 배선(110), 반도체 칩(120), 밀봉 부재(130), 재배선 패턴층(140), 언더필 층(160) 및 외측 연결 부재(170)을 포함한다.1 and 2, the semiconductor package 100 may include a through wiring 110, a semiconductor chip 120, a sealing member 130, a redistribution pattern layer 140, an underfill layer 160, and an outer connection member. And 170.
관통 배선(110)은 밀봉 부재(130)를 관통하도록 위치할 수 있다. 관통 배선(110)은 재배선 패턴층(140)에 의하여 반도체 칩(120)과 전기적으로 연결될 수 있다. 즉, 관통 배선(110)은 재배선 패턴(144) 및 반도체 칩 연결 부재(124)를 통하여 반도체 칩(120)의 반도체 칩 패드(122)와 전기적으로 연결될 수 있다. 관통 배선(110)은 하기의 도 3 내지 도 22를 참조하여 설명한 바와 같이 도전 부재(111, 도 4 참조)로부터 형성된 돌출부(113, 도 4 참조)를 이용하여 형성할 수 있다.The through wire 110 may be positioned to penetrate the sealing member 130. The through wiring 110 may be electrically connected to the semiconductor chip 120 by the redistribution pattern layer 140. That is, the through wire 110 may be electrically connected to the semiconductor chip pad 122 of the semiconductor chip 120 through the redistribution pattern 144 and the semiconductor chip connection member 124. The through wire 110 may be formed using the protrusions 113 (see FIG. 4) formed from the conductive member 111 (see FIG. 4), as described with reference to FIGS. 3 to 22 below.
밀봉 부재(130)로부터 노출된 관통 배선(110)은 밀봉 부재(130)의 표면(135)에 비하여 리세스된 표면(115)을 가질 수 있다. 대안적으로, 밀봉 부재(130)의 표면과 관통 배선(110)의 노출된 표면은 동일 평면 상에 위치할 수 있다. The through wiring 110 exposed from the sealing member 130 may have a recessed surface 115 as compared to the surface 135 of the sealing member 130. Alternatively, the surface of the sealing member 130 and the exposed surface of the through wiring 110 may be located on the same plane.
밀봉 부재(130)는 절연물을 포함할 수 있고, 예를 들어 에폭시 몰딩 컴파운드(epoxy mold compound, EMC)를 포함할 수 있다.The sealing member 130 may include an insulator and may include, for example, an epoxy mold compound (EMC).
재배선 패턴층(140)은 밀봉 부재(130)와 관통 배선(110) 상에 위치할 수 있고, 관통 배선(110)과 전기적으로 연결될 수 있다. 재배선 패턴층(140)과 연결되는 관통 배선(110)의 표면(116)은 밀봉 부재(130)의 표면(136)과 동일 평면 상에 위치할 수 있다. 재배선 패턴층(140)은 제1 절연층(142), 재배선 패턴(144), 및 제2 절연층(146)을 포함할 수 있다. 재배선 패턴(144)은 제1 절연층(142)과 제2 절연층(146)에 의하여 둘러싸일 수 있다. 재배선 패턴(144)은 도전물을 포함할 수 있고, 예를 들어 금속을 포함할 수 있고, 구리, 구리 합금, 알루미늄, 또는 알루미늄 합금을 포함할 수 있다. 재배선 패턴(144)은 관통 배선(110)을 재배선 할 수 있고, 및/또는 반도체 칩(120)을 재배선할 수 있다. 이에 따라, 재배선 패턴(144)은 반도체 칩(120)의 입출력 단자를 미세화할 수 있고, 또한 상기 입출력 단자의 갯수를 증가시킬 수 있다. 또한, 재배선 패턴(144)에 의하여, 반도체 패키지(100)는 팬-아웃 구조를 가질 수 있다.The redistribution pattern layer 140 may be positioned on the sealing member 130 and the through wiring 110, and may be electrically connected to the through wiring 110. The surface 116 of the through wire 110 connected to the redistribution pattern layer 140 may be coplanar with the surface 136 of the sealing member 130. The redistribution pattern layer 140 may include a first insulating layer 142, a redistribution pattern 144, and a second insulating layer 146. The redistribution pattern 144 may be surrounded by the first insulating layer 142 and the second insulating layer 146. The redistribution pattern 144 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy. The redistribution pattern 144 may redistribute the through wiring 110 and / or the redistribution of the semiconductor chip 120. Accordingly, the redistribution pattern 144 may reduce the size of the input / output terminals of the semiconductor chip 120 and increase the number of the input / output terminals. In addition, by the redistribution pattern 144, the semiconductor package 100 may have a fan-out structure.
또한, 재배선 패턴층(140)은 미리 제조된 구조체로 구성될 수 있고, 이러한 구조체가 압착, 접착, 리플로우 등에 의하여 밀봉 부재(130)에 접착되는 경우도 본 발명의 기술적 사상에 포함된다.In addition, the redistribution pattern layer 140 may be formed of a prefabricated structure, and the structure of the redistribution pattern layer 140 is also included in the technical idea of the present invention when the structure is adhered to the sealing member 130 by pressing, bonding, or reflowing.
반도체 칩(120)은 재배선 패턴층(140) 상에 위치하고 재배선 패턴층(140)과 전기적으로 연결될 수 있다. 예를 들어, 반도체 칩(120)의 반도체 칩 패드(122)는 반도체 칩 연결 부재(124)를 통하여 재배선 패턴층(140)의 재배선 패턴(144)과 전기적으로 연결될 수 있다. 반도체 칩(120)은 메모리 칩이거나 또는 로직 칩일 수 있다. 이러한 메모리 칩은, 예를 들어 디램(DRAM), 에스램(SRAM), 플래시(flash), 피램(PRAM), 알이램(ReRAM), 에프이램(FeRAM) 또는 엠램(MRAM)을 포함할 수 있다. 이러한 로직 칩은 메모리칩들을 제어하는 제어기일 수 있다.The semiconductor chip 120 may be positioned on the redistribution pattern layer 140 and electrically connected to the redistribution pattern layer 140. For example, the semiconductor chip pad 122 of the semiconductor chip 120 may be electrically connected to the redistribution pattern 144 of the redistribution pattern layer 140 through the semiconductor chip connection member 124. The semiconductor chip 120 may be a memory chip or a logic chip. Such a memory chip may include, for example, DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, or MRAM. have. Such a logic chip may be a controller for controlling the memory chips.
반도체 칩(120)은 반도체 칩 연결 부재(124)에 높이에 의하여 재배선 패턴층(140)으로부터 이격될 수 있다. 대안적으로, 반도체 칩(120)이 재배선 패턴층(140)에 접촉되는 경우도 본 발명의 기술적 사상에 포함된다. 이러한 경우에는, 반도체 패키지(100)가 언더필 층(160)를 포함하지 않을 수 있다.The semiconductor chip 120 may be spaced apart from the redistribution pattern layer 140 by the height of the semiconductor chip connection member 124. Alternatively, the case where the semiconductor chip 120 is in contact with the redistribution pattern layer 140 is also included in the technical idea of the present invention. In this case, the semiconductor package 100 may not include the underfill layer 160.
언더필 층(160)는, 반도체 칩(120)과 재배선 패턴층(140) 사이의 공간을 충전하도록, 반도체 칩(120)과 재배선 패턴층(140) 사이에 위치할 수 있다. 언더필 층(160)는 반도체 칩 연결 부재(124) 사이의 공간을 충전할 수 있다. 언더필 층(160)는 절연물을 포함할 수 있고, 예를 들어 에폭시 몰딩 컴파운드, 실리카, 레진, 유리질 물질, 또는 폴리머 등일 수 있다. 언더필 층(160)는 반도체 칩(120)이 재배선 패턴층(140)에 접촉된 상태로 고정하는 기능을 수행할 수 있고, 이를 위하여 외부 충격에 의한 크랙을 방지할 수 있는 적절한 인성(toughness)을 가질 수 있다.The underfill layer 160 may be positioned between the semiconductor chip 120 and the redistribution pattern layer 140 to fill a space between the semiconductor chip 120 and the redistribution pattern layer 140. The underfill layer 160 may fill the space between the semiconductor chip connection members 124. Underfill layer 160 may include an insulator and may be, for example, an epoxy molding compound, silica, resin, glassy material, a polymer, or the like. The underfill layer 160 may function to fix the semiconductor chip 120 while being in contact with the redistribution pattern layer 140. For this purpose, the underfill layer 160 may have appropriate toughness to prevent cracking due to external impact. Can have
외측 연결 부재(170)는 재배선 패턴층(140)과는 반대 위치에서 관통 배선(110)과 전기적으로 연결될 수 있고, 이에 따라 재배선 패턴층(140)을 통하여 반도체 칩(120)과 전기적으로 연결될 수 있다. 또한, 외측 연결 부재(170)는 반도체 칩(120)을 외부 장치와 전기적으로 연결할 수 있다. 외측 연결 부재(170)와 관통 배선(110)의 전기적 연결을 위하여, 관통 배선(110)은 리세스된 표면(115)을 가질 수 있고, 외측 연결 부재(170)가 밀봉 부재(130)에 의하여 정렬 및/또는 고정될 수 있다. 외측 연결 부재(170)는 관통 배선(110)에 수직적으로 동일한 위치에 위치할 수 있다. 외측 연결 부재(170)는 도전물을 포함할 수 있고, 예를 들어 금속을 포함할 수 있다. 외측 연결 부재(170)는 솔더볼일 수 있다.The outer connection member 170 may be electrically connected to the through wiring 110 at a position opposite to the redistribution pattern layer 140, and thus may be electrically connected to the semiconductor chip 120 through the redistribution pattern layer 140. Can be connected. In addition, the outer connection member 170 may electrically connect the semiconductor chip 120 with an external device. For electrical connection of the outer connecting member 170 and the through wiring 110, the through wiring 110 may have a recessed surface 115, and the outer connecting member 170 may be formed by the sealing member 130. It may be aligned and / or fixed. The outer connection member 170 may be located at the same position perpendicular to the through wire 110. The outer connecting member 170 may include a conductive material, for example, may include a metal. The outer connection member 170 may be a solder ball.
도 1에 도시된 바와 같이, 반도체 패키지(100)의 중앙 부분에 반도체 칩(120)이 위치할 수 있다. 그러나, 이는 예시적이며 본 발명의 기술적 사상은 이에 한정되지 않고, 반도체 칩(120)이 반도체 패키지(100)의 임의의 부분에 위치하는 경우도 본 발명의 기술적 사상에 포함된다.As illustrated in FIG. 1, the semiconductor chip 120 may be located at a central portion of the semiconductor package 100. However, this is exemplary and the technical idea of the present invention is not limited thereto, and the case where the semiconductor chip 120 is located at any part of the semiconductor package 100 is also included in the technical idea of the present invention.
외측 연결 부재(170)는 반도체 칩(120)의 외곽에 위치할 수 있다. 또한, 외측 연결 부재(170)는 반도체 칩(120)과 중첩하여 위치할 수 있다. 도 1에 도시된 외측 연결 부재(170)의 배열은 예시적이며, 본 발명의 기술적 사상은 이에 한정되지 않고, 외측 연결 부재(170)의 다양한 배열들이 본 발명의 기술적 사상에 포함된다.The outer connection member 170 may be located outside the semiconductor chip 120. In addition, the outer connection member 170 may overlap the semiconductor chip 120. The arrangement of the outer connecting member 170 shown in FIG. 1 is exemplary, and the technical idea of the present invention is not limited thereto, and various arrangements of the outer connecting member 170 are included in the technical idea of the present invention.
도 3 내지 도 22는 본 발명의 일 실시예에 따른 도 1의 반도체 패키지(100)를 제조하는 제조 방법을 공정 단계에 따라 도시하는 단면도들이다.3 to 22 are cross-sectional views illustrating a manufacturing method of manufacturing the semiconductor package 100 of FIG. 1 according to an embodiment of the present invention according to the process steps.
도 3을 참조하면, 도전 부재(111)를 준비한다. 도전 부재(111)는 평판 형상을 가질 수 있다. 도전 부재(111)는 도전성 물질을 포함할 수 있고, 예를 들어 금속을 포함할 수 있다. 도전 부재(111)는, 예를 들어 구리, 구리 합금, 알루미늄, 또는 알루미늄 합금을 포함할 수 있다.Referring to FIG. 3, the conductive member 111 is prepared. The conductive member 111 may have a flat plate shape. The conductive member 111 may include a conductive material, for example, may include a metal. The conductive member 111 may include, for example, copper, a copper alloy, aluminum, or an aluminum alloy.
도 4를 참조하면, 도전 부재(111)의 일부 영역을 제거하여, 평면부(112) 및 평면부(112)로부터 돌출된 돌출부(113)를 형성한다. 상기 공정을 하프 식각(half etching) 공정으로 지칭할 수 있으나, 돌출부(113)의 높이가 평면부(112)의 높이와 동일한 경우에 한정되는 것은 아니다. 돌출부(113)의 높이는 후속의 공정에서 형성되는 관통 배선(110, 도 11 참조)과 동일한 높이를 가지거나 약간 더 큰 높이를 가질 수 있다. 평면부(112)의 높이는 다양하게 변화할 수 있고, 후속의 제거 공정을 위하여는 얇을수록 바람직하지만, 도전 부재(111)의 휨 현상 등을 방지하기 위하여는 일정 두께를 가질 수 있다. 이러한 돌출부(113)를 형성하는 공정은 포토리소그래피 및 식각 공정을 이용하여 도전 부재(111)의 일부 영역을 제거하여 수행될 수 있다. 대안적으로, 프레스 장치를 이용하여 도전 부재(111)를 몰드에 압착하여 돌출부(113)를 형성할 수 있다. 돌출부(113)를 형성한 후에, 원하지 않는 잔류물을 제거하기 위하여 세정 공정을 더 수행할 수 있다.Referring to FIG. 4, a portion of the conductive member 111 is removed to form the flat portion 112 and the protrusion 113 protruding from the flat portion 112. The process may be referred to as a half etching process, but the height of the protrusion 113 is not limited to the height of the flat part 112. The height of the protrusion 113 may have the same height as the through wiring 110 (refer to FIG. 11) formed in a subsequent process or may have a slightly larger height. The height of the planar portion 112 may vary, and the thinner is preferable for the subsequent removal process, but may have a predetermined thickness to prevent the warping phenomenon of the conductive member 111. The process of forming the protrusion 113 may be performed by removing a portion of the conductive member 111 using photolithography and etching processes. Alternatively, the protruding portion 113 may be formed by pressing the conductive member 111 into the mold using a press device. After forming the protrusions 113, a cleaning process may be further performed to remove unwanted residues.
도 5를 참조하면, 도전 부재(111)를 제1 캐리어 기판(119) 상에 부착한다. 예를 들어 도전 부재(111)는 제1 캐리어 기판(119) 상에 제1 접착 부재(118)를 이용하여 부착될 수 있다. 평면부(112)는 제1 캐리어 기판(119)을 향할 수 있고, 제1 접착 부재(118)와 접촉할 수 있다. 제1 캐리어 기판(119)은 실리콘(silicon), 유리(glass), 세라믹(ceramic), 플라스틱(plastic), 또는 폴리머(polymer)를 포함할 수 있다. 제1 접착 부재(118)는 액상 접착제 또는 접착 테이프일 수 있다.Referring to FIG. 5, the conductive member 111 is attached onto the first carrier substrate 119. For example, the conductive member 111 may be attached onto the first carrier substrate 119 using the first adhesive member 118. The planar portion 112 may face the first carrier substrate 119 and may contact the first adhesive member 118. The first carrier substrate 119 may include silicon, glass, ceramic, plastic, or polymer. The first adhesive member 118 may be a liquid adhesive or an adhesive tape.
도 6을 참조하면, 도전 부재(111)를 밀봉하는 밀봉 부재(130)를 형성한다. 또한, 밀봉 부재(130)는 도전 부재(111)의 돌출부(113) 사이를 충전할 수 있다. 또한, 밀봉 부재(130)는 도전 부재(111)를 덮도록 형성될 수 있다. 밀봉 부재(130)는 절연물을 포함할 수 있고, 예를 들어 에폭시 몰딩 컴파운드(epoxy mold compound, EMC)를 포함할 수 있다. Referring to FIG. 6, a sealing member 130 for sealing the conductive member 111 is formed. In addition, the sealing member 130 may fill between the protrusions 113 of the conductive member 111. In addition, the sealing member 130 may be formed to cover the conductive member 111. The sealing member 130 may include an insulator and may include, for example, an epoxy mold compound (EMC).
도 7을 참조하면, 밀봉 부재(130)의 일부를 제거하여, 밀봉 부재(130)로부터 도전 부재(111)의 돌출부(113)를 노출한다. 상기 제거 공정은 연마, 에치백 또는 기계적 화학적 연마(mechanical chemical polishing, CMP)를 이용하여 수행될 수 있다. Referring to FIG. 7, a portion of the sealing member 130 is removed to expose the protrusion 113 of the conductive member 111 from the sealing member 130. The removal process may be performed using polishing, etch back or mechanical chemical polishing (CMP).
도 8을 참조하면, 밀봉 부재(130) 상에 제2 접착 부재(138)를 부착한다. 이에 따라, 노출된 도전 부재(111) 상에 제2 접착 부재(138)가 부착될 수 있다. 제2 접착 부재(138)는 액상 접착제 또는 접착 테이프일 수 있다. 제1 접착 부재(118)와 제2 접착 부재(138)는 동일한 물질을 포함하거나 또는 서로 다른 물질을 포함할 수 있다.Referring to FIG. 8, a second adhesive member 138 is attached onto the sealing member 130. Accordingly, the second adhesive member 138 may be attached onto the exposed conductive member 111. The second adhesive member 138 may be a liquid adhesive or an adhesive tape. The first adhesive member 118 and the second adhesive member 138 may include the same material or different materials.
도 9를 참조하면, 제2 접착 부재(138) 상에 제2 캐리어 기판(139)을 부착한다. 즉, 제2 캐리어 기판(139)은 도전 부재(111)의 노출된 돌출부(113) 상에 부착된다. 이에 따라, 제2 캐리어 기판(139)는 도전 부재(111)를 기준으로 제1 캐리어 기판(119)에 대하여 반대 방향으로 부착된다. 제2 캐리어 기판(139)은 실리콘(silicon), 유리(glass), 세라믹(ceramic), 플라스틱(plastic), 또는 폴리머(polymer)를 포함할 수 있다. 제1 캐리어 기판(119)과 제2 캐리어 기판(139)은 동일한 물질을 포함하거나 또는 서로 다른 물질을 포함할 수 있다.9, the second carrier substrate 139 is attached onto the second adhesive member 138. That is, the second carrier substrate 139 is attached on the exposed protrusion 113 of the conductive member 111. Accordingly, the second carrier substrate 139 is attached in the opposite direction to the first carrier substrate 119 based on the conductive member 111. The second carrier substrate 139 may include silicon, glass, ceramic, plastic, or polymer. The first carrier substrate 119 and the second carrier substrate 139 may include the same material or different materials.
도 10을 참조하면, 제1 캐리어 기판(119)과 제1 접착 부재(118)를 제거한다. 또한, 도전 부재(111)의 평면부(112)가 상측을 향하도록 뒤집는다.Referring to FIG. 10, the first carrier substrate 119 and the first adhesive member 118 are removed. In addition, the flat portion 112 of the conductive member 111 is turned upside down.
도 11을 참조하면, 밀봉 부재(130)의 일부와 도전 부재(111)의 평면부(112)를 제거하여, 밀봉 부재(130)로부터 도전 부재(111)의 돌출부(113)를 노출한다. 상기 노출된 도전 부재(111)의 돌출부(113)는 관통 배선(110)을 형성한다. 관통 배선(110)은 TSV(through silicon via) 또는 TSV(through substrate via)일 수 있다. 관통 배선(110)은 구리, 구리 합금, 알루미늄, 또는 알루미늄 합금을 포함할 수 있다. 상기 제거 공정은 연마, 에치백 또는 기계적 화학적 연마(mechanical chemical polishing, CMP)를 이용하여 수행될 수 있다. 관통 배선(110)를 형성한 후에, 원하지 않는 잔류물을 제거하기 위하여 세정 공정을 더 수행할 수 있다.Referring to FIG. 11, a part of the sealing member 130 and the planar portion 112 of the conductive member 111 are removed to expose the protrusion 113 of the conductive member 111 from the sealing member 130. The protrusion 113 of the exposed conductive member 111 forms a through wiring 110. The through wiring 110 may be through silicon via (TSV) or through substrate via (TSV). The through wiring 110 may include copper, a copper alloy, aluminum, or an aluminum alloy. The removal process may be performed using polishing, etch back or mechanical chemical polishing (CMP). After the through wiring 110 is formed, a cleaning process may be further performed to remove unwanted residues.
도 12 내지 도 14를 참조하면, 관통 배선(110) 상에 재배선 패턴층(140)을 형성한다.12 to 14, the redistribution pattern layer 140 is formed on the through wiring 110.
도 12를 참조하면, 밀봉 부재(130)와 노출된 관통 배선(110) 상에 제1 절연층(142)을 형성한다. 이어서, 제1 절연층(142)의 일부 영역을 제거하여, 관통 배선(110)을 노출하는 제1 개구부(141)를 형성한다. 제1 절연층(142)은 절연물을 포함할 수 있고, 예를 들어 산화물, 질화물, 또는 에폭시 몰딩 컴파운드 등을 포함할 수 있다.Referring to FIG. 12, a first insulating layer 142 is formed on the sealing member 130 and the exposed through wiring 110. Subsequently, a portion of the first insulating layer 142 is removed to form a first opening 141 exposing the through wiring 110. The first insulating layer 142 may include an insulator and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like.
도 13을 참조하면, 제1 절연층(142) 상에 관통 배선(110)과 전기적으로 연결된 재배선 패턴(144)을 형성한다. 재배선 패턴(144)은 제1 개구부(141)를 충전할 수 있다. 재배선 패턴(144)은 도전물을 포함할 수 있고, 예를 들어 금속을 포함할 수 있고, 구리, 구리 합금, 알루미늄, 또는 알루미늄 합금을 포함할 수 있다. 재배선 패턴(144)은 증착, 도금, 등 다양한 방법을 이용하여 형성될 수 있다. 재배선 패턴(144)은 관통 배선(110)을 재배선할 수 있다.Referring to FIG. 13, a redistribution pattern 144 electrically connected to the through wire 110 is formed on the first insulating layer 142. The redistribution pattern 144 may fill the first opening 141. The redistribution pattern 144 may include a conductive material, for example, may include a metal, and may include copper, a copper alloy, aluminum, or an aluminum alloy. The redistribution pattern 144 may be formed using various methods such as deposition, plating, and the like. The redistribution pattern 144 may redistribute the through wiring 110.
도 14를 참조하면, 재배선 패턴(144) 상에 제2 절연층(146)을 형성한다. 이어서, 제2 절연층(146)의 일부 영역을 제거하여, 재배선 패턴(144)의 일부 영역을 노출하는 제2 개구부(143)를 형성한다. 제2 절연층(146)은 절연물을 포함할 수 있고, 예를 들어 산화물, 질화물, 또는 에폭시 몰딩 컴파운드 등을 포함할 수 있다. 제1 절연층(142)과 제2 절연층(146)은 동일한 물질을 포함하거나 또는 다른 물질을 포함할 수 있다. 제1 절연층(142), 재배선 패턴(144), 및 제2 절연층(146)은 재배선 패턴층(140)을 구성할 수 있다.Referring to FIG. 14, a second insulating layer 146 is formed on the redistribution pattern 144. Subsequently, a portion of the second insulating layer 146 is removed to form a second opening 143 that exposes a portion of the redistribution pattern 144. The second insulating layer 146 may include an insulator and may include, for example, an oxide, a nitride, an epoxy molding compound, or the like. The first insulating layer 142 and the second insulating layer 146 may include the same material or different materials. The first insulating layer 142, the redistribution pattern 144, and the second insulating layer 146 may constitute the redistribution pattern layer 140.
또한, 재배선 패턴층(140)은 미리 제조된 구조체로 구성될 수 있고, 이러한 구조체가 압착, 접착, 리플로우 등에 의하여 밀봉 부재(130)에 접착되는 경우도 본 발명의 기술적 사상에 포함된다.In addition, the redistribution pattern layer 140 may be formed of a prefabricated structure, and the structure of the redistribution pattern layer 140 is also included in the technical idea of the present invention when the structure is adhered to the sealing member 130 by pressing, bonding, or reflowing.
도 15를 참조하면, 제2 캐리어 기판(139)과 제2 접착 부재(138)를 제거한다. 이에 따라, 관통 배선(110)이 노출될 수 있다. 구체적으로, 재배선 패턴층(140)에 반대에 위치하는 관통 배선(110)의 표면이 노출될 수 있다.Referring to FIG. 15, the second carrier substrate 139 and the second adhesive member 138 are removed. As a result, the through wire 110 may be exposed. In detail, the surface of the through wiring 110 positioned opposite to the redistribution pattern layer 140 may be exposed.
도 16을 참조하면, 재배선 패턴층(140) 상에 제3 캐리어 기판(149)을 부착한다. 예를 들어, 제3 캐리어 기판(149)은 제3 접착 부재(148)를 이용하여 재배선 패턴층(140) 상에 부착될 수 있다. 제3 캐리어 기판(149)은 실리콘(silicon), 유리(glass), 세라믹(ceramic), 플라스틱(plastic), 또는 폴리머(polymer)를 포함할 수 있다. 제3 접착 부재(148)는 액상 접착제 또는 접착 테이프일 수 있다. 제3 캐리어 기판(149)은 제1 캐리어 기판(119) 및/또는 제2 캐리어 기판(139)과 동일한 물질을 포함하거나 또는 서로 다른 물질을 포함할 수 있다. 제3 접착 부재(148)는 제1 접착 부재(118) 및/또는 제2 접착 부재(138)와 동일한 물질을 포함하거나 또는 서로 다른 물질을 포함할 수 있다.Referring to FIG. 16, a third carrier substrate 149 is attached onto the redistribution pattern layer 140. For example, the third carrier substrate 149 may be attached onto the redistribution pattern layer 140 using the third adhesive member 148. The third carrier substrate 149 may include silicon, glass, ceramic, plastic, or polymer. The third adhesive member 148 may be a liquid adhesive or an adhesive tape. The third carrier substrate 149 may include the same material as the first carrier substrate 119 and / or the second carrier substrate 139 or may include different materials. The third adhesive member 148 may include the same material as the first adhesive member 118 and / or the second adhesive member 138 or may include different materials.
도 15와 도 16에 도시된 공정들은 서로 반대의 순서로 수행될 수 있다. 예를 들어 재배선 패턴층(140) 상에 제3 캐리어 기판(149)을 부착한 후에 제2 캐리어 기판(139)과 제2 접착 부재(138)를 제거할 수 있다.15 and 16 may be performed in a reverse order. For example, after attaching the third carrier substrate 149 to the redistribution pattern layer 140, the second carrier substrate 139 and the second adhesive member 138 may be removed.
도 17을 참조하면, 노출된 관통 배선(110)의 일부를 제거하여, 밀봉 부재(130)의 표면(135)에 비하여 리세스된 표면(115)을 가지는 관통 배선(110)을 형성한다. 상기 관통 배선(110)의 일부를 제거하는 단계는 습식 식각을 이용하여 수행될 수 있다. 상기 습식 식각에 의하여, 관통 배선(110)의 표면이 세정될 수 있다.Referring to FIG. 17, a portion of the exposed through wire 110 is removed to form a through wire 110 having a recessed surface 115 as compared with the surface 135 of the sealing member 130. Removing a part of the through wire 110 may be performed using wet etching. By the wet etching, the surface of the through wire 110 may be cleaned.
도 18을 참조하면, 제3 캐리어 기판(149)과 제3 접착 부재(148)를 제거한다. 이에 따라, 재배선 패턴층(140)의 재배선 패턴(144)이 노출될 수 있다. 또한, 제2 개구부(143)에 의하여 재배선 패턴(144)이 노출된다. 결과적으로, 관통 배선(110)과 재배선 패턴층(140)을 포함하는 독립적인 구조체(150)를 구성할 수 있다. 구조체(150)는 일 측은 재배선 패턴층(140)의 재배선 패턴(144)이 노출되고, 재배선 패턴층(140)과 전기적으로 연결되는 반도체 칩(120, 도 19 참조)이 실장되는 영역을 가질 수 있다. 상기 일 측에 반대인 타 측은 관통 배선(110)이 밀봉 부재(130)로부터 노출되고, 관통 배선(110)과 전기적으로 연결되는 외부 연결 부재(170, 도 22 참조)가 부착되는 영역을 가질 수 있다. 이러한 구조체(150)는 인터포저로서 기능할 수 있다.Referring to FIG. 18, the third carrier substrate 149 and the third adhesive member 148 are removed. Accordingly, the redistribution pattern 144 of the redistribution pattern layer 140 may be exposed. In addition, the redistribution pattern 144 is exposed by the second opening 143. As a result, an independent structure 150 including the through wiring 110 and the redistribution pattern layer 140 may be configured. The structure 150 is a region in which a redistribution pattern 144 of the redistribution pattern layer 140 is exposed and a semiconductor chip 120 (see FIG. 19) electrically connected to the redistribution pattern layer 140 is mounted. Can have The other side opposite to the one side may have a region to which the through wiring 110 is exposed from the sealing member 130 and to which an external connection member 170 (refer to FIG. 22) electrically connected to the through wiring 110 is attached. have. Such structure 150 may function as an interposer.
도 19를 참조하면, 구조체(150) 상에 반도체 칩(120)을 실장한다. 예를 들어, 재배선 패턴층(140) 상에 반도체 칩(120)을 실장한다. 반도체 칩(120)은 메모리 칩이거나 또는 로직 칩일 수 있다. 반도체 칩(120)은 하나의 반도체 칩을 포함하거나 또는 복수의 반도체 칩들을 포함할 수 있다. 반도체 칩(120)은 반도체 칩 패드(122)를 포함한다. 반도체 칩 패드(122)에는 솔더 범프와 같은 반도체 칩 연결 부재(124)가 부착될 수 있다. 반도체 칩 연결 부재(124)는 제2 개구부(143)에 의하여 노출된 재배선 패턴(144)과 접촉하여 서로 전기적으로 연결될 수 있다. 이러한 경우에 리플로우 공정을 더 수행하여 반도체 칩 연결 부재(124)를 재배선 패턴(144)에 부착시킬 수 있다. 대안적으로, 제2 개구부(143)에 의하여 노출된 재배선 패턴(144)에 반도체 칩 연결 부재(124)를 형성한 후에, 반도체 칩(120)의 반도체 칩 패드(122)와 반도체 칩 연결 부재(124)와 전기적으로 연결되도록 반도체 칩(120)을 구조체(150) 상에 실장할 수 있다. Referring to FIG. 19, the semiconductor chip 120 is mounted on the structure 150. For example, the semiconductor chip 120 is mounted on the redistribution pattern layer 140. The semiconductor chip 120 may be a memory chip or a logic chip. The semiconductor chip 120 may include one semiconductor chip or may include a plurality of semiconductor chips. The semiconductor chip 120 includes a semiconductor chip pad 122. The semiconductor chip connection member 124 such as solder bumps may be attached to the semiconductor chip pad 122. The semiconductor chip connection members 124 may be in electrical contact with each other by contacting the redistribution pattern 144 exposed by the second opening 143. In this case, a reflow process may be further performed to attach the semiconductor chip connection member 124 to the redistribution pattern 144. Alternatively, after the semiconductor chip connection member 124 is formed in the redistribution pattern 144 exposed by the second opening 143, the semiconductor chip pad 122 and the semiconductor chip connection member of the semiconductor chip 120 may be formed. The semiconductor chip 120 may be mounted on the structure 150 to be electrically connected to the 124.
반도체 칩(120)은 재배선 패턴층(140)의 재배선 패턴(144)에 의하여 재배선될 수 있다. 이에 따라, 재배선 패턴(144)은 반도체 칩(120)의 입출력 단자를 미세화할 수 있고, 또한 상기 입출력 단자의 갯수를 증가시킬 수 있다. 또한, 재배선 패턴(144)에 의하여, 반도체 패키지(100)는 팬-아웃 구조를 가질 수 있다.The semiconductor chip 120 may be redistributed by the redistribution pattern 144 of the redistribution pattern layer 140. Accordingly, the redistribution pattern 144 may reduce the size of the input / output terminals of the semiconductor chip 120 and increase the number of the input / output terminals. In addition, by the redistribution pattern 144, the semiconductor package 100 may have a fan-out structure.
도 20을 참조하면, 도 19의 공정에 의하여 구조체(150) 상에 반도체 칩(120)이 실장된 결과물이 도시되어 있다. 반도체 칩 연결 부재(124)에 높이에 의하여 반도체 칩(120)이 재배선 패턴층(140)으로부터 이격되어 있다. 대안적으로, 제2 개구부(143)의 깊이와 반도체 칩 연결 부재(124)의 높이가 동일하여 반도체 칩(120)이 재배선 패턴층(140)에 접촉되는 경우도 본 발명의 기술적 사상에 포함된다.Referring to FIG. 20, the result of mounting the semiconductor chip 120 on the structure 150 by the process of FIG. 19 is illustrated. The semiconductor chip 120 is spaced apart from the redistribution pattern layer 140 by the height of the semiconductor chip connection member 124. Alternatively, the semiconductor chip 120 may be in contact with the redistribution pattern layer 140 because the depth of the second opening 143 and the height of the semiconductor chip connection member 124 are the same. do.
도 21을 참조하면, 반도체 칩(120)의 하측에 언더필(underfill) 층(160)를 형성한다. 언더필 층(160)는 반도체 칩(120)과 재배선 패턴층(140) 사이의 공간을 충전한다. 언더필 층(160)는 반도체 칩 연결 부재(124) 사이를 충전하도록 적절한 점도를 가질 수 있다. 언더필 층(160)는 절연물을 포함할 수 있고, 예를 들어 에폭시 몰딩 컴파운드, 실리카, 레진, 유리질 물질, 또는 폴리머 등일 수 있다. 언더필 층(160)는 액상 언더필 물질을 이용하여 반도체 칩(120)과 재배선 패턴층(140) 사이의 공간을 충전한 후, 가열이나 건조를 하여 상기 액상 언더필 물질을 고상화하여 형성할 수 있다.Referring to FIG. 21, an underfill layer 160 is formed below the semiconductor chip 120. The underfill layer 160 fills a space between the semiconductor chip 120 and the redistribution pattern layer 140. The underfill layer 160 may have a suitable viscosity to fill between the semiconductor chip connection members 124. Underfill layer 160 may include an insulator and may be, for example, an epoxy molding compound, silica, resin, glassy material, a polymer, or the like. The underfill layer 160 may be formed by filling the space between the semiconductor chip 120 and the redistribution pattern layer 140 using a liquid underfill material and then heating or drying the liquid underfill material to solidify the liquid underfill material. .
도 22를 참조하면, 관통 배선(110)에 전기적으로 연결된 외측 연결 부재(170)를 형성한다. 외측 연결 부재(170)는 도전물을 포함할 수 있고, 예를 들어 금속을 포함할 수 있다. 외측 연결 부재(170)는 솔더볼일 수 있다. 리플로우 공정을 통하여, 관통 배선(110)에 외측 연결 부재(170)를 부착시킬 수 있다. 이에 따라, 반도체 패키지(100)를 완성한다.Referring to FIG. 22, an outer connection member 170 electrically connected to the through wire 110 is formed. The outer connecting member 170 may include a conductive material, for example, may include a metal. The outer connection member 170 may be a solder ball. Through the reflow process, the outer connection member 170 may be attached to the through wiring 110. Thus, the semiconductor package 100 is completed.
도 23은 본 발명의 일 실시예에 따른 반도체 패키지(200)를 도시하는 단면도이다. 본 실시예들에 따른 반도체 패키지(200)는 상술한 실시예의 반도체 패키지에서 일부 구성을 변형한 것이고, 따라서 중복된 설명은 생략하기로 한다.23 is a cross-sectional view illustrating a semiconductor package 200 according to an embodiment of the present invention. The semiconductor package 200 according to the present embodiments is a modification of some components in the semiconductor package of the above-described embodiment, and thus duplicated description will be omitted.
도 23을 참조하면, 반도체 패키지(200)는 밀봉 부재(130)를 관통하여 위치하는 관통 배선(110), 관통 배선(110) 상에 위치하고 전기적으로 연결된 재배선 패턴층(140), 재배선 패턴층(140) 상에 위치하고 전기적으로 연결된 제1 반도체 칩(220a)과 제2 반도체 칩(220b), 제1 반도체 칩(220a)과 제2 반도체 칩(220b)을 재배선 패턴층(140)에 고정하도록 제1 반도체 칩(220a)과 재배선 패턴층(140)의 사이의 공간과 제2 반도체 칩(220b)과 재배선 패턴층(140)의 사이의 공간을 충전하는 언더필 층(160) 및 재배선 패턴층(140)과는 반대 위치에서 관통 배선(110)과 전기적으로 연결된 외측 연결 부재(170)을 포함한다.Referring to FIG. 23, the semiconductor package 200 includes a through wiring 110 positioned through the sealing member 130, a redistribution pattern layer 140 disposed on the through wiring 110, and electrically connected thereto. The first semiconductor chip 220a and the second semiconductor chip 220b, the first semiconductor chip 220a, and the second semiconductor chip 220b are disposed on the layer 140 and electrically connected to the redistribution pattern layer 140. An underfill layer 160 filling a space between the first semiconductor chip 220a and the redistribution pattern layer 140 and a space between the second semiconductor chip 220b and the redistribution pattern layer 140 to be fixed; The outer connecting member 170 may be electrically connected to the through wiring 110 at a position opposite to the redistribution pattern layer 140.
제1 반도체 칩(220a)과 제2 반도체 칩(220b)은 도 1의 반도체 칩(120)과 유사하게 재배선 패턴층(140)에 전기적으로 연결될 수 있다. 제1 반도체 칩(220a)과 제2 반도체 칩(220b)은 서로 동일한 크기를 가지거나 서로 다른 크기를 가질 수 있다. 제1 반도체 칩(220a)과 제2 반도체 칩(220b)은 메모리 칩이거나 또는 로직 칩일 수 있다. 또한, 제1 반도체 칩(220a)과 제2 반도체 칩(220b)은 서로 동일한 기능을 가지는 동종 제품들이거나 또는 서로 다른 기능을 가지는 이종 제품들일 수 있다. 예를 들어, 제1 반도체 칩(220a)은 로직칩이고 제2 반도체 칩(220b)은 메모리 칩일 수 있고, 또는 이와 반대일 수 있다. 반도체 패키지(200)는 SOC(system on chip) 또는 SIP(system in package)를 구성할 수 있다. 또한, 제1 반도체 칩(220a) 및/또는 제2 반도체 칩(220b) 각각이 복수의 반도체 칩들이 적층된 구조체인 경우도 본 발명의 기술적 사상에 포함된다.The first semiconductor chip 220a and the second semiconductor chip 220b may be electrically connected to the redistribution pattern layer 140 similarly to the semiconductor chip 120 of FIG. 1. The first semiconductor chip 220a and the second semiconductor chip 220b may have the same size or different sizes. The first semiconductor chip 220a and the second semiconductor chip 220b may be memory chips or logic chips. In addition, the first semiconductor chip 220a and the second semiconductor chip 220b may be homogeneous products having the same function or heterogeneous products having different functions. For example, the first semiconductor chip 220a may be a logic chip and the second semiconductor chip 220b may be a memory chip, or vice versa. The semiconductor package 200 may configure a system on chip (SOC) or a system in package (SIP). In addition, the case where each of the first semiconductor chip 220a and / or the second semiconductor chip 220b is a structure in which a plurality of semiconductor chips are stacked is included in the technical idea of the present invention.
도 23에서는 제1 반도체 칩(220a)과 제2 반도체 칩(220b)이 평면적으로 배열된 경우에 대하여 도시되어 있으나, 수직적으로 적층된 경우도 본 발명의 기술적 사상에 포함된다. Although FIG. 23 illustrates a case in which the first semiconductor chip 220a and the second semiconductor chip 220b are arranged in a planar manner, the case in which the first semiconductor chip 220a and the second semiconductor chip 220b are vertically stacked is also included in the technical concept of the present invention.
도 24은 본 발명의 일 실시예에 따른 반도체 패키지(300)를 도시하는 단면도이다. 본 실시예들에 따른 반도체 패키지(300)는 상술한 실시예의 반도체 패키지에서 일부 구성을 변형한 것이고, 따라서 중복된 설명은 생략하기로 한다.24 is a cross-sectional view illustrating a semiconductor package 300 according to an embodiment of the present invention. The semiconductor package 300 according to the present exemplary embodiments is a modification of some components of the semiconductor package of the above-described embodiment, and thus a redundant description thereof will be omitted.
도 24를 참조하면, 반도체 패키지(300)는 밀봉 부재(130)를 관통하여 위치하는 관통 배선(110), 관통 배선(110) 상에 위치하고 전기적으로 연결된 재배선 패턴층(140), 재배선 패턴층(140) 상에 위치하고 전기적으로 연결된 반도체 칩(120), 반도체 칩(120)을 재배선 패턴층(140)에 고정하도록 반도체 칩(120)과 재배선 패턴층(140)의 사이의 공간을 충전하는 언더필 층(160) 및 재배선 패턴층(140)과는 반대 위치에서 관통 배선(110)과 전기적으로 연결된 외측 연결 부재(170)을 포함한다. 또한, 재배선 패턴층(140) 상에 위치하고 반도체 칩(120)을 밀봉하는 외부 밀봉 부재(380)를 더 포함한다. 외부 밀봉 부재(380)는 절연물을 포함할 수 있고, 예를 들어 에폭시 몰딩 컴파운드(epoxy mold compound, EMC)를 포함할 수 있다. 외부 밀봉 부재(380)는 반도체 칩(120)을 외부로부터 보호하는 기능 및/또는 반도체 칩(120)에서 발생하는 열을 외부로 방출하는 기능을 수행할 수 있다. 외부 밀봉 부재(380)는 밀봉 부재(130)와 동일한 물질을 포함하거나 또는 서로 다른 물질을 포함할 수 있다. 또한, 외부 밀봉 부재(380)는 언더필 층(160)와 동일한 물질을 포함하거나 또는 서로 다른 물질을 포함할 수 있다. Referring to FIG. 24, the semiconductor package 300 includes a through wiring 110 positioned through the sealing member 130, a redistribution pattern layer 140 disposed on the through wiring 110, and electrically connected thereto. The space between the semiconductor chip 120 and the redistribution pattern layer 140 may be formed to fix the semiconductor chip 120 and the semiconductor chip 120 on the layer 140 and electrically connected to the redistribution pattern layer 140. The underfill layer 160 and the redistribution pattern layer 140 may include an outer connection member 170 electrically connected to the through wire 110 at a position opposite to the filling. In addition, the semiconductor device may further include an external sealing member 380 disposed on the redistribution pattern layer 140 and sealing the semiconductor chip 120. The outer seal member 380 may include an insulator and may include, for example, an epoxy mold compound (EMC). The outer sealing member 380 may perform a function of protecting the semiconductor chip 120 from the outside and / or discharging heat generated from the semiconductor chip 120 to the outside. The outer sealing member 380 may include the same material as the sealing member 130 or may include different materials. In addition, the outer sealing member 380 may include the same material as the underfill layer 160 or may include different materials.
또한, 도 24의 반도체 패키지(300)에 도 23의 반도체 패키지(200)의 기술적 특징이 조합되는 경우도 본 발명의 기술적 사상에 포함된다.In addition, the case in which the technical features of the semiconductor package 200 of FIG. 23 are combined with the semiconductor package 300 of FIG. 24 is also included in the technical idea of the present invention.
이상에서 설명한 본 발명의 기술적 사상이 전술한 실시예 및 첨부된 도면에 한정되지 않으며, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것은, 본 발명의 기술적 사상이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The technical spirit of the present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in the art.
본 발명을 이용하면 반도체 패키지에서 정밀하고 공정 결함이 낮은 관통 배선을 제조할 수 있다.According to the present invention, it is possible to manufacture through wirings with precision and low process defects in semiconductor packages.

Claims (20)

  1. 도전 부재를 준비하는 단계;Preparing a conductive member;
    상기 도전 부재의 일부 영역을 제거하여 평면부 및 상기 평면부로부터 돌출된 돌출부를 형성하는 단계;Removing a portion of the conductive member to form a flat portion and a protrusion protruding from the flat portion;
    상기 도전 부재를 밀봉하는 밀봉 부재를 형성하는 단계;Forming a sealing member for sealing the conductive member;
    상기 밀봉 부재의 일부를 제거하여 상기 밀봉 부재로부터 상기 도전 부재의 상기 돌출부를 노출하여 관통 배선을 형성하는 단계; Removing a portion of the sealing member to expose the protrusion of the conductive member from the sealing member to form a through wiring;
    상기 관통 배선 상에 상기 관통 배선과 전기적으로 연결되는 재배선 패턴층을 형성하는 단계;Forming a redistribution pattern layer electrically connected to the through wiring on the through wiring;
    상기 재배선 패턴층 상에 반도체 칩을 실장하는 단계; 및Mounting a semiconductor chip on the redistribution pattern layer; And
    상기 관통 배선에 전기적으로 연결된 외측 연결 부재를 형성하는 단계;를 포함하는 반도체 패키지의 제조 방법.Forming an outer connection member electrically connected to the through wiring.
  2. 제 1 항에 있어서, The method of claim 1,
    상기 반도체 칩을 실장하는 단계를 수행한 후에,After the step of mounting the semiconductor chip,
    상기 반도체 칩과 재배선 패턴층 사이의 공간을 충전하는 언더필 층을 형성하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And forming an underfill layer filling the space between the semiconductor chip and the redistribution pattern layer.
  3. 제 1 항에 있어서, The method of claim 1,
    상기 재배선 패턴층을 형성하는 단계를 수행한 후에,After the step of forming the redistribution pattern layer,
    상기 관통 배선의 일부를 제거하여, 상기 밀봉 부재의 표면에 비하여 리세스된 표면을 가지는 관통 배선을 형성하는 단계;를 더 포함하고,Removing a portion of the through wiring to form a through wiring having a recessed surface relative to the surface of the sealing member;
    상기 외측 연결 부재는 상기 관통 배선의 상기 리세스된 표면에 부착되는 것을 특징으로 하는 반도체 패키지의 제조 방법.And the outer connecting member is attached to the recessed surface of the through wiring.
  4. 제 3 항에 있어서,The method of claim 3, wherein
    상기 리세스된 표면을 가지는 관통 배선을 형성하는 단계는 습식 식각을 이용하여 수행되는 것을 특징으로 하는 반도체 패키지의 제조 방법.And forming a through wiring having the recessed surface is performed using wet etching.
  5. 제 1 항에 있어서,The method of claim 1,
    상기 돌출부를 형성하는 단계를 수행한 후에,After performing the step of forming the protrusions,
    상기 도전 부재에서 원하지 않는 잔류물을 제거하기 위하여, 상기 돌출부가 형성된 상기 도전 부재를 세정하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Cleaning the conductive member on which the protrusion is formed in order to remove unwanted residues from the conductive member.
  6. 제 1 항에 있어서, The method of claim 1,
    상기 관통 배선을 형성하는 단계는,Forming the through wiring,
    상기 밀봉 부재의 일부와 상기 도전 부재의 상기 평면부를 연마, 에치백 또는 기계적 화학적 연마를 이용하여 제거하는 단계;를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Removing a portion of the sealing member and the planar portion of the conductive member by polishing, etch back, or mechanical chemical polishing.
  7. 제 6 항에 있어서,The method of claim 6,
    상기 관통 배선을 형성하는 단계는,Forming the through wiring,
    상기 밀봉 부재의 일부와 상기 도전 부재의 상기 평면부를 연마, 에치백 또는 기계적 화학적 연마를 이용하여 제거하는 단계를 수행한 후에,After removing a part of the sealing member and the planar portion of the conductive member using polishing, etch back or mechanical chemical polishing,
    원하지 않는 잔류물을 제거하기 위하여, 상기 관통 배선을 세정하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Cleaning the through wires in order to remove unwanted residues.
  8. 제 1 항에 있어서, The method of claim 1,
    상기 밀봉 부재를 형성하는 단계를 수행하기 전에, Before performing the step of forming the sealing member,
    상기 도전 부재를 제1 캐리어 기판 상에 부착하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And attaching the conductive member on the first carrier substrate.
  9. 제 8 항에 있어서,The method of claim 8,
    상기 돌출부를 노출하여 상기 관통 배선을 형성하는 단계는,Exposing the protrusion to form the through wiring,
    상기 노출된 돌출부 상에 제2 캐리어 기판을 부착하는 단계; 및Attaching a second carrier substrate on the exposed protrusions; And
    상기 제1 캐리어 기판을 제거하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And removing the first carrier substrate.
  10. 제 9 항에 있어서,The method of claim 9,
    상기 재배선 패턴층을 형성하는 단계를 수행한 후에,After the step of forming the redistribution pattern layer,
    상기 제2 캐리어 기판을 제거하는 단계; 및Removing the second carrier substrate; And
    상기 재배선 패턴층 상에 제3 캐리어 기판을 부착하는 단계;를 더 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And attaching a third carrier substrate on the redistribution pattern layer.
  11. 제 1 항에 있어서, The method of claim 1,
    상기 재배선 패턴층을 형성하는 단계는,Forming the redistribution pattern layer,
    상기 관통 배선 상에, 상기 관통 배선을 노출하는 제1 절연층을 형성하는 단계;Forming a first insulating layer on the through wiring to expose the through wiring;
    상기 제1 절연층 상에 상기 관통 배선과 전기적으로 연결되는 재배선 패턴을 형성하는 단계; 및Forming a redistribution pattern electrically connected to the through wiring on the first insulating layer; And
    상기 재배선 패턴 상에, 상기 재배선 패턴의 일부 영역을 노출하는 제2 절연층을 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And forming a second insulating layer on the redistribution pattern, exposing a portion of the redistribution pattern.
  12. 제 1 항에 있어서,The method of claim 1,
    상기 돌출부를 형성하는 단계는, Forming the protrusions,
    상기 도전 부재를 포토리소그래피 및 식각 공정을 이용하여 일부 영역을 제거하여 상기 돌출부를 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.Forming the protrusion by removing a portion of the conductive member using photolithography and etching processes.
  13. 제 1 항에 있어서,The method of claim 1,
    상기 돌출부를 형성하는 단계는, Forming the protrusions,
    상기 도전 부재를 프레스 가공하여 상기 돌출부를 형성하는 단계;를 포함하는 것을 특징으로 하는 반도체 패키지의 제조 방법.And pressing the conductive member to form the protruding portion.
  14. 도전 부재의 일부 영역을 제거하여 형성한 돌출부를 이용하여 형성된 관통 배선;A through wiring formed by using a protrusion formed by removing a portion of the conductive member;
    상기 관통 배선 상에 위치하고, 상기 관통 배선과 전기적으로 연결되는 재배선 패턴층;A redistribution pattern layer disposed on the through wiring and electrically connected to the through wiring;
    상기 재배선 패턴층 상에 위치하고, 상기 재배선 패턴층과 전기적으로 연결된 반도체 칩; 및A semiconductor chip disposed on the redistribution pattern layer and electrically connected to the redistribution pattern layer; And
    상기 관통 배선과 전기적으로 연결되는 외부 연결 부재;를 포함하는 반도체 패키지.And an external connection member electrically connected to the through wiring.
  15. 제 14 항에 있어서,The method of claim 14,
    상기 반도체 칩과 재배선 패턴층 사이의 공간을 충전하는 언더필 층;을 더 포함하는 것을 특징으로 하는 반도체 패키지.And an underfill layer filling the space between the semiconductor chip and the redistribution pattern layer.
  16. 제 14 항에 있어서,The method of claim 14,
    상기 반도체 칩은 복수의 반도체 칩들을 포함하는 것을 특징으로 하는 반도체 패키지.The semiconductor chip comprises a plurality of semiconductor chips.
  17. 제 14 항에 있어서,The method of claim 14,
    상기 재배선 패턴층 상에 위치하고 상기 반도체 칩을 밀봉하는 외부 밀봉 부재;를 더 포함하는 것을 특징으로 하는 반도체 패키지.And an outer sealing member disposed on the redistribution pattern layer and sealing the semiconductor chip.
  18. 제 14 항에 있어서, The method of claim 14,
    상기 관통 배선은 상기 밀봉 부재의 표면에 비하여 리세스된 표면을 가지고,The through wiring has a recessed surface compared to the surface of the sealing member,
    상기 외측 연결 부재는 상기 관통 배선의 상기 리세스된 표면에 부착된 것을 특징으로 하는 반도체 패키지.And the outer connecting member is attached to the recessed surface of the through wiring.
  19. 제 14 항에 있어서, The method of claim 14,
    상기 관통 배선은 구리, 구리 합금, 알루미늄, 또는 알루미늄 합금을 포함하는 것을 특징으로 하는 반도체 패키지.The through wiring comprises a copper, a copper alloy, aluminum, or an aluminum package.
  20. 제 14 항에 있어서, The method of claim 14,
    상기 밀봉 부재는 에폭시 몰딩 컴파운드를 포함하는 것을 특징으로 하는 반도체 패키지.And the sealing member comprises an epoxy molding compound.
PCT/KR2012/002626 2012-03-30 2012-04-06 Semiconductor package and method for manufacturing same WO2013147359A1 (en)

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