WO2013128998A1 - 撮像素子および電子機器 - Google Patents
撮像素子および電子機器 Download PDFInfo
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- WO2013128998A1 WO2013128998A1 PCT/JP2013/051720 JP2013051720W WO2013128998A1 WO 2013128998 A1 WO2013128998 A1 WO 2013128998A1 JP 2013051720 W JP2013051720 W JP 2013051720W WO 2013128998 A1 WO2013128998 A1 WO 2013128998A1
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14601—Structural or functional details thereof
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- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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Definitions
- This technology relates to an image sensor. Specifically, the present invention relates to an image sensor and electronic equipment that detect weak light.
- CMOS Complementary Metal Oxide Semiconductor
- feeble light can be detected by counting the number of photons incident on each pixel of the CMOS image sensor (photon counting).
- the pixel signal at the time of detecting the weak light is very small, it is desired to reflect the electron generated by the photoelectric conversion in the intensity of the image signal without losing as much as possible.
- carriers electrons generated in the photodiode are transferred to the floating diffusion, carriers (electrons) are trapped in the interface order generated due to defects (interface defects) existing at the gate oxide film interface of the transfer transistor. End up. As a result, a part of the generated electrons is lost.
- the maximum number of trapped electrons is several tens, the number of trapped electrons is given to the pixel signal in a general application in which a large number of electrons are accumulated (for example, shooting a landscape). There is little influence.
- it is assumed that the influence of the number of trapped electrons on the pixel signal increases. Therefore, it is important to improve the detection accuracy (photon counting accuracy) by reducing the number of trapped electrons.
- This technology was created in view of these circumstances, and aims to improve the accuracy of photon counting.
- a first aspect of the present technology includes a transfer transistor configured by a buried channel type MOS transistor, and the transfer transistor in an on-state from a photodiode.
- a pixel that outputs a pixel signal based on the charge transferred to the floating diffusion, and the output pixel signal is converted into a digital value, and the converted digital value is compared with a threshold value to generate the pixel signal.
- the photodiode includes a charge storage region configured by a first conductivity type impurity diffusion layer, and the floating diffusion is configured by the first conductivity type impurity diffusion layer.
- the transfer transistor includes a channel region serving as a channel between the photodiode and the floating diffusion, and the channel region has an impurity diffusion layer of the first conductivity type having a concentration of 1 ⁇ 10 15 atoms / cm 3 or more. It may be configured by.
- the channel region is formed by the first conductivity type impurity diffusion layer having a concentration of 1 ⁇ 10 15 atoms / cm 3 or more.
- the channel region may have an impurity peak formed at a depth within 0.2 ⁇ m from the substrate surface on the side where the gate electrode of the transfer transistor is formed. As a result, a channel region having an impurity peak is formed at a depth within 0.2 ⁇ m from the substrate surface.
- the channel region functions as an overflow drain for discharging surplus charges from the charge storage region to the impurity diffusion layer when the transfer transistor is in an OFF state. You may make it like the image pick-up element of description. As a result, the transfer transistor functions as a channel region overflow drain when the transfer transistor is in the OFF state.
- the transfer transistor is configured to reduce the potential on the surface of the substrate facing the gate electrode due to a work function difference between the gate electrode of the transfer transistor and the substrate facing the gate electrode.
- the channel may be formed at a position away from the surface of the substrate facing the gate electrode toward the inside of the substrate.
- the potential at the surface of the substrate facing the gate electrode is reduced, and the channel is formed at a position away from the surface of the substrate facing the gate electrode toward the inside of the substrate.
- the transfer transistor has an impurity peak formed at a depth within 0.2 ⁇ m from the substrate surface on the side where the gate electrode of the transfer transistor is formed, and the impurity peak
- a second conductivity type impurity diffusion layer may be formed between the gate electrode and the gate electrode.
- an impurity peak is formed at a depth within 0.2 ⁇ m from the substrate surface on the side where the gate electrode of the transfer transistor is formed, and the second conductivity type is formed between the impurity peak and the gate electrode.
- the impurity diffusion layer is formed.
- a second aspect of the present technology includes a transfer transistor configured by a buried channel MOS transistor, and outputs a pixel signal based on the charge transferred from the photodiode to the floating diffusion by the transfer transistor in the on state.
- a determination unit that converts a pixel and the output pixel signal into a digital value, compares the converted digital value with a plurality of threshold values, and determines the number of photons that have entered the pixel that generated the pixel signal; It is an image pick-up element which comprises.
- a third aspect of the present technology includes a transfer transistor including a buried channel MOS transistor, and outputs a pixel signal based on the charge transferred from the photodiode to the floating diffusion by the transfer transistor in the on state.
- a determination unit that converts a pixel and the output pixel signal into a digital value, compares the converted digital value with a threshold value, and binaryly determines whether a photon is incident on the pixel that generated the pixel signal; Is an electronic device. This brings about the effect of reducing the influence of the interface state in the transfer transistor in the electronic device that binaryly determines whether or not the photon is incident on the pixel.
- FIG. 3 is a schematic diagram illustrating an example of a circuit configuration of a pixel 310 according to the first embodiment of the present technology.
- FIG. FIG. 3 is a diagram schematically illustrating an example of a layout of a pixel 310 according to the first embodiment of the present technology. It is a figure showing typically the section composition of transfer transistor 312 of pixel 310 of a 1st embodiment of this art.
- FIG. 6 is a diagram schematically showing a potential profile in the depth direction (position indicated by the line AB in FIG. 4) of the transfer gate electrode 541 of the transfer transistor 312 according to the first embodiment of the present technology.
- FIG. 6 is a diagram schematically showing a potential profile in the lateral direction (position on the CD line in FIG. 4) of the n-type diffusion layer 542 in the first embodiment of the present technology.
- FIG. 3 is a diagram schematically illustrating an electron transfer path in a pixel 310 provided in the image sensor 100 according to the first embodiment of the present technology and an electron transfer path in a pixel provided in another image sensor. It is a figure showing typically the section composition of the transfer transistor of the pixel of a 2nd embodiment of this art.
- FIG. 9 is a diagram schematically illustrating a potential profile in a depth direction (a position indicated by a line AB in FIG. 8) of a transfer gate electrode 611 according to the second embodiment of the present technology.
- FIG. 14 is a graph showing the relationship between the average number of photons incident on each pixel during a unit exposure period and the count probability in the third embodiment of the present technology.
- First embodiment imaging control: an example in which a buried channel type transfer transistor is configured using a work function of a transfer gate electrode
- Second Embodiment Imaging Control: Example in which a buried channel type transfer transistor is configured by adjusting an impurity profile
- Third Embodiment Imaging Control: Example of Photon Detection
- FIG. 1 is a conceptual diagram illustrating an example of a basic configuration example of the image sensor 100 according to the first embodiment of the present technology.
- the image sensor 100 is a light detector provided in a system for detecting faint light (for example, an imaging plate fluorescent scanner, a radiation scintillation counter, etc.).
- the image sensor 100 is realized by, for example, a CMOS (Complementary Metal Metal Oxide Semiconductor) sensor.
- the image sensor 100 includes a pixel array unit 300, a first vertical drive circuit 112, a determination circuit 400, a register 114, a second vertical drive circuit 115, and an output circuit 118.
- the determination circuit and the register for processing the signal of the pixel driven by the second vertical drive circuit 115 are the determination circuit (the determination circuit 400) for processing the signal of the pixel driven by the first vertical drive circuit 112. ) And the register (register 114), the description is omitted.
- the pixel array unit 300 includes a plurality of pixels (pixels 310) arranged in a two-dimensional matrix (n ⁇ m).
- pixels 310) arranged in a two-dimensional matrix (n ⁇ m).
- n ⁇ m two-dimensional matrix
- the pixels 310 of 128 rows ⁇ 128 columns are arranged in the pixel array unit 300.
- Half of the pixels 310 arranged in the pixel array unit 300 (pixels located in the upper half of the pixel array unit 300 in FIG. 1) have a control line (control line 330) from the first vertical drive circuit 112. Wired in rows.
- control lines are wired from the second vertical drive circuit 115 in units of rows. Note that the circuit configuration of the pixel 310 will be described with reference to FIG.
- a vertical signal line (vertical signal line 341) is wired to the pixel 310 in units of columns.
- the vertical signal line 341 connected to the pixel to which the control line 330 is wired from the first vertical drive circuit 112 is connected to the determination circuit 400 facing the upper side of the pixel array unit 300.
- the vertical signal line 341 connected to the pixel to which the control line 330 is wired from the second vertical driving circuit 115 is connected to the determination circuit 400 facing the lower side of the pixel array unit 300.
- the first vertical drive circuit 112 supplies a signal to the pixel 310 via the control line 330 and sequentially scans the pixel 310 in units of rows in the vertical direction (column direction). As the first vertical drive circuit 112 performs selective scanning in units of rows, a signal is output from the pixels 310 in units of rows.
- the control line 330 includes a pixel reset line 331 and a charge transfer line 332. Since the pixel reset line 331 and the charge transfer line 332 will be described with reference to FIG. 2, description thereof is omitted here.
- the second vertical drive circuit 115 is the same except that the pixel 310 to be controlled is different from the first vertical drive circuit 112, and thus the description thereof is omitted here.
- the determination circuit 400 calculates the amount of light incident on the pixel 310 based on the output signal supplied from the pixel 310.
- the determination circuit 400 is provided for each vertical signal line 341. That is, at the position facing the upper side of the pixel array unit 300, 128 pieces connected to 128 vertical signal lines 341 wired to pixels (64 rows ⁇ 128 columns) driven by the first vertical drive circuit 112, respectively. Determination circuit 400 is provided. Further, at the position facing the lower side of the pixel array unit 300, 128 pieces connected to 128 vertical signal lines 341 wired to pixels (64 rows ⁇ 128 columns) driven by the second vertical drive circuit 115, respectively. Determination circuit 400 is provided.
- the register 114 is provided for each determination circuit 400, and temporarily holds the determination result supplied from the determination circuit 400.
- the register 114 sequentially outputs the determination results to be held to the output circuit 118 during the period in which the signal of the next row of pixels is read (reading period).
- the output circuit 118 outputs a signal generated by the image sensor 100 to an external circuit.
- FIG. 2 is a schematic diagram illustrating an example of a circuit configuration of the pixel 310 according to the first embodiment of the present technology.
- the pixel 310 converts an optical signal that is incident light into an electrical signal by performing photoelectric conversion.
- the pixel 310 amplifies the converted electric signal and outputs it as a pixel signal.
- the pixel 310 amplifies an electric signal by an FD amplifier having a floating diffusion layer (floating diffusion: FD).
- the pixel 310 includes a photodiode 311, a transfer transistor 312, a reset transistor 313, and an amplifier transistor 314.
- the photodiode 311 has its anode terminal grounded and its cathode terminal connected to the source terminal of the transfer transistor 312.
- the transfer transistor 312 has a gate terminal connected to the charge transfer line 332 and a drain terminal connected to the source terminal of the reset transistor 313 and the gate terminal of the amplifier transistor 314 via the floating diffusion (FD 322).
- the reset transistor 313 has its gate terminal connected to the pixel reset line 331 and its drain terminal connected to the power supply line 323 and the drain terminal of the amplifier transistor 314.
- the source terminal of the amplifier transistor 314 is connected to the vertical signal line 341.
- the photodiode 311 is a photoelectric conversion element that generates an electric charge according to the intensity of light.
- a pair of electrons and holes is generated by photons incident on the photodiode 311, and the generated electrons are stored here.
- the transfer transistor 312 transfers electrons generated in the photodiode 311 to the FD 322 in accordance with a signal (transfer pulse) from the vertical drive circuit (the first vertical drive circuit 112 or the second vertical drive circuit 115). For example, when a signal (pulse) is supplied from the charge transfer line 332 supplied to the gate terminal of the transfer transistor 312, the transfer transistor 312 becomes conductive and transfers electrons generated in the photodiode 311 to the FD 322.
- the transfer transistor 312 is realized by a buried channel type MOS transistor in order to prevent carriers from being trapped by interface defects. Note that details of the transfer transistor 312 will be described with reference to FIG.
- the reset transistor 313 is for resetting the potential of the FD 322 in accordance with a signal (reset pulse) supplied from the vertical drive circuit (the first vertical drive circuit 112 or the second vertical drive circuit 115).
- the reset transistor 313 becomes conductive when a reset pulse is supplied to the gate terminal via the pixel reset line 331, and a current flows from the FD 322 to the power supply line 323.
- a reset potential As a result, electrons accumulated in the floating diffusion (FD 322) are extracted to the power source, and the FD 322 is reset (hereinafter, this potential is referred to as a reset potential). Note that when the photodiode 311 is reset, the transfer transistor 312 and the reset transistor 313 are simultaneously turned on.
- a potential (power supply) flowing through the power supply line 323 is a power supply used for resetting and a source follower, and for example, 3 V is supplied.
- the amplifier transistor 314 is for amplifying the potential of the floating diffusion (FD 322) and outputting a signal (output signal) corresponding to the amplified potential to the vertical signal line 341.
- the amplifier transistor 314 When the potential of the floating diffusion (FD 322) is reset (in the case of the reset potential), the amplifier transistor 314 outputs an output signal (hereinafter referred to as a reset signal) corresponding to the reset potential vertically. Output to the signal line 341.
- the amplifier transistor 314 outputs an output signal (hereinafter referred to as an accumulated signal) corresponding to the amount of transferred electrons to the vertical signal. Output to line 341.
- a selection transistor may be provided for each pixel between the amplifier transistor 314 and the vertical signal line 341.
- the basic circuit and operation mechanism of the pixel as shown in FIG. 2 are the same as those of a normal pixel, and various other variations are possible.
- the pixel assumed in the present invention is designed so that the conversion efficiency is significantly higher than that of the conventional pixel.
- the pixel is designed so that the parasitic capacitance (parasitic capacitance of the FD 322) of the gate terminal of the amplifier (amplifier transistor 314) constituting the source follower is effectively reduced to the limit.
- FIG. 3 is a diagram schematically illustrating an example of the layout of the pixel 310 according to the first embodiment of the present technology.
- a photodiode 311, an FD 322, and a vertical signal line 341 are shown in the layout of the pixel 310 shown in FIG. 3.
- the gate terminal wiring (gate wiring 362) of the transfer transistor 312, the reset transistor 313 gate terminal wiring (gate wiring 363), and the amplifier transistor 314 gate terminal wiring (gate wiring 364) are shown in FIG. 3.
- the FD 322 is indicated by a thick broken line
- the vertical signal line 341 is indicated by a thin broken line
- the gate wirings 362 to 364 are indicated by hatched rectangles.
- FIG. 3 shows an impurity diffusion layer (diffusion layer 371) corresponding to the drain terminal of the transfer transistor 312, the source terminal of the reset transistor 313, and the wiring between the two terminals.
- FIG. 3 also shows an impurity diffusion layer (diffusion layer 372) corresponding to the drain terminal of the reset transistor 313, the drain terminal of the amplifier transistor 314, and the wiring between the two terminals.
- FIG. 3 shows an impurity diffusion layer (diffusion layer 373) corresponding to the source terminal of the amplifier transistor 314.
- the diffusion layers 371 to 373 are indicated by rectangles with fine dots.
- a contact (contact 382) for connecting the gate wiring 362 to the charge transfer line 332 and a contact (contact 383) for connecting the gate wiring 363 to the pixel reset line 331 are shown. Yes.
- This layout also shows a contact (contact 384) for connecting the gate wiring 364 to the FD 322 and a contact (contact 385) for connecting the diffusion layer 371 to the FD 322.
- a contact (contact 386) for connecting the diffusion layer 372 to the power supply line 323 and a contact (contact 387) for connecting the diffusion layer 373 to the vertical signal line 341 are shown. .
- the diffusion layer 371 and the gate wiring 364 are part of a floating diffusion that has the same potential fluctuation as that of the FD 322. However, for convenience of explanation, another reference numeral is given in FIG.
- the layout of the pixel 310 will be described by focusing on the size of the FD 322.
- the layout of the pixel 310 is designed so that the parasitic capacitance in the FD 322 is minimized. Therefore, in the pixel 310, the layout is designed so that the FD 322, which is a wiring portion that connects the diffusion layer 371 to the gate wiring 364, the diffusion layer 371, and the gate wiring 364 have the smallest possible area. Further, in the pixel 310, the width of the drain terminal of the amplifier transistor 314 (near the gate wiring 364 of the diffusion layer 373) is narrowed, and at the same time, the wiring of the FD 322 is connected to the source terminal of the amplifier transistor 314 (vertical signal line 341). Most are covered flatly.
- the output of the source follower has a gain close to 1 with respect to the input, the substantial parasitic capacitance between the vertical signal line 341 and the FD 322 is very small. For this reason, as shown in FIG. 3, by using a shield structure in which the FD 322 is covered with the vertical signal line 341, the parasitic capacitance in the FD 322 can be minimized and the conversion efficiency can be greatly increased.
- the output signal is sufficiently larger than the random noise, so in principle one photon Can be detected.
- an output signal of a pixel including a photodiode and an amplifier transistor can be handled as binary data or analog data having a gradation when the conversion efficiency is sufficiently high.
- a pixel has a problem that the upper limit (dynamic range) of the detected light amount in one imaging is small.
- it is effective to increase the frame rate by increasing the reading speed of the signal output from the pixel and accumulate the results of reading multiple times. For example, in the case of binary determination of the incidence of photons, if 1023 exposures and readouts are performed and the results are integrated, the dynamic range per pixel becomes 10-bit gradation data.
- the dynamics per pixel is 10-bit gradation data.
- the maximum number of accumulated electrons is 1000e ⁇ and the number of photons is determined after analog output, if the results are accumulated by performing 16 exposures and readings, the maximum number of accumulated electrons is 16, Equivalent to the output of a pixel that is 000e ⁇ .
- the dynamic range can also be improved by arranging a plurality of fine pixels in an array and using the plurality of pixels as one light receiving surface. For example, when a pixel (pixel group) of 8 rows ⁇ 8 columns is used as one light-receiving surface, it corresponds to 6 bits by binary determination of the photons incident on the pixels of 8 rows ⁇ 8 columns and summing them. The determination result of the light intensity of 64 gradations can be acquired. Furthermore, when such surface division is used in combination with time division, the dynamic range can be further increased.
- FIG. 4 is a diagram schematically illustrating a cross-sectional configuration of the transfer transistor 312 of the pixel 310 according to the first embodiment of the present technology.
- FIG. 4 focuses on the transfer transistor 312, and shows a cross section of the positions of the photodiode 311, the gate wiring 362, and the diffusion layer 371 in the plan view shown in FIG.
- the configuration of the pixel 310 is set inside a p-well (p-well 512) formed with an appropriate impurity profile using several stages of ion implantation in an n-type high-resistance epitaxial substrate (substrate 511).
- p-well 512 p-well 512
- substrate 511 n-type high-resistance epitaxial substrate
- the explanation is based on the assumption that a part is built. Note that “+” and “ ⁇ ” shown in FIG. 4 indicate impurity concentrations. For example, in a p-type layer, the impurity concentration relationship is p ⁇ ⁇ p ⁇ p +.
- FIG. 4 shows a substrate 511, a p-well 512, a storage region 521, a p-type diffusion layer 522, a floating diffusion region 531, a transfer gate electrode 541, and an n-type diffusion layer 542.
- the insulating film 551 made of an oxide film and the element isolation region 552 are indicated by dotted regions.
- the floating diffusion region 531 is a region corresponding to the floating diffusion (FD), and is composed of an n + type impurity layer.
- the floating diffusion region 531 corresponds to the diffusion layer 371 in FIG. That is, the potential fluctuation in the floating diffusion region 531 is output as a pixel signal via the amplifier transistor 314.
- the accumulation area 521 is an accumulation area for accumulating charges generated by photoelectric conversion.
- the accumulation region 521 is a charge accumulation region in the photodiode 311 and is formed of an n-type impurity layer.
- a p + -type impurity diffusion layer (p-type diffusion layer 522) is formed facing the insulating film 551 on the interface side of the accumulation region 521 (upper side in FIG. 4).
- the p-type diffusion layer 522 functions as a hole accumulation region in the photodiode 311.
- a buried photodiode having a pnp-type HAD (Hole Accumulated Diode) structure is formed in the pixel 310.
- the transfer gate electrode 541 is a p + type silicon layer provided on the insulating film 551.
- the transfer gate electrode 541 faces the n-type region (n-type diffusion layer 542) via the insulating film 551, and forms a buried channel type MOS transistor.
- the transfer gate electrode 541 corresponds to the gate terminal of the transfer transistor 312 (see FIG. 2), and is made conductive, whereby charges are transferred from the accumulation region 521 to the floating diffusion region 531.
- the transfer gate electrode 541 corresponds to the gate wiring 362 shown in FIG.
- the transfer gate electrode 541 is formed by doping a p-type impurity (for example, boron) having a high concentration of, for example, 1 ⁇ 10 19 atoms / cm 3 or more. Thereby, the difference between the potential in the vicinity of the insulating film 551 (the substrate surface facing the transfer gate electrode 541) facing the transfer gate electrode 541 and the potential in the p well 512 is reduced. That is, by introducing a P-type impurity having a high concentration into the transfer gate electrode 541, the potential is raised in a direction in which the potential depression on the substrate surface facing the transfer gate electrode 541 becomes shallow due to the work function difference.
- a p-type impurity for example, boron
- the n-type diffusion layer 542 is an n-type impurity layer provided directly below the transfer gate electrode 541 (the lower side in FIG. 4).
- the n-type diffusion layer 542 is formed such that the ends (the right end and the left end of the n-type diffusion layer 542 shown in FIG. 4) are in contact with the accumulation region 521 and the floating diffusion region 531.
- the n-type diffusion layer 542 is formed by doping an n-type impurity (for example, arsenic or phosphorus) having a high concentration of 1 ⁇ 10 15 atoms / cm 3 or more, for example.
- the n-type diffusion layer 542 is formed so that an impurity concentration peak exists at a depth within 0.2 ⁇ m from the insulating film 551 (substrate surface) in order to ensure the operation as a buried channel.
- the channel path when the transfer transistor 312 is in a conductive state (hereinafter referred to as a gate-on state) is away from the substrate surface, and a completely embedded channel is formed. Note that details of the n-type diffusion layer 542 will be described with reference to FIGS. 5 and 6, and a description thereof will be omitted here.
- FIG. 5 and FIG. 6 the relationship between on / off of the transfer transistor 312 and the channel in the n-type diffusion layer 542 will be described by showing potential transitions in the AB line and the CD line shown in FIG. .
- FIG. 5 is a diagram schematically illustrating a potential profile in the depth direction (position indicated by the line AB in FIG. 4) of the transfer gate electrode 541 of the transfer transistor 312 according to the first embodiment of the present technology.
- FIG. 5a shows the potential profile in the gate-off state
- b in FIG. 5 shows the potential profile in the gate-on state.
- FIG. 5 shows the potential along the line AB shown in FIG.
- FIG. 5 shows a region (region 561) indicating the position of a region where the potential is minimized (potential depression) and a black circle (electron 562) indicating electrons.
- the transfer gate electrode 541 is doped p + type, so that it is depleted due to a work function difference. Therefore, in the vicinity of the substrate surface of the n-type diffusion layer 542, the potential is raised in a shallow direction (upper side in FIG. 5). Therefore, in the n-type diffusion layer 542, a potential depression (region 561) is formed at a location away from the insulating film 551.
- a potential depression region 561 where electrons flow is formed in a region away from the insulating film 551.
- FIG. 6 is a diagram schematically illustrating a potential profile in the horizontal direction (position along the line CD in FIG. 4) of the n-type diffusion layer 542 according to the first embodiment of the present technology.
- FIG. 6a shows the potential profile in the gate-off state
- FIG. 6b shows the potential profile in the gate-on state.
- FIG. 6 shows the potential along the CD line shown in FIG. In FIG. 6, the vertical direction is an axis indicating potential, and the downward direction (lower side in FIG. 6) is a positive potential.
- the potential depression (region 561) shown in FIG. 5 is indicated by a region (region 571) surrounded by a chain line. Note that the vertical size (vertical width) of the region 571 will be described as indicating the height of the potential barrier formed in the potential depression.
- the potential in the potential depression (region 571) formed in the n-type diffusion layer 542 is the potential in the accumulation region 521 and the floating diffusion region 531. It becomes shallower than the bottom. Further, the potential in the potential depression (region 571) becomes deeper than the potential of the potential barrier formed by the p-well 512 surrounding the accumulation region 521. That is, the potential of the potential depression (region 571) in the gate-off state is more positive than the potential of the p-well 512, but is more negative than the accumulation region 521 and the floating diffusion region 531.
- electrons accumulated in the accumulation region 521 are scraped off at the height of the barrier formed by the potential depression (region 571).
- electrons accumulated in the accumulation region 521 are indicated by a grayed region (region 572), and the electron path over the potential depression (region 571) is indicated by a broken arrow (arrow 574). ).
- the surplus electrons overcome the barrier due to the potential depression (region 571). It is discharged to the floating diffusion region 531. That is, when the transfer transistor 312 is in a gate-off state, the n-type diffusion layer 542 functions as a lateral overflow drain, and prevents electrons overflowing from the accumulation region 521 from leaking to other pixels.
- the electrons discharged to the floating diffusion region 531 are discharged to the power source by turning on the reset transistor 313 (see FIG. 2) during the electron accumulation period (exposure period).
- the potential in the potential depression (region 571) formed in the n-type diffusion layer 542 is lower than the potential bottom in the accumulation region 521. Is also modulated to be deeper. Note that the bottom of the potential of the floating diffusion region 531 is deeper than the potential of the modulated potential depression (region 571). As described above, as the potential increases from the accumulation region 521 toward the floating diffusion region 531, the electrons accumulated in the accumulation region 521 are completely transferred to the floating diffusion region 531.
- the n-type diffusion layer 542 functions as an electron transfer path and also functions as a lateral overflow drain.
- FIG. 7 is a diagram schematically illustrating an electron transfer path in the pixel 310 included in the image sensor 100 according to the first embodiment of the present technology and an electron transfer path in a pixel included in another image sensor. is there.
- FIG. 7a shows an electron transfer path in a pixel included in another image sensor
- b in FIG. 7 shows an electron transfer path in a pixel 310 included in the image sensor 100.
- the 7 includes a substrate 591, a p-well 592, a storage region 593, a p-type diffusion layer 594, a floating diffusion region 595, a transfer gate electrode 596, an insulating film 597, An element isolation region 598 is shown.
- the transfer gate electrode is an n + type silicon layer, and the channel is formed on the substrate surface (position immediately below the insulating film 597).
- the channel is formed on the substrate surface, some of the transferred electrons are trapped in the interface state existing on the substrate surface. Since the number of electrons trapped at the interface state existing on the substrate surface is several to several tens of levels as long as there is no abnormality at the interface, the level is not a problem in normal imaging. However, when weak light such as one-photon detection is detected, the number of transferred electrons is small (for example, one for one-photon detection), which is a big problem.
- the noise (decrease in electrons) generated by this trap is a noise factor that cannot be relatively reduced even if the conversion efficiency in the amplifier transistor is increased, so that the number of accumulated electrons (that is, the number of incident photons) is digitally determined. (For example, a photon counting device) generates a serious error.
- the electron transfer path in the pixel 310 is not affected by the interface state because the channel is completely embedded as indicated by the arrow 582.
- the capture cross section of various carrier traps in silicon is about 1 ⁇ 10 ⁇ 14 cm ⁇ 2, so that the square root of the capture cross section of 1 ⁇ 10 ⁇ 7 cm or more is separated from the substrate surface.
- the channel is designed to pass through the substrate surface at least near the drain of the transfer transistor. As a result, a large potential fluctuation in the channel is secured, the leak path in the gate-off state is cut, and the saturation charge amount Qs is set to a large value.
- the imaging device (imaging device 100) for detecting weak light it is sufficient if several electrons can be held in the accumulation region 521.
- one electron is a practical saturation charge amount Qs. Therefore, by designing the transfer transistor using a buried channel type transistor, the accumulated charge can be transferred without being affected by the interface state. In addition, since the channel also functions as an overflow drain, leakage of electrons to other pixels can be easily prevented.
- the n-type diffusion layer 542 is formed by doping an n-type impurity (eg, arsenic or phosphorus) having a high concentration of 1 ⁇ 10 15 atoms / cm 3 or more, thereby accumulating only a few electrons. It can be a pixel that transfers accumulated electrons without being affected by the level. That is, by forming an n-type diffusion layer 542 by doping an n-type impurity having a high concentration of 1 ⁇ 10 15 atoms / cm 3 or more, a pixel suitable for detecting weak light can be formed. .
- an n-type impurity eg, arsenic or phosphorus
- Second Embodiment> In the first embodiment of the present technology, the example in which the transfer gate electrode is formed of a p + type silicon layer and the buried channel is formed using the work function of the transfer gate electrode has been described. However, the formation of the buried channel is not limited to this, and the buried channel can be formed only by adjusting the impurity profile in the substrate.
- FIG. 8 is a diagram schematically illustrating a cross-sectional configuration of the transfer transistor of the pixel according to the second embodiment of the present technology.
- the substrate 511, the p well 512, the storage region 521, the p-type diffusion layer 522, the floating diffusion region 531, the insulating film 551, and the element isolation region 552 are formed in the cross-sectional configuration shown in FIG. Is shown. Further, in the cross-sectional configuration shown in FIG. 8, a transfer gate electrode 611 is shown instead of the transfer gate electrode 541 in FIG. 8 shows a p-type diffusion layer 612 and an n-type diffusion layer 613 instead of the n-type diffusion layer 542 in FIG.
- the transfer gate electrode 611 is an n + type silicon layer provided on the insulating film 551. Note that the transfer gate electrode 611 is similar to the transfer gate electrode 596 (a gate electrode of a transfer transistor provided in another image sensor) illustrated in FIG. 7A, and thus description thereof is omitted here.
- the p-type diffusion layer 612 is a p-type impurity layer provided immediately below the transfer gate electrode 611.
- the p-type diffusion layer 612 is formed so that the ends (the right end and the left end of the p-type diffusion layer 612 shown in FIG. 8) are in contact with the accumulation region 521 and the floating diffusion region 531.
- the p-type diffusion layer 612 has an upper surface facing the insulating film 551 and a lower surface facing the n-type diffusion layer 613. By providing the p-type diffusion layer 612 facing the substrate surface, the potential on the substrate surface is raised in a direction in which the dent becomes shallower.
- the n-type diffusion layer 613 is an n-type impurity layer and is the same layer as the n-type diffusion layer 542 illustrated in FIG.
- the n-type diffusion layer 613 has an upper surface facing the p-type diffusion layer 612, a lower surface facing the p-well 512, and left and right surfaces facing the accumulation region 521 and the floating diffusion region 531.
- the n-type diffusion layer 613 is a layer having the same role as the n-type diffusion layer 542, and thus description thereof is omitted here. That is, the n-type diffusion layer 613 is formed so that the impurity concentration peak exists at a depth within 0.2 ⁇ m from the insulating film 551 (the surface of the substrate).
- the n-type diffusion layer 613 is formed by doping an n-type impurity (for example, arsenic or phosphorus) having a high concentration of 1 ⁇ 10 15 atoms / cm 3 or more.
- FIG. 9 is a diagram schematically illustrating a potential profile in the depth direction (position indicated by the line AB in FIG. 8) of the transfer gate electrode 611 according to the second embodiment of the present technology.
- FIG. 9a shows the potential profile in the gate-off state
- FIG. 9b shows the potential profile in the gate-on state.
- FIG. 9 shows the potential along the line AB shown in FIG.
- FIG. 9 corresponds to the potential profile of FIG. 5, here, differences from the potential profile of FIG. 5 will be described.
- a potential depression (region 631) is formed at a location away from the insulating film 551, similarly to the n-type diffusion layer 542 shown in FIG.
- the role of the potential depression (region 631) is the same as that of the potential depression (region 571) shown in FIG. That is, the potential depression (region 631) has a deeper potential than the potential barrier formed by the p-well 512 surrounding the accumulation region 521, and thus functions as a lateral overflow drain in the gate-off state.
- the potential in the potential depression (region 631) is deeper than the bottom of the potential in the accumulation region 521, and the electrons accumulated in the accumulation region 521 are in the floating diffusion region 531. Is completely transferred to.
- the n-type diffusion layer 613 functions as an electron transfer path and also functions as a lateral overflow drain.
- a buried channel type transfer transistor can be generated only by adjusting the impurity profile in the substrate. That is, according to the second embodiment of the present technology, the accuracy of photon counting can be improved.
- the imaging device to which the first and second embodiments of the present technology are applied is manufactured for a weak light detection device having a multilevel storage signal, the number of electrons that can be stored in the storage region There is also a possibility that the yield may deteriorate due to variations.
- the performance of the accumulation region is sufficient if at least one electron can be accumulated. That is, when the imaging device to which the first and second embodiments of the present technology are applied is used in a one-photon detection device, the variation in the manufacturing process of the accumulation region is not a big problem. As described above, the image sensor to which the first and second embodiments of the present technology are applied is most effective in the one-photon detection and becomes an image sensor suitable for the one-photon detection.
- the configuration of the pixel of the image sensor in the third embodiment of the present technology is the same as that of the first and second embodiments of the present technology, and thus description thereof is omitted here.
- a description will be given focusing on a determination circuit that processes a signal output from a pixel for one-photon detection.
- FIG. 10 illustrates an example of a functional configuration example of a determination circuit (one-photon detection determination circuit 700) for detecting one photon and an operation example of the one-photon detection determination circuit 700 according to the third embodiment of the present technology. It is a conceptual diagram which shows an example.
- a one-photon detection determination circuit 700 shown in FIG. 10 is provided in the image sensor instead of the determination circuit 400 of FIG.
- FIG. 10 a as a functional configuration of the one-photon detection determination circuit 700, an ACDS (Analog Correlated Double Sampling) unit 710, a DCDS (Digital ; CDS; digital correlation double sampling) unit 720, A binary determination unit 730, an adder 741, and a memory 742 are shown.
- ACDS Analog Correlated Double Sampling
- DCDS Digital ; CDS; digital correlation double sampling
- the ACDS unit 710 performs noise removal by analog CDS, and includes a switch 712, a capacitor 713, and a comparator 711.
- the switch 712 is a switch for connecting the vertical signal line 341 to either an input terminal for inputting a reference voltage to the comparator 711 or an input terminal for inputting a signal to be compared to the comparator 711.
- the switch 712 connects the vertical signal line 341 to an input terminal (left terminal to which the capacitor 713 is connected) for inputting a reference voltage.
- the comparator 711 outputs the result of analog CDS
- the switch 712 connects the vertical signal line 341 to an input terminal (a right terminal without a capacitor) for inputting a signal to be compared.
- the capacitor 713 is a storage capacitor for sampling and holding the reset signal of the pixel 310.
- the comparator 711 outputs the difference between the sampled and held signal and the signal to be compared. That is, the comparator 711 outputs the difference between the reset signal sampled and held and the signal (accumulated signal or reset signal) supplied from the vertical signal line 341. That is, the comparator 711 outputs a signal from which noise generated in the pixel 310 such as kTC noise is removed.
- the comparator 711 is realized by an operational amplifier with a gain of 1, for example.
- the comparator 711 supplies the difference signal to the DCDS unit 720.
- the difference signal between the reset signal and the reset signal is referred to as no signal
- the difference signal between the reset signal and the accumulation signal is referred to as a net accumulation signal.
- the DCDS unit 720 performs noise removal by digital CDS, and includes an AD (Analog Digital) conversion unit 721, a register 722, a switch 723, and a subtractor 724.
- AD Analog Digital
- the AD conversion unit 721 performs AD conversion on the signal supplied from the comparator 711.
- the switch 723 is a switch for switching the supply destination of the signal after AD conversion generated by the AD conversion unit 721.
- the switch 723 supplies the signal to the register 722 and causes the register 722 to latch (hold).
- the offset values of the comparator 711 and the AD conversion unit 721 are held in the register 722.
- the switch 723 supplies this signal to the subtractor 724 when the AD conversion unit 721 outputs the result of AD conversion of the net accumulated signal (digital net accumulated signal).
- the register 722 holds the result of no signal AD conversion.
- the register 722 supplies the held result of no signal AD conversion (digital no signal) to the subtractor 724.
- the subtractor 724 subtracts a digital no-signal value from the digital net accumulated signal value.
- the subtractor 724 supplies the subtraction result (net digital value) to the binary determination unit 730.
- the binary determination unit 730 performs binary determination (digital determination).
- the binary determination unit 730 compares the net digital value with the reference signal of the binary determination unit 730 (indicated as “REF” in FIG. 10), and determines whether or not the photon is incident on the pixel 310.
- the determination result (indicated as “BINOUT” in FIG. 10) is output.
- the reference signal (REF) is an intermediate between the digital value of the signal (no signal) output from the pixel 310 when no photon is incident and the digital value of the signal (no signal) output from the pixel 310 when the photon is incident.
- a value near the value is set (for example, “50” between “0” and “100” is a reference signal). That is, the reference signal (REF) functions as a threshold value.
- a signal (BINOUT) having a value of “1” is output as “photon incident”.
- a signal (BINOUT) having a value of “0” is output as “no photon incidence”. That is, the binary determination unit 730 outputs the presence / absence of photon incidence as a digital value (0 or 1) of the binary determination result.
- the binary determination unit 730 supplies the determination result (BINOUT) to the adder 741.
- the adder 741 adds the digital value of the determination result supplied from the binary determination unit 730 to the count value for each pixel held in the memory 742.
- the adder 741 acquires from the memory 742 the count value of the pixel 310 that has generated the accumulation signal converted into a digital value by binary determination, and adds the digital value of the binary determination result to the acquired count value. Then, the adder 741 supplies the added count value to the memory 742 and updates the count value of the pixel.
- the memory 742 is a memory that digitally stores a count value indicating the light intensity for each pixel.
- the memory 742 outputs a count value obtained by integrating the binary determination result a predetermined number of times from the output circuit.
- signal lines to the output circuit are omitted.
- the binary determination unit 730 and the adder 741 are assumed to be provided for each one-photon detection determination circuit 700.
- the present invention is not limited to this, and a plurality of one-photon detection determinations are provided.
- the binary determination unit 730 and the adder 741 may be shared.
- the binary determination unit 730 and the adder 741 may be provided in a signal processing chip that receives and processes a signal from the semiconductor imaging chip, in addition to being provided in the semiconductor imaging chip (imaging device 100).
- the operation of the one-photon detection determination circuit 700 in the case of binary determination of the presence / absence of photon incidence in one pixel 310 will be described with reference to FIG.
- FIG. 10b shows a flowchart illustrating an example of the operation of the one-photon detection determination circuit 700.
- the frame of each procedure of the flowchart shown by b in FIG. 10 substantially corresponds to the frame surrounding each component shown by a in FIG. That is, the procedure indicated by the double frame indicates the procedure of the pixel 310, the procedure indicated by the long dashed line frame indicates the procedure of the ACDS unit 710, and the procedure indicated by the short dashed line frame indicates the procedure of the DCDS unit 720.
- the procedure indicated by a thick solid line frame indicates the procedure of the binary determination unit 730.
- the ACDS processing by the ACDS unit 710 is not illustrated and will be described together in the procedure when the DCDS unit 720 performs AD conversion.
- the potential of the gate terminal of the amplifier transistor 314 (the potential of the FD 322) is reset, and a reset signal is output to the vertical signal line 341 (step 761).
- the reset signal output from the pixel 310 is sampled and held by the capacitor 713 of the ACDS unit 710 (step 762). Thereafter, a difference signal (no signal) between the reset signal sampled and held and the reset signal output from the pixel 310 is AD-converted by the AD conversion unit 721 of the DCDS unit 720 (step 763).
- the AD-converted no signal includes noise generated by the comparator 711 and the AD conversion unit 721, and a value for canceling (offset) these noises is digitally detected. .
- the result of the AD conversion with no signal is held in the register 722 as an offset value (step 764).
- the electrons accumulated in the photodiode 311 are transferred to the FD 322, and an accumulation signal is output from the pixel 310 (step 765).
- a difference signal (net accumulation signal) between the sampled and held reset signal and the accumulation signal output from the pixel 310 is AD-converted by the AD conversion unit 721 of the DCDS unit 720 (step 766). Note that the AD conversion result includes noise generated by the comparator 711 and the AD conversion unit 721.
- the subtracter 724 outputs a value obtained by subtracting the non-signal AD conversion result (first time) held in the register 722 from the AD conversion result (second time) value of the net accumulated signal. (Step 767). Thereby, noise (offset component) caused by the comparator 711 and the AD conversion unit 721 is canceled, and a digital value (net digital value) of only the accumulated signal output from the pixel 310 is output.
- the reference signal (REF) is near an intermediate value between the digital value of the signal (no signal) output from the pixel 310 when no photon is incident and the digital value of the signal (no signal) output from the pixel 310 when the photon is incident. (For example, “50” between “0” and “100” is a reference signal).
- the value of the digital value output from the subtracter 724 exceeds the value of the reference signal (REF)
- the value “1” is set as “photon incident”.
- Signal (BINOUT) is output.
- a signal (BINOUT) having a value of “0” is output as “no photon incidence”. That is, the image sensor 100 outputs the presence or absence of photon incidence as a digital value (0 or 1) as a binary determination result.
- the digital value of the binary determination result is added to the count value of the pixel 310 that generated the accumulated signal, and the count value of the pixel is updated (step 769).
- one-photon detection is assumed, and the binary determination (binary determination) between “with photon incidence” and “without photon incidence” has been described.
- a plurality of reference signals (REF) are used.
- REF reference signals
- two systems of reference signals (REF) are prepared, and one system is set to an intermediate value between a digital value when the number of photons is “0” and a digital value when the number of photons is “1”.
- the other system is set to an intermediate value between the digital value when the number of photons is “1” and the digital value when the number of photons is “2”.
- the signal output from the pixel 310 is determined as a digital value in the one-photon detection determination circuit 700, so that it is compared with a conventional image sensor that handles analog output (1024 gradations for 10-bit data). Therefore, it is almost completely unaffected by noise during transmission.
- the binary determination result in the plurality of shared pixels is added via the count value, and the plurality of pixels Can be handled as data of one light receiving surface. In this way, the dynamic range in imaging can be improved.
- FIG. 11 is a graph showing the relationship between the average number of photons incident on each pixel during a unit exposure period and the count probability in the third embodiment of the present technology.
- the average number of photons incident on each pixel within the unit exposure period (average number of photons) and the probability that the incident photons are counted (determined as “1” by the one-photon detection determination circuit 700).
- the relationship with (count probability) follows the Poisson distribution.
- P (k) is a probability that photon incidence occurs k times (k photons are incident) in the unit pixel within the unit exposure period.
- ⁇ is the average number of photons incident on the unit pixel (average photon number) within the unit exposure period.
- E is the base of the natural logarithm ( ⁇ 2.718).
- the probability P (k) of the above-described formula 1 indicates the probability that the number of incident photons is the number k of photons when the number of photons incident on each pixel during the unit exposure period is the average number of photons ⁇ . .
- the probability that the photons incident on the unit pixel overlap is smaller as the number of overlapping photons increases.
- the probability that the digital value is “0” is “0.8105”, which is the probability of the case where the number of photons incident on the unit pixel is zero.
- the digital value output from the one-photon detection determination circuit 700 is “1”, this is all cases where one or more photons are incident on the unit pixel.
- the probability that the digital value is “1” (count probability) is “0.1894”, which is the sum of the probabilities of one or more photons incident on the unit pixel.
- the count probability “0.1894” indicates that about 10% of the incident photons are not counted (count loss). This count loss is caused by counting “1” when two or more photons are incident on a unit pixel within the unit exposure period. Therefore, the count loss increases as the average photon number ⁇ increases.
- the average photon number ⁇ is “0.21”.
- the relationship between the average photon number ⁇ and the count probability is such that the photons are spatially and temporally uniform. It is unique when incident randomly. That is, when the vertical axis is the axis indicating the count probability and the horizontal axis is the average number of photons incident on each pixel during the unit exposure period, the relationship between the count probability and the average photon number is represented by the solid line ( The relationship is shown by a line 791).
- the position of the average photon number indicated by a chain line indicates a position where about 10% of the incident photons are counted loss (10% detection loss position).
- a count loss of about 10% is allowed, linearity can be guaranteed when the average number of photons is “0.21” or less. If this is viewed from the side of the digital output value generated by the image sensor, that is, if the count probability in the digital value generated by the image sensor is “0.1894” or less, the image is captured with the illuminance and exposure conditions that can guarantee linearity. It is judged that On the other hand, when the count probability exceeds “0.1894” (the range indicated by the compression area 793 in FIG. 11), it is determined that the count loss is large and linearity cannot be guaranteed.
- the count value can be corrected.
- a count probability (a ratio of pixels having a value of “1” in all pixels) is calculated based on a digital value generated by the image sensor, and the relationship shown in the table of FIG. 11 is shown.
- the average photon number is calculated from the data.
- the number of photons incident on the image sensor is calculated from the calculated average number of photons.
- one-photon determination can be performed without being influenced by the interface state by designing the transfer transistor with a buried channel type transistor. That is, an n-type diffusion layer having an impurity concentration peak at a depth within 0.2 ⁇ m from the insulating film (substrate surface) is formed with an n-type impurity having a high concentration of 1 ⁇ 10 15 atoms / cm 3 or more.
- a transfer transistor suitable for one-photon detection can be provided in the pixel.
- the accuracy of photon counting can be improved by designing the transfer transistor with a buried channel type transistor. That is, by performing photon counting using a CMOS image sensor to which the present technology is applied, it is possible to suppress noise generated during charge transfer in the pixel, such as electron trapping due to interface states. That is, one-photon detection can be performed with pixels having a structure similar to that of a normal CMOS image sensor, and photon counting can be performed with ultra-low noise and ultra-high sensitivity imaging.
- the image pickup element shown in the embodiment of the present technology can be widely applied as a light detection unit in a conventional electronic device provided with a photomultiplier tube, an avalanche photodiode, or a photodiode.
- a fluorescence scanner of an imaging plate and a scintillation counter of radiation can be applied to DNA chip detectors, X-ray imaging devices called DR (Digital Radiography), CT (Computed Tomography) devices, SPECT (Single Photon Emission Tomography) devices, and the like.
- DR Digital Radiography
- CT Computed Tomography
- SPECT Single Photon Emission Tomography
- CMOS image sensor since it is a CMOS image sensor and can be mass-produced at a low price, a large number of light detection units are provided in an electronic device in which only a small number of light detection units are provided due to the high price of photomultiplier tubes. As a result, the detection speed can be improved.
- the imaging device shown in the embodiment of the present technology is introduced into a detector of a CT apparatus, it is possible to detect scintillation light with a much higher sensitivity than a detector using a conventional photodiode or the like, and high accuracy of detection. This can contribute to the reduction in exposure due to the reduction of the X-ray dose and the X-ray dose.
- a photomultiplier tube such as SPECT or PET.
- the effect is not limited only to an electronic device provided with a large number of detection heads, but the same effect can be obtained in an electronic device using a single detection head.
- a pocket dosimeter having a small size and a light weight and an ultra-high sensitivity can be realized using an inexpensive semiconductor imaging device.
- the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it.
- this recording medium for example, a hard disk, CD (Compact Disc), MD (MiniDisc), DVD (Digital Versatile Disc), memory card, Blu-ray Disc (Blu-ray Disc (registered trademark)) or the like can be used.
- this technique can also take the following structures.
- a pixel that includes a transfer transistor configured by a buried channel MOS transistor, and that outputs a pixel signal based on the charge transferred from the photodiode to the floating diffusion by the transfer transistor in the on state;
- a determination unit that converts the output pixel signal into a digital value, compares the converted digital value with a threshold value, and binary-determines whether a photon is incident on the pixel that generated the pixel signal;
- Image sensor a pixel that includes a transfer transistor configured by a buried channel MOS transistor, and that outputs a pixel signal based on the charge transferred from the photodiode to the floating diffusion by the transfer transistor in the on state.
- the photodiode includes a charge storage region configured by an impurity diffusion layer of a first conductivity type,
- the floating diffusion is constituted by the impurity diffusion layer of the first conductivity type
- the transfer transistor includes a channel region serving as a channel between the photodiode and the floating diffusion, and the channel region is the impurity diffusion layer of the first conductivity type having a concentration of 1 ⁇ 10 15 atoms / cm 3 or more.
- the imaging device according to (1) configured by: (3) The imaging device according to (2), wherein the channel region has an impurity peak formed at a depth within 0.2 ⁇ m from a substrate surface on a side where the gate electrode of the transfer transistor is formed.
- the imaging device according to (2) wherein the channel region functions as an overflow drain for discharging surplus charges from the charge accumulation region to the impurity diffusion layer when the transfer transistor is in an OFF state. .
- the transfer transistor modulates the potential on the surface of the substrate facing the gate electrode by a work function difference between the gate electrode of the transfer transistor and the substrate facing the gate electrode in a direction of decreasing the potential.
- the imaging device according to (2), wherein the channel is formed at a position away from the surface of the substrate facing the gate electrode toward the inside of the substrate.
- an impurity peak is formed at a depth within 0.2 ⁇ m from the substrate surface on the side where the gate electrode of the transfer transistor is formed, and the peak of the impurity and the gate electrode.
- a pixel that includes a transfer transistor configured by a buried channel MOS transistor, and that outputs a pixel signal based on the charge transferred from the photodiode to the floating diffusion by the transfer transistor in the on state;
- a determination unit that converts the output pixel signal into a digital value, compares the converted digital value with a plurality of threshold values, and determines the number of photons that have entered the pixel that generated the pixel signal; Image sensor.
- a pixel that includes a transfer transistor configured by a buried channel MOS transistor, and that outputs a pixel signal based on the charge transferred from the photodiode to the floating diffusion by the transfer transistor in the on state;
- a determination unit that converts the output pixel signal into a digital value, compares the converted digital value with a threshold value, and binary-determines whether a photon is incident on the pixel that generated the pixel signal; Electronics.
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Abstract
Description
1.第1の実施の形態(撮像制御:転送ゲート電極の仕事関数を利用して埋め込みチャネル型の転送トランジスタを構成する例)
2.第2の実施の形態(撮像制御:不純物プロファイルの調整で埋め込みチャネル型の転送トランジスタを構成する例)
3.第3の実施の形態(撮像制御:1光子検出の例)
[撮像素子の構成例]
図1は、本技術の第1の実施の形態の撮像素子100の基本構成例の一例を示す概念図である。
図2は、本技術の第1の実施の形態の画素310の回路構成の一例を示す模式図である。
図3は、本技術の第1の実施の形態の画素310のレイアウトの一例を模式的に示す図である。
図4は、本技術の第1の実施の形態の画素310の転送トランジスタ312の断面構成を模式的に示す図である。
図5は、本技術の第1の実施の形態における転送トランジスタ312の転送ゲート電極541の深さ方向(図4のA-B線で示す位置)のポテンシャルプロファイルを模式的に示す図である。
図6は、本技術の第1の実施の形態におけるn型拡散層542の横方向(図4のC-D線における位置)のポテンシャルプロファイルを模式的に示す図である。
図7は、本技術の第1の実施の形態の撮像素子100に備えられる画素310における電子の転送経路と、他の撮像素子に備えられる画素における電子の転送経路とを模式的に示す図である。
本技術の第1の実施の形態では、転送ゲート電極をp+型のシリコンの層で形成し、転送ゲート電極の仕事関数を利用して埋め込みチャネルを形成する例について説明した。しかしながら、埋め込みチャネルの形成はこれに限定されるものではなく、基板における不純物プロファイルの調整のみで埋め込みチャネルを形成することもできる。
図8は、本技術の第2の実施の形態の画素の転送トランジスタの断面構成を模式的に示す図である。
図9は、本技術の第2の実施の形態における転送ゲート電極611の深さ方向(図8のA-B線で示す位置)のポテンシャルプロファイルを模式的に示す図である。
本技術の第1および第2の実施の形態では、微弱光により発生した電子を、界面準位の影響を受けずにフローティングディフュージョンに転送する例について説明した。なお、多値の蓄積信号を検出する場合には、画素に蓄積可能な電子の数に基づいて露光時間などの撮像条件を決定することにより、微弱光を適切に検出することができる。しかしながら、蓄積可能な電子の数は、蓄積領域の製造工程における僅かなバラつきにより、画素ごとに異なる可能性がある。すなわち、本技術の第1および第2の実施の形態を適用した撮像素子を、蓄積信号が多値である微弱光の検出装置のために製造する場合には、蓄積領域における蓄積可能電子数のバラつきなどにより歩留まりが悪くなる可能性も考えられる。
図10は、本技術の第3の実施の形態の1光子を検出するための判定回路(1光子検出用判定回路700)の機能構成例の一例および1光子検出用判定回路700の動作例の一例を示す概念図である。
図11は、本技術の第3の実施の形態において、単位露光期間に各画素に入射する光子の平均数とカウント確率との関係を示すグラフである。
単位画素に入射する光子が0個(k=0)の確率:0.8105
単位画素に入射する光子が1個(k=1)の確率:0.1702
単位画素に入射する光子が2個(k=2)の確率:0.0179
単位画素に入射する光子が3個(k=3)の確率:0.0013
・・・(これ以下は、値が非常に小さい(0.00007以下)ので省略)
(1) 埋め込みチャネル型MOSトランジスタにより構成される転送トランジスタを備え、オン状態の前記転送トランジスタによりフォトダイオードからフローティングディフュージョンに転送された電荷に基づいて画素信号を出力する画素と、
前記出力された画素信号をデジタル値に変換し、当該変換されたデジタル値を閾値と比較して、当該画素信号を生成した画素への光子の入射の有無をバイナリ判定する判定部と
を具備する撮像素子。
(2) 前記フォトダイオードは、第1導電型の不純物拡散層により構成される電荷蓄積領域を備え、
前記フローティングディフュージョンは、前記第1導電型の不純物拡散層により構成され、
前記転送トランジスタは、前記フォトダイオードと前記フローティングディフュージョンとの間のチャネルとなるチャネル領域を備え、前記チャネル領域は、1×1015atoms/cm3以上の濃度の前記第1導電型の不純物拡散層により構成される
前記(1)に記載の撮像素子。
(3) 前記チャネル領域は、前記転送トランジスタのゲート電極が形成される側の基板表面から0.2μm以内の深さにおいて不純物のピークが形成される前記(2)に記載の撮像素子。
(4) 前記チャネル領域は、前記転送トランジスタのオフ状態の際には、前記電荷蓄積領域から前記不純物拡散層に余剰電荷を排出するためのオーバーフロードレインとして機能する前記(2)に記載の撮像素子。
(5) 前記転送トランジスタは、当該転送トランジスタのゲート電極と当該ゲート電極が面する基板との仕事関数差により当該ゲート電極が面する基板の表面におけるポテンシャルを浅くする方向に変調させることにより、当該ゲート電極が面する基板の表面から当該基板の内部側に離れた位置に前記チャネルが形成される前記(2)に記載の撮像素子。
(6) 前記転送トランジスタは、当該転送トランジスタのゲート電極が形成される側の基板表面から0.2μm以内の深さにおいて不純物のピークが形成されるとともに、当該不純物のピークと前記ゲート電極との間に第2導電型の不純物拡散層が形成される前記(2)に記載の撮像素子。
(7) 埋め込みチャネル型MOSトランジスタにより構成される転送トランジスタを備え、オン状態の前記転送トランジスタによりフォトダイオードからフローティングディフュージョンに転送された電荷に基づいて画素信号を出力する画素と、
前記出力された画素信号をデジタル値に変換し、当該変換されたデジタル値を複数の閾値と比較して、当該画素信号を生成した画素へ入射した光子の個数を判定する判定部と
を具備する撮像素子。
(8) 埋め込みチャネル型MOSトランジスタにより構成される転送トランジスタを備え、オン状態の前記転送トランジスタによりフォトダイオードからフローティングディフュージョンに転送された電荷に基づいて画素信号を出力する画素と、
前記出力された画素信号をデジタル値に変換し、当該変換されたデジタル値を閾値と比較して、当該画素信号を生成した画素への光子の入射の有無をバイナリ判定する判定部と
を具備する電子機器。
112 第1垂直駆動回路
114 レジスタ
115 第2垂直駆動回路
118 出力回路
300 画素アレイ部
310 画素
311 フォトダイオード
312 転送トランジスタ
313 リセットトランジスタ
314 アンプトランジスタ
511 基板
512 pウェル
521 蓄積領域
522 p型拡散層
531 浮遊拡散領域
541 転送ゲート電極
542 n型拡散層
551 絶縁膜
552 素子分離領域
Claims (8)
- 埋め込みチャネル型MOSトランジスタにより構成される転送トランジスタを備え、オン状態の前記転送トランジスタによりフォトダイオードからフローティングディフュージョンに転送された電荷に基づいて画素信号を出力する画素と、
前記出力された画素信号をデジタル値に変換し、当該変換されたデジタル値を閾値と比較して、当該画素信号を生成した画素への光子の入射の有無をバイナリ判定する判定部と
を具備する撮像素子。 - 前記フォトダイオードは、第1導電型の不純物拡散層により構成される電荷蓄積領域を備え、
前記フローティングディフュージョンは、前記第1導電型の不純物拡散層により構成され、
前記転送トランジスタは、前記フォトダイオードと前記フローティングディフュージョンとの間のチャネルとなるチャネル領域を備え、前記チャネル領域は、1×1015atoms/cm3以上の濃度の前記第1導電型の不純物拡散層により構成される
請求項1記載の撮像素子。 - 前記チャネル領域は、前記転送トランジスタのゲート電極が形成される側の基板表面から0.2μm以内の深さにおいて不純物のピークが形成される請求項2記載の撮像素子。
- 前記チャネル領域は、前記転送トランジスタのオフ状態の際には、前記電荷蓄積領域から前記不純物拡散層に余剰電荷を排出するためのオーバーフロードレインとして機能する請求項2記載の撮像素子。
- 前記転送トランジスタは、当該転送トランジスタのゲート電極と当該ゲート電極が面する基板との仕事関数差により当該ゲート電極が面する基板の表面におけるポテンシャルを浅くする方向に変調させることにより、当該ゲート電極が面する基板の表面から当該基板の内部側に離れた位置に前記チャネルが形成される請求項2記載の撮像素子。
- 前記転送トランジスタは、当該転送トランジスタのゲート電極が形成される側の基板表面から0.2μm以内の深さにおいて不純物のピークが形成されるとともに、当該不純物のピークと前記ゲート電極との間に第2導電型の不純物拡散層が形成される請求項2記載の撮像素子。
- 埋め込みチャネル型MOSトランジスタにより構成される転送トランジスタを備え、オン状態の前記転送トランジスタによりフォトダイオードからフローティングディフュージョンに転送された電荷に基づいて画素信号を出力する画素と、
前記出力された画素信号をデジタル値に変換し、当該変換されたデジタル値を複数の閾値と比較して、当該画素信号を生成した画素へ入射した光子の個数を判定する判定部と
を具備する撮像素子。 - 埋め込みチャネル型MOSトランジスタにより構成される転送トランジスタを備え、オン状態の前記転送トランジスタによりフォトダイオードからフローティングディフュージョンに転送された電荷に基づいて画素信号を出力する画素と、
前記出力された画素信号をデジタル値に変換し、当該変換されたデジタル値を閾値と比較して、当該画素信号を生成した画素への光子の入射の有無をバイナリ判定する判定部と
を具備する電子機器。
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JP2016092137A (ja) * | 2014-10-31 | 2016-05-23 | キヤノン株式会社 | 撮像装置 |
WO2016125601A1 (ja) * | 2015-02-05 | 2016-08-11 | ソニー株式会社 | 固体撮像装置および電子機器 |
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JP2021073688A (ja) * | 2016-03-14 | 2021-05-13 | パナソニックIpマネジメント株式会社 | 撮像装置 |
JP7336709B2 (ja) | 2016-03-14 | 2023-09-01 | パナソニックIpマネジメント株式会社 | 撮像装置 |
CN110651366A (zh) * | 2017-05-25 | 2020-01-03 | 松下知识产权经营株式会社 | 固体摄像元件及摄像装置 |
CN110651366B (zh) * | 2017-05-25 | 2023-06-23 | 松下知识产权经营株式会社 | 固体摄像元件及摄像装置 |
JP2021090134A (ja) * | 2019-12-03 | 2021-06-10 | キヤノン株式会社 | 撮像装置およびその制御方法 |
JP7444589B2 (ja) | 2019-12-03 | 2024-03-06 | キヤノン株式会社 | 撮像装置およびその制御方法 |
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US9653509B2 (en) | 2017-05-16 |
CN104170372B (zh) | 2019-10-15 |
US20150021461A1 (en) | 2015-01-22 |
EP2822270A1 (en) | 2015-01-07 |
JP6113711B2 (ja) | 2017-04-12 |
JPWO2013128998A1 (ja) | 2015-07-30 |
CN104170372A (zh) | 2014-11-26 |
JP2017108457A (ja) | 2017-06-15 |
JP6392918B2 (ja) | 2018-09-19 |
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