WO2013114758A1 - 共振形dc-dcコンバータの制御装置 - Google Patents
共振形dc-dcコンバータの制御装置 Download PDFInfo
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- WO2013114758A1 WO2013114758A1 PCT/JP2012/083068 JP2012083068W WO2013114758A1 WO 2013114758 A1 WO2013114758 A1 WO 2013114758A1 JP 2012083068 W JP2012083068 W JP 2012083068W WO 2013114758 A1 WO2013114758 A1 WO 2013114758A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
- H02M3/33573—Full-bridge at primary side of an isolation transformer
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/081—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters wherein the phase of the control voltage is adjustable with reference to the AC source
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/3353—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having at least two simultaneously operating switches on the input side, e.g. "double forward" or "double (switched) flyback" converter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33538—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type
- H02M3/33546—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current
- H02M3/33553—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type with automatic control of the output voltage or current with galvanic isolation between input and output of both the power stage and the feedback loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
- H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/01—Resonant DC/DC converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a DC-DC converter that obtains a DC output voltage insulated from a DC power supply.
- a resonant DC-DC converter suitable as a battery charger in which the power supply voltage and the output voltage change in a wide range It relates to the technology to control.
- FIG. 14 is a main circuit configuration diagram of a conventional DC-DC converter, which is described in Patent Document 1.
- E d is a DC power source
- Q 1 to Q 4 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) as semiconductor switching elements
- Tr is a transformer
- N p is a primary winding of the transformer Tr (the number of turns is also N p
- N s is the secondary winding (the number of turns is also N s )
- D 1 to D 4 are diodes
- Sn 1 to Sn 4 are snubber circuits
- L o is an inductor
- C o is a capacitor.
- V out and R tn are output terminals
- V in is a DC input voltage
- V O is a DC output voltage.
- the AC voltage generated in the secondary winding N s of the transformer Tr by the switching of MOSFET Q 1 ⁇ Q 4 is full wave rectified by a bridge rectifier circuit composed of diodes D 1 ⁇ D 4, into a DC voltage Is done.
- This DC voltage is smoothed by a smoothing circuit including an inductor L o and a smoothing capacitor C o , and is output from output terminals V out and R tn .
- This prior art includes snubber circuits Sn 1 to Sn 4 in order to suppress a surge voltage generated when the diodes D 1 to D 4 are reversely recovered.
- snubber circuits Sn 1 to Sn 4 increases as the switching frequency increases, and the conversion efficiency as a DC-DC converter decreases.
- FIG. 15 is a main circuit configuration diagram of a conventional resonant DC-DC converter, which is described in Patent Document 2 and Patent Document 3.
- an inductor L r and a capacitor C r constituting an LC series resonance circuit are connected to the primary winding N p of the transformer Tr, and other elements are denoted by the same symbols as in FIG. is there.
- the AC voltage generated in the secondary winding N s of the transformer Tr is full-wave rectified by a bridge rectifier circuit composed of diodes D 1 ⁇ D 4, is converted into a DC voltage.
- the DC voltage is smoothed by the smoothing capacitor C o, DC output terminal V out, is output from the R tn.
- FIG. 16 shows the relationship between the standardized frequency F and the standardized voltage conversion rate M in the frequency modulation control described in Patent Document 4.
- the characteristics of the standardized frequency F and the standardized voltage conversion rate M change depending on the load weight as shown in FIG.
- the standardized frequency F is increased infinitely, the standardized voltage conversion rate M does not become a certain value or less, so the output voltage range is narrow. Therefore, when this resonance type DC-DC converter is used for a battery charger or the like, it is difficult to charge an overdischarged battery.
- FIG. 17 shows the relationship between the standardized frequency F and the standardized voltage conversion rate M in the phase modulation control based on Patent Document 2.
- the reference frequency F is 1, that is, the switching frequency F s is made equal to the series resonance frequency F r and phase modulation control (phase shift control) is performed.
- the output voltage range of the DC-DC converter is larger than that in FIG.
- FIG. 18 shows the relationship between the standardized frequency F and the standardized voltage conversion rate M in the frequency modulation control and phase modulation control disclosed in Patent Document 3.
- frequency modulation control is performed in a range from the standardized frequency F to the maximum frequency F max , and a voltage range that cannot be output by frequency modulation control is set to a switching frequency.
- phase modulation control in which F s is fixed at the maximum frequency F max , the output voltage range is expanded as compared with FIG.
- FIG. 19 is a timing chart showing the operation when the phase modulation control is performed on the circuit shown in FIG. 15, and is described in Patent Document 2.
- MOSFETs Q 1 and Q 3 are turned on during a period from time t 2 to t 3 within one cycle T, and MOSFETs Q 2 and Q 4 are turned on during a period from time t 4 to t 5.
- the output voltage V uv of the full bridge circuit composed of MOSFET Q 1 ⁇ Q 4 is a time t com becomes zero (commutation period)
- the output voltage V uv is + V in or -V in A period t on (conduction period) is generated.
- the commutation period t com is a period in which the voltage of the DC power source E d is not applied to the series resonant circuit
- the MOSFET Q 1 ⁇ Q 4 by controlling the conduction period t on to shift the on or off is to phase, it is possible to control the DC output voltage V o to a predetermined value.
- Japanese Laid-Open Patent Publication No. 1-295675 lower right column on page 1, lines 2 to 13, FIG. 3 etc.
- JP 2010-11625 A paragraphs [0028] to [0037], FIGS. 1 to 4 etc.
- Japanese Patent Laid-Open No. 2002-262569 paragraphs [0014], [0015], FIG. 1, etc.
- Japanese Patent Laying-Open No. 2006-174571 paragraphs [0009] to [0017], FIGS. 1 to 5 etc.
- the voltage range operated by phase modulation control can be narrowed, so that the conduction loss due to the above-described return current is reduced. Reduction is possible.
- the switching frequency F s is operated in a region higher than the series resonance frequency F r , and the current flowing through the MOSFET at the timing when the MOSFETs Q 1 to Q 4 are turned off is the peak of the resonance current. Since this value may be close to the value, there is a problem that this causes an increase in switching loss and a decrease in conversion efficiency.
- an object of the present invention is to expand the voltage range that can be output by the resonant DC-DC converter.
- Another object of the present invention is to reduce the conduction loss and turn-off loss due to the return current between the semiconductor switching elements, and improve the power conversion efficiency of the resonant DC-DC converter.
- the present invention provides a DC power supply, an input side connected to both ends thereof, and a primary winding of a transformer connected to an output side via a series resonance circuit, and a semiconductor switching element.
- a full bridge circuit configured, a rectifier circuit connected to the secondary winding of the transformer, and a smoothing capacitor connected to the output side of the circuit.
- the semiconductor switching element is turned on and off to generate a resonance current in the series resonance circuit.
- the present invention relates to a control device for a resonant DC-DC converter that outputs a DC voltage via a transformer, a rectifier circuit, and a smoothing capacitor.
- the control device of the present invention detects a quantity of electricity such as a DC output voltage and a DC output current according to the load state of the resonance type DC-DC converter, and controls a control quantity for controlling on / off of the semiconductor switching element.
- Means to determine are provided. Further, based on the determined control amount, frequency modulation control means for frequency modulation controlling the semiconductor switching element at a frequency lower than the resonance frequency of the series resonance circuit, and a fixed frequency control for controlling the semiconductor switching element near the resonance frequency Frequency control means, and pulse distribution means for generating a drive pulse of the semiconductor switching element by a logical operation based on outputs of the frequency modulation control means and the fixed frequency control means.
- the control amount becomes a value such that the DC output voltage of the resonant DC-DC converter exceeds the maximum value that can be output in the fixed frequency control region
- the control amount is changed from fixed frequency control to frequency modulation control. It is to switch.
- the fixed frequency control means generates a pulse width modulation signal by comparing the control amount with the carrier signal generated by the frequency modulation control means, thereby changing the pulse width of the semiconductor switching element of the resonant DC-DC converter. It is desirable to control the modulation.
- the fixed frequency control unit generates a pulse width modulation signal by comparing the control amount with the carrier signal, and generates a phase modulation signal from the pulse width modulation signal and the frequency modulation signal generated by the frequency modulation control unit.
- the semiconductor switching element of the converter may be subjected to phase modulation control.
- the fixed frequency control means may be one that performs pulse width modulation control and phase modulation control on the semiconductor switching element of the converter.
- the fixed frequency control means compares the control amount with the carrier signal to generate a pulse width modulation signal, generates a phase modulation signal from the pulse width modulation signal and the frequency modulation signal, and outputs the DC output of the converter.
- the pulse width modulation control and the phase modulation control are switched according to the current or the DC output voltage.
- the fixed frequency control means may perform pulse width modulation control at the time of starting the converter, and may switch to phase modulation control after initially charging the smoothing capacitor in a state where the pulse width is shorter than a half cycle of the resonance frequency. Furthermore, after the smoothing capacitor is initially charged, it may be switched to frequency modulation control.
- the control amount is preferably determined by an error amplifier or the like using these detected values so that the DC output voltage and DC output current of the converter have predetermined values.
- the fixed frequency control is performed near the resonance frequency of the series resonance circuit, and the frequency modulation control is performed at a frequency lower than the resonance frequency, thereby expanding the voltage range that the resonance type DC-DC converter can output, It is possible to eliminate a change in DC output voltage when switching between fixed frequency control and frequency modulation control.
- the fixed frequency control means is constituted by pulse width modulation control means or phase modulation control means, and the main part of these control means can be realized by sharing a limiter, a comparator and the like. Further, since the semiconductor switching element is turned off after a half period of the resonance current, the instantaneous value of the resonance current at the time of turn-off becomes sufficiently smaller than the peak value of the resonance current, and the turn-off loss can be reduced.
- the conduction loss due to the return current between the semiconductor switching elements increases as the load is lighter.
- the non-excitation period of the transformer is switched to semiconductor switching. Since all the elements are turned off, no reflux current is generated, and conduction loss can be reduced. For this reason, according to the present invention, it is possible to improve the power conversion efficiency of the resonant DC-DC converter.
- 1 is a circuit diagram showing a main circuit of a resonant DC-DC converter according to an embodiment of the present invention together with a control device. It is a characteristic view which shows the relationship between the standardization frequency and standardization voltage conversion rate in embodiment of this invention. In the embodiment of the present invention, it is a characteristic diagram showing the relationship between the control amount for turning on and off the MOSFET, the standardized frequency and the duty. It is a block diagram which shows the 1st Example of the control apparatus in embodiment of this invention. It is a wave form diagram showing control operation at the time of pulse width modulation control in the 1st example. It is a wave form diagram showing the main circuit operation at the time of pulse width modulation control in the 1st example.
- FIG. 1 is a circuit diagram showing a main circuit 100 of a resonant DC-DC converter according to an embodiment of the present invention together with a control device Cont.
- a full-bridge circuit comprising a MOSFET Q 1 ⁇ Q 4 as the semiconductor switching element.
- G 1 to G 4 are the gates of the MOSFETs Q 1 to Q 4 , and in the following description, the same reference numerals G 1 to G 4 are also applied to the gate pulses.
- an inductor L r Between the series connection point of the MOSFETs Q 1 and Q 2 and the series connection point of the MOSFETs Q 3 and Q 4 , an inductor L r , a primary winding N p of the transformer Tr, and a capacitor Cr are connected in series. Yes.
- the inductor L r and the capacitor C r constitute an LC series resonance circuit.
- a bridge rectifier circuit composed of diodes D 1 to D 4 is connected to both ends of the secondary winding N s of the transformer Tr, and a smoothing capacitor Co is connected between its DC output terminals. Further, at both ends of the smoothing capacitor C o resistance R a, the series circuit of R b is connected.
- V out and R tn are DC output terminals, V in is a DC input voltage, V u is a voltage at the series connection point of MOSFETs Q 1 and Q 2 , V v is a voltage at a series connection point of MOSFETs Q 3 and Q 4 , V uv is a difference voltage between V u and V v .
- the voltage obtained by dividing the voltage across the smoothing capacitor C o by the resistors R a and R b is used as the DC output voltage detection value V o
- the current detector CT connected to the negative line of the bridge rectifier circuit is used.
- a DC output current detection value Io is obtained from the output.
- the DC output voltage detection value V o and the DC output current detection value I o are input to the control device Cont, and gate pulses G 1 to G as drive pulses for the MOSFETs Q 1 to Q 4 are calculated by the control device Cont. 4 is generated.
- MOSFET Q 1 ⁇ Q 4 are switched.
- the primary current I p and secondary of the transformer Tr it may be used to detect values of current I s additionally.
- FIG. 2 is a characteristic diagram showing the relationship between the standardized frequency F and the standardized voltage conversion rate M.
- FIG. 3 shows the relationship between the control amount ⁇ for turning on and off the MOSFETs Q 1 to Q 4 , the standardized frequency F, and the duty D s .
- the control amount ⁇ is adjusted using an error amplifier or the like so that the DC output voltage and the DC output current become desired values based on the DC output voltage detection value V o and the DC output current detection value I o in FIG.
- the range of the control amount ⁇ is 0 ⁇ ⁇ ⁇ 1.
- the duty D s is the ratio of the on-time of each MOSFET to the switching period in the first embodiment (FIG. 4) of the control device Cont, which will be described later, and in the second embodiment (FIG. 9) of the control device Cont, FIG.
- the reference frequency F is limited to F min when ⁇ exceeds ⁇ lim .
- the reason will be described below.
- F min is set to a frequency higher than the frequency at which the normalized voltage conversion rate M of the heavy load characteristic in the characteristic of FIG. 2 is reached, and normalized in the region where ⁇ > ⁇ lim .
- the frequency F is limited to Fmin .
- FIG. 4 is a block diagram showing a first example of the control device Cont in the present embodiment.
- 11 is a frequency modulation circuit as frequency modulation control means
- 21 is a pulse width modulation circuit as fixed frequency control means
- 31 is a pulse distribution circuit.
- the frequency modulation signal V pfm output from the frequency modulation circuit 11 and the pulse width modulation signal V pwm output from the pulse width modulation circuit 21 are input to the pulse distribution circuit 31, and logical operation in the pulse distribution circuit 31 is performed.
- MOSFET Q 1 ⁇ gate pulse G 1 ⁇ G 4 of Q 4 is generated.
- the frequency modulation circuit 11 includes a limiter LIM 1 to which a deviation between “1” and the control amount ⁇ is input, an integrator INT 1 to which an output signal of the limiter LIM 1 is input, and a carrier output from the integrator INT 1.
- Comparator CMP 1 for comparing the magnitude relationship between the signal V tr and the reference voltage V 1, and a T flip-flop T-FF serving as a frequency dividing means to which an output signal of the comparator CMP 1 is input.
- a frequency modulation signal V pfm is output from the FF.
- the reference voltage V 1 of the comparator CMP 1 is set equal to the lambda c value.
- the control amount ⁇ is generated based on the DC output voltage detection value V o and the DC output current detection value I o as described above.
- the integrator INT 1 is reset by the output signal (reset signal reset) from the comparator CMP 1 when the output carrier signal V tr reaches ⁇ c , so that the carrier signal V tr has a sawtooth shape.
- the pulse width modulation circuit 21 includes a limiter LIM 2 to which a control amount ⁇ is input, and a comparator CMP 2 that compares the magnitude relationship between the output signal of the limiter LIM 2 and the carrier signal V tr . Then, the output signal of the comparator CMP 2 is input to the pulse distribution circuit 31 as a pulse width modulated signal V pwm.
- the pulse distribution circuit 31 includes an AND gate AND 1 to which the frequency modulation signal V pfm and the pulse width modulation signal V pwm are input, a NOT gate NOT 1 that inverts the logic of the frequency modulation signal V pfm , and an output of the NOT gate NOT 1 . And AND gate AND 2 to which the pulse width modulation signal V pwm is input, and on-delay circuits DT 1 and DT 2 to which the output signals of AND gates AND 1 and AND 2 are input, respectively.
- gate pulse G 1, G 4 as the output of the delay circuit DT 1 is a gate pulse G 2, G 3 is adapted to obtain each as an output of the on-delay circuit DT 2.
- on-delay circuit DT 1, DT 2 is, MOSFET Q 1, simultaneous on-Q 2 'or, in order to prevent the simultaneous ON of MOSFET Q 3, Q 4, the gate pulse G 1, G 4 and the gate pulse G 2, the G 3 by time t d is intended to delay.
- the lower limit value of the limiter LIM 1 is set to 1- ⁇ c
- the upper limit value is set to ⁇ lim in FIG. 3
- the lower limit value of the limiter LIM 2 is set to 0, and the upper limit value is set to ⁇ c in FIG.
- FIG. 5 is a waveform diagram for explaining the operation of the control device Cont during the pulse width modulation control in the first embodiment
- FIG. 6 is a waveform diagram for explaining the operation of the main circuit.
- the pulse width modulation signal V pwm is output from the comparator CMP 2 in accordance with the magnitude relationship between the control amount ⁇ and the carrier signal V tr .
- a frequency modulation signal V pfm obtained by dividing the output signal of the comparator CMP 1 is output from the T flip-flop T-FF.
- the AND gates AND 1 and AND 2 in the pulse distribution circuit 31 of FIG. 4 perform a logical operation using the pulse width modulation signal V pwm , the frequency modulation signal V pfm and its inverted signal. Further, as shown in FIG. 5, on delay circuits DT 1 and DT 2 add delay time t d to the output signals of AND gates AND 1 and AND 2 and gate pulses G 1 to G 4 of MOSFETs Q 1 to Q 4. 4 is generated.
- MOSFET Q 1 ⁇ Q 4 By switching MOSFET Q 1 ⁇ Q 4 by the gate pulse G 1 ⁇ G 4, the voltage V uv in the main circuit of Figure 1 has a waveform as shown in the lower part of FIG. Further, the voltage and current waveforms of the respective parts in the main circuit of FIG. 1 including the voltage V uv are as shown in FIG.
- FIG. 7 is a waveform diagram for explaining the operation of the control device Cont during frequency modulation control in the first embodiment
- FIG. 8 is a waveform diagram for explaining the operation of the main circuit.
- the MOSFET in the frequency modulation control region, the MOSFET is turned off after the half period of the resonance current has passed, so that the instantaneous value of the resonance current at the time of turn-off is sufficiently smaller than the peak value of the resonance current. It becomes equal to the exciting current of Tr (the broken line part in the waveform of Ip ). For this reason, according to the present embodiment, the turn-off loss can be reduced.
- FIG. 9 is a block diagram showing a second example of the control device Cont in the present embodiment.
- the same components as those in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.
- reference numeral 41 denotes a phase modulation circuit as a fixed frequency control means, and this phase modulation circuit 41 is constituted by a limiter LIM 2 , a comparator CMP 2 , and an exclusive OR gate XOR 1 .
- the exclusive OR gate XOR 1 receives the pulse width modulation signal V pwm that is the output of the comparator CMP 2 and the frequency modulation signal V pfm that is the output of the T flip-flop T-FF, and outputs the exclusive OR gate XOR 1 .
- the phase modulation signal V ps and the frequency modulation signal V pfm are input to the pulse distribution circuit 32.
- Pulse distribution circuit 32 includes an on-delay circuit DT 1 for generating a gate pulse G 1 are denoted by the delay time t d to the frequency-modulated signal V pfm, a NOT gate NOT 1 which inverts the logic of the frequency-modulated signal V pfm, An on-delay circuit DT 2 that generates a gate pulse G 2 by adding a delay time t d to the output signal of the NOT gate NOT 1 .
- the pulse distribution circuit 32 includes an on-delay circuit DT 3 for generating a gate pulse G 3 are denoted by the delay time to the phase-modulated signal V ps t d, NOT gate NOT 2 for inverting the logic of the phase modulation signal V ps And an on-delay circuit DT 4 that generates a gate pulse G 4 by adding a delay time t d to the output signal of the NOT gate NOT 2 .
- FIG. 10 is a waveform diagram for explaining the operation of the control device Cont during phase modulation control in the second embodiment
- FIG. 11 is a waveform diagram showing the main circuit operation during phase modulation control
- FIG. 12 is a waveform diagram for explaining the operation of the control device Cont during frequency modulation control.
- the main circuit operation waveform during frequency modulation control is the same as that in FIG.
- the frequency modulation signal V pfm and the pulse width modulation signal V pwm are output in accordance with the magnitude relationship between ⁇ and ⁇ c , the waveforms of V pfm and V pwm in FIG. Is the same.
- the phase modulation signal V ps is generated by exclusive OR of the frequency modulation signal V pfm and the pulse width modulation signal V pwm, and this phase modulation signal V p ps is supplied to the pulse distribution circuit 32 together with the frequency modulation signal V pfm .
- the resonance current instantaneous value at the time of turn-off is sufficiently smaller than the peak value of the resonance current, It becomes equal to the exciting current of the transformer Tr (the broken line portion in the waveform of I p ). For this reason, the turn-off loss can be reduced also in the present embodiment.
- FIG. 13 is a block diagram showing a third example of the control device Cont in the present embodiment.
- the same components as those in FIG. 9 are denoted by the same reference numerals, and the description thereof will be omitted.
- the control device Cont of the third embodiment includes a frequency modulation circuit 11, a phase modulation circuit 41, a phase modulation / pulse width modulation switching circuit 51, and a pulse distribution circuit 33.
- the configurations of the frequency modulation circuit 11 and the phase modulation circuit 41 are the same as those in FIG.
- the phase modulation / pulse width modulation switching circuit 51 includes a state determination circuit 51a and a D flip-flop D-FF.
- the state discriminating circuit 51a discriminates the magnitude of the load, the magnitude of the DC output voltage, etc., and outputs the discrimination result to the D flip-flop D-FF. Operates to switch between modulation control.
- a frequency modulation signal V pfm is input to the D flip-flop D-FF as a clock signal, and the D flip-flop D-FF operates by a so-called leading edge trigger method. That is, the D flip-flop D-FF is operated at the rising timing of the frequency modulation signal V pfm in order to prevent the gate pulses G 1 to G 4 from being switched halfway when the state determination result by the state determination circuit 51a changes.
- phase modulation control and pulse width modulation control are switched.
- the frequency modulation signal V pfm is input to one input terminal of each of the AND gates AND 1 , AND 5 , and NOR gate NOR 1 , and the NOT gate NOT 1 .
- the phase modulation signal V ps is input to the NOT gate NOT 2 , one input terminal of the AND gate AND 4 , the other input terminal of the AND gate AND 5 , and the other input terminal of the NOR gate NOR 1.
- the outputs of the NOT gates NOT 1 and NOT 2 are respectively input to one input terminals of the AND gates AND 2 and AND 3 .
- the output of the AND gate AND 5 is input to one input terminal of the AND gate AND 6
- the output of the NOR gate NOR 1 is input to one input terminal of the AND gate AND 7 .
- the Q output of the D flip-flop D-FF is input to the other input terminals of the AND gates AND 1 to AND 4 , and the inverted output of the D flip-flop D-FF is the other of the AND gates AND 6 and AND 7 . Input to the input terminal.
- the outputs of the AND gates AND 1 to AND 4 are respectively input to one input terminals of the OR gates OR 1 to OR 4 .
- the output of the AND gate AND 6 is input to the other input terminal of the OR gates OR 1 and OR 4
- the output of the AND gate AND 7 is input to the other input terminal of the OR gates OR 2 and OR 3 , respectively.
- the outputs of the OR gates OR 1 to OR 4 are respectively input to the on-delay circuits DT 1 to DT 4 with a delay time t d and output as gate pulses G 1 to G 4 of the MOSFETs Q 1 to Q 4 .
- the state determination circuit 51a detects that the load is light, and switches to pulse width modulation control via the D flip-flop D-FF. As a result, all the MOSFETs are turned off during the non-excitation period of the transformer Tr in FIG. 1, so that no return current is generated between the MOSFETs, and conduction loss can be reduced.
- the DC output side smoothing capacitor Co is not charged at the time of starting the DC-DC converter 100 or the like, when the phase modulation control or the frequency modulation control is performed, the above-described resonance shift occurs, and the parasitic capacitance of the MOSFET is increased.
- the MOSFET may be damaged by reverse recovery of the diode.
- state discrimination circuit 51a it is desirable that the DC-DC converter 100 based on the DC output voltage V o is detected that the running state.
- pulse width modulation control using a pulse having a width sufficiently shorter than a half cycle of the resonance frequency F r is performed via the D flip-flop D-FF, and the smoothing capacitor Co is initially charged to a certain voltage. By switching to phase modulation control or frequency modulation control later, the reverse recovery described above can be prevented and the MOSFET can be protected.
- the first to third embodiments of the control device Cont shown in FIGS. 4, 9, and 13 may be realized by an analog circuit, or may be realized by digital control means having a similar function. .
- the present invention can be applied to various resonance DC-DC converters for obtaining a predetermined DC voltage, including an in-vehicle charging device for charging a battery of a hybrid vehicle or an electric vehicle.
- E d DC power supply
- Q 1 , Q 2 , Q 3 , Q 4 MOSFET
- L r Inductor C r, C o: Capacitor Tr: trans N p: 1 winding N s: 2 winding D 1, D 2, D 3 , D 4: diodes
- R a, R b resistance
- LIM 1 , LIM 2 Limiter INT 1 : Integrator CMP 1 , CMP 2 : Comparator
- T-FF T flip-flop
- D-FF D flip-flop
- XOR 1 Exclusive OR gate AND 1 to AND 7 : AND gate OR 1 to OR 4 : OR gate NOT 1 , NOT 2 : Not gate NOR 1 : NOR gate DT 1 to DT 4 : On-delay circuit Cont:
Abstract
Description
図14において、Edは直流電源、Q1~Q4は半導体スイッチング素子としてのMOSFET(Metal Oxide Semiconductor Field Effect Transistor)、Trはトランス、NpはトランスTrの1次巻線(巻数もNpとする)、Nsは同じく2次巻線(巻数もNsとする)、D1~D4はダイオード、Sn1~Sn4はスナバ回路、Loはインダクタ、Coはコンデンサである。また、Vout,Rtnは出力端子、Vinは直流入力電圧、Voは直流出力電圧を示す。
図15において、トランスTrの1次巻線NpにはLC直列共振回路を構成するインダクタLr及びコンデンサCrが接続されており、その他の素子については、図14と同じ記号を付してある。
図15の回路において、トランスTrの2次巻線Nsに発生した交流電圧はダイオードD1~D4からなるブリッジ整流回路により全波整流され、直流電圧に変換される。そして、この直流電圧は平滑コンデンサCoにより平滑され、直流出力端子Vout,Rtnから出力される。
図16は、特許文献4に記載された周波数変調制御における基準化周波数Fと基準化電圧変換率Mとの関係を示している。ここで、基準化周波数Fは、図15のスイッチング素子Q1~Q4のスイッチング周波数Fsと、インダクタLr及びコンデンサCrによる直列共振周波数Frとの比率であり、F=Fs/Frによって表される。
また、基準化電圧変換率Mは、直流出力電圧Voと直流入力電圧Vinとの比率(Vo/Vin)にトランスTrの巻数比n=Np/Nsを掛けたものであり、M=n・Vo/Vinによって表される。
特許文献2に開示された技術では、図17に示すように基準化周波数Fを1、つまりスイッチング周波数Fsを直列共振周波数Frと等しくして位相変調制御(位相シフト制御)することで、DC-DCコンバータの出力電圧範囲を図16よりも拡大している。
特許文献3に開示された技術では、図18に示すように、基準化周波数Fから最大周波数Fmaxまでの範囲では周波数変調制御とし、周波数変調制御では出力不可能な電圧範囲については、スイッチング周波数Fsを最大周波数Fmaxに固定した位相変調制御に切り替えることで、出力電圧範囲を図16よりも拡大している。
上記の導通期間tonは直流電源Edの電圧が直列共振回路に加わる期間、転流期間tcomは直流電源Edの電圧が直列共振回路に加わらない期間であり、MOSFETQ1~Q4をオンまたはオフさせる位相をシフトして導通期間tonを制御することにより、直流出力電圧Voを所定値に制御することが可能である。
すなわち、図19において、MOSFET Q1,Q3またはMOSFET Q2,Q4の同時オンにより電圧Vuvが零になる転流期間tcomが長いほど、オン状態のMOSFETQ1,Q3間、または、MOSFET Q2,Q4間の還流電流に起因した導通損失が大きくなり、DC-DCコンバータとしての電力変換効率が低下する。
しかしながら、図18から明らかなように、スイッチング周波数Fsを直列共振周波数Frよりも高い領域で動作させることになり、MOSFETQ1~Q4がターンオフするタイミングでMOSFETを流れる電流が共振電流のピーク値付近になる場合があるため、これがスイッチング損失の増大、変換効率の低下を招くという問題がある。
また、本発明の他の目的は、半導体スイッチング素子間の還流電流に起因する導通損失やターンオフ損失を低減し、共振形DC-DCコンバータの電力変換効率を向上させることにある。
そして、本発明は、前記制御量が、共振形DC-DCコンバータの直流出力電圧が固定周波数制御領域において出力可能な最大値を超えるような値になるときに、固定周波数制御から周波数変調制御に切り替えるものである。
この場合、固定周波数制御手段は、制御量とキャリア信号とを比較してパルス幅変調信号を生成し、このパルス幅変調信号と周波数変調信号とから位相変調信号を生成すると共に、コンバータの直流出力電流または直流出力電圧に応じて、パルス幅変調制御と位相変調制御とを切り替える。
また、固定周波数制御手段は、コンバータの起動時にパルス幅変調制御し、パルス幅が共振周波数の半周期よりも短い状態で平滑コンデンサを初期充電した後に、位相変調制御に切り替えてもよい。更に、上記平滑コンデンサを初期充電した後に、周波数変調制御に切り替えてもよい。
なお、前記制御量は、コンバータの直流出力電圧や直流出力電流が所定値になるように、これらの検出値を用いて誤差増幅器等により決定することが望ましい。
また、共振電流の半周期を過ぎてから半導体スイッチング素子をターンオフするため、ターンオフ時の共振電流瞬時値は共振電流のピーク値よりも十分小さくなり、ターンオフ損失を低減することができる。更に、位相変調制御時には、軽負荷時ほど半導体スイッチング素子間の還流電流による導通損失が増加するが、本発明では、軽負荷時にパルス幅変調制御を行うことにより、トランスの非励磁期間は半導体スイッチング素子がすべでオフの状態になるので、還流電流が発生せず、導通損失の低減が可能である。
このため、本発明によれば、共振形DC-DCコンバータの電力変換効率を向上させることができる。
まず、図1は、本発明の実施形態に係る共振形DC-DCコンバータの主回路100を制御装置Contと共に示した回路図である。
MOSFET Q1,Q2の直列接続点とMOSFET Q3,Q4の直列接続点との間には、インダクタLr、トランスTrの1次巻線Np、コンデンサCrが直列に接続されている。ここで、インダクタLr及びコンデンサCrはLC直列共振回路を構成している。
Vout,Rtnは直流出力端子であり、Vinは直流入力電圧、VuはMOSFETQ1,Q2の直列接続点の電圧、VvはMOSFET Q3,Q4の直列接続点の電圧、VuvはVuとVvとの差電圧である。
ここで、制御装置ContによりゲートパルスG1~G4を生成するに当たっては、直流出力電圧検出値Vo及び直流出力電流検出値Ioに加えて、トランスTrの1次電流Ipや2次電流Isの検出値を追加的に用いてもよい。
図2は、基準化周波数Fと基準化電圧変換率Mとの関係を示す特性図であり、前述したように、基準化周波数F=Fs/Fr(Fs:MOSFETQ1~Q4のスイッチング周波数,Fr:共振周波数)、基準化電圧変換率M=n・Vo/Vin(n:トランスTrの巻数比,Vo:直流出力電圧,Vin:直流入力電圧)である。
そして、固定周波数制御領域において、直流出力電圧VoがDC-DCコンバータの出力可能な最大値を超えるときに、制御方法を固定周波数制御から周波数変調制御に切り替える。つまり、図2において、M=0から、F=1の特性線と負荷特性線(軽負荷特性線、中負荷特性線、重負荷特性線)との交点までの距離が、固定周波数制御領域における出力可能な電圧範囲に相当する。
また、Mが1を超える領域を周波数変調制御領域とすることで、固定周波数制御との切替前後において、DC-DCコンバータの出力電圧を急激に変化させずにシームレスに切り替えることができる。
制御量λは、図1における直流出力電圧検出値Vo及び直流出力電流検出値Ioに基づいて、直流出力電圧及び直流出力電流が所望の値となるように誤差増幅器などを用いて調整される。この制御量λの範囲は、0≦λ≦1である。
デューティDsは、後述する制御装置Contの第1実施例(図4)では、各MOSFETのオン時間とスイッチング周期との比とし、制御装置Contの第2実施例(図9)では、図1におけるMOSFETQ1,Q2の直列接続点の電圧VuとMOSFET Q3,Q4の直列接続点の電圧Vvとの位相変調時間と、スイッチング周期との比とする。
図2において、各負荷特性で基準化電圧変換率Mがピークとなる点よりも制御周波数Fが小さくなると、共振はずれと呼ばれる状態になる。共振はずれが発生すると、図1における直列接続された2個のMOSFETのうち一方のMOSFETに流れる共振電流が寄生ダイオードに転流し、このタイミングで他方のMOSFETがオンする。このとき、一方のMOSFETの寄生ダイオードが急峻な電流変化率で逆回復することにより、MOSFETが破損する場合がある。これを防止するために、図3では、図2の特性において重負荷特性の基準化電圧変換率Mのピークとなる周波数より高い周波数にFminを設定し、λ>λlimの領域では基準化周波数FをFminに制限しているものである。
図4において、11は周波数変調制御手段としての周波数変調回路、21は固定周波数制御手段としてのパルス幅変調回路、31はパルス分配回路である。周波数変調回路11から出力される周波数変調信号Vpfmとパルス幅変調回路21から出力されるパルス幅変調信号Vpwmとはパルス分配回路31に入力されており、このパルス分配回路31における論理演算によりMOSFETQ1~Q4のゲートパルスG1~G4が生成される。
なお、コンパレータCMP1の基準電圧V1はλcと等しい値に設定されている。また、制御量λは、前述したように直流出力電圧検出値Vo及び直流出力電流検出値Ioに基づいて生成されるものとする。
また、コンパレータCMP1の出力信号はTフリップフロップT-FFにより分周され、TフリップフロップT-FFからはデューティ50%(Ds=0.5)の周波数変調信号Vpfmが出力される。
上記オンディレイ回路DT1,DT2は、MOSFET Q1,Q2の同時オン、または、MOSFET Q3,Q4の同時オンを防止するため、ゲートパルスG1,G4及びゲートパルスG2,G3を時間tdだけ遅延させるものである。
図5は、第1実施例におけるパルス幅変調制御時の制御装置Contの動作を説明するための波形図、図6は主回路の動作を説明するための波形図である。
図5に示すように、制御量λとキャリア信号Vtrとの大小関係に応じて、コンパレータCMP2からパルス幅変調信号Vpwmが出力される。一方、TフリップフロップT-FFからは、コンパレータCMP1の出力信号を分周した周波数変調信号Vpfmが出力される。
上記ゲートパルスG1~G4によってMOSFET Q1~Q4をスイッチングすることにより、図1の主回路における電圧Vuvは図5の下段に示すような波形となる。
また、電圧Vuvを含めて、図1の主回路における各部の電圧、電流波形は図6のようになる。
図7は、第1実施例における周波数変調制御時の制御装置Contの動作を説明するための波形図、図8は主回路の動作を説明するための波形図である。
周波数変調制御領域では、図8から明らかなように、共振電流の半周期を過ぎてからMOSFETをターンオフしているので、ターンオフ時の共振電流瞬時値は共振電流のピーク値よりも十分小さく、トランスTrの励磁電流(Ipの波形における破線部分)と等しくなる。このため、本実施例によれば、ターンオフ損失を低減することができる。
図9において、41は固定周波数制御手段としての位相変調回路であり、この位相変調回路41は、リミッタLIM2、コンパレータCMP2、及びエクスクルーシブオアゲートXOR1によって構成されている。エクスクルーシブオアゲートXOR1には、コンパレータCMP2の出力であるパルス幅変調信号Vpwmと、TフリップフロップT-FFの出力である周波数変調信号Vpfmとが入力され、エクスクルーシブオアゲートXOR1の出力である位相変調信号Vps及び前記周波数変調信号Vpfmがパルス分配回路32に入力されている。
この第2実施例においても、λとλcとの大小関係に応じて周波数変調信号Vpfm、パルス幅変調信号Vpwmが出力されるので、図10におけるVpfm,Vpwmの波形は図4と同一である。ただし、第2実施例では、図9,図10に示すように周波数変調信号Vpfmとパルス幅変調信号Vpwmとの排他的論理和により位相変調信号Vpsが生成され、この位相変調信号Vpsが周波数変調信号Vpfmと共にパルス分配回路32に与えられる。
図13に示すように、第3実施例の制御装置Contは、周波数変調回路11と、位相変調回路41と、位相変調・パルス幅変調切替回路51と、パルス分配回路33と、を備えている。ここで、周波数変調回路11及び位相変調回路41の構成は、図9と同一である。
DフリップフロップD-FFにはクロック信号として周波数変調信号Vpfmが入力されており、DフリップフロップD-FFはいわゆるリーディングエッジトリガ方式にて動作する。すなわち、状態判別回路51aによる状態判別結果が変化した際にゲートパルスG1~G4が途中で切り替わるのを防ぐために、DフリップフロップD-FFを周波数変調信号Vpfmの立ち上がりのタイミングで動作させて位相変調制御とパルス幅変調制御とを切り替えるようになっている。
DフリップフロップD-FFのQ出力は、アンドゲートAND1~AND4の各他方の入力端子に入力され、DフリップフロップD-FFの反転出力は、アンドゲートAND6,AND7の各他方の入力端子に入力されている。
そして、オアゲートOR1~OR4の出力はオンディレイ回路DT1~DT4にそれぞれ入力されて遅延時間tdが付され、MOSFETQ1~Q4のゲートパルスG1~G4として出力される。
Q1,Q2,Q3,Q4:MOSFET
Lr:インダクタ
Cr,Co:コンデンサ
Tr:トランス
Np:1次巻線
Ns:2次巻線
D1,D2,D3,D4:ダイオード
Ra,Rb:抵抗
LIM1,LIM2:リミッタ
INT1:積分器
CMP1,CMP2:コンパレータ
T-FF:Tフリップフロップ
D-FF:Dフリップフロップ
XOR1:エクスクルーシブオアゲート
AND1~AND7:アンドゲート
OR1~OR4:オアゲート
NOT1,NOT2:ノットゲート
NOR1:ノアゲート
DT1~DT4:オンディレイ回路
Cont:制御装置
CT:電流検出器
11:周波数変調回路
21:パルス幅変調回路
31,32,33:パルス分配回路
41:位相変調回路
51:位相変調・パルス幅変調切替回路
51a:状態判別回路
100:主回路
Claims (10)
- 直流電源と、
前記直流電源の両端に入力側が接続され、かつ、出力側に直列共振回路を介してトランスの1次巻線が接続されると共に、半導体スイッチング素子により構成されたフルブリッジ回路と、
前記トランスの2次巻線に接続された整流回路と、
前記整流回路の出力側に接続された平滑コンデンサと、を備え、
前記半導体スイッチング素子をオンオフさせて前記直列共振回路に共振電流を流すことにより、前記トランス、前記整流回路及び前記平滑コンデンサを介して直流電圧を出力する共振形DC-DCコンバータにおいて、
前記共振形DC-DCコンバータの負荷の状態に応じた電気量を検出して前記半導体スイッチング素子のオンオフを制御するための制御量を決定する手段と、
前記制御量に基づいて、前記直列共振回路の共振周波数よりも低い周波数で前記半導体スイッチング素子を周波数変調制御する周波数変調制御手段と、
前記制御量に基づいて、前記共振周波数付近で前記半導体スイッチング素子を固定周波数制御する固定周波数制御手段と、
前記周波数変調制御手段及び前記固定周波数制御手段の出力に基づいて前記半導体スイッチング素子の駆動パルスを生成するパルス分配手段と、を備え、
前記制御量が、前記共振形DC-DCコンバータの直流出力電圧が固定周波数制御領域において出力可能な最大値を超えるような値になるときに、前記固定周波数制御手段による制御動作から前記周波数変調制御手段による制御動作に切り替えることを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項1に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記半導体スイッチング素子をパルス幅変調制御することを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項2に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記制御量と前記周波数変調制御手段により生成されたキャリア信号とを比較してパルス幅変調信号を生成することを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項1に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記半導体スイッチング素子を位相変調制御することを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項4に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記制御量と前記周波数変調制御手段により生成されたキャリア信号とを比較してパルス幅変調信号を生成し、このパルス幅変調信号と前記周波数変調制御手段により生成された周波数変調信号とから位相変調信号を生成することを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項1に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記半導体スイッチング素子をパルス幅変調制御及び位相変調制御することを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項6に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記制御量と前記周波数変調制御手段により生成されたキャリア信号とを比較してパルス幅変調信号を生成し、このパルス幅変調信号と前記周波数変調制御手段により生成された周波数変調信号とから位相変調信号を生成すると共に、前記共振形DC-DCコンバータの直流出力電流または直流出力電圧に応じて、パルス幅変調制御と位相変調制御とを切り替えることを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項7に記載した共振形DC-DCコンバータの制御装置において、
前記固定周波数制御手段は、前記共振形DC-DCコンバータの起動時にパルス幅変調制御し、パルス幅が前記直列共振回路の共振周波数の半周期よりも短い状態で前記平滑コンデンサを初期充電した後に、位相変調制御に切り替えることを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項2に記載した共振形DC-DCコンバータの制御装置において、
前記共振形DC-DCコンバータの起動時には前記固定周波数制御手段がパルス幅変調制御し、パルス幅が前記直列共振回路の共振周波数の半周期よりも短い状態で前記平滑コンデンサを初期充電した後に、前記周波数変調手段による周波数変調制御に切り替えることを特徴とする共振形DC-DCコンバータの制御装置。 - 請求項1~9の何れか1項に記載した共振形DC-DCコンバータの制御装置において、
前記制御量を決定するために、前記共振形DC-DCコンバータの直流出力電圧検出値及び直流出力電流検出値を用いることを特徴とする共振形DC-DCコンバータの制御装置。
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US14/372,449 US9379617B2 (en) | 2012-02-03 | 2012-12-20 | Resonant DC-DC converter control device |
KR1020147019420A KR101964224B1 (ko) | 2012-02-03 | 2012-12-20 | 공진형 dc-dc 컨버터의 제어장치 |
JP2013556218A JP5928913B2 (ja) | 2012-02-03 | 2012-12-20 | 共振形dc−dcコンバータの制御装置 |
CN201280066796.XA CN104040861B (zh) | 2012-02-03 | 2012-12-20 | 谐振型dc‑dc变换器的控制装置 |
EP12867379.5A EP2811638B1 (en) | 2012-02-03 | 2012-12-20 | Control device for resonance-type dc-dc converter |
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JP7332395B2 (ja) | 2019-09-02 | 2023-08-23 | 新電元工業株式会社 | 電源回路の制御装置及び制御方法 |
WO2023089916A1 (ja) * | 2021-11-22 | 2023-05-25 | 株式会社日立製作所 | 電力変換装置および電力変換装置の制御方法 |
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EP2811638B1 (en) | 2017-12-20 |
JP5928913B2 (ja) | 2016-06-01 |
JPWO2013114758A1 (ja) | 2015-05-11 |
KR20140123046A (ko) | 2014-10-21 |
US20140355313A1 (en) | 2014-12-04 |
EP2811638A1 (en) | 2014-12-10 |
CN104040861B (zh) | 2016-12-14 |
US9379617B2 (en) | 2016-06-28 |
KR101964224B1 (ko) | 2019-04-01 |
EP2811638A4 (en) | 2016-04-20 |
CN104040861A (zh) | 2014-09-10 |
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