WO2013089242A1 - Dispositif semi-conducteur de module de puissance et procédé de fabrication de ce dernier - Google Patents

Dispositif semi-conducteur de module de puissance et procédé de fabrication de ce dernier Download PDF

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Publication number
WO2013089242A1
WO2013089242A1 PCT/JP2012/082555 JP2012082555W WO2013089242A1 WO 2013089242 A1 WO2013089242 A1 WO 2013089242A1 JP 2012082555 W JP2012082555 W JP 2012082555W WO 2013089242 A1 WO2013089242 A1 WO 2013089242A1
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Prior art keywords
voltage side
terminal electrode
low
electrode pattern
semiconductor device
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PCT/JP2012/082555
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English (en)
Japanese (ja)
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将 笹川
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ローム株式会社
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Publication of WO2013089242A1 publication Critical patent/WO2013089242A1/fr

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    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
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    • H01L2924/1304—Transistor
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    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a power module semiconductor device and a manufacturing method thereof, and more particularly, to a power module semiconductor device and a manufacturing method thereof capable of reducing the size of a transfer mold.
  • SiC silicon carbide
  • FIG. 28A shows a schematic bird's-eye view configuration of a conventional dual inline package 300a.
  • FIG. 28 (b) shows a schematic bird's-eye view configuration of a conventional dual in-line package 300b that is simply reduced in size.
  • the inter-terminal distance t1 in FIG. 28A becomes t2 ( ⁇ t1) as shown in FIG. 28B, and the inter-terminal distance is reduced.
  • An object of the present invention is to provide a power module semiconductor device that realizes miniaturization of a transfer mold and a manufacturing method thereof.
  • the substrate, the low-voltage side gate terminal electrode disposed on the first side of the substrate, the low-voltage side disposed on the first side, and the low-voltage side A low voltage side source terminal electrode disposed adjacent to the gate terminal electrode; and a high voltage side gate disposed on the first side and spaced apart from the low voltage side gate terminal electrode and the low voltage side source terminal electrode.
  • the first copper plate layer on the ceramic substrate is patterned, and the low voltage side gate terminal electrode pattern, the low voltage side source terminal electrode pattern, and the high voltage are formed on the first side of the ceramic substrate.
  • a low-voltage side transistor and a low-voltage side diode connected in reverse parallel to the low-voltage side transistor are mounted on the low-voltage side drain electrode pattern, and reversely parallel to the high-voltage side transistor and the high-voltage side transistor on the high-voltage side drain electrode pattern
  • a power module half comprising a step of connecting a source pad electrode and an anode electrode of the high-voltage side diode by bonding wire, and connecting an anode electrode of the high-voltage side diode and the low-voltage side drain electrode pattern by bonding wire.
  • the present invention it is possible to provide a power module semiconductor device that realizes miniaturization of a transfer mold and a manufacturing method thereof.
  • FIG. 1 The typical external appearance plane block diagram of the power module semiconductor device which concerns on embodiment
  • FIG. 1 The back surface block diagram of Fig.1
  • FIG.1 The typical bird's-eye view block diagram of the power module semiconductor device which concerns on embodiment.
  • it is a figure for demonstrating the variation of the bending process of a gate terminal electrode, Comprising: (a) Typical side surface structure figure in case the bending process is not given, (b) Bending Schematic side surface structure diagram when processing is performed, (c) Schematic side surface structure diagram when mounting is not performed, (d) Schematic surface diagram when mounting is performed Side structure diagram.
  • the typical bird's-eye view block diagram at the time of bending all the terminal electrodes.
  • the typical bird's-eye view block diagram which shows the structure which mounted the terminal electrode, the transistor, and the diode in the power module semiconductor device which concerns on embodiment.
  • the enlarged view of A part of FIG. The typical plane pattern block diagram which shows the structure which mounted the terminal electrode, transistor, and diode of the power module semiconductor device which concerns on embodiment.
  • Typical cross-section FIG. (2) explaining 1 process of the manufacturing method of the power module semiconductor device which concerns on embodiment.
  • FIG. 3 is a circuit configuration diagram in which a capacitor C is connected between a power supply voltage supply terminal electrode PL and a ground potential terminal electrode NL in the power module semiconductor device according to the embodiment.
  • the typical circuit block diagram of the three-phase inverter comprised using the power module semiconductor device which concerns on embodiment.
  • FIG. 4 is a schematic cross-sectional structure diagram of a SiC MOSFET that includes a source pad electrode SP and a gate pad electrode GP, which is an example of a semiconductor device applied to the power module semiconductor device according to the embodiment.
  • A The typical external appearance plane block diagram of the power module semiconductor device which concerns on the modification 1 of embodiment,
  • b The back surface block diagram of Fig.24 (a).
  • A The typical external appearance plane block diagram of the power module semiconductor device which concerns on the modification 2 of embodiment, (b) The back surface block diagram of Fig.25 (a).
  • FIG. 1A The schematic external plan configuration of the power module semiconductor device 1 according to the embodiment is represented as shown in FIG. 1A, and the back configuration of FIG. 1A is represented as shown in FIG. Is done.
  • FIG. Is done A schematic bird's-eye view configuration along the XYZ-axis direction of the power module semiconductor device 1 according to the embodiment is expressed as shown in FIG.
  • the power module semiconductor device 1 includes a substrate, low-voltage side gate terminal electrodes GL4, GL5, and GL6, low-voltage side source terminal electrodes SL4, SL5, and SL6, Side gate terminal electrodes GL1, GL2, and GL3, high-voltage side source terminal electrodes SL1, SL2, and SL3, output terminal electrodes UL, VL, and WL, a power supply voltage supply terminal electrode PL, and a ground potential terminal electrode NL.
  • the low-voltage side gate terminal electrodes GL4, GL5, and GL6 are disposed on the first side of the substrate.
  • the low-voltage side source terminal electrodes SL4, SL5, and SL6 are arranged on the first side and are arranged adjacent to the low-voltage side gate terminal electrodes GL4, GL5, and GL6, respectively.
  • the high-voltage side gate terminal electrodes GL1, GL2, and GL3 are arranged on the first side, and are separated from the low-voltage side gate terminal electrodes GL4, GL5, and GL6 and the low-voltage side source terminal electrodes SL4, SL5, and SL6.
  • the high-voltage side source terminal electrodes SL1, SL2, and SL3 are arranged on the first side and are arranged adjacent to the high-voltage side gate terminal electrodes GL1, GL2, and GL3, respectively.
  • the output terminal electrodes UL, VL, WL are arranged on the second side opposite to the first side of the substrate.
  • the power supply voltage supply terminal electrode PL is arranged on a third side of the substrate different from the first side and the second side.
  • the ground potential terminal electrode NL is disposed on the third side and is spaced apart from the power supply voltage supply terminal electrode PL.
  • the substrate is a ceramic substrate 10, a first copper plate layer 10 a disposed on the surface of the ceramic substrate 10, and a second copper plate disposed on the back surface of the ceramic substrate 10.
  • a layer 10b is
  • the inter-terminal distance L4 between the low-voltage side source terminal electrode SL6 and the high-voltage side gate terminal electrode GL1 is, for example, about 6 mm, and between the high-voltage side source terminal electrode SL1 and the high-voltage side gate terminal electrode GL2.
  • the inter-terminal distance L5 is about 6 mm, for example, and the inter-terminal distance L6 between the high-voltage side source terminal electrode SL2 and the high-voltage side gate terminal electrode GL3 is about 6 mm, for example.
  • the inter-terminal distance L1 between the output terminal electrode UL and the output terminal electrode VL is, for example, about 6 mm
  • the inter-terminal distance L2 between the output terminal electrode VL and the output terminal electrode WL is, for example, about 6 mm
  • the inter-terminal distance L3 between the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL is, for example, about 6 mm.
  • the distance between the terminals along the edge of the ceramic substrate between the high-voltage side source terminal electrode SL3 and the ground potential terminal electrode NL is, for example, about 6 mm.
  • the inter-terminal distance along the edge of the ceramic substrate between the output terminal electrode WL and the power supply voltage supply terminal electrode PL is, for example, about 6 mm. Furthermore, the distance between the terminal electrodes GL4, SL4, GL5, SL5, GL6, and SL6 is, for example, about 1 mm. Similarly, the distance between the terminal electrodes GL1 and SL1, the distance between the terminal electrodes GL2 and SL2, and the distance between the terminal electrodes GL3 and SL3 are about 1 mm, for example.
  • the inter-terminal distances L1 and L2 are preferably longer than the inter-terminal distances L4 and L5.
  • a second copper plate layer 10b is disposed on the back surface of the ceramic substrate 10, and has a function as a heat sink.
  • the width W1 of the transfer mold resin 12 is about 6 mm or more, for example.
  • the length L in the X-axis direction of the transfer mold resin 12 is about 48 mm
  • the width W in the Y-axis direction is about 32 mm
  • the thickness in the Z-axis direction is about 3.5 mm. is there.
  • the thickness of the ceramic substrate 10 is about 0.35 to 0.68 mm.
  • the thickness of about 3.5 mm in the Z-axis direction is the dimension of the entire thickness of the transfer mold resin 12 molded on the front and back surfaces of the ceramic substrate 10 (see FIG. 17).
  • the thickness is increased, and the thickness is about 29 mm.
  • a transfer mold module is formed in order to reduce the size.
  • the terminal electrode can be taken out from the three directions of the mold package to obtain an insulation distance.
  • the high-voltage side signal terminal is arranged away from the low-voltage side signal terminal during the inverter operation, and the low-voltage side signal terminal is arranged side by side. Therefore, the low voltage side signal terminals are arranged side by side, the high voltage side signal terminals are arranged apart from each other, the output terminals are arranged apart from the low voltage side and high voltage side signal terminals, and the power supply voltage The terminal and the ground potential terminal are arranged separately from the output terminal and the signal terminal.
  • the power source voltage terminal, the ground potential terminal, the low-voltage side and the high-voltage side signal terminal and the output terminal are taken out from the three directions of the transfer mold module package, and the insulation distance may be taken. it can.
  • the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL are disposed adjacent to each other in order to facilitate the connection between the power supply V and the capacitor C.
  • the width of the output terminal electrodes UL, VL, WL may be set wide in a portion where strain stress is applied when the resin of the transfer mold resin is injected. That is, in the power module semiconductor device 1 according to the embodiment, the resin injection gate is formed on the power terminal side of the high heat resistant mold module, and the protrusion for preventing the slip is formed on the power terminal of the high heat resistant mold module. Also good.
  • the high heat-resistant resin is somewhat hard, and a thin signal wire bonding wire may come off during resin injection molding. Since the power bonding wire on the power terminal side is thicker than the signal wire bonding wire, it is desirable to inject the resin of the high heat-resistant resin from the power terminal side.
  • the diameter of the bonding wire for signal lines is, for example, about 150 ⁇ m
  • the diameter of the bonding wire for power is, for example, about 350 ⁇ m.
  • the convex part is formed in the power terminal.
  • the convex portion By forming the convex portion inside the power terminal, it is possible to increase the strength of the power terminal and to prevent the power bonding wire from coming off. That is, since the heat-resistant resin having a relatively high hardness is injected from the side resistant to stress during resin injection molding, defects during assembly can be reduced.
  • the terminal electrode may be bent in the height direction of the substrate when the power module semiconductor device 1 is mounted on the mounting substrate 200.
  • FIG. 3 is a diagram for explaining a variation of the bending process of the gate terminal electrode GL in the power module semiconductor device 1 according to the embodiment.
  • FIG. 3A illustrates the case where bending is not performed
  • FIG. 3B illustrates the case where the fold-shaped bending GLs is performed at a substantially central portion of the gate terminal electrode GL. If such a U-shaped bending process GLs is performed, the stress can be absorbed even when the gate terminal electrode GL receives some load.
  • FIG. 3 (c) shows a case in which the bending is gently inclined to the left side in the drawing
  • FIG. 3 (d) shows a case in which bending processing GLk is applied to the left side in the drawing. Is illustrated.
  • the direction of FIG. Can bring the tip GLt of the gate terminal electrode GL closer to the power module semiconductor device 1 side.
  • the power module semiconductor device 1 according to the embodiment is covered with the transfer mold resin 12 and is therefore denoted by reference numeral 12.
  • the power module semiconductor device 1 according to the embodiment is mounted on the mounting substrate 200 via an adhesive 13.
  • the adhesive 13 may be a conductive adhesive or a solder layer.
  • the gate terminal electrode GL includes the gate terminal electrodes GL1, GL2, GL3, and GL4 in FIG. -It corresponds to GL5 and GL6. 3 (a) to 3 (d), the variation of the bending process of the gate terminal electrode GL has been described. However, other source terminal electrodes SL1, SL2, SL3, SL4, SL5, SL6, output terminal electrodes The same applies to UL / VL / WL, ground potential terminal electrode NL, power supply voltage supply terminal electrode PL, and the like.
  • a schematic bird's-eye view configuration showing a structure in which terminal electrodes, transistors, and diodes are mounted is expressed as shown in FIG. 5 and an enlarged view of a portion A in FIG. Is expressed as shown in FIG.
  • a low-voltage side transistor Q4 is disposed on the low-voltage side drain electrode pattern D (K4), and the gate pad electrode GP4 of the low-voltage side transistor Q4 is surrounded by the source pad electrode SP4.
  • FIG. 7 the schematic planar pattern configuration showing the structure in which the terminal electrode, the transistor, and the diode of the power module semiconductor device 1 according to the embodiment are mounted is expressed as shown in FIG. 7, and the power module semiconductor according to the embodiment The circuit configuration of the device 1 is expressed as shown in FIG.
  • the first copper plate layer 10a includes the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 and the low-voltage side source terminal electrode pattern SLP4, as shown in FIGS. SLP5, SLP6, high-voltage side gate terminal electrode patterns GLP1, GLP2, and GLP3, high-voltage side source terminal electrode patterns SLP1, SLP2, and SLP3, and low-voltage side drain electrode pattern D (on which low-voltage side transistors Q4, Q5, and Q6 are mounted) K4), D (K5), D (K6), a high voltage side drain electrode pattern D (K) on which the high voltage side transistors Q1, Q2, Q3 are mounted, and a ground electrode pattern EP.
  • the low-voltage side transistor Q4 includes the low-voltage side drain electrode patterns D (K4), D (K5), and D (K6). ⁇ Low-voltage side diodes D4, D5, and D6 connected in reverse parallel to Q5 and Q6 are mounted, and the high-voltage side drain electrode pattern D (K) is connected to high-voltage side transistors Q1, Q2, and Q3 in reverse parallel connection. Diodes D1, D2, and D3 are mounted.
  • the chip size of the transistors Q1, Q2, Q3, Q4, Q5, and Q6 is, for example, about 4.8 mm ⁇ 4.8 mm, and the thickness is, for example, about 0.25 mm.
  • the chip sizes of the diodes D1, D2, D3, D4, D5, and D6 are, for example, about 5.14 mm ⁇ 5.14 mm, and the thickness is, for example, about 0.25 mm.
  • the thickness of the ground electrode pattern EP is, for example, about 0.3 to 0.4 mm.
  • the thickness of each terminal electrode is about 0.2 mm, for example.
  • the thickness of the solder layers 14 and 15 is, for example, about 0.1 mm.
  • the power module semiconductor device 1 includes the first bonding wires SW4, SW5, and SW6, the second bonding wires GW4, GW5, and GW6, as shown in FIGS. Bonding wires SW1, SW2, SW3, fourth bonding wires GW1, GW2, GW3, fifth bonding wires AW4, AW5, AW6, sixth bonding wires AW1, AW2, AW3, and seventh bonding wires BW1, BW2, BW3.
  • first bonding wires SW4, SW5, and SW6 connect the low-voltage side source terminal electrode patterns SLP4, SLP5, and SLP6 to the source pad electrodes SP4, SP5, and SP6 of the low-voltage side transistors Q4, Q5, and Q6.
  • the second bonding wires GW4, GW5, and GW6 connect the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 to the gate pad electrodes GP4, GP5, and GP6 of the low-voltage side transistors Q4, Q5, and Q6.
  • the third bonding wires SW1, SW2, and SW3 connect the high-voltage side source terminal electrode patterns SLP1, SLP2, and SLP3 to the source pad electrodes SP1, SP2, and SP3 of the high-voltage side transistors Q1, Q2, and Q3.
  • the fourth bonding wires GW1, GW2, and GW3 connect the high-voltage side gate terminal electrode patterns GLP1, GLP2, and GLP3 to the gate pad electrodes GP1, GP2, and GP3 of the high-voltage side transistors Q1, Q2, and Q3.
  • the fifth bonding wires AW4, AW5, and AW6 include the ground electrode pattern EP, the source pad electrodes SP4, SP5, and SP6 of the low-voltage side transistors Q4, Q5, and Q6, and the anode electrodes A4, A5, and A6 of the low-voltage side diodes D4, D5, and D6. And the stitch bonding connection.
  • the sixth bonding wires AW1, AW2, and AW3 connect the source pad electrodes SP1, SP2, and SP3 of the high-voltage side transistors Q1, Q2, and Q3 to the anode electrodes A1, A2, and A3 of the high-voltage side diodes D1, D2, and D3.
  • the seventh bonding wires BW1, BW2, and BW3 connect the anode electrodes A1, A2, and A3 of the high-voltage side diodes D1, D2, and D3 to the low-voltage side drain electrode patterns D (K4), D (K5), and D (K6).
  • the sixth bonding wires AW1, AW2, and AW3 and the seventh bonding wires BW1, BW2, and BW3 may be stitch-bonded.
  • the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 are mounted with the low-voltage side gate terminal electrodes GL4, GL5, and GL6, and the low-voltage side source terminal electrode patterns SLP4, SLP5, and Low-voltage side source terminal electrodes SL4, SL5, and SL6 are mounted on SLP6, and high-voltage side gate terminal electrodes GL1, GL2, and GL3 are mounted on high-voltage side gate terminal electrode patterns GLP1, GLP2, and GLP3.
  • the electrode patterns SLP1, SLP2, and SLP3 have high-voltage side source terminal electrodes SL1, SL2, and SL3 mounted thereon, the ground electrode pattern EP has a ground potential terminal electrode NL mounted thereon, and the high-voltage side drain electrode pattern D (K).
  • the high-voltage side drain electrode pattern D (K) Is equipped with a power supply voltage supply terminal electrode PL, and a low-voltage side drain electrode pattern D (K4)
  • the D (K5) ⁇ D (K6), the output terminal electrode UL ⁇ VL ⁇ WL is mounted.
  • the output terminal electrodes UL, VL, and WL may include output terminal electrode expansion portions UE, VE, and WE for increasing the strength, as shown in FIG. good.
  • the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL have a power supply voltage supply terminal electrode extension PLE for increasing the strength, as shown in FIG. Also, a ground potential terminal electrode extension NLE may be provided.
  • the electrode expansion portions for increasing the strength include the high-voltage side gate terminal electrodes GL1, GL2, and GL3, the high-voltage side source terminal electrodes SL1, SL2, and SL3, and the low-voltage side gate terminal electrode GL4. -You may form in each connection part of GL5 * GL6 and low voltage
  • the transfer is performed on the front and back surfaces of the ceramic substrate 10 except on the second copper plate layer 10b.
  • a mold resin 12 is provided.
  • the ceramic substrate 10 can be formed of aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), or silicon nitride (SiN).
  • FIG. 14 a schematic planar pattern configuration of the power module semiconductor device 1 according to the embodiment corresponding to the process of FIG. 13 is represented as shown in FIG. 14, and the power module according to the embodiment corresponding to the process of FIG.
  • a schematic planar pattern configuration of the semiconductor device 1 is expressed as shown in FIG.
  • the first copper plate layer 10 a on the ceramic substrate 10 is patterned to form the first side of the ceramic substrate 10.
  • Low voltage side gate terminal electrode patterns GLP4, GLP5, GLP6, Low voltage side source terminal electrode patterns SLP4, SLP5, SLP6, High voltage side gate terminal electrode patterns GLP1, GLP2, GLP3, and High voltage side source terminal electrode patterns SLP1, SLP2, SLP3 And spaced apart to the first side, the low-voltage side drain electrode pattern D (K4) / D (K5) / D (K6), the high-voltage side drain electrode pattern D (K), and the ground electrode pattern EP And forming a process.
  • the method for manufacturing the power module semiconductor device 1 includes the low-voltage side transistor Q 4 ⁇ on the low-voltage side drain electrode pattern D (K 4) ⁇ D (K 5) ⁇ D (K 6).
  • Low-voltage side diodes D4, D5, and D6 connected in reverse parallel to Q5 and Q6 and low-voltage side transistors Q4, Q5, and Q6 are mounted, and high-voltage side transistors Q1, Q2, and Q3 and high-voltage side drain electrode pattern D (K)
  • the manufacturing method of the power module semiconductor device 1 includes the low-voltage side gate terminal electrode on the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 on the first side of the ceramic substrate 10.
  • Connect GL4, GL5, and GL6 connect low-voltage side source terminal electrode patterns SLP4, SLP5, and SLP6 to low-voltage side source terminal electrodes SL4, SL5, and SL6, and connect high-voltage side gate terminal electrode patterns GLP1, GLP2, and GLP3 to high-voltage side gates
  • the terminal electrodes GL1, GL2, and GL3 are connected, the high-voltage side source terminal electrode patterns SLP1, SLP2, and SLP3 are connected to the high-voltage side source terminal electrodes SL1, SL2, and SL3, and the second side different from the first side of the ceramic substrate 10 is connected.
  • the method of manufacturing the power module semiconductor device 1 includes the source pads of the low-voltage side source terminal electrode patterns SLP4, SLP5, and SLP6 and the low-voltage side transistors Q4, Q5, and Q6.
  • the electrodes SP4, SP5, and SP6 are connected using bonding wires SW4, SW5, and SW6, and the gate pad electrodes GP4, GP5, and GP6 of the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 and the low-voltage side transistors Q4, Q5, and Q6 are connected.
  • SLP1, SLP2, and SLP3 are connected to the source pad electrodes SP1, SP2, and SP3 of the high-voltage transistors Q1, Q2, and Q3.
  • the high-voltage side gate terminal electrode patterns GLP1, GLP2, and GLP3 are connected to the gate pad electrodes GP1, GP2, and GP3 of the high-voltage side transistors Q1, Q2, and Q3 using bonding wires GW1, GW2, and GW3, and ground pattern electrodes EP is stitch bonded to the source pad electrodes SP4, SP5, and SP6 of the low-voltage side transistors Q4, Q5, and Q6 and the anode electrodes A4, A5, and A6 of the low-voltage side diodes D4, D5, and D6 using bonding wires AW4, AW5, and AW6.
  • bonding wires SW1, SW2, SW3, SW4, SW5, SW6 and bonding wires GW1, GW2, GW3, GW4, GW5, and GW6 use relatively thin bonding wires.
  • Bonding wires AW1, AW2, AW3, AW4, AW5, and AW6 and bonding wires BW1, BW2, and BW3 use relatively thick bonding wires. Although shown as one in the drawing, for example, about four relatively thick bonding wires may be connected in parallel.
  • the relatively thick bonding wire connection before the relatively thin bonding wire connection. Further, it is desirable to perform the bonding wire connection between the transistors Q1, Q2, Q3, Q4, Q5, and Q6 and the diodes D1, D2, D3, D4, D5, and D6 before the bonding wire connection of the terminal electrode pattern. . This is to prevent the relatively thin bonding wire from being damaged by the force applied when the relatively thick bonding wire is connected.
  • the method for manufacturing the power module semiconductor device 1 includes a low-voltage drain electrode pattern D (K4) / D (K5) / D of the ceramic substrate 10 as shown by an arrow B in FIGS.
  • FIGS. 9 to 13, 15 and 17 show schematic cross-sectional structures taken along the line II in FIG.
  • the first copper plate layer 10a is patterned to form a high-voltage side source terminal electrode pattern SLP3, a ground electrode pattern EP, a high-voltage side drain electrode pattern D (K), and a low-voltage side drain. Electrode pattern D (K6) is formed.
  • the high voltage side transistor Q1 and the high voltage side diode D3 are mounted on the high voltage side drain electrode pattern D (K) via the solder layer 15.
  • the high voltage side transistor Q1 and the high voltage side diode D3 are connected in reverse parallel to each other, and the high voltage side drain electrode pattern D (K) is connected to the drain electrode of the high voltage side transistor Q1 and the cathode electrode of the high voltage side diode D3.
  • the high-voltage side source terminal electrode SL3 is connected to the high-voltage side source terminal electrode pattern SLP3 via the solder layer 14, and the low-voltage side drain electrode pattern D (K6) is formed.
  • the output terminal electrode WL is connected through the solder layer 16.
  • the high-voltage source terminal electrode pattern SLP3 and the source pad electrode SP3 of the high-voltage transistor Q3 are connected using a bonding wire SW3, and the source pad electrode SP3 of the high-voltage transistor Q3 is connected.
  • the anode electrode A3 of the high-voltage side diode D3 are connected using a bonding wire AW3, and the anode electrode A3 of the high-voltage side diode D3 and the low-voltage side drain electrode pattern D (K6) are connected using a bonding wire BW3.
  • the low-voltage side source terminal electrode patterns SLP4, SLP5, and SLP6 and the source pad electrodes SP4, SP5, and SP6 of the low-voltage side transistors Q4, Q5, and Q6 are bonded to the bonding wires SW4 and SW5. -Connect using SW6.
  • the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 are connected to the gate pad electrodes GP4, GP5, and GP6 of the low-voltage side transistors Q4, Q5, and Q6 using bonding wires GW4, GW5, and GW6.
  • the high-voltage side source terminal electrode patterns SLP1, SLP2, and SLP3 are connected to the source pad electrodes SP1, SP2, and SP3 of the high-voltage side transistors Q1, Q2, and Q3 using bonding wires SW1, SW2, and SW3.
  • the high-voltage side gate terminal electrode patterns GLP1, GLP2, and GLP3 are connected to the gate pad electrodes GP1, GP2, and GP3 of the high-voltage side transistors Q1, Q2, and Q3 using bonding wires GW1, GW2, and GW3.
  • ground electrode pattern EP and the source pad electrodes SP4, SP5, and SP6 of the low-voltage side transistors Q4, Q5, and Q6 and the anode electrodes A4, A5, and A6 of the low-voltage side diodes D4, D5, and D6 are bonded to the bonding wires AW4, AW5, and AW6.
  • the source pad electrodes SP1, SP2, and SP3 of the high-voltage side transistors Q1, Q2, and Q3 and the anode electrodes A1, A2, and A3 of the high-voltage side diodes D1, D2, and D3 are bonded using bonding wires AW1, AW2, and AW3.
  • the anode electrodes A1, A2, and A3 of the high-voltage side diodes D1, D2, and D3 and the low-voltage side drain electrode patterns D (K4), D (K5), and D (K6) are stitch-bonded using bonding wires BW1, BW2, and BW3. Connecting. Further, the portion indicated by the bonding wire AW1 and the bonding wire BW1 may be stitch-bonded continuously with one bonding wire. The same applies to bonding wire AW2 and bonding wire BW2, and bonding wire AW3 and bonding wire BW3.
  • the portion indicated by the bonding wire AW4 is different between the ground electrode pattern EP and the source pad electrode SP4 of the low voltage side transistor Q4, and between the source pad electrode SP4 of the low voltage side transistor Q4 and the anode electrode A4 of the low voltage side diode D4.
  • Wire bonding connection may be performed using a bonding wire. The same applies to the bonding wire AW5 and the bonding wire AW6.
  • transfer mold resin 12 is injected from the side of the ceramic substrate 10 where the low-voltage drain electrode pattern D (K6) is disposed.
  • the transfer mold resin 12 is formed from the side of the ceramic substrate 10 on which the low-voltage drain electrode patterns D (K4), D (K5), and D (K6) are formed. Inject.
  • a material of the transfer mold resin 12 for example, a thermosetting epoxy resin can be applied.
  • gate bonding wires (thin wire wires) GW4, GW5, and GW4 that connect the low-voltage side gate terminal electrode patterns GLP4, GLP5, and GLP6 of the ceramic substrate 10 to the gate pad electrodes GP4, GP5, and GP6 of the low-voltage side transistors Q4, Q5, and Q6.
  • the transfer mold resin 12 may be injected from the direction facing the GW 6.
  • the transfer mold resin 12 is formed on the front surface and the back surface of the ceramic substrate 10.
  • the transfer mold resin 12 is formed so as to cover the front surface and the back surface of the ceramic substrate 10 except on the second copper plate layer 10b.
  • the power module semiconductor device 1 As a result of the above steps, the power module semiconductor device 1 according to the embodiment shown in FIGS. 1 and 2 is completed.
  • FIG. 18A a schematic planar pattern configuration in the vicinity of the output terminal electrode WL is expressed as shown in FIG. 18A, and is a schematic diagram taken along line II-II in FIG. A typical cross-sectional structure is represented as shown in FIG.
  • the output terminal electrode WL includes the output terminal electrode extension WE as shown in FIG. 18, whereby the low-voltage side drain electrode pattern D (K6) and the output terminal electrode WL are provided. Connection strength can be increased. For this reason, disconnection between the output terminal electrode WL and the low-voltage side drain electrode pattern D (K6) can be prevented, and the connection reliability can be improved.
  • a schematic bird's-eye view configuration for explaining a state where the electrolytic capacitor 20 is connected between the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL is expressed as shown in FIG.
  • the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL may include pinholes 18P and 18N for connecting the pins 22P and 22N of the electrolytic capacitor 20, as shown in FIG.
  • the SiC MOSFET can be miniaturized and can conduct a large current. In the SiMOSFET and the Si-based IGBT, the allowable power amount has been limited to 10 W / cc, but in the power module semiconductor device 1 according to the embodiment in which the SiC-based MOSFET is mounted, 50 W / cc can be achieved.
  • the power module In Si devices, relatively little current can flow. For this reason, in a power module using a Si-based device, the power module is arranged on the printed board and a circuit is formed on the printed board, and a capacitor such as an electrolytic capacitor is connected to and arranged on the power module.
  • pin holes 18P and 18N for connecting the pins 22P and 22N of the electrolytic capacitor 20 to the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL are formed, and the electrolytic capacitor 20 and the power supply voltage are supplied.
  • the connection between the terminal electrode PL and the ground potential terminal electrode NL can be realized by inserting the pins 22P and 22N of the electrolytic capacitor 20 into the pinholes 18P and 18N.
  • the size of the electrolytic capacitor 20 connected between the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL is, for example, about 6 mm in length and about 1 mm in diameter, and the value of the capacitor is about 100 ⁇ F to about 3 mF. Degree.
  • a circuit configuration in which the capacitor C is connected between the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL is expressed as shown in FIG.
  • a large surge voltage Ldi / dt is generated due to the high switching speed of the SiC device due to the inductance L of the connection line.
  • the surge voltage Ldi / dt varies depending on the value of the inductance L
  • the surge voltage Ldi / dt is superimposed on the power supply V.
  • the surge voltage Ldi / dt can be absorbed by the capacitor C connected between the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL.
  • the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL are rounded around the pinholes 18P and 18N for connecting the pins 22P and 22N of the electrolytic capacitor 20. You may provide the extended part which gave. By providing such an extended structure with roundness around the pinholes 18P and 18N, the connection strength at the time of connecting the pins 22P and 22N of the electrolytic capacitor 20 can be increased.
  • the three-phase AC inverter includes a gate drive unit 50, a power module unit 52 connected to the gate drive unit 50, and a three-phase AC motor unit 54.
  • the power module unit 52 is connected to U, V, and W phase inverters corresponding to the U phase, V phase, and W phase of the three-phase AC motor unit 54.
  • the inverter-structured SiC MOSFETs Q1 and Q4, Q2 and Q5, and Q3 and Q6 are connected between the plus terminal (+) and the minus terminal ( ⁇ ) to which the capacitor C is connected. Furthermore, diodes D1 to D6 are connected in antiparallel between the sources and drains of the SiC MOSFETs Q1 to Q6, respectively.
  • a schematic cross-sectional structure of SiC • MOSFET includes a semiconductor substrate 26 formed of an n ⁇ high resistance layer, and a semiconductor A p base region 28 formed on the surface side of the substrate 26, a source region 30 formed on the surface of the p base region 28, and a gate insulating film 32 disposed on the surface of the semiconductor substrate 26 between the p base regions 28.
  • a region 24 and a drain pad electrode 36 connected to the n + drain region 24 are provided.
  • the semiconductor device 100 is composed of a planar gate type n-channel vertical SiC • MOSFET, but may be composed of a trench gate type n-channel vertical SiC • MOSFET.
  • Si-based MOSFETs, GaN-based FETs, and the like can be applied to the semiconductor device 100 applied to the power module semiconductor device 1 according to the embodiment instead of SiC • MOSFETs.
  • any one of Si-based, SiC-based, GaN-based, or AlN-based power devices can be applied.
  • the semiconductor device 100 applied to the power module semiconductor device 1 according to the embodiment can use a semiconductor having a band gap energy of, for example, 1.1 eV to 8 eV.
  • FIG. 23 is an example of the semiconductor device 100 applied to the power module semiconductor device 1 according to the embodiment, and a schematic cross-sectional structure of the SiC MOSFET including the source pad electrode SP and the gate pad electrode GP is represented as shown in FIG. Is done.
  • the gate pad electrode GP is connected to the gate electrode 38 disposed on the gate insulating film 32, and the source pad electrode SP is connected to the source electrode 34 connected to the source region 30 and the p base region 28.
  • the gate pad electrode GP and the source pad electrode SP are disposed on a passivation interlayer insulating film 44 covering the surface of the semiconductor device 100.
  • illustration is omitted, but as in the central portion of FIG. 22 or FIG. A transistor structure having a structure may be formed.
  • the source pad electrode SP may be extended and disposed on the interlayer insulating film 44 for passivation also in the transistor structure in the central portion.
  • the gate pad electrode GP may be extended and disposed on the passivation interlayer insulating film 44.
  • FIG. 24A A schematic external plan configuration of the power module semiconductor device 1a according to the first modification of the embodiment is represented as shown in FIG. 24A, and the back configuration of FIG. 24A is shown in FIG. Represented as shown.
  • the power module semiconductor device 1a according to the first modification of the embodiment has a configuration in which the side of the substrate on which the output terminal electrodes UL, VL, and WL are arranged is changed as compared with the embodiment.
  • the power module semiconductor device 1a includes a substrate, low-voltage side gate terminal electrodes GL4, GL5, and GL6, and a low-voltage source.
  • Terminal electrodes SL4, SL5, and SL6, high-voltage side gate terminal electrodes GL1, GL2, and GL3, high-voltage side source terminal electrodes SL1, SL2, and SL3, output terminal electrodes UL, VL, and WL, and a power supply voltage supply terminal electrode PL And a ground potential terminal electrode NL.
  • the low-voltage side gate terminal electrodes GL4, GL5, and GL6 are disposed on the first side of the substrate.
  • the low-voltage side source terminal electrodes SL4, SL5, and SL6 are arranged on the first side and are arranged adjacent to the low-voltage side gate terminal electrodes GL4, GL5, and GL6, respectively.
  • the high-voltage side gate terminal electrodes GL1, GL2, and GL3 are arranged on the first side, and are separated from the low-voltage side gate terminal electrodes GL4, GL5, and GL6 and the low-voltage side source terminal electrodes SL4, SL5, and SL6.
  • the high-voltage side source terminal electrodes SL1, SL2, and SL3 are arranged on the first side and are arranged adjacent to the high-voltage side gate terminal electrodes GL1, GL2, and GL3, respectively.
  • the output terminal electrodes UL, VL, and WL are arranged on a second side different from the first side of the substrate.
  • the power supply voltage supply terminal electrode PL is disposed on the third side of the substrate facing the second side.
  • the ground potential terminal electrode NL is disposed on the third side and is separated from the power supply voltage supply terminal electrode PL.
  • FIG. 25A A schematic external plan configuration of the power module semiconductor device 1a according to the second modification of the embodiment is represented as shown in FIG. 25A, and the back configuration of FIG. 25A is shown in FIG. Represented as shown.
  • the power module semiconductor device 1a according to the second modification of the embodiment has a configuration in which the sides on which the power supply voltage supply terminal electrode PL and the ground potential terminal electrode NL are arranged are further changed as compared with the first modification of the embodiment. .
  • the power module semiconductor device 1 includes a substrate, low-voltage side gate terminal electrodes GL4, GL5, and GL6, and a low-voltage source.
  • Terminal electrodes SL4, SL5, and SL6, high-voltage side gate terminal electrodes GL1, GL2, and GL3, high-voltage side source terminal electrodes SL1, SL2, and SL3, output terminal electrodes UL, VL, and WL, and a power supply voltage supply terminal electrode PL And a ground potential terminal electrode NL.
  • the low-voltage side gate terminal electrodes GL4, GL5, and GL6 are disposed on the first side of the substrate.
  • the low-voltage side source terminal electrodes SL4, SL5, and SL6 are arranged on the first side and are arranged adjacent to the low-voltage side gate terminal electrodes GL4, GL5, and GL6, respectively.
  • the high-voltage side gate terminal electrodes GL1, GL2, and GL3 are arranged on the first side, and are separated from the low-voltage side gate terminal electrodes GL4, GL5, and GL6 and the low-voltage side source terminal electrodes SL4, SL5, and SL6.
  • the high-voltage side source terminal electrodes SL1, SL2, and SL3 are arranged on the first side and are arranged adjacent to the high-voltage side gate terminal electrodes GL1, GL2, and GL3, respectively.
  • the output terminal electrodes UL, VL, and WL are arranged on a second side different from the first side of the substrate.
  • the power supply voltage supply terminal electrode PL is disposed on the third side of the substrate facing the first side.
  • the ground potential terminal electrode NL is disposed on the third side and is separated from the power supply voltage supply terminal electrode PL.
  • FIG. 26A A schematic external plan configuration of a power module semiconductor device 1a according to the third modification of the embodiment is represented as shown in FIG. 26A, and the back configuration of FIG. 26A is shown in FIG. Represented as shown.
  • the power module semiconductor device 1a according to the third modification of the embodiment has a configuration corresponding to a single-phase inverter in terms of circuit configuration.
  • the power module semiconductor device 1a includes a substrate, a low-voltage side gate terminal electrode GL4, a low-voltage side source terminal electrode SL4, The high-voltage side gate terminal electrode GL1, the high-voltage side source terminal electrode SL1, the output terminal electrode UL, the power supply voltage supply terminal electrode PL, and the ground potential terminal electrode NL.
  • the low-voltage side gate terminal electrode GL4 is disposed on the first side of the substrate.
  • the low-voltage side source terminal electrode SL4 is disposed on the first side and adjacent to the low-voltage side gate terminal electrode GL4.
  • the high-voltage side gate terminal electrode GL1 is arranged on the first side and is arranged apart from the low-voltage side gate terminal electrode GL4 and the low-voltage side source terminal electrode SL4.
  • the high-voltage side source terminal electrode SL1 is disposed on the first side and is disposed adjacent to the high-voltage side gate terminal electrode GL1.
  • the output terminal electrode UL is disposed on the second side opposite to the first side of the substrate.
  • the power supply voltage supply terminal electrode PL is disposed on the third side of the substrate different from the first side and the second side.
  • the ground potential terminal electrode NL is disposed on the third side and is separated from the power supply voltage supply terminal electrode PL.
  • FIG. 27A a schematic external plan configuration of the power module semiconductor device 1a according to the fourth modification of the embodiment is expressed as shown in FIG. 27A, and the back configuration of FIG. 27A is shown in FIG. ).
  • the power module semiconductor device 1a according to the fourth modification of the embodiment has a configuration in which the side of the substrate on which the output terminal electrode UL is arranged is changed as compared with the third modification of the embodiment.
  • the power module semiconductor device 1a according to the fourth modification of the embodiment also has a configuration corresponding to a single-phase inverter in terms of circuit configuration.
  • the power module semiconductor device 1a includes a substrate, a low-voltage side gate terminal electrode GL4, a low-voltage side source terminal electrode SL4, The high-voltage side gate terminal electrode GL1, the high-voltage side source terminal electrode SL1, the output terminal electrode UL, the power supply voltage supply terminal electrode PL, and the ground potential terminal electrode NL.
  • the low-voltage side gate terminal electrode GL4 is disposed on the first side of the substrate.
  • the low-voltage side source terminal electrode SL4 is disposed on the first side and adjacent to the low-voltage side gate terminal electrode GL4.
  • the high-voltage side gate terminal electrode GL1 is arranged on the first side and is arranged apart from the low-voltage side gate terminal electrode GL4 and the low-voltage side source terminal electrode SL4.
  • the high-voltage side source terminal electrode SL1 is disposed on the first side and is disposed adjacent to the high-voltage side gate terminal electrode GL1.
  • the output terminal electrode UL is disposed on a second side different from the first side of the substrate.
  • the power supply voltage supply terminal electrode PL is disposed on the third side of the substrate facing the second side.
  • the ground potential terminal electrode NL is disposed on the third side and is separated from the power supply voltage supply terminal electrode PL.
  • the semiconductor device of the present invention can be applied to all power devices such as electric vehicles, hybrid vehicles, industrial equipment, power conditioners, inverters, power semiconductor modules mounted on home appliances, and intelligent power modules.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Inverter Devices (AREA)

Abstract

La présente invention a pour objectif un dispositif semi-conducteur de module de puissance pour réduire la taille d'un moulage de transfert. La solution proposée par la présente invention comprend : des électrodes de borne de grille côté basse pression (GL4, GL5 et GL6) disposées sur un premier côté d'un substrat (10) ; des électrodes de borne de source côté basse pression (SL4, SL5 et SL6) disposées de façon adjacente aux électrodes de borne de grille côté basse pression ; des électrodes de borne de grille côté haute pression (GL1, GL2 et GL3) disposées au niveau du premier côté loin des électrodes de borne de grille côté basse pression et des électrodes de borne de source côté basse pression ; des électrodes de borne de source côté haute pression (SL1, SL2 et SL3) disposées au niveau du premier côté de façon adjacente aux électrodes de borne de source côté haute pression ; des électrodes de borne de sortie (UL, Vl et WL) disposées au niveau d'un deuxième côté qui est différent du premier côté ; une électrode de borne d'alimentation en tension de source d'alimentation (PL) disposée au niveau d'un troisième côté qui est différent du premier côté et du deuxième côté ; et d'une électrode de borne de potentiel de masse (NL) disposée au niveau du troisième côté loin de l'électrode de borne d'alimentation en tension de source d'alimentation.
PCT/JP2012/082555 2011-12-14 2012-12-14 Dispositif semi-conducteur de module de puissance et procédé de fabrication de ce dernier WO2013089242A1 (fr)

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WO2018109069A1 (fr) 2016-12-16 2018-06-21 Abb Schweiz Ag Module semiconducteur de puissance à faible inductance de chemin de grille
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US12068290B2 (en) 2019-05-14 2024-08-20 Hitachi Energy Ltd Power semiconductor module with low inductance gate crossing

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