TWI459536B - 多晶片封裝 - Google Patents

多晶片封裝 Download PDF

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Publication number
TWI459536B
TWI459536B TW99124924A TW99124924A TWI459536B TW I459536 B TWI459536 B TW I459536B TW 99124924 A TW99124924 A TW 99124924A TW 99124924 A TW99124924 A TW 99124924A TW I459536 B TWI459536 B TW I459536B
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Taiwan
Prior art keywords
wafer
metal layer
drain
source
mosfet
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TW99124924A
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English (en)
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TW201104828A (en
Inventor
Anup Bhalla
Yi Su
David Grey
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Alpha & Omega Semiconductor
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Publication of TW201104828A publication Critical patent/TW201104828A/zh
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Publication of TWI459536B publication Critical patent/TWI459536B/zh

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Description

多晶片封裝
本發明主要涉及半導體封裝，更確切地說，是關於半導體封裝以及製作半導體封裝的方法。
在許多MOSFET開關電路中，經常以互補的方式切換一對功率MOSFET。一種典型的MOSFET開關電路如第1圖所示，它包括兩個MOSFET--12和14，通過電壓源V輸入 和接地端，串聯在一起。MOSFET12和14分別代表高端和低端MOSFET。
為了開啟開關迴圈，首先要關閉MOSFET14。因此，MOSFET14的體二極體開啟，並驅動電流。延遲後，MOSFET12開啟，關閉MOSFET的體二極體。從而產生恢復電流IL ，以及與開關電路10有關的追蹤電感（沒有表示出來）、產生振盪。
為了節省空間和成本，常常把MOSFET12和14封裝在一起，如圖中虛線所示。MOSFET12和14的目的在於獲得最高的功率密度，以便高效地工作。功率密度與晶片面積密切相關，也就是說，晶片越大，漏極至源極導通電阻Rdson越低。如第2圖所示，其特點在於，MOSFET12和14在獨立的晶片墊上，共同封裝在一起。整體的封裝結構如虛線中所示。傳統的功率MOSFET 12和14為垂直器件，源極S1和S2、柵極G1和G2分別位於一側，漏極D1和D2分別位於另一側。MOSFET 12貼在晶片墊16上，其引腳繼續延伸，可以連接到漏極D1上。MOSFET 14貼在晶片墊18上。低端晶片墊通過雙側無引腳扁平（DFN）封裝的底部，裸露在外，以便外部連接到漏極D2和源極S1上。由於MOSFET 14通常開啟較長的持續時間，因此與高端MOSFET 14相比，低端MOSFET 14的特點是具有較大的晶片面積。源極S1通過導線從S1到晶片墊18，連接到漏極D2上。柵極G1和G2以及源極S2通過導線，連接到合適的引腳上。MOSFET 12和14的晶片面積受到封裝尺寸以及晶片共同封裝結構的約束。
因此，必須通過最大化MOSFET的晶片面積，來改善使用性能，使Rdson最小，而且不額外地增加電路的總尺寸。
本發明的一種含有多個引腳的多晶片封裝，包括：
第一和第二半導體晶片，迭印並連接在一起，定義一個具有對立的第一和第二邊的晶片堆疊，每個所述的第一和第二半導體晶片都有柵極、漏極和源極區域，以及柵極、漏極和源極接頭，所述的第一對立邊具有所述的第二半導體晶片的所述的漏極接頭，所述的漏極接頭與第一套所述的多個引腳電接觸，所述的第一半導體晶片的所述的柵極、漏極和源極接頭，與所述的第二半導體晶片的柵極和源極接頭設置在所述的第二個對立邊上，並與第二套所述的多個引腳電接觸，其中所述的第一半導體晶片的源極接頭與所述的第二半導體晶片的漏極接頭電接觸。
上述的封裝，所述的第二邊包括第一和第二隔開的表面，所述的第一表面包括一個設置在所述的第二半導體晶片上方的導電金屬層，所述的第一半導體晶片的漏極接頭面對著所述的第一表面，並接觸所述的導電金屬層，絕緣材料在所述的第二半導體晶片和所述的導電金屬層之間延伸，並使所述的第二半導體晶片與所述的導電金屬層絕緣。
上述的封裝，所述的第二邊包括第一和第二隔開的表面，所述的第一表面包括一個設置在所述的第二半導體晶片上方的導電金屬層，所述的第一半導體晶片的漏極接頭與所述的導電金屬層的第一部分迭印並接觸，所述的導電金屬層的第二部分與所述的第一部分並排在一起，絕緣材料在所述的第二半導體晶片和所述的導電金屬層之間延伸，其中所述的第二部分作為導電互聯的焊接墊。
上述的封裝，所述的第二邊包括所述的第二半導體晶片的一個表面，以及所述的第一半導體晶片的第一表面，背離所述的第二半導體晶片的所述的表面，所述的第一半導體晶片的柵極、漏極和源極接頭位於所述的第一半導體晶片的所述的第一表面中，其中所述的第一半導體晶片不導電地附著在第二半導體晶片所述的表面上。
上述的封裝，所述的第二半導體晶片的面積大於所述的第一半導體晶片的面積。
本發明的一種晶片堆疊，包括：
一個底部晶片；
一個堆積在底部晶片上的頂部晶片；以及
一個設置在底部晶片上的浮動金屬層，通過絕緣材料，浮動金屬層與底部晶片絕緣，其中浮動金屬層不僅作為頂部晶片的導電晶片墊，還作為導電互聯的焊接墊。
上述的晶片堆疊，底部晶片和頂部晶片均為分立的半導體器。
上述的晶片堆疊，底部晶片為一個頂端具有源極、底端具有漏極的第一MOSFET，其中浮動金屬層通過絕緣材料，與所述的第一MOSFET所述的源極絕緣，頂部晶片為一個一側設置源極、另一個側設置漏極的第二MOSFET，並且所述第二MOSFET漏極與所述的浮動金屬層接觸。
上述的晶片堆疊，還包括一個引線框晶片墊，其中底部晶片的漏極附著在引線框晶片墊上，頂部晶片的源極通過導電互聯，連接到所述的引線框晶片墊上。
上述的晶片堆疊，還包括引線框引腳；以及
第一套導電互聯，連接在所述的浮動導電層的焊接墊部分和所述的第一套引線框引腳之間。
上述的晶片堆疊，所述的底部晶片為低端MOSFET，所述的頂部晶片為高端MOSFET。
上述的晶片堆疊，還包括在底部晶片上方、絕緣材料和一部分浮動金屬下方的頂部金屬，其中源極金屬並不在浮動金屬層的焊接墊部分下方。
本發明的一種半導體封裝，包括：
第一和第二晶片堆疊，每個堆疊都含有一個底部晶片，一個頂部晶片；以及
一個設置在底部晶片上的浮動金屬層，通過絕緣材料，浮動金屬層與底部晶片絕緣，其中浮動金屬層不僅作為頂部晶片的導電晶片墊，還作為導電互聯的焊接墊，並且其中所述的底部晶片為低端MOSFET，所述的頂部晶片為高端MOSFET。
上述的封裝，第一和第二晶片堆疊並聯在一起。
上述的封裝，第一和第二晶片堆疊構成一個全橋式電路。
本發明的一種堆積兩個分立晶片的方法，包括：
在底部晶片上方製備一個浮動金屬層，通過絕緣材料，浮動金屬層與底部晶片電絕緣；
將頂部晶片的底部導電連接到浮動金屬層；並且
利用浮動金屬層，從頂部晶片的底部引出一個連接。
上述的方法，分立的半導體器件為MOSFET。
上述的方法，底部晶片為一個頂端具有源極、底端具有漏極的第一MOSFET，其中浮動金屬層通過絕緣材料，與所述的第一MOSFET所述的源極絕緣，其中頂部晶片為一個頂端設置源極接頭、底端設置漏極接頭的第二MOSFET，所述的第二MOSFET的所述漏極接頭附著到所述的浮動金屬層上。
上述的方法，還包括將源極接頭置於底部晶片上方，使其位於絕緣材料和浮動金屬層的第一部分下方，但不在用於焊接導電互聯的一部分浮動金屬層下方。
上述的方法，底部晶片為低端MOSFET，頂部晶片為高端MOSFET。
依照本發明的一個方面，一種多晶片封裝，具有多個引腳，並由迭印和焊接在一起的第一和第二半導體晶片構成，定義一個晶片堆疊。晶片堆疊具有相對的第一和第二個邊，每個第一和第二半導體晶片都具有柵極、漏極和源極區域，以及柵極、漏極和源極接頭。第一個對邊上有第二半導體晶片的漏極接頭，漏極接頭與第一套多個引腳電接觸。第一半導體晶片的柵極、漏極和源極接頭，以及第二半導體晶片的柵極和源極接頭，設置在第二對邊上，以出現在不同平面中，與第二套多個引腳電接觸。依靠這種結構，無需額外的增加電路的總尺寸，第一和第二半導體晶片的晶片面積就可以達到最大化。依據本發明的另一個實施例，可以在第一和第二半導體晶片的其中一個晶片上，設置一個浮動金屬層，作為晶片墊和焊接墊，用於剩餘的第一和第二半導體晶片的半導體晶片。本發明的這些和其他方面，將在下文中詳細闡述。
參照第1圖和第3圖，本發明的一個實施例含有一個多晶片封裝30，其中提出了MOSFET開關電路10。因此，採用第一28和第二32半導體晶片。半導體封裝30的結構如圖中虛線所示。第二半導體晶片32貼在一個外殼的晶片焊接墊34（圖中沒有表示出），以及引腳36-39和41-44上。半導體晶片32含有一個帶有柵極、漏極和源極區（圖中沒有表示出）的MOSFET，每個柵極、漏極和源極區都含有一個接頭，用於定義柵極接頭50、漏極接頭（在其底面上，圖中沒有表示出）以及源極接頭46。 漏極接頭設置在半導體晶片32的與表面54相對的表面（圖中沒有表示出）上， 柵極接頭50和源極接頭46位於表面54上。通過焊接墊34，獲得半導體晶片32的漏極電連接。在這種封裝類型中，儘管一個焊接墊裸露在封裝的底部，但是焊接墊34可以單獨作為一個引腳。因此，使用導電粘合劑（圖中沒有表示出），例如焊錫、導電環氧樹脂、低共溶合金等，將半導體晶片32固定在焊接墊34上。通過任何已知的電連接技術，包括：夾片、電鍍、色帶以及類似的方式，將源極接頭46與引腳42-44電連接起來。在本例中，利用鋁、金、銅等類似的材料，進行引線接合。通過引線接合，將柵極接頭50與引腳41電連接起來。不用引線接合的話，也可選用其他合適的互聯方式，例如夾片、電鍍或導電色帶等。
第一半導體晶片28與第二半導體晶片32迭印，利用非導電附著襯底（圖中沒有表示出），例如非導電環氧樹脂，連接在一起構成晶片堆疊55。第一半導體晶片28含有一個帶有柵極、漏極和源極區域（圖中沒有表示出）的MOSFET，每個區域都含有一個接頭，定義柵極接頭56、漏極接頭58和源極接頭60。柵極接頭56、漏極接頭58、和源極接頭60設置在第一半導體晶片28的公共面62上，第一半導體晶片28朝向離第二半導體晶片32很遠的地方。第二半導體晶片32在第一半導體晶片28上方的區域連接在一起，並與柵極接頭50和源極接頭46的焊接區分隔開，以便於在此處放置接合線。因此，第二半導體晶片32的晶片面積，大於第一半導體晶片28的晶片面積。通過在焊接墊34和源極接頭60之間延伸的接合引線，將源極接頭60與第二半導體晶片32的漏極接頭（圖中沒有表示出），電連接在一起。利用接合引線，漏極接頭58與引腳36-38電連接在一起，柵極接頭56與引腳39電連接在一起。將第一半導體晶片28和第二半導體晶片32迭印在一起，使晶片面積達到最大。
半導體晶片28和32保護多種MOSFET，例如雙N-溝道、雙P-溝道或極性互補。在實際應用中，MOSFET晶片的參數可能相同或不同，對於高端和低端切換，可以優化這些參數。第二半導體晶片32還包括一個集成肖特基整流器，以便進一步提高性能。晶片堆疊55可以封裝在各種塑膠模具（圖中沒有表示出）中，並同各種引線框一起使用，用於製備含有D-PAK、D2-Pak、多引腳TO-220、DFN或其他任何封裝結構的傳統封裝。堆積式晶片結構，無疑使同樣的半導體封裝尺寸中，可以容納更大的晶片面積，而且Rdson也更低。同樣的封裝引腳面積，可以獲得更低的Rdson。也可選用較小的封裝，來獲得同樣的或更好的Rdson。
參照第4圖和第5圖，在一個可選實施例中，多晶片封裝130包括第一半導體晶片128和第二半導體晶片32。如上所述，第二半導體晶片32附著在晶片焊接墊34上。更確切地說，利用導電粘合劑（圖中沒有表示出），將第二半導體晶片32固定在含有多個引腳35-44的外殼（圖中沒有表示出）的焊接墊34上。半導體晶片32包括一個具有柵極、漏極和源極區域（圖中沒有表示出）的MOSFET，每個區域都含有一個接頭，定義柵極接頭50、漏極接頭48以及源極接頭46。漏極接頭48設置在半導體晶片32的表面52上，柵極接頭50和源極接頭46位於表面54上，表面54位於表面52的對面。通過焊接墊34，獲得引腳35/40和漏極48之間的電接觸。利用鋁、金、銅等類似的材料，進行引線接合，通過引線接合，將源極接頭46與引腳42-44電連接起來。通過引線接合，將柵極接頭50與引腳41電連接起來。
第一半導體晶片128與第二半導體晶片32迭印，利用導電粘合劑（圖中沒有表示出），連接在一起構成晶片堆疊155。第一半導體晶片128含有一個帶有柵極、漏極和源極區域（圖中沒有表示出）的MOSFET，每個區域都含有一個相應的接頭，定義柵極接頭156、漏極接頭158和源極接頭160。漏極接頭158設置在半導體晶片128的表面上，柵極接頭156和源極接頭160位於其對面的表面上。漏極接頭158面對著第二半導體晶片32，並與源極接頭46迭印在一起。通過設置在源極接頭46上方的鈍化層129，漏極接頭158與源極接頭46絕緣。鈍化層129所用的鈍化材料應該能夠承受第一半導體晶片128的漏極，與第二半導體晶片32的源極之間的電壓差。為了便於引腳36-38和漏極接頭158之間的電傳導，半導體晶片32還具有一個導電材料層131（例如一個浮動金屬層），位於鈍化層129上方。
確定層131的尺寸，使第一半導體晶片128與層131的子部分迭印，剩餘區域133不與第一半導體晶片128迭印，第一半導體晶片128的尺寸適合於引線接合。因此，層131不僅可以作為第一半導體晶片128的底部電極（例如漏極接頭158）的晶片墊，還可以作為導電互聯的焊接墊，就像接合線一樣連接在底部電極上，同時與第二半導體晶片32絕緣。第4圖的剖面圖中沒有表示出接合線，以免產生混淆。柵極接頭50和源極接頭46的上方，可以選用一層導電材料（圖中沒有表示出），使接頭區域的頂部與導電層131頂部共面，以便更輕鬆地接觸柵極和源極。按照第3圖所示的方式，柵極接頭156通過柵極接頭56，與引腳39電接觸，源極接頭160通過源極接頭60，與晶片墊34電接觸。多晶片封裝130不僅具有第3圖所示的多晶片封裝30的優點，例如較大的晶片面積，較小的Rdson。而且，多晶片封裝130還具有另一優點：利用標準的垂直MOSFET，製備高端MOSFET128和低端32MOSFET，源極和柵極位於上方，漏極位於下方。
參照第6圖，在某些特殊情況下，除去源極接頭46與區域133中有引線接合的135部分迭印的那部分，必定是十分有利的。我們發現，用某種金屬製作源極接頭46，鈍化層129的結構完整性將受到損壞和開裂，導致層131和源極接頭46之間短接。如果製備源極接頭46的金屬為易於成型的軟材料，例如鋁等，層131上的引線接合過程中產生的力，直接作用在源極接頭46上，會引起中間的鈍化層開裂。如果實在無法避免上述問題，那麼為了減少上述問題，層131上的引線接合發生在層131的135部分中，沒有源極金屬46直接位於層131的135部分下方。為引線接合，留出一部分上方不帶有源極金屬46的第二半導體晶片32，可能會犧牲一小部分的有源區，但也會使半導體封裝更加穩固，並獲得更高的成品率。
參照第7圖，本發明的一種應用方式是，像電路215一樣，用於配置一對並聯的MOSFET114和214。但是可以配置一對MOSFET 314和414，使每一個都連接到公共負載上，如第8圖所示的全橋式電路415。如第9圖所示，利用本應用中所述的兩個晶片堆疊，可以配置電路215或415作為封裝500，分別如第7圖和第8圖所示。引腳Vcc/DA1 和Vcc/DB1 可以從封裝500的外部連接在一起。
上述說明僅用於舉例說明本發明，各種沒有背離本發明意圖和範圍的修正，都不應認為是本發明範圍的局限。例如，高端和低端MOSFET可以使用薄晶圓，以保持很小的封裝厚度。因此，本發明的範圍應由所附的權利要求書及其等價內容的完整範圍所決定。
10‧‧‧開關電路
12、14、114、214、314、414‧‧‧MOSFET
16、18‧‧‧晶片墊
28、128‧‧‧第一半導體晶片
30‧‧‧半導體封裝
32‧‧‧第二半導體晶片
34‧‧‧焊接墊
35、36、37、38、39‧‧‧引腳
40、41、42、43、44‧‧‧引腳
46、60、160‧‧‧源極接頭
48‧‧‧漏極
50、56、156‧‧‧柵極接頭
52、54‧‧‧表面
55、155‧‧‧晶片堆疊
58、158‧‧‧漏極接頭
62‧‧‧公共面
129‧‧‧鈍化層
130‧‧‧多晶片封裝
131、135‧‧‧層
133‧‧‧區域
215‧‧‧電路
415‧‧‧全橋式電路
500‧‧‧封裝
D1、D2‧‧‧漏極
G1、G2‧‧‧柵極
S1、S2‧‧‧源極
Vcc/DA1、Vcc/DB1‧‧‧引腳
第1圖表示依據原有技術的MOSFET開關電路的示意圖；
第2圖表示依據原有技術的一種多晶片封裝的俯視圖；
第3圖表示依據本發明的一個實施例，一種多晶片封裝的俯視圖；
第4圖表示依據本發明的第二實施例，一種多晶片封裝的俯視圖；
第5圖表示第4圖所示的多晶片封裝沿5-5線的剖面圖；
第6圖表示依據本發明的一個可選實施例，第5圖所示的多晶片封裝的剖面圖；
第7圖表示利用本發明所製備的電路的電路原理圖；
第8圖表示利用本發明所製備的完整橋式電路的電路原理圖；以及
第9圖表示依據本發明的另一個實施例，用於製備第7圖和第8圖所示的電路的多晶片封裝的俯視圖。
28‧‧‧第一半導體晶片
30‧‧‧半導體封裝
32‧‧‧第二半導體晶片
34‧‧‧焊接墊
35、36、37、38、39‧‧‧引腳
41、42、43、44‧‧‧引腳
46、60‧‧‧源極接頭
50、56‧‧‧柵極接頭
54‧‧‧表面
55‧‧‧晶片堆疊
58‧‧‧漏極接頭
62‧‧‧公共面

Claims (20)

  1. 一種含有多個引腳的多晶片封裝，包括：
    第一和第二半導體晶片，迭印並連接在一起，定義一個具有對立的第一和第二邊的晶片堆疊，每個所述的第一和第二半導體晶片都有柵極、漏極和源極區域，以及柵極、漏極和源極接頭，所述的第一對立邊具有所述的第二半導體晶片的所述的漏極接頭，所述的漏極接頭與第一套所述的多個引腳電接觸，所述的第一半導體晶片的所述的柵極、漏極和源極接頭，與所述的第二半導體晶片的柵極和源極接頭設置在所述的第二個對立邊上，並與第二套所述的多個引腳電接觸，其中所述的第一半導體晶片的源極接頭與所述的第二半導體晶片的漏極接頭電接觸。
  2. 如申請專利範圍第1項所述的封裝，其中所述的第二邊包括第一和第二隔開的表面，所述的第一表面包括一個設置在所述的第二半導體晶片上方的導電金屬層，所述的第一半導體晶片的漏極接頭面對著所述的第一表面，並接觸所述的導電金屬層，絕緣材料在所述的第二半導體晶片和所述的導電金屬層之間延伸，並使所述的第二半導體晶片與所述的導電金屬層絕緣。
  3. 如申請專利範圍第1項所述的封裝，其中所述的第二邊包括第一和第二隔開的表面，所述的第一表面包括一個設置在所述的第二半導體晶片上方的導電金屬層，所述的第一半導體晶片的漏極接頭與所述的導電金屬層的第一部分迭印並接觸，所述的導電金屬層的第二部分與所述的第一部分並排在一起，絕緣材料在所述的第二半導體晶片和所述的導電金屬層之間延伸，其中所述的第二部分作為導電互聯的焊接墊。
  4. 如申請專利範圍第1項所述的封裝，其中所述的第二邊包括所述的第二半導體晶片的一個表面，以及所述的第一半導體晶片的第一表面，背離所述的第二半導體晶片的所述的表面，所述的第一半導體晶片的柵極、漏極和源極接頭位於所述的第一半導體晶片的所述的第一表面中，其中所述的第一半導體晶片不導電地附著在第二半導體晶片所述的表面上。
  5. 如申請專利範圍第1項所述的封裝，其中所述的第二半導體晶片的面積大於所述的第一半導體晶片的面積。
  6. 一種晶片堆疊，包括：
    一個底部晶片；
    一個堆積在底部晶片上的頂部晶片；以及
    一個設置在底部晶片上的浮動金屬層，通過絕緣材料，浮動金屬層與底部晶片絕緣，其中浮動金屬層不僅作為頂部晶片的導電晶片墊，還作為導電互聯的焊接墊。
  7. 如申請專利範圍第6項所述的晶片堆疊，其中底部晶片和頂部晶片均為分立的半導體器。
  8. 如申請專利範圍第7項所述的晶片堆疊，其中底部晶片為一個頂端具有源極、底端具有漏極的第一MOSFET，其中浮動金屬層通過絕緣材料，與所述的第一MOSFET所述的源極絕緣，頂部晶片為一個一側設置源極、另一個側設置漏極的第二MOSFET，並且所述第二MOSFET漏極與所述的浮動金屬層接觸。
  9. 如申請專利範圍第8項所述的晶片堆疊，還包括一個引線框晶片墊，其中底部晶片的漏極附著在引線框晶片墊上，頂部晶片的源極通過導電互聯，連接到所述的引線框晶片墊上。
  10. 如申請專利範圍第9項所述的晶片堆疊，還包括引線框引腳；以及
    第一套導電互聯，連接在所述的浮動導電層的焊接墊部分和所述的第一套引線框引腳之間。
  11. 如申請專利範圍第10項所述的晶片堆疊，其中所述的底部晶片為低端MOSFET，所述的頂部晶片為高端MOSFET。
  12. 如申請專利範圍第7項所述的晶片堆疊，還包括在底部晶片上方、絕緣材料和一部分浮動金屬下方的頂部金屬，其中源極金屬並不在浮動金屬層的焊接墊部分下方。
  13. 一種半導體封裝，包括：
    第一和第二晶片堆疊，每個堆疊都含有一個底部晶片，一個頂部晶片；以及
    一個設置在底部晶片上的浮動金屬層，通過絕緣材料，浮動金屬層與底部晶片絕緣，其中浮動金屬層不僅作為頂部晶片的導電晶片墊，還作為導電互聯的焊接墊，並且其中所述的底部晶片為低端MOSFET，所述的頂部晶片為高端MOSFET。
  14. 如申請專利範圍第13項所述的封裝，其中第一和第二晶片堆疊並聯在一起。
  15. 如申請專利範圍第13項所述的封裝，其中第一和第二晶片堆疊構成一個全橋式電路。
  16. 一種堆積兩個分立晶片的方法，包括：
    在底部晶片上方製備一個浮動金屬層，通過絕緣材料，浮動金屬層與底部晶片電絕緣；
    將頂部晶片的底部導電連接到浮動金屬層；並且
    利用浮動金屬層，從頂部晶片的底部引出一個連接。
  17. 如申請專利範圍第16項所述的方法，其中分立的半導體器件為MOSFET。
  18. 如申請專利範圍第16項所述的方法，其中底部晶片為一個頂端具有源極、底端具有漏極的第一MOSFET，其中浮動金屬層通過絕緣材料，與所述的第一MOSFET所述的源極絕緣，其中頂部晶片為一個頂端設置源極接頭、底端設置漏極接頭的第二MOSFET，所述的第二MOSFET的所述漏極接頭附著到所述的浮動金屬層上。
  19. 如申請專利範圍第16項所述的方法，還包括將源極接頭置於底部晶片上方，使其位於絕緣材料和浮動金屬層的第一部分下方，但不在用於焊接導電互聯的一部分浮動金屬層下方。
  20. 如申請專利範圍第18項所述的方法，其中底部晶片為低端MOSFET，頂部晶片為高端MOSFET。
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