CN102655140A - 多晶片封装 - Google Patents

多晶片封装 Download PDF

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Publication number
CN102655140A
CN102655140A CN2012101853341A CN201210185334A CN102655140A CN 102655140 A CN102655140 A CN 102655140A CN 2012101853341 A CN2012101853341 A CN 2012101853341A CN 201210185334 A CN201210185334 A CN 201210185334A CN 102655140 A CN102655140 A CN 102655140A
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Prior art keywords
wafer
mosfet
metal level
drain electrode
unsteady
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CN2012101853341A
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CN102655140B (zh
Inventor
安荷·叭剌
苏毅
大卫·格雷
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Alpha and Omega Semiconductor Cayman Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种多晶片封装，具有多个引脚以及第一和第二半导体晶片，叠印并连接在一起，定义一个晶片堆叠。晶片堆叠具有相对的第一和第二边，每个第一和第二半导体晶片都带有栅极、漏极和源极区，以及栅极、漏极和源极接头。第一个对立边具有第二半导体晶片的漏极接头，漏极接头与第一套多个引脚电接触。第一半导体晶片的栅极、漏极和源极接头以及第二半导体晶片的栅极和源极接头，设置在第二个所述的对立边上，并与第二套多个引脚电接触。第一半导体晶片的源极引脚可以与第二半导体晶片的漏极引脚相同。

Description

多晶片封装
技术领域
本发明主要涉及半导体封装，更确切地说，是关于半导体封装以及制作半导体封装的方法。
背景技术
在许多MOSFET开关电路中，经常以互补的方式切换一对功率MOSFET。一种典型的MOSFET开关电路如图1所示，它包括两个MOSFET--12和14，通过电压源V输入和接地端，串联在一起。MOSFET12和14分别代表高端和低端MOSFET。
为了开启开关循环，首先要关闭MOSFET14。因此，MOSFET14的体二极管开启，并驱动电流。延迟后，MOSFET12开启，关闭MOSFET的体二极管。从而产生恢复电流IL，以及与开关电路10有关的追踪电感（没有表示出来）、产生振荡。
为了节省空间和成本，常常把MOSFET12和14封装在一起，如图中虚线所示。MOSFET12和14的目的在于获得最高的功率密度，以便高效地工作。功率密度与晶片面积密切相关，也就是说，晶片越大，漏极至源极导通电阻Rdson越低。如图2所示，其特点在于，MOSFET12和14在独立的晶片垫上，共同封装在一起。整体的封装结构如虚线中所示。传统的功率MOSFET 12和14为垂直器件，源极S1和S2、栅极G1和G2分别位于一侧，漏极D1和D2分别位于另一侧。MOSFET 12贴在晶片垫16上，其引脚继续延伸，可以连接到漏极D1上。MOSFET 14贴在晶片垫18上。低端晶片垫通过双侧无引脚扁平（DFN）封装的底部，裸露在外，以便外部连接到漏极D2和源极S1上。由于MOSFET 14通常开启较长的持续时间，因此与高端MOSFET 14相比，低端MOSFET 14的特点是具有较大的晶片面积。源极S1通过导线从S1到晶片垫18，连接到漏极D2上。栅极G1和G2以及源极S2通过导线，连接到合适的引脚上。MOSFET 12和14的晶片面积受到封装尺寸以及晶片共同封装结构的约束。
因此，必须通过最大化MOSFET的晶片面积，来改善使用性能，使Rdson最小，而且不额外地增加电路的总尺寸。
发明内容
本发明的一种含有多个引脚的多晶片封装，包括：
第一和第二半导体晶片，叠印并连接在一起，定义一个具有对立的第一和第二边的晶片堆叠，每个所述的第一和第二半导体晶片都有栅极、漏极和源极区域，以及栅极、漏极和源极接头，所述的第一对立边具有所述的第二半导体晶片的所述的漏极接头，所述的漏极接头与第一套所述的多个引脚电接触，所述的第一半导体晶片的所述的栅极、漏极和源极接头，与所述的第二半导体晶片的栅极和源极接头设置在所述的第二个对立边上，并与第二套所述的多个引脚电接触，其中所述的第一半导体晶片的源极接头与所述的第二半导体晶片的漏极接头电接触。
上述的封装，所述的第二边包括第一和第二隔开的表面，所述的第一表面包括一个设置在所述的第二半导体晶片上方的导电金属层，所述的第一半导体晶片的漏极接头面对着所述的第一表面，并接触所述的导电金属层，绝缘材料在所述的第二半导体晶片和所述的导电金属层之间延伸，并使所述的第二半导体晶片与所述的导电金属层绝缘。
上述的封装，所述的第二边包括第一和第二隔开的表面，所述的第一表面包括一个设置在所述的第二半导体晶片上方的导电金属层，所述的第一半导体晶片的漏极接头与所述的导电金属层的第一部分叠印并接触，所述的导电金属层的第二部分与所述的第一部分并排在一起，绝缘材料在所述的第二半导体晶片和所述的导电金属层之间延伸，其中所述的第二部分作为导电互联的焊接垫。
上述的封装，所述的第二边包括所述的第二半导体晶片的一个表面，以及所述的第一半导体晶片的第一表面，背离所述的第二半导体晶片的所述的表面，所述的第一半导体晶片的栅极、漏极和源极接头位于所述的第一半导体晶片的所述的第一表面中，其中所述的第一半导体晶片不导电地附着在第二半导体晶片所述的表面上。
上述的封装，所述的第二半导体晶片的面积大于所述的第一半导体晶片的面积。
本发明的一种晶片堆叠，包括：
一个底部晶片；
一个堆积在底部晶片上的顶部晶片；以及
一个设置在底部晶片上的浮动金属层，通过绝缘材料，浮动金属层与底部晶片绝缘，其中浮动金属层不仅作为顶部晶片的导电晶片垫，还作为导电互联的焊接垫。
上述的晶片堆叠，底部晶片和顶部晶片均为分立的半导体器。
上述的晶片堆叠，底部晶片为一个顶端具有源极、底端具有漏极的第一MOSFET，其中浮动金属层通过绝缘材料，与所述的第一MOSFET所述的源极绝缘，顶部晶片为一个一侧设置源极、另一个侧设置漏极的第二MOSFET，并且所述第二MOSFET漏极与所述的浮动金属层接触。
上述的晶片堆叠，还包括一个引线框晶片垫，其中底部晶片的漏极附着在引线框晶片垫上，顶部晶片的源极通过导电互联，连接到所述的引线框晶片垫上。
上述的晶片堆叠，还包括引线框引脚；以及
第一套导电互联，连接在所述的浮动导电层的焊接垫部分和所述的第一套引线框引脚之间。
上述的晶片堆叠，所述的底部晶片为低端MOSFET，所述的顶部晶片为高端MOSFET。
上述的晶片堆叠，还包括在底部晶片上方、绝缘材料和一部分浮动金属下方的顶部金属，其中源极金属并不在浮动金属层的焊接垫部分下方。
本发明的一种半导体封装，包括：
第一和第二晶片堆叠，每个堆叠都含有一个底部晶片，一个顶部晶片；以及
一个设置在底部晶片上的浮动金属层，通过绝缘材料，浮动金属层与底部晶片绝缘，其中浮动金属层不仅作为顶部晶片的导电晶片垫，还作为导电互联的焊接垫，并且其中所述的底部晶片为低端MOSFET，所述的顶部晶片为高端MOSFET。
上述的封装，第一和第二晶片堆叠并联在一起。
上述的封装，第一和第二晶片堆叠构成一个全桥式电路。
本发明的一种堆积两个分立晶片的方法，包括：
在底部晶片上方制备一个浮动金属层，通过绝缘材料，浮动金属层与底部晶片电绝缘；
将顶部晶片的底部导电连接到浮动金属层；并且
利用浮动金属层，从顶部晶片的底部引出一个连接。
上述的方法，分立的半导体器件为MOSFET。
上述的方法，底部晶片为一个顶端具有源极、底端具有漏极的第一MOSFET，其中浮动金属层通过绝缘材料，与所述的第一MOSFET所述的源极绝缘，其中顶部晶片为一个顶端设置源极接头、底端设置漏极接头的第二MOSFET，所述的第二MOSFET的所述漏极接头附着到所述的浮动金属层上。
上述的方法，还包括将源极接头置于底部晶片上方，使其位于绝缘材料和浮动金属层的第一部分下方，但不在用于焊接导电互联的一部分浮动金属层下方。
上述的方法，底部晶片为低端MOSFET，顶部晶片为高端MOSFET。
依照本发明的一个方面，一种多晶片封装，具有多个引脚，并由叠印和焊接在一起的第一和第二半导体晶片构成，定义一个晶片堆叠。晶片堆叠具有相对的第一和第二个边，每个第一和第二半导体晶片都具有栅极、漏极和源极区域，以及栅极、漏极和源极接头。第一个对边上有第二半导体晶片的漏极接头，漏极接头与第一套多个引脚电接触。第一半导体晶片的栅极、漏极和源极接头，以及第二半导体晶片的栅极和源极接头，设置在第二对边上，以出现在不同平面中，与第二套多个引脚电接触。依靠这种结构，无需额外的增加电路的总尺寸，第一和第二半导体晶片的晶片面积就可以达到最大化。依据本发明的另一个实施例，可以在第一和第二半导体晶片的其中一个晶片上，设置一个浮动金属层，作为晶片垫和焊接垫，用于剩余的第一和第二半导体晶片的半导体晶片。本发明的这些和其他方面，将在下文中详细阐述。
附图说明
图1表示依据原有技术的MOSFET开关电路的示意图；
图2表示依据原有技术的一种多芯片封装的俯视图；
图3表示依据本发明的一个实施例，一种多芯片封装的俯视图；
图4表示依据本发明的第二实施例，一种多芯片封装的俯视图；
图5表示图4所示的多芯片封装沿5-5线的剖面图；
图6表示依据本发明的一个可选实施例，图5所示的多芯片封装的剖面图；
图7表示利用本发明所制备的电路的电路原理图；
图8表示利用本发明所制备的完整桥式电路的电路原理图；以及
图9表示依据本发明的另一个实施例，用于制备图7和图8所示的电路的多芯片封装的俯视图。
具体实施方式
参照图1和图3，本发明的一个实施例含有一个多晶片封装30，其中提出了MOSFET开关电路10。因此，采用第一28和第二32半导体晶片。半导体封装30的结构如图中虚线所示。第二半导体晶片32贴在一个外壳的晶片焊接垫34（图中没有表示出），以及引脚36-39和41-44上。半导体晶片32含有一个带有栅极、漏极和源极区（图中没有表示出）的MOSFET，每个栅极、漏极和源极区都含有一个接头，用于定义栅极接头50、漏极接头（在其底面上，图中没有表示出）以及源极接头46。 漏极接头设置在半导体晶片32的与表面54相对的表面（图中没有表示出）上， 栅极接头50和源极接头46位于表面54上。通过焊接垫34，获得半导体晶片32的漏极电连接。在这种封装类型中，尽管一个焊接垫裸露在封装的底部，但是焊接垫34可以单独作为一个引脚。因此，使用导电粘合剂（图中没有表示出），例如焊锡、导电环氧树脂、低共溶合金等，将半导体晶片32固定在焊接垫34上。通过任何已知的电连接技术，包括：夹片、电镀、色带以及类似的方式，将源极接头46与引脚42-44电连接起来。在本例中，利用铝、金、铜等类似的材料，进行引线接合。通过引线接合，将栅极接头50与引脚41电连接起来。不用引线接合的话，也可选用其他合适的互联方式，例如夹片、电镀或导电色带等。
第一半导体晶片28与第二半导体晶片32叠印，利用非导电附着衬底（图中没有表示出），例如非导电环氧树脂，连接在一起构成晶片堆叠55。第一半导体晶片28含有一个带有栅极、漏极和源极区域（图中没有表示出）的MOSFET，每个区域都含有一个接头，定义栅极接头56、漏极接头58和源极接头60。栅极接头56、漏极接头58、和源极接头60设置在第一半导体晶片28的公共面62上，第一半导体晶片28朝向离第二半导体晶片32很远的地方。第二半导体晶片32在第一半导体晶片28上方的区域连接在一起，并与栅极接头50和源极接头46的焊接区分隔开，以便于在此处放置接合线。因此，第二半导体晶片32的晶片面积，大于第一半导体晶片28的晶片面积。通过在焊接垫34和源极接头60之间延伸的接合引线，将源极接头60与第二半导体晶片32的漏极接头（图中没有表示出），电连接在一起。利用接合引线，漏极接头58与引脚36-38电连接在一起，栅极接头56与引脚39电连接在一起。将第一半导体晶片28和第二半导体晶片32叠印在一起，使晶片面积达到最大。
半导体晶片28和32保护多种MOSFET，例如双N-沟道、双P-沟道或极性互补。在实际应用中，MOSFET晶片的参数可能相同或不同，对于高端和低端切换，可以优化这些参数。第二半导体晶片32还包括一个集成肖特基整流器，以便进一步提高性能。晶片堆叠55可以封装在各种塑料模具（图中没有表示出）中，并同各种引线框一起使用，用于制备含有D-PAK、D2-Pak、多引脚TO-220、DFN或其他任何封装结构的传统封装。堆积式晶片结构，无疑使同样的半导体封装尺寸中，可以容纳更大的晶片面积，而且Rdson也更低。同样的封装引脚面积，可以获得更低的Rdson。也可选用较小的封装，来获得同样的或更好的Rdson。
参照图4和图5，在一个可选实施例中，多晶片封装130包括第一半导体晶片128和第二半导体晶片32。如上所述，第二半导体晶片32附着在晶片焊接垫34上。更确切地说，利用导电粘合剂（图中没有表示出），将第二半导体晶片32固定在含有多个引脚35-44的外壳（图中没有表示出）的焊接垫34上。半导体晶片32包括一个具有栅极、漏极和源极区域（图中没有表示出）的MOSFET，每个区域都含有一个接头，定义栅极接头50、漏极接头48以及源极接头46。漏极接头48设置在半导体晶片32的表面52上，栅极接头50和源极接头46位于表面54上，表面54位于表面52的对面。通过焊接垫34，获得引脚35/40和漏极48之间的电接触。利用铝、金、铜等类似的材料，进行引线接合，通过引线接合，将源极接头46与引脚42-44电连接起来。通过引线接合，将栅极接头50与引脚41电连接起来。
第一半导体晶片128与第二半导体晶片32叠印，利用导电粘合剂（图中没有表示出），连接在一起构成晶片堆叠155。第一半导体晶片128含有一个带有栅极、漏极和源极区域（图中没有表示出）的MOSFET，每个区域都含有一个相应的接头，定义栅极接头156、漏极接头158和源极接头160。漏极接头158设置在半导体晶片128的表面上，栅极接头156和源极接头160位于其对面的表面上。漏极接头158面对着第二半导体晶片32，并与源极接头46叠印在一起。通过设置在源极接头46上方的钝化层129，漏极接头158与源极接头46绝缘。钝化层129所用的钝化材料应该能够承受第一半导体晶片128的漏极，与第二半导体晶片32的源极之间的电压差。为了便于引脚36-38和漏极接头158之间的电传导，半导体晶片32还具有一个导电材料层131（例如一个浮动金属层），位于钝化层129上方。
确定层131的尺寸，使第一半导体晶片128与层131的子部分叠印，剩余区域133不与第一半导体晶片128叠印，第一半导体晶片128的尺寸适合于引线接合。因此，层131不仅可以作为第一半导体晶片128的底部电极（例如漏极接头158）的晶片垫，还可以作为导电互联的焊接垫，就像接合线一样连接在底部电极上，同时与第二半导体晶片32绝缘。图4的剖面图中没有表示出接合线，以免产生混淆。栅极接头50和源极接头46的上方，可以选用一层导电材料（图中没有表示出），使接头区域的顶部与导电层131顶部共面，以便更轻松地接触栅极和源极。按照图3所示的方式，栅极接头156通过栅极接头56，与引脚39电接触，源极接头160通过源极接头60，与晶片垫34电接触。多晶片封装130不仅具有图3所示的多晶片封装30的优点，例如较大的晶片面积，较小的Rdson。而且，多晶片封装130还具有另一优点：利用标准的垂直MOSFET，制备高端MOSFET128和低端32MOSFET，源极和栅极位于上方，漏极位于下方。
参照图6，在某些特殊情况下，除去源极接头46与区域133中有引线接合的135部分叠印的那部分，必定是十分有利的。我们发现，用某种金属制作源极接头46，钝化层129的结构完整性将受到损坏和开裂，导致层131和源极接头46之间短接。如果制备源极接头46的金属为易于成型的软材料，例如铝等，层131上的引线接合过程中产生的力，直接作用在源极接头46上，会引起中间的钝化层开裂。如果实在无法避免上述问题，那么为了减少上述问题，层131上的引线接合发生在层131的135部分中，没有源极金属46直接位于层131的135部分下方。为引线接合，留出一部分上方不带有源极金属46的第二半导体晶片32，可能会牺牲一小部分的有源区，但也会使半导体封装更加稳固，并获得更高的成品率。
参照图7，本发明的一种应用方式是，像电路215一样，用于配置一对并联的MOSFET114和214。但是可以配置一对MOSFET 314和414，使每一个都连接到公共负载上，如图8所示的全桥式电路415。如图9所示，利用本应用中所述的两个晶片堆叠，可以配置电路215或415作为封装500，分别如图7和图8所示。引脚Vcc/DA1和Vcc/DB1可以从封装500的外部连接在一起。
上述说明仅用于举例说明本发明，各种没有背离本发明意图和范围的修正，都不应认为是本发明范围的局限。例如，高端和低端MOSFET可以使用薄晶圆，以保持很小的封装厚度。因此，本发明的范围应由所附的权利要求书及其等价内容的完整范围所决定。

Claims (15)

1.一种晶片堆叠，其特征在于，包括：
一个底部晶片；
一个堆积在底部晶片上的顶部晶片；以及
一个设置在底部晶片上的浮动金属层，通过绝缘材料，浮动金属层与底部晶片绝缘，其中浮动金属层不仅作为顶部晶片的导电晶片垫，还作为导电互联的焊接垫。
2.如权利要求1所述的晶片堆叠，其特征在于，底部晶片和顶部晶片均为分立的半导体器。
3.如权利要求2所述的晶片堆叠，其特征在于，底部晶片为一个顶端具有源极、底端具有漏极的第一MOSFET，其中浮动金属层通过绝缘材料，与所述的第一MOSFET所述的源极绝缘，顶部晶片为一个一侧设置源极、另一个侧设置漏极的第二MOSFET，并且所述第二MOSFET漏极与所述的浮动金属层接触。
4.如权利要求3所述的晶片堆叠，其特征在于，还包括一个引线框晶片垫，其中底部晶片的漏极附着在引线框晶片垫上，顶部晶片的源极通过导电互联，连接到所述的引线框晶片垫上。
5.如权利要求4所述的晶片堆叠，其特征在于，还包括引线框引脚；以及
第一套导电互联，连接在所述的浮动导电层的焊接垫部分和所述的第一套引线框引脚之间。
6.如权利要求5所述的晶片堆叠，其特征在于，所述的底部晶片为低端MOSFET，所述的顶部晶片为高端MOSFET。
7.如权利要求2所述的晶片堆叠，其特征在于，还包括在底部晶片上方、绝缘材料和一部分浮动金属下方的顶部金属，其中源极金属并不在浮动金属层的焊接垫部分下方。
8.一种半导体封装，其特征在于，包括：
第一和第二晶片堆叠，每个堆叠都含有一个底部晶片，一个顶部晶片；以及
一个设置在底部晶片上的浮动金属层，通过绝缘材料，浮动金属层与底部晶片绝缘，其中浮动金属层不仅作为顶部晶片的导电晶片垫，还作为导电互联的焊接垫，并且其中所述的底部晶片为低端MOSFET，所述的顶部晶片为高端MOSFET。
9.如权利要求8所述的封装，其特征在于，第一和第二晶片堆叠并联在一起。
10.如权利要求8所述的封装，其特征在于，第一和第二晶片堆叠构成一个全桥式电路。
11.一种堆积两个分立晶片的方法，其特征在于，包括：
在底部晶片上方制备一个浮动金属层，通过绝缘材料，浮动金属层与底部晶片电绝缘；
将顶部晶片的底部导电连接到浮动金属层；并且
利用浮动金属层，从顶部晶片的底部引出一个连接。
12.如权利要求11所述的方法，其特征在于，分立的半导体器件为MOSFET。
13.如权利要求11所述的方法，其特征在于，底部晶片为一个顶端具有源极、底端具有漏极的第一MOSFET，其中浮动金属层通过绝缘材料，与所述的第一MOSFET所述的源极绝缘，其中顶部晶片为一个顶端设置源极接头、底端设置漏极接头的第二MOSFET，所述的第二MOSFET的所述漏极接头附着到所述的浮动金属层上。
14.如权利要求11所述的方法，其特征在于，还包括将源极接头置于底部晶片上方，使其位于绝缘材料和浮动金属层的第一部分下方，但不在用于焊接导电互联的一部分浮动金属层下方。
15.如权利要求13所述的方法，其特征在于，底部晶片为低端MOSFET，顶部晶片为高端MOSFET。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630671A (zh) * 2017-03-23 2018-10-09 罗姆股份有限公司 半导体器件
CN109449090A (zh) * 2018-09-28 2019-03-08 深圳赛意法微电子有限公司 一种超小型微处理器的封装方法

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9257375B2 (en) * 2009-07-31 2016-02-09 Alpha and Omega Semiconductor Inc. Multi-die semiconductor package
US8178954B2 (en) * 2009-07-31 2012-05-15 Alpha & Omega Semiconductor, Inc. Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors
CN102169873B (zh) * 2010-02-25 2013-12-11 万国半导体有限公司 一种应用于功率切换器电路的半导体封装结构
TWI426595B (zh) * 2010-03-01 2014-02-11 Alpha & Omega Semiconductor 一種應用於功率切換器電路的半導體封裝結構
TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
US8896131B2 (en) * 2011-02-03 2014-11-25 Alpha And Omega Semiconductor Incorporated Cascode scheme for improved device switching behavior
US8847408B2 (en) * 2011-03-02 2014-09-30 International Rectifier Corporation III-nitride transistor stacked with FET in a package
US8963338B2 (en) * 2011-03-02 2015-02-24 International Rectifier Corporation III-nitride transistor stacked with diode in a package
TWI469311B (zh) * 2011-04-29 2015-01-11 萬國半導體股份有限公司 聯合封裝的功率半導體元件
US8643176B2 (en) * 2011-07-27 2014-02-04 Infineon Technologies Ag Power semiconductor chip having two metal layers on one face
US8692361B2 (en) * 2012-07-30 2014-04-08 Infineon Technologies Ag Electric device package comprising a laminate and method of making an electric device package comprising a laminate
US9589929B2 (en) 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
EP2973690B1 (en) * 2013-03-14 2020-11-18 Vishay-Siliconix Stack die package
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
US9673170B2 (en) 2014-08-05 2017-06-06 Infineon Technologies Ag Batch process for connecting chips to a carrier
US10886228B2 (en) 2015-12-23 2021-01-05 Intel Corporation Improving size and efficiency of dies
US11328984B2 (en) 2017-12-29 2022-05-10 Texas Instruments Incorporated Multi-die integrated circuit packages and methods of manufacturing the same
CN110120386B (zh) * 2018-02-05 2020-12-18 扬智科技股份有限公司 半导体封装结构
EP3882969B1 (en) * 2020-03-18 2024-05-01 Nexperia B.V. A cascode semiconductor device and method of manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674279A (zh) * 2004-03-24 2005-09-28 三垦电气株式会社 半导体器件
US20070284720A1 (en) * 2006-05-10 2007-12-13 Infineon Technologies Ag Power semiconductor device and method for its production
US20080258277A1 (en) * 2007-04-19 2008-10-23 Infineon Technologies Ag Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5530284A (en) 1995-03-06 1996-06-25 Motorola, Inc. Semiconductor leadframe structure compatible with differing bond wire materials
JPH09312367A (ja) 1996-05-23 1997-12-02 Mitsubishi Electric Corp 高周波半導体装置
DE19635582C1 (de) 1996-09-02 1998-02-19 Siemens Ag Leistungs-Halbleiterbauelement für Brückenschaltungen mit High- bzw. Low-Side-Schaltern
US5814884C1 (en) 1996-10-24 2002-01-29 Int Rectifier Corp Commonly housed diverse semiconductor die
EP0927433B1 (en) 1997-07-19 2005-11-16 Koninklijke Philips Electronics N.V. Semiconductor device assemblies and circuits
US6184585B1 (en) 1997-11-13 2001-02-06 International Rectifier Corp. Co-packaged MOS-gated device and control integrated circuit
US20010019490A1 (en) 1997-12-03 2001-09-06 Fuji Electric Co., Ltd. Switching power supply
US6249041B1 (en) 1998-06-02 2001-06-19 Siliconix Incorporated IC chip package with directly connected leads
US6424035B1 (en) 1998-11-05 2002-07-23 Fairchild Semiconductor Corporation Semiconductor bilateral switch
JP3539549B2 (ja) 1999-09-20 2004-07-07 シャープ株式会社 半導体装置
US6265763B1 (en) 2000-03-14 2001-07-24 Siliconware Precision Industries Co., Ltd. Multi-chip integrated circuit package structure for central pad chip
JP2002217416A (ja) 2001-01-16 2002-08-02 Hitachi Ltd 半導体装置
US6858922B2 (en) 2001-01-19 2005-02-22 International Rectifier Corporation Back-to-back connected power semiconductor device package
US6593622B2 (en) 2001-05-02 2003-07-15 International Rectifier Corporation Power mosfet with integrated drivers in a common package
US7057273B2 (en) 2001-05-15 2006-06-06 Gem Services, Inc. Surface mount package
US7088074B2 (en) 2002-01-02 2006-08-08 International Business Machines Corporation System level device for battery and integrated circuit integration
US6677669B2 (en) 2002-01-18 2004-01-13 International Rectifier Corporation Semiconductor package including two semiconductor die disposed within a common clip
US7183616B2 (en) 2002-03-31 2007-02-27 Alpha & Omega Semiconductor, Ltd. High speed switching MOSFETS using multi-parallel die packages with/without special leadframes
US6841852B2 (en) 2002-07-02 2005-01-11 Leeshawn Luo Integrated circuit package for semiconductor devices with improved electric resistance and inductance
TWI236126B (en) 2002-07-02 2005-07-11 Alpha & Omega Semiconductor Integrated circuit package for semiconductor devices with improved electric resistance and inductance
US6777800B2 (en) 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7215012B2 (en) 2003-01-03 2007-05-08 Gem Services, Inc. Space-efficient package for laterally conducting device
TWI221333B (en) 2003-01-14 2004-09-21 Advanced Semiconductor Eng Bridge connection type of MCM package
KR100541393B1 (ko) 2003-04-26 2006-01-10 삼성전자주식회사 멀티칩 ｂｇａ 패키지
JP4115882B2 (ja) 2003-05-14 2008-07-09 株式会社ルネサステクノロジ 半導体装置
JP2005011986A (ja) 2003-06-19 2005-01-13 Sanyo Electric Co Ltd 半導体装置
DE10333800B3 (de) 2003-07-24 2004-10-28 Infineon Technologies Ag Halbleiterbauteil sowie dafür geeignetes Herstellungsverfahren
US6933593B2 (en) 2003-08-14 2005-08-23 International Rectifier Corporation Power module having a heat sink
JP3789443B2 (ja) 2003-09-01 2006-06-21 Ｎｅｃエレクトロニクス株式会社 樹脂封止型半導体装置
US7250672B2 (en) 2003-11-13 2007-07-31 International Rectifier Corporation Dual semiconductor die package with reverse lead form
WO2005122249A2 (en) 2004-06-03 2005-12-22 International Rectifier Corporation Semiconductor device module with flip chip devices on a common lead frame
US7008820B2 (en) * 2004-06-10 2006-03-07 St Assembly Test Services Ltd. Chip scale package with open substrate
DE102004047306B4 (de) 2004-09-29 2008-02-07 Infineon Technologies Ag Leistungs-Halbleiterbauteil mit mehreren Bauteilkomponenten
US7115985B2 (en) 2004-09-30 2006-10-03 Agere Systems, Inc. Reinforced bond pad for a semiconductor device
WO2006068643A1 (en) * 2004-12-20 2006-06-29 Semiconductor Components Industries, L.L.C. Semiconductor package structure having enhanced thermal dissipation characteristics
US7884454B2 (en) 2005-01-05 2011-02-08 Alpha & Omega Semiconductor, Ltd Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package
US20060145312A1 (en) 2005-01-05 2006-07-06 Kai Liu Dual flat non-leaded semiconductor package
US7898092B2 (en) 2007-11-21 2011-03-01 Alpha & Omega Semiconductor, Stacked-die package for battery power management
US7511361B2 (en) 2005-01-05 2009-03-31 Xiaotian Zhang DFN semiconductor package having reduced electrical resistance
US7612439B2 (en) 2005-12-22 2009-11-03 Alpha And Omega Semiconductor Limited Semiconductor package having improved thermal performance
US7504733B2 (en) 2005-08-17 2009-03-17 Ciclon Semiconductor Device Corp. Semiconductor die package
DE102005039478B4 (de) * 2005-08-18 2007-05-24 Infineon Technologies Ag Leistungshalbleiterbauteil mit Halbleiterchipstapel und Verfahren zur Herstellung desselben
US7838977B2 (en) 2005-09-07 2010-11-23 Alpha & Omega Semiconductor, Ltd. Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers
US7829989B2 (en) 2005-09-07 2010-11-09 Alpha & Omega Semiconductor, Ltd. Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside
US7508012B2 (en) 2006-01-18 2009-03-24 Infineon Technologies Ag Electronic component and method for its assembly
US7291869B2 (en) * 2006-02-06 2007-11-06 Infieon Technologies A.G. Electronic module with stacked semiconductors
US7598603B2 (en) 2006-03-15 2009-10-06 Infineon Technologies Ag Electronic component having a power switch with an anode thereof mounted on a die attach region of a heat sink
TW200812066A (en) * 2006-05-30 2008-03-01 Renesas Tech Corp Semiconductor device and power source unit using the same
US20080111219A1 (en) 2006-11-14 2008-05-15 Gem Services, Inc. Package designs for vertical conduction die
US20080185695A1 (en) * 2007-02-07 2008-08-07 Kim Hong Hyoun Package-on-package device and method for manufacturing the same by using a leadframe
US7776746B2 (en) 2007-02-28 2010-08-17 Alpha And Omega Semiconductor Incorporated Method and apparatus for ultra thin wafer backside processing
DE102007013186B4 (de) 2007-03-15 2020-07-02 Infineon Technologies Ag Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben
US20080242054A1 (en) * 2007-03-29 2008-10-02 Andy Antonelli Dicing and drilling of wafers
US20080242052A1 (en) 2007-03-30 2008-10-02 Tao Feng Method of forming ultra thin chips of power devices
US7868465B2 (en) 2007-06-04 2011-01-11 Infineon Technologies Ag Semiconductor device with a metallic carrier and two semiconductor chips applied to the carrier
KR100826989B1 (ko) 2007-06-20 2008-05-02 주식회사 하이닉스반도체 반도체 패키지 및 그의 제조방법
US8048775B2 (en) 2007-07-20 2011-11-01 Alpha And Omega Semiconductor Incorporated Process of forming ultra thin wafers having an edge support ring
US8097945B2 (en) 2007-11-21 2012-01-17 Lynda Harnden, legal representative Bi-directional, reverse blocking battery switch
US7969018B2 (en) * 2008-07-15 2011-06-28 Infineon Technologies Ag Stacked semiconductor chips with separate encapsulations

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1674279A (zh) * 2004-03-24 2005-09-28 三垦电气株式会社 半导体器件
US20070284720A1 (en) * 2006-05-10 2007-12-13 Infineon Technologies Ag Power semiconductor device and method for its production
US20080258277A1 (en) * 2007-04-19 2008-10-23 Infineon Technologies Ag Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630671A (zh) * 2017-03-23 2018-10-09 罗姆股份有限公司 半导体器件
CN108630671B (zh) * 2017-03-23 2021-09-28 罗姆股份有限公司 半导体器件
CN109449090A (zh) * 2018-09-28 2019-03-08 深圳赛意法微电子有限公司 一种超小型微处理器的封装方法

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US8164199B2 (en) 2012-04-24
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