WO2013064023A1 - 一种形成金属回路的方法 - Google Patents

一种形成金属回路的方法 Download PDF

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WO2013064023A1
WO2013064023A1 PCT/CN2012/083335 CN2012083335W WO2013064023A1 WO 2013064023 A1 WO2013064023 A1 WO 2013064023A1 CN 2012083335 W CN2012083335 W CN 2012083335W WO 2013064023 A1 WO2013064023 A1 WO 2013064023A1
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metal
layer
forming
metal layer
reflective coating
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PCT/CN2012/083335
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French (fr)
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陈亚威
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • the present invention relates to semiconductor fabrication processes, and more particularly to a method of forming a metal loop in an aluminum metal interconnect process.
  • an aluminum metal layer is formed on the surface of the semiconductor device, and then the aluminum metal layer is patterned to etch the desired metal loop.
  • the interface of the metal grains in the metal circuit captures the residue of the photoresist (PR) used in the patterning process, and the residue will induce the metal circuit Produce defects such as metal residues (metal Residue).
  • PR photoresist
  • metal loop defect greatly increases the risk of bridging adjacent metal wires, ultimately leading to failure of device functionality.
  • the prior art In order to suppress the occurrence of defects in the metal circuit, the prior art generally achieves the above object by improving the internal condition of the metal etching chamber. For example, using the method of periodic maintenance of equipment (PM Method), that is, limiting the metal etching during a certain period of time (usually the first few hours) during the PM period, during which the inner wall of the metal etching chamber forms the least amount of polymer, which is insufficient to produce the metal loop defect.
  • PM Method periodic maintenance of equipment
  • this method requires a long cycle time, resulting in a decrease in the yield of a single batch, while also not addressing the root cause of the defects in the metal circuit.
  • the present invention provides a method of forming a metal circuit, comprising: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a metal layer on the insulating layer; Forming an anti-reflective coating on the metal layer; oxidizing the anti-reflective coating; forming a photoresist layer on the surface of the anti-reflective coating, patterning the metal layer, and etching the A metal layer to form a metal loop.
  • the anti-reflective coating is formed using a chemical vapor deposition process or a spin coating process.
  • the material of the anti-reflective coating is polyimide, silicon oxynitride or amorphous silicon.
  • the oxidatively treated oxidant is nitrous oxide.
  • the flow rate of the nitrous oxide is 500-3000 sccm.
  • the temperature of the oxidation treatment is from 330 to 370 °C.
  • the duration of the oxidation treatment is 40-60 s.
  • the insulating layer is a material layer having a low dielectric constant.
  • the material of the metal layer is aluminum.
  • a thin oxide layer is formed on the surface of the anti-reflective coating by forming an anti-reflective coating on the metal layer and oxidizing the anti-reflective coating, thereby making the surface topography of the anti-reflective coating more flat;
  • PR photoresist
  • the probability of trapping the PR residue at the interface of the metal crystal grains can be reduced, and the generation of defects in the metal circuit can be fundamentally suppressed, in the etching apparatus.
  • the metal etching can be performed at any time period in the PM cycle.
  • FIGS. 1A-1D are schematic cross-sectional views showing respective steps of a method of forming a metal circuit according to the present invention.
  • FIG. 2 is a flow chart of a method of forming a metal loop proposed by the present invention.
  • FIGS. 1A-1D there are shown schematic cross-sectional views of various steps of a method of forming a metal loop proposed by the present invention.
  • a semiconductor substrate 100 is provided.
  • the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), or the like.
  • the semiconductor substrate 100 is formed of a single crystal silicon material. Isolation trenches, buried layers, and various well structures are formed in the semiconductor substrate 100, and are omitted in the drawings for the sake of simplicity.
  • insulating layer 101 is usually a material layer having a low dielectric constant, which is used in this embodiment. Silicon oxide layer.
  • a metal layer 102 is formed on the insulating layer 101 by a chemical vapor deposition process or a physical vapor deposition process.
  • the material of the metal layer 102 is typically aluminum.
  • an anti-reflective coating (ARC) 103 is formed on the metal layer 102.
  • the anti-reflective coating layer 103 may be formed by a chemical vapor deposition process or a spin coating process, and examples of the material of the anti-reflective coating layer 103 include polyimide, silicon oxynitride or amorphous silicon. In this embodiment, the material of the anti-reflective coating layer 103 is silicon oxynitride.
  • the anti-reflective coating layer 103 is oxidized using nitrous oxide (N 2 O) gas 104.
  • N 2 O is ionized in a plasma state to form a chemical bond with the anti-reflective coating layer 103, thereby forming a thin oxide layer on the surface of the anti-reflective coating layer 103, thereby making the surface of the anti-reflective coating layer 103 The shape is flatter.
  • PR photoresist
  • the process conditions of the oxidation treatment are as follows: the flow rate of N 2 O is 500-3000 sccm, the temperature is 330-370 ° C, and the duration is 40-60 s.
  • a PR layer is formed on the surface of the anti-reflection coating layer 103.
  • a conventional patterning process is then performed to transfer the desired pattern onto the metal layer 102.
  • the metal layer 102 is etched, and after the etching is completed, the remaining PR and ARC on the metal layer 102 are removed to obtain a desired metal loop.
  • the processes used in the patterning process, the etching process, the process of removing the remaining PR, and the ARC may employ a process method well known to those skilled in the art, and will not be further described herein.
  • the fabrication of the entire semiconductor device can be completed by a subsequent process, which can be identical to the conventional semiconductor device processing process.
  • the generation of defects in the metal circuit can be fundamentally suppressed, and the metal etching is not restricted by the internal conditions of the metal etching chamber, and the cycle time can be shortened, thereby increasing the yield.
  • the process is simple, does not require additional equipment, is fully compatible with existing semiconductor manufacturing processes, and does not produce any side effects.
  • FIG. 2 there is shown a flow chart of a method of forming a metal loop proposed by the present invention for schematically showing the flow of the entire manufacturing process.
  • step 201 a semiconductor substrate is provided, an insulating layer is formed on the semiconductor substrate, and a metal layer is formed on the insulating layer;
  • step 202 forming an anti-reflective coating on the metal layer
  • step 203 the anti-reflective coating is subjected to an oxidation treatment
  • a PR layer is formed on the surface of the anti-reflective coating to pattern the metal layer.
  • step 205 the metal layer is etched to form a metal loop.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

提供一种形成金属回路的方法，包括：提供半导体衬底（100），在半导体衬底上形成绝缘层（101），且在绝缘层上形成一金属层（102）；在金属层上形成一抗反射涂层（103）；对抗反射涂层进行氧化处理；在抗反射涂层的表面形成光致抗蚀剂（PR）层，图案化金属层；并蚀刻金属层。该方法可以从根本上抑制金属回路缺陷的产生，并且金属蚀刻不受金属蚀刻腔内部状况的制约，可以缩短工艺周期，从而提高产量。该工艺过程简单，不需要增加额外的设备，与现有的半导体制造工艺完全兼容，不会产生任何副效应。

Description

一种形成金属回路的方法
【技术领域】
本发明涉及半导体制造工艺，具体而言涉及铝金属互连工艺中的一种形成金属回路的方法。
【背景技术】
在传统的铝金属互连工艺中，在半导体器件的表面形成一铝金属层，然后图案化所述铝金属层以蚀刻出所需要的金属回路。在所述蚀刻过程结束后，所述金属回路中的金属晶粒的界面会俘获所述图案化过程中所使用的光致抗蚀剂（PR）的残渣,该残渣将会诱导所述金属回路产生缺陷，例如金属残留（metal residue）。对于0.13微米存储器的制造工艺而言，所述金属回路缺陷使邻近的金属导线发生桥连的风险大大提高，最终导致器件功能的失效。
为了抑制所述金属回路缺陷的产生，现有技术通常通过改善金属蚀刻腔的内部状况来实现上述目的。例如，采用设备周期性维护的方法（PM method）,即在PM周期内限制某个时间段（通常是前几个小时）进行金属蚀刻，在此时间段内金属蚀刻腔的内壁形成的聚合物最少，不足以产生所述金属回路缺陷。但是，此方法需要较长的循环周期，从而导致单批次产量的下降，同时也未解决产生所述金属回路缺陷的根本原因。
因此，需要一种针对上述问题的改进技术，从根本上解决产生所述金属回路缺陷的原因。
【发明内容】
针对现有技术的不足，本发明提供一种形成金属回路的方法，包括：提供半导体衬底，在所述半导体衬底上形成绝缘层，且在所述绝缘层上形成一金属层；在所述金属层上形成一抗反射涂层；对所述抗反射涂层进行氧化处理；在所述抗反射涂层的表面形成光致抗蚀剂层，图案化所述金属层，并蚀刻所述金属层，以形成金属回路。
优选地，采用化学气相沉积工艺或旋涂工艺形成所述抗反射涂层。
优选地，所述抗反射涂层的材料是聚酰亚胺、氧氮化硅或无定形硅。
优选地，所述氧化处理的氧化剂为一氧化二氮。
优选地，所述一氧化二氮的流量为500-3000sccm。
优选地，所述氧化处理的温度为330-370℃。
优选地，所述氧化处理的持续时间为40-60s。
优选地，所述绝缘层为具有低介电常数的材料层。
优选地，所述金属层的材料为铝。
根据本发明，通过在金属层上形成一抗反射涂层并对抗反射涂层进行氧化处理，在抗反射涂层的表面形成一薄氧化层，从而使抗反射涂层的表面形貌更加平坦;在光致抗蚀剂（PR）显影之后，蚀刻金属层的过程中，能够降低金属晶粒的界面俘获PR残留物的几率，可以从根本上抑制所述金属回路缺陷的产生，在蚀刻设备的PM周期内的任何时间段都可以进行所述金属蚀刻。
【附图说明】
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1A-图1D为本发明提出的形成金属回路的方法的各步骤的示意性剖面图；
图2为本发明提出的形成金属回路的方法的流程图。
【具体实施方式】
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明，将在下列的描述中提出详细的步骤，以便阐释本发明提出的形成金属回路的方法。显然，本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
下面，参照图1A-图1D和图2来描述本发明提出的形成金属回路的方法的详细步骤。
参照图1A-图1D，其中示出了本发明提出的形成金属回路的方法的各步骤的示意性剖面图。
首先，如图1A所示，提供半导体衬底100，所述半导体衬底100的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅（SOI）等。作为示例，在本实施例中，半导体衬底100选用单晶硅材料构成。在半导体衬底100中形成有隔离槽，埋层，以及各种阱(well)结构，为了简化，图示中予以省略。
在所述半导体衬底100上，形成有各种元件，为了简化，图示中予以省略，这里仅示出一绝缘层101，其通常为具有低介电常数的材料层，本实施例中采用氧化硅层。
接下来，采用化学气相沉积工艺或物理气相沉积工艺在所述绝缘层101上形成一金属层102。所述金属层102的材料通常为铝。
接着，如图1B所示，在所述金属层102上形成一抗反射涂层（ARC）103。可采用化学气相沉积工艺或旋涂工艺形成所述抗反射涂层103，所述抗反射涂层103的材料实例包括聚酰亚胺、氧氮化硅或无定形硅。本实施例中，所述抗反射涂层103的材料为氧氮化硅。
接着，如图1C所示，使用一氧化二氮（N2O）气体104对所述抗反射涂层103进行氧化处理。N2O在等离子状态下离子化而与所述抗反射涂层103形成化学键，由此在所述抗反射涂层103的表面形成一薄氧化层，从而使所述抗反射涂层103的表面形貌更加平坦。实验证明，在光致抗蚀剂（PR）显影之后，蚀刻所述金属层102的过程中，本发明的方法大大降低了金属晶粒的界面俘获PR残留物的几率，从而抑制了所述金属回路缺陷的产生。
所述氧化处理的工艺条件如下：N2O的流量为500-3000sccm，温度为330-370℃，持续时间为40-60s。
接着，如图1D所示，在所述抗反射涂层103的表面形成PR层。随后进行常规的图案化过程，将所需要的图形转移到所述金属层102上。接下来，蚀刻所述金属层102，蚀刻结束后去除所述金属层102上剩余的PR以及ARC，得到所需要的金属回路。所述图案化过程、蚀刻过程、去除剩余的PR以及ARC的过程所采用的工艺可采用本领域技术人员公知的工艺方法，在此不再加以赘述。
至此，完成了根据本发明示例性实施例的方法实施的全部工艺步骤， 接下来，可以通过后续工艺完成整个半导体器件的制作，所述后续工艺可以与传统的半导体器件加工工艺完全相同。根据本发明，可以从根本上抑制所述金属回路缺陷的产生，并且所述金属蚀刻不受金属蚀刻腔内部状况的制约，可以缩短工艺周期，从而提高产量。本工艺过程简单，不需要增加额外的设备，与现有的半导体制造工艺完全兼容，不会产生任何副效应。
参照图2，其中示出了本发明提出的形成金属回路的方法的流程图，用于简要示出整个制造工艺的流程。
在步骤201中，提供半导体衬底，在所述半导体衬底上形成绝缘层，且在所述绝缘层上形成一金属层；
在步骤202中，在所述金属层上形成一抗反射涂层；
在步骤203中，对所述抗反射涂层进行氧化处理；
在步骤204中，在所述抗反射涂层的表面形成PR层，图案化所述金属层。
在步骤205中，蚀刻所述金属层，以形成金属回路。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (9)

  1. 一种形成金属回路的方法，包括：
    提供半导体衬底，在所述半导体衬底上形成绝缘层，且在所述绝缘层上形成一金属层；
    在所述金属层上形成一抗反射涂层；
    对所述抗反射涂层进行氧化处理；
    在所述抗反射涂层的表面形成光致抗蚀剂层，图案化所述金属层，并蚀刻所述金属层，以形成金属回路。
  2. 根据权利要求1所述的方法，其特征在于，采用化学气相沉积工艺或旋涂工艺形成所述抗反射涂层。
  3. 根据权利要求1所述的方法，其特征在于，所述抗反射涂层的材料是聚酰亚胺、氧氮化硅或无定形硅。
  4. 根据权利要求1所述的方法，其特征在于，所述氧化处理的氧化剂为一氧化二氮。
  5. 根据权利要求4所述的方法，其特征在于，所述一氧化二氮的流量为500-3000sccm。
  6. 根据权利要求1所述的方法，其特征在于，所述氧化处理的温度为330-370℃。
  7. 根据权利要求1所述的方法，其特征在于，所述氧化处理的持续时间为40-60s。
  8. 根据权利要求1所述的方法，其特征在于，所述绝缘层为具有低介电常数的材料层。
  9. 根据权利要求1所述的方法，其特征在于，所述金属层的材料为铝。
PCT/CN2012/083335 2011-11-03 2012-10-22 一种形成金属回路的方法 WO2013064023A1 (zh)

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US20020094442A1 (en) * 2001-01-12 2002-07-18 Aaron Lee Bottom anti-reflection coating sandwich structure
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CN101359616A (zh) * 2007-07-30 2009-02-04 中芯国际集成电路制造(上海)有限公司 金属连接器件的形成方法

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