TW400559B - A method of manufacturing the gate spacer of the semiconductor chip - Google Patents

Abstract

It is the manufacturing method for the gate spacer of the semiconductor chip. This invention provides a method of manufacturing the gate spacer of the semiconductor chip. Such a gate protrudes from the surface of the chip, and its surface of the chip comprises at least a field oxide settled in the neighboring regions of the gate which is used for the electric isolation. The top region of this gate is higher than that of the field oxide. Such a method initially forms the first dielectric on the surface of the chip to cover the gate and the field oxide, wherein the thickness covered at the top of the gate in the first dielectric is larger than that of covered at the top of the field oxide in the same dielectric. Next step is to form a second dielectric on the surface of the chip covered the first one which planarizes the surface of the chip. Then, the following procedure is to proceed the first etch toward the surface of the chip which deprieves of the second dielectric into the predetermined depth and lowers the thickness of the first dielectric at the top of the gate simultaneously. Later, please proceed the second etch from the surface of the chip of the second dielectric in order to remove the surface of the chip from the second one completely. Finally, please proceed the anisotropical third etch process toward the first dielectric of the surface of the chip to remove the first dielectric at the top of the gate completely and to form the spacer on the side-wall of the gate.

Description

This invention relates to a method for providing a wall. In the half (Spacer) (Source) can be used to make gate-growth USG dielectric gates. In the conductor process, the gate gap of the semiconductor wafer can be used to isolate the gate and the drain. (Drain), the source: is electrically connected, and the structure formed by the barrier and the gate is also a mask of heavily doped (Heavy Doping). The one-pole gap wall method is to use an undoped siHcate glass (layer) layer on the surface of the semiconductor wafer to remove part of the USG dielectric layer using the last engraving process, and place the side-wal 1 ) The gap formed by the unremoved USG dielectric layer is shown in FIGS. 1 to 3, and FIGS. 1 to 3 are schematic diagrams of a conventional method for fabricating the gate 18 and the spacer 12 of the semiconductor wafer 10. The semiconductor wafer used to make the gate spacer 10 includes a silicon substrate 14 (Substrate), two field oxide layers 16 and 17 are disposed on the silicon substrate 14 for electrical isolation, and a gate 18 is disposed on the field oxide layer 17 On the surface of the semi-conductor wafer wafer 0, the top of the gate electrode 18 is higher than the top of the field oxide layer 16, as shown in Fig. 1. When making the gap wall of the gate electrode 18, the semiconductor wafer is firstly丨 〇 Perform an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process to form a USG dielectric layer 20 on the surface of the semiconductor wafer 10 so that the USG dielectric layer 20 covers the gate 18 and the field Above the oxide layer 16, as shown in Figure 2 Because of the gate

V. Description of the invention (2) The top of 18 is higher than the top of field oxide layer 16, so the step coverage problem will occur during the APCVD process, which makes the thickness of the USG dielectric layer 20 deposited on the top of the gate 18 a The thickness b of the USG dielectric layer 20 is larger than the top of the field oxide layer 16. After the USG dielectric layer 20 is deposited, an anisotropic dry etching (Anisotropic Etch) process is performed to remove the USG dielectric layer 20 ′ on the surface of the semiconductor wafer 10 and deposited on the sidewalls surrounding the gate 18 without being The removed USG dielectric layer 20 forms two spacers 12, as shown in FIG. However, in order to completely remove the 1 ^ 0 dielectric layer 20 having a thickness of 3 at the top end of the gate electrode 18, an over-etching phenomenon often occurs on the USG dielectric layer 20 having a thickness b at the top of the field oxide layer 16 to make the field The thickness of the oxide layer 16 is reduced (a_b), thereby reducing the electrical isolation effect. The top of the field oxide layer 16 above the etched field oxide layer 16 in FIG. 3, and the solid line represents the top of the field oxide layer 16 that is over-etched. Therefore, the main object of the present invention is to provide a method of gate spacers, which can be used to maintain the thickness of the oxide layer of the field oxide layer and reduce the electrical isolation effect of the oxide layer. Brief description of the drawing Figures to Figure 2 are the intentions of making the thick knitting quilt μ. Figures 4 to 9 of the method of the gate spacer of the navigator wafer are shown in Figure 4 to Figure 9.

Figure 10 is a flowchart of the process of manufacturing the gate spacer of the semiconductor wafer according to the present invention. 32 Gate 3 6 field oxide layer 40 SOG dielectric layer pattern symbol description 3 〇 semiconductor wafer 34 spacer 38 USG dielectric layer March reference diagram 4 to 9 are schematic diagrams of a method for fabricating a gate 32 and a spacer 34 of a semiconductor wafer 30 according to the present invention. As shown in FIG. 4, the semiconductor wafer 30 used to make the gate spacer includes a silicon substrate 31, and a field oxide layer 36 and 37 are provided on the surface of the silicon substrate 31 for ionization. And a gate 32 is disposed on the field oxide layer 37 and protrudes from the surface of the semiconductor wafer 30 so that the top of the gate 32 is higher than the top of the field oxide layer 36 in the vicinity. g The method of manufacturing the gate 32 gap of the semiconductor wafer 30 according to the present invention ^ first performs an APCVD process to form a USG ^ electric layer 38 on the surface of the semiconductor wafer 30 to cover the gate 32 and field oxidation Layers 36, 37, as shown in Figure 5 = ° Because the top of the gate 32 is higher than the top of the field oxide layer 36, the thickness of the US (J dielectric layer 38 covering the top of the gate 32 is larger than that of the USG dielectric layer 38 Then, the thickness b of the top of the oxide layer 36. Then, a coating process is performed, and the liquid spin-on glass (Spin_On GUss, SOG) is uniformly coated on the USG substrate by spin coating. On the electrical layer 38, a SOG dielectric is formed.

5. Description of the Invention (4) The electric layer 40 'is used to planarize the surface of the semiconductor wafer 30. As shown in FIG. 6, the thickness of the SOG dielectric layer 40 covering the top of the gate electrode 32 is relatively thin, while the thickness of the SOG dielectric layer 40 covering the top of the field oxide layer 36 is relatively thick. Then, a plasma etching (Plasma Etch) process is performed on the surface of the semiconductor wafer 30 to remove the SOG dielectric layer 40 to a predetermined depth, not only completely removing the SOG dielectric layer 40 on the top of the gate 32, but also removing the gate. A portion of the USG dielectric layer 38 on the top of the electrode 32 reduces the thickness of the USG dielectric layer 38 on the top of the gate 32 from a to a ', a' and the thickness of the USG dielectric layer 38 on the top of the field oxide layer 36. The thickness b is approximately equal, as shown in FIG. The dashed line above the gate 32 in FIG. 7 indicates the top of the USG dielectric layer 38 before the thickness is reduced. Then, a full Etch process is performed on the surface of the semiconductor wafer 30 to completely remove the SOG dielectric layer 40 on the surface of the semiconductor wafer 30, as shown in FIG. The wet etching (Wet Etch) process uses an etching solution containing potassium hydroxide (P 〇 t a s s i u m H y d r ο X i d e, K 0 Η) or hydrofluoric acid (H y d r 〇 f 1 u 〇 r i c

Ac d, HF), other etching solutions can also be used, such as Buffered Oxide Etcher (BOE). Finally, an anisotropic dry etching process is performed to remove most of the USG dielectric layer 38 deposited on the surface of the semiconductor wafer 30, so that the USG dielectric layer 38 on the top of the gate 32 is completely removed, and The unremoved USG dielectric layer 38 on the side wall surrounding the gate electrode 32 forms a gap wall 34, as shown in FIG. This dry name is engraved by a process containing carbon tetrafluoride (Carbon

Tetrachloride (CF4), Carbon Trifluoride,

Ar), dry etching of a mixed gas of hydrogen or oxygen V. Description of the invention (5) CHF3), argon (Argon, engraving process. The method of the spacer 34 of the wafer interrogator 32 is prior to the semiconductor wafer 30 Two dielectric layers are formed on the surface. The first dielectric layer is a USG dielectric layer 38, the second dielectric layer is a SOG dielectric layer 40, and the second dielectric layer is made of a liquid dielectric material. In the spin coating method, the surface of the undulating semiconductor wafer 30 is flattened. Then, plasma etching, thirst etching, and anisotropic drying processes are sequentially performed to remove the semiconductor wafer 30. The SOG dielectric layer 40 and the USG dielectric layer 38, and a gap wall 34 is formed on the "side wall of the gate." The plasma etching process will remove a portion of the USG dielectric layer 38 on the top of the gate. The thickness a of the USG dielectric layer 38 on the top of the gate 32 is approximately the same as the thickness b of the usg dielectric layer 38 on the top of the field oxide layer 36. Therefore, a dry etching process is performed at the end to completely remove the USG dielectric on the top of the gate 32. When the electric layer 38 is used, the thickness of the field oxide layer 36 can be reduced, and the thickness of the field oxide layer 36 will not be reduced. This reduces the effect of the electrical isolation of the field oxide layer 36. Please refer to FIG. 10, which is a flow chart of the manufacturing process of the gate 32 and the spacer 34 of the semiconductor wafer 30 of the present invention. To sum up, the present invention The process 4 2 of making the barrier wall 34 of the gate 32 includes the following steps: Step 44: Perform an APCVD process to form a USG dielectric layer 38 on the surface of the semiconductor wafer 30 to cover the gate 32 and field oxygen.

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化 层 3 6. Step 46: A coating process is performed to form a sog dielectric layer 40 on the USG dielectric layer 38 to planarize the surface of the semiconductor wafer 30. Step 48: A plasma etching process is performed to remove the SOJ dielectric layer 40 to a predetermined depth, and at the same time reduce the thickness of the USG dielectric layer 38 on the top of the gate 32. Step 50: Wet etching process To completely remove the SOG dielectric layer 40 on the surface of the semiconductor wafer 30. Step 52: Perform an anisotropic dry etching process to completely remove the USG dielectric layer 38 on the top of the gate 32, and A gap wall 34 is formed on the side wall around the gate electrode 32. Compared with the conventional method of manufacturing the gate electrode 8 and the gap wall method 2, the method for manufacturing the gate electrode 32 gap wall 34 of the semiconductor wafer 30 according to the present invention is based on USG dielectrics. A SOG dielectric layer 40 is formed on the layer 38 by spin coating to planarize the surface of the semiconductor wafer 30, and then a plasma etching process, a wet etching process, and a dry etching process are sequentially performed. The plasma etching process is removed. Part of the USG dielectric layer 38 on the top of the gate 32. Therefore, in the subsequent etching process to completely remove the USG dielectric layer 38 on the top of the gate, the thickness of the field oxide layer 36 can be reduced to a smaller extent, and the field The electrical isolation effect of the oxide layer 36. The above is only described Preferred embodiment of the present invention, where the present patent application scope of the invention modifications and alterations made, the patent also belong to the present invention

Page 10 V. Description of Invention (7) Scope. iwm page 11

Claims (1)

6. Scope of Patent Application 1. A method for making a gate of a semiconductor wafer The gate is protruded from the surface of the semiconductor wafer, and the surface of the semiconductor wafer further includes at least one field An oxide layer (Field Oxide) is provided in the vicinity of the gate for electrical isolation. The top of the gate is attached to the top of the field oxide layer. The method includes the following steps: On the semiconductor wafer A first dielectric layer is formed on the surface to cover the gate and the field oxide layer. The thickness of the first dielectric layer covering the top of the gate is greater than that of the first dielectric layer covering the field oxide layer. The thickness of the top end; forming a second dielectric layer on the surface of the semiconductor wafer to cover the first dielectric layer to flatten the surface of the semiconductor wafer; and performing a first etching (Etch) process on the surface of the semiconductor wafer For removing the second dielectric layer to a predetermined depth, and at the same time reducing the thickness of the first dielectric layer on the top of the gate; performing a second etching process on the surface of the semiconductor wafer to Completely remove the second dielectric layer; and perform an anisotropic third-name process on the first dielectric layer on the surface of the semiconductor wafer to completely remove the first dielectric layer on the top of the gate and A side wall (Side_Wal 丨) of the gate electrode forms the gap wall. 2. The method according to item 丨 in the scope of patent application, wherein during the first etching process, the thickness of the first dielectric layer on the top of the gate electrode is reduced to a level where the first dielectric layer covers the The thickness of the top of the field oxide layer ^. Page 12 6. Scope of patent application 3. The method described in item 1 of the scope of patent application, wherein the first dielectric layer is composed of an undoped silicon glass (Undoped Si 1 icate Glass). of. 4. The method according to item 丨 of the scope of patent application, wherein the second dielectric layer is uniformly coated on the surface of the semiconductor wafer by a spin coating method using a liquid dielectric material. 5. The method according to item 4 of the scope of patent application, wherein the liquid dielectric material is a liquid spin-on glass. 6. The method according to item 1 of the scope of patent application, wherein the first etching process is a Plasma Etch process. 7. The method according to item 1 of the scope of patent application, wherein the second etching process is a Wet Etching process. 8. The method described in item 7 of the scope of the patent application, wherein the engraving solution used in the wet etching process includes rhenium hydroxide (p〇tassiUffl Hydroxide, KOH) or hydrofluoric acid (HF) 〇9 The method according to item 7 of the scope of patent application, wherein the wet etching process Page 13 VI. Scope of Patent Application The etching solution used is a buffer oxide of silicon oxide (Buffered Oxide Etcher, BOE) at a ratio of 10: 1. 10. The method as described in item 1 of the scope of the patent application, wherein the third etching process is a method including carbon tetrafluoride (CF4), carbon trifluoride (CHF3), and argon. (Argon, Ar), hydrogen or oxygen mixed gas dry etching process. Page 14