TW400559B - A method of manufacturing the gate spacer of the semiconductor chip - Google Patents
A method of manufacturing the gate spacer of the semiconductor chip Download PDFInfo
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- TW400559B TW400559B TW88102126A TW88102126A TW400559B TW 400559 B TW400559 B TW 400559B TW 88102126 A TW88102126 A TW 88102126A TW 88102126 A TW88102126 A TW 88102126A TW 400559 B TW400559 B TW 400559B
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Description
種製作半導體晶片之閘極(Gate)間隙 本發明係提供_ 壁的方法。 在半 (Spacer) (Source) 可用來做 般製作閘 積製程形 USG)介電 閘極周圍 壁〇 導體製程中,半導體晶片之閘極(Gate)間隙壁 ,可以用來隔絕閘極與汲極(Drain)、源極 :的電性連通,而間隙壁與閘極所形成的結構也 ‘·、、汲極與源極重摻雜(Heavy D〇pi ng)的罩幕。一 極間隙壁的方法,是在半導體晶片表面上利用沉 成一無摻雜矽玻璃(Undoped siHcate glass, 層’再利用姓刻製程去除部份USG介電層,並於 侧壁(side-wal 1 )未被去除的USG介電層形成間隙 請參閱圖一至圖三,圖一至圖三為習知製作半導體晶 片10之閘極18間隙壁12方法的示意圖。用來製作閘極間隙 壁的半導體晶片10包含有一矽基材14 (Substrate),二個 場氧化層16、17設於矽基材14之上,用來做為電性隔離, 以及一閘極1 8設於場氧化層1 7之上並突出於半導艘晶片工〇 的表面’使閘極18之頂端高於場氧化層16之頂端,如圖一 所示。習知製作閘極1 8的間隙壁時,先對半導體晶片丨〇進 行一常壓化學氣相沉積(Atmospheric Pressure Chemical Vapor Deposition ’ 簡稱APCVD)製程,以形成 一 USG介電層20於半導體晶片10表面上,使USG介電層20覆 蓋於閘極18以及場氧化層16之上,如圖二所示。由於閘極This invention relates to a method for providing a wall. In the half (Spacer) (Source) can be used to make gate-growth USG dielectric gates. In the conductor process, the gate gap of the semiconductor wafer can be used to isolate the gate and the drain. (Drain), the source: is electrically connected, and the structure formed by the barrier and the gate is also a mask of heavily doped (Heavy Doping). The one-pole gap wall method is to use an undoped siHcate glass (layer) layer on the surface of the semiconductor wafer to remove part of the USG dielectric layer using the last engraving process, and place the side-wal 1 ) The gap formed by the unremoved USG dielectric layer is shown in FIGS. 1 to 3, and FIGS. 1 to 3 are schematic diagrams of a conventional method for fabricating the gate 18 and the spacer 12 of the semiconductor wafer 10. The semiconductor wafer used to make the gate spacer 10 includes a silicon substrate 14 (Substrate), two field oxide layers 16 and 17 are disposed on the silicon substrate 14 for electrical isolation, and a gate 18 is disposed on the field oxide layer 17 On the surface of the semi-conductor wafer wafer 0, the top of the gate electrode 18 is higher than the top of the field oxide layer 16, as shown in Fig. 1. When making the gap wall of the gate electrode 18, the semiconductor wafer is firstly丨 〇 Perform an Atmospheric Pressure Chemical Vapor Deposition (APCVD) process to form a USG dielectric layer 20 on the surface of the semiconductor wafer 10 so that the USG dielectric layer 20 covers the gate 18 and the field Above the oxide layer 16, as shown in Figure 2 Because of the gate
五、發明說明(2) 18之頂端高於場氧化層16之頂端,因此進行APCVD製程時 會產生階梯覆蓋(step coverage)的問題,使沈積於閘極 18頂端之USG介電層20厚度a大於場氧化層16頂端之USG介 電層20厚度b。 沈積USG介電層20之後進行一非等向性乾蝕刻 (Anisotropic Etch)製程,以去除半導體晶月1〇表面上的 USG介電層20 ’而沈積在閘極18之周圍側壁上且未被去除 的USG介電層20便形成兩個間隙壁12,如圖三所示。不 過,為了完全去除閘極18之頂端厚度為3的1^〇介電層2〇, 在場氧化層16之頂端厚度為b的USG介電層2〇上常發生過度 蝕刻的現象,使場氧化層16的厚度降低了(a_b),進而降 =化=的電性隔離效果。圖三中場氧化層16上方的 = 刻的場氧化層16頂端,而實線表 π赞生過度蝕刻的場氧化層16頂端。 因此本發明之主要目的在於提供一 之閘極間隙壁的方法,卩 ^作+導想曰曰片 進而維持場爱彳場氧化層厚度降低的程度, %氧化層的電性隔離效果。 圖式之簡單說明 圖至圖二為習知製作丰揉被μ 意圖。 導艘晶片之閘極間隙壁方法的示 圖四至圖九為本發明製 1下牛導體晶片之閘極間隙壁方法的 第6.頁V. Description of the invention (2) The top of 18 is higher than the top of field oxide layer 16, so the step coverage problem will occur during the APCVD process, which makes the thickness of the USG dielectric layer 20 deposited on the top of the gate 18 a The thickness b of the USG dielectric layer 20 is larger than the top of the field oxide layer 16. After the USG dielectric layer 20 is deposited, an anisotropic dry etching (Anisotropic Etch) process is performed to remove the USG dielectric layer 20 ′ on the surface of the semiconductor wafer 10 and deposited on the sidewalls surrounding the gate 18 without being The removed USG dielectric layer 20 forms two spacers 12, as shown in FIG. However, in order to completely remove the 1 ^ 0 dielectric layer 20 having a thickness of 3 at the top end of the gate electrode 18, an over-etching phenomenon often occurs on the USG dielectric layer 20 having a thickness b at the top of the field oxide layer 16 to make the field The thickness of the oxide layer 16 is reduced (a_b), thereby reducing the electrical isolation effect. The top of the field oxide layer 16 above the etched field oxide layer 16 in FIG. 3, and the solid line represents the top of the field oxide layer 16 that is over-etched. Therefore, the main object of the present invention is to provide a method of gate spacers, which can be used to maintain the thickness of the oxide layer of the field oxide layer and reduce the electrical isolation effect of the oxide layer. Brief description of the drawing Figures to Figure 2 are the intentions of making the thick knitting quilt μ. Figures 4 to 9 of the method of the gate spacer of the navigator wafer are shown in Figure 4 to Figure 9.
圖十為本發明製作半導體晶片之閘極間隙壁製程流程圖 32閘極 3 6場氧化層 40 SOG介電層 圖式之符號說明 3 〇半導體晶片 34間隙壁 38 USG介電層 3月參閱圖四至圖九,圖四至圖九為本發明製作半導體 晶片30之閘極32間隙壁34方法的示意圖。如圖四所示,用 來製作閘極間隙壁的半導體晶片3〇包含有一矽基材31 , =個場氧化層36、37設於矽基材31之表面,用來做為電性 離,以及一閘極32設於場氧化層37之上並突出於半導體 晶片30之表面,使閘極32之頂端高於附近區域之場氧化層 36的頂端。 g 本發明之製作半導體晶片3 〇之閘極3 2間隙壁的方法, ^先進行一APCVD製程,於半導體晶片30表面上形成一USG ^電層38,用來覆蓋閘極3 2及場氧化層36、37,如圖五所 =°由於閘極32之頂端高於場氧化層36之頂端,因此US(J 介電層38覆蓋於閘極3 2頂端之厚度^大於USG介電層38覆蓋 於,氧化層36頂端之厚度b。隨後進行一塗佈製程,利用 液態之旋塗式玻璃(Spin_〇n GUss,s〇G)以旋塗(Spin Coating)的方式均勻塗佈於USG介電層38上,形成一s〇G介Figure 10 is a flowchart of the process of manufacturing the gate spacer of the semiconductor wafer according to the present invention. 32 Gate 3 6 field oxide layer 40 SOG dielectric layer pattern symbol description 3 〇 semiconductor wafer 34 spacer 38 USG dielectric layer March reference diagram 4 to 9 are schematic diagrams of a method for fabricating a gate 32 and a spacer 34 of a semiconductor wafer 30 according to the present invention. As shown in FIG. 4, the semiconductor wafer 30 used to make the gate spacer includes a silicon substrate 31, and a field oxide layer 36 and 37 are provided on the surface of the silicon substrate 31 for ionization. And a gate 32 is disposed on the field oxide layer 37 and protrudes from the surface of the semiconductor wafer 30 so that the top of the gate 32 is higher than the top of the field oxide layer 36 in the vicinity. g The method of manufacturing the gate 32 gap of the semiconductor wafer 30 according to the present invention ^ first performs an APCVD process to form a USG ^ electric layer 38 on the surface of the semiconductor wafer 30 to cover the gate 32 and field oxidation Layers 36, 37, as shown in Figure 5 = ° Because the top of the gate 32 is higher than the top of the field oxide layer 36, the thickness of the US (J dielectric layer 38 covering the top of the gate 32 is larger than that of the USG dielectric layer 38 Then, the thickness b of the top of the oxide layer 36. Then, a coating process is performed, and the liquid spin-on glass (Spin_On GUss, SOG) is uniformly coated on the USG substrate by spin coating. On the electrical layer 38, a SOG dielectric is formed.
五、發明說明(4) 電層40 ’用來平坦化半導體晶片30的表面。如圖六所示, 覆蓋於閘極32頂端上之SOG介電層40的厚度較薄,而相對 地覆蓋於場氧化層36頂端上之SOG介電層40的厚度較厚。 然後對半導體晶片30表面進行一電漿蝕刻(Plasma Etch)製程’用來去除s〇G介電層40至一預定深度,不僅完 全去除閘極32頂端上之S0G介電層40,還去除閘極32頂端 上之部份USG介電層38,使閘極32頂端上之USG介電層38的 厚度由a降低至a’,a'與場氧化層36頂端上之USG介電層38 的厚度b約略相等,如圖七所示。圖七閘極32上方的虛線 表示厚度降低前的USG介電層38頂端。接著對半導體晶片 30表面進行一滿钱刻(fet Etch)製程,以完全去除半導體 晶片3 0表面上之S0G介電層4 0,如圖八所示。這個濕蝕刻 (Wet Etch)製程所使用的蝕刻溶液包含有氫氧化鉀 (P 〇 t a s s i u m H y d r ο X i d e,K 0 Η)或是氫氟酸(H y d r 〇 f 1 u 〇 r i c5. Description of the Invention (4) The electric layer 40 'is used to planarize the surface of the semiconductor wafer 30. As shown in FIG. 6, the thickness of the SOG dielectric layer 40 covering the top of the gate electrode 32 is relatively thin, while the thickness of the SOG dielectric layer 40 covering the top of the field oxide layer 36 is relatively thick. Then, a plasma etching (Plasma Etch) process is performed on the surface of the semiconductor wafer 30 to remove the SOG dielectric layer 40 to a predetermined depth, not only completely removing the SOG dielectric layer 40 on the top of the gate 32, but also removing the gate. A portion of the USG dielectric layer 38 on the top of the electrode 32 reduces the thickness of the USG dielectric layer 38 on the top of the gate 32 from a to a ', a' and the thickness of the USG dielectric layer 38 on the top of the field oxide layer 36. The thickness b is approximately equal, as shown in FIG. The dashed line above the gate 32 in FIG. 7 indicates the top of the USG dielectric layer 38 before the thickness is reduced. Then, a full Etch process is performed on the surface of the semiconductor wafer 30 to completely remove the SOG dielectric layer 40 on the surface of the semiconductor wafer 30, as shown in FIG. The wet etching (Wet Etch) process uses an etching solution containing potassium hydroxide (P 〇 t a s s i u m H y d r ο X i d e, K 0 Η) or hydrofluoric acid (H y d r 〇 f 1 u 〇 r i c
Ac l d,HF ),也可使用其他蝕刻溶液,例如丨〇 :丨的氧化矽 緩衝蝕刻液(Buffered Oxide Etcher, B0E)。 最後’進行一非等向性之乾蝕刻製程,用來去除大部 分沉積於半導體晶片30表面上之USG介電層38,使閘極32 之頂端上的USG介電層38被完全去除,並於閘極32之周圍 側壁上未被去除之USG介電層38形成間隙壁34,如圖九所 示。這個乾姓刻製程為一種包含有四氟化碳(CarbonAc d, HF), other etching solutions can also be used, such as Buffered Oxide Etcher (BOE). Finally, an anisotropic dry etching process is performed to remove most of the USG dielectric layer 38 deposited on the surface of the semiconductor wafer 30, so that the USG dielectric layer 38 on the top of the gate 32 is completely removed, and The unremoved USG dielectric layer 38 on the side wall surrounding the gate electrode 32 forms a gap wall 34, as shown in FIG. This dry name is engraved by a process containing carbon tetrafluoride (Carbon
Tetrachloride, CF4)、三敗曱烧(Carbon Trifluoride,Tetrachloride (CF4), Carbon Trifluoride,
Ar)、氫氣或氧氣之混合氣體的乾蝕 五、發明說明(5) CHF3)、氬氣(Argon, 刻製程。 曰片問極32之間隙壁34的方法,是先於半導體 曰曰片30表面形成二層介電層,第一介電層為USG介電層 38,第二介電層則為S0G介電層4〇,而第二介電層是利用 液態的介電材才斗以旋塗的彳式所Μ,則吏高低起伏之半 導體晶片30表面平坦化。然後依序進行電漿蝕刻、渴蝕 刻、以及非等向性之乾㈣製程,以去除半導趙晶片3〇上 之S0G介電層40與USG介電層38,並於閘極“之周圍側壁上 形成間隙壁34。由於電漿蝕刻製程會去除閘極”頂端上之 部份USG介電層38 ’則吏閘極32頂端上之USG介電層38的厚 度a與場氧化層36頂端上之usg介電層38厚度b約略相等。 因此在最後進行乾蝕刻製程以完全去除閘極32頂端上之 USG介電層38時’可以使場氧化層36厚度降低的程度減 少,甚至場氧化層36厚度不會減少,進而維持場氧化層36 之電性隔離的效果。 請參考圖十,圖十為本發明半導體晶片3〇之閘極32間 隙壁34的製程流程圖。綜、合以上所述,本發明製作閘極32 的間隙壁3 4的流程4 2包含有下列步驟: 步驟44 :進行APCVD製程,於半導體晶片3〇表面上形 成USG介電層38,用來復蓋閘極32以及場氧Ar), dry etching of a mixed gas of hydrogen or oxygen V. Description of the invention (5) CHF3), argon (Argon, engraving process. The method of the spacer 34 of the wafer interrogator 32 is prior to the semiconductor wafer 30 Two dielectric layers are formed on the surface. The first dielectric layer is a USG dielectric layer 38, the second dielectric layer is a SOG dielectric layer 40, and the second dielectric layer is made of a liquid dielectric material. In the spin coating method, the surface of the undulating semiconductor wafer 30 is flattened. Then, plasma etching, thirst etching, and anisotropic drying processes are sequentially performed to remove the semiconductor wafer 30. The SOG dielectric layer 40 and the USG dielectric layer 38, and a gap wall 34 is formed on the "side wall of the gate." The plasma etching process will remove a portion of the USG dielectric layer 38 on the top of the gate. The thickness a of the USG dielectric layer 38 on the top of the gate 32 is approximately the same as the thickness b of the usg dielectric layer 38 on the top of the field oxide layer 36. Therefore, a dry etching process is performed at the end to completely remove the USG dielectric on the top of the gate 32. When the electric layer 38 is used, the thickness of the field oxide layer 36 can be reduced, and the thickness of the field oxide layer 36 will not be reduced. This reduces the effect of the electrical isolation of the field oxide layer 36. Please refer to FIG. 10, which is a flow chart of the manufacturing process of the gate 32 and the spacer 34 of the semiconductor wafer 30 of the present invention. To sum up, the present invention The process 4 2 of making the barrier wall 34 of the gate 32 includes the following steps: Step 44: Perform an APCVD process to form a USG dielectric layer 38 on the surface of the semiconductor wafer 30 to cover the gate 32 and field oxygen.
第9頁Page 9
化層3 6。 步驟46 :進行塗佈製程,於USG介電層38之上形成s〇g 介電層40,用來平坦化半導體晶片3〇的表 面。 步驟48 :進行電漿蝕刻製程,用來去除s〇(J介電層4〇 至一預定深度,並同時降低閘極32頂端上之 USG介電層38的厚度。 步驟50 :進行濕蝕刻製程,用來完全去除半導體晶片 30表面上之s〇G介電層40。 步驟5 2 :進行非等向性之乾蝕刻製程,用來完全去除 閘極32頂端上之USG介電層38,並於閘極32 之周圍侧壁形成間隙壁34。 相較於習知製作閘極丨8間隙壁丨2方法,本發明製作半 導體晶片30之閘極32間隙壁34的方法,是於USG介電層38 上以旋塗的方式形成S0G介電層4〇,以使半導體晶片3〇表 面平坦化,再依序進行電漿蝕刻製程、濕蝕刻製程以及乾 蝕刻製程。而電漿蝕刻製程會去除閘極32頂端上之部份 USG介電層38。因此在後續蝕刻製程以完全去除閘極以頂 端上之USG介電層38時,可以使場氧化層36厚度降低的程 度減少,進而維持場氧化層3 6的電性隔離效果。 以上所述僅為本發明之較佳實施例,凡本發明申請專 利範圍所做之均等變化與修飾,皆應屬本發明專利之涵蓋化 层 3 6. Step 46: A coating process is performed to form a sog dielectric layer 40 on the USG dielectric layer 38 to planarize the surface of the semiconductor wafer 30. Step 48: A plasma etching process is performed to remove the SOJ dielectric layer 40 to a predetermined depth, and at the same time reduce the thickness of the USG dielectric layer 38 on the top of the gate 32. Step 50: Wet etching process To completely remove the SOG dielectric layer 40 on the surface of the semiconductor wafer 30. Step 52: Perform an anisotropic dry etching process to completely remove the USG dielectric layer 38 on the top of the gate 32, and A gap wall 34 is formed on the side wall around the gate electrode 32. Compared with the conventional method of manufacturing the gate electrode 8 and the gap wall method 2, the method for manufacturing the gate electrode 32 gap wall 34 of the semiconductor wafer 30 according to the present invention is based on USG dielectrics. A SOG dielectric layer 40 is formed on the layer 38 by spin coating to planarize the surface of the semiconductor wafer 30, and then a plasma etching process, a wet etching process, and a dry etching process are sequentially performed. The plasma etching process is removed. Part of the USG dielectric layer 38 on the top of the gate 32. Therefore, in the subsequent etching process to completely remove the USG dielectric layer 38 on the top of the gate, the thickness of the field oxide layer 36 can be reduced to a smaller extent, and the field The electrical isolation effect of the oxide layer 36. The above is only described Preferred embodiment of the present invention, where the present patent application scope of the invention modifications and alterations made, the patent also belong to the present invention
第10頁 五、發明說明(7) 範圍。 iwm 第11頁Page 10 V. Description of Invention (7) Scope. iwm page 11
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