KR101037690B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR101037690B1 KR101037690B1 KR1020040001520A KR20040001520A KR101037690B1 KR 101037690 B1 KR101037690 B1 KR 101037690B1 KR 1020040001520 A KR1020040001520 A KR 1020040001520A KR 20040001520 A KR20040001520 A KR 20040001520A KR 101037690 B1 KR101037690 B1 KR 101037690B1
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 16
- 210000004027 cell Anatomy 0.000 description 14
- 239000007789 gas Substances 0.000 description 14
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 description 7
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Natural products C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 7
- 239000007788 liquid Substances 0.000 description 5
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 1
- 210000004692 intercellular junction Anatomy 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/42—Stripping or agents therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
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Abstract
본 발명은 반도체소자의 제조방법에 관해 개시한 것으로서, 셀영역과 페리영역이 정의된 반도체기판을 제공하는 단계와, 기판 위에 각각의 워드라인을 형성하는 단계와, 워드라인을 포함한 기판 전면에 버퍼산화막, 제 2실리콘 질화막 및 실리콘 산화막의 3중 적층 구조의 스페이서를 형성하는 단계와, 스페이서를 포함한 기판 전면에 상기 셀영역은 노출시키고 상기 페리영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막패턴을 마스크로 하고 상기 기판 전면에 CH3OH 및 HF 가스를 공급하여 셀영역의 실리콘 산화막을 제거하는 단계와, 마이크로파를 공급한 상태에서 CF4 및 O2가스를 공급하여 상기 감광막 패턴을 에슁하는 단계를 포함한다.The present invention relates to a method for manufacturing a semiconductor device, comprising the steps of providing a semiconductor substrate having a cell region and a ferry region defined, forming each word line on the substrate, and a buffer on the front surface of the substrate including the word line Forming a spacer having a triple stacked structure of an oxide film, a second silicon nitride film, and a silicon oxide film, forming a photoresist pattern covering the ferry region and exposing the cell region on the entire surface of the substrate including the spacer; Supplying CH 3 OH and HF gas to the entire surface of the substrate as a mask to remove the silicon oxide film in the cell region, and supplying CF 4 and O 2 gas in the state of microwave supply to etch the photoresist pattern.
Description
도 1a 내지 도 1d는 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명은 반도체 소자의 형성방법에 관한 것으로, 보다 구체적으로는 수 있는 감광막패턴을 이용하여 페리영역은 덮고 셀영역의 게이트전극의 스페이서 중에서 실리콘산화막만을 습식액을 이용하여 제거하는 공정에 있어서, 상기 감광막이 게이트전극 사이의 공간에 잔류됨에 따라 상기 습식액을 이용한 옥사이드막의 식각공정 시, 옥사이드막이 잔류되어 파티클 소오스(particle source)로서 작용하는 것을 방지할 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method of forming a semiconductor device, and more particularly, in a process of removing only a silicon oxide film using a wet liquid from a spacer of a gate electrode of a cell region by covering a ferry region using a photoresist pattern. The present invention relates to a method of manufacturing a semiconductor device capable of preventing an oxide film from remaining as a particle source during the etching process of an oxide film using the wet liquid as the photosensitive film remains in a space between gate electrodes.
최근 디램소자의 워드라인 형성 공정에 있어서, 소자의 특성을 개선하기 위해 워드라인을 식각한 후, 상기 워드라인의 측벽에 형성되는 스페이서로서 버퍼산화막, 실리콘 질화막 및 실리콘산화막의 3중 적층 구조를 이용한다. 이때, 상기 실리콘질화막은 90Å 두께로 형성하며, 상기 버퍼산화막으로는 CVD 방식에 의해 SiO2막을 이용한다. In a word line forming process of a DRAM device, a word layer is etched to improve device characteristics, and a triple stacked structure of a buffer oxide film, a silicon nitride film, and a silicon oxide film is used as a spacer formed on the sidewall of the word line. . In this case, the silicon nitride film is formed to a thickness of 90Å, the SiO 2 film is used by the CVD method as the buffer oxide film.
여기서, 이후의 도전플러그 형성용 콘택 형성 시, 감광막패턴을 이용하여 페리영역은 덮고 셀영역의 워드라인 스페이서의 외곽에 위치된 실리콘산화막을 선택적으로 제거한다. Here, in the subsequent formation of the conductive plug forming contact, the silicon oxide film positioned on the periphery of the word line spacer of the cell region is selectively removed by using the photoresist pattern.
그러나, 셀지역에서는 게이트전극과 게이트전극 간의 스페이서 CD(Critical Dimension)가 10㎚ 이하로 좁아지며, 상기 좁아진 게이트전극 사이에 감광막 성분이 잔류하게 된다. 이 후, 상기 감광막패턴을 마스크로 셀영역의 실리콘산화막을 제거하는 공정에서 상기 실리콘산화막 성분이 잔류되어 이 후 파티클 소오스로 작용하여 셀 정션(cell junction) 트랜지스터가 비정상적으로 작동하게 된다.However, in the cell region, the spacer CD (critical dimension) between the gate electrode and the gate electrode is narrowed to 10 nm or less, and photosensitive film components remain between the narrowed gate electrodes. Subsequently, in the process of removing the silicon oxide film of the cell region using the photoresist pattern as a mask, the silicon oxide film component remains and then acts as a particle source, thereby abnormally operating a cell junction transistor.
따라서, 이러한 문제점을 해결하고자, 디스컴(descum)이라는 감광막 제거공정을 적용하였으나, 이러한 감광막 제거공정은 측면 감광막 에슁비보다 수직한 감광막 에슁비가 더 빨라 페리지역의 잔류된 감광막 두께가 낮아지고 이후 습식식각 시 감광막 리프팅(lifting)이나 손상(attack)이 발생되는 문제점이 있다.Therefore, in order to solve this problem, a photoresist removal process called a descum is applied. However, the photoresist removal process has a faster vertical photoresist ratio than a side photoresist ratio so that the remaining photoresist thickness in the ferry region is lowered and then wetted. When etching, there is a problem in that the photoresist lifting or lifting occurs.
본 발명의 목적은 감광막패턴을 이용하여 페리영역은 덮고 셀영역의 게이트전극 위의 옥사이드막만을 제거한 다음, 마이크로파를 공급한 상태에서 CF4 및 O2가스를 공급하여 상기 감광막패턴을 제거하여 감광막패턴의 측면식각비와 수직식각비를 일정하게 유지시킴으로써, 감광막패턴을 제거하기 위한 애슁타겟을 감소시킬 수 있는 반도체소자의 제조방법을 제공하려는 것이다.An object of the present invention is to remove the oxide film on the gate electrode of the cell region by covering the ferry region by using the photoresist pattern, and then supply the CF4 and O2 gas in the state of microwave supply to remove the photoresist pattern to the side of the photoresist pattern. By maintaining the etch ratio and the vertical etch ratio constant, to provide a method for manufacturing a semiconductor device that can reduce the asset target for removing the photosensitive film pattern.
상기 목적을 달성하고자, 본 발명에 따른 반도체소자의 제조방법은 셀영역과 페리영역이 정의된 반도체기판을 제공하는 단계와, 기판 위에 각각의 워드라인을 형성하는 단계와, 워드라인을 포함한 기판 전면에 버퍼산화막, 제 2실리콘 질화막 및 실리콘 산화막의 3중 적층 구조의 스페이서를 형성하는 단계와, 스페이서를 포함한 기판 전면에 상기 셀영역은 노출시키고 상기 페리영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막패턴을 마스크로 하고 상기 기판 전면에 CH3OH 및 HF 가스를 공급하여 셀영역의 실리콘 산화막을 제거하는 단계와, 마이크로파를 공급한 상태에서 CF4 및 O2가스를 공급하여 상기 감광막 패턴을 에슁하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of providing a semiconductor substrate having a cell region and a ferry region defined, forming each word line on the substrate, the front surface of the substrate including the word line Forming a spacer having a triple stacked structure of a buffer oxide film, a second silicon nitride film, and a silicon oxide film, exposing the cell region on the entire surface of the substrate including the spacer, and forming a photoresist pattern covering the ferry region; Removing the silicon oxide film in the cell region by supplying CH3OH and HF gas to the entire surface of the substrate using a pattern as a mask, and supplying CF4 and O2 gas under microwave supply to etch the photoresist pattern. It is characterized by.
상기 감광막패턴을 에슁하는 공정은 측면식각과 수직식각이 1;1 비율을 유지하는 것이 바람직하다.In the process of etching the photoresist pattern, the side etching and the vertical etching are preferably maintained at a ratio of 1: 1.
상기 에슁공정은 CF4:O2의 비율은 1:2 이상으로 하고, 파워를 500Wm, 압력은 500mTorr이상으로 하여 측면 식각율을 증가시키는 것이 바람직하다.In the etching process, the ratio of CF4: O2 is 1: 2 or more, the power is 500Wm, and the pressure is 500mTorr or more.
본 발명에 따르면, 감광막에 대한 측면 에슁비과 수직한 에슁비를 1;1로 형성시켜, 에싱타겟을 감소시킴으로써, 페리지역에 잔류된 감광막 두께를 기존보다 증가시켜 이후의 습식액에 의한 손상을 방지한다.According to the present invention, by forming the vertical ratio and the vertical ratio of the side to the photoresist to 1, by reducing the ashing target, to increase the thickness of the photoresist remaining in the ferry region than before to prevent damage by the subsequent wet liquid do.
(실시예)(Example)
도 1a 내지 도 1d는 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다. 1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
본 발명에 따른 반도체소자의 제조방법은, 도 1a에 도시된 바와 같이, 먼저 셀영역과 페리영역이 구비된 반도체기판(1)을 제공한다. 이어, 상기 기판(1) 전면에 각각의 워드라인(G)을 형성한다. 이때, 상기 워드라인(G)은 폴리실리콘층, 텅스텐 실리사이드층 및 하드마스크인 제 1실리콘질화막의 3중 적층 구조를 가진다. In the method of manufacturing a semiconductor device according to the present invention, as shown in FIG. 1A, first, a
이어, 상기 워드라인(G)을 포함한 기판(1) 전면에 버퍼산화막(3), 제 2실리콘 질화막(5) 및 실리콘산화막(7)을 차례로 형성하여 워드라인(G)을 덮는 3중 스페이서를 형성한다. Subsequently, a buffer spacer 3, a second silicon nitride layer 5, and a silicon oxide layer 7 are sequentially formed on the entire surface of the
그런 다음, 도 1b에 도시된 바와 같이, 상기 결과물 위에 감광막을 도포하고 노광 및 현상하여 셀영역은 노출시키고 페리영역은 덮는 감광막패턴(20)을 형성한다. 이후, 상기 감광막패턴(20)을 포함한 기판을 챔버(30) 내로 로딩(loading)시킨다. 이때, 상기 챔버의 내부는 60∼80℃ 온도 및 100 ∼300Torr압력으로 유지한 상태에서, CH3OH 및 HF의 혼합가스를 유입된다. 또한, 상기 CH3OH는 핫(hot)N2 버블링(bubbling)을 이용하여 증기화한 후, 100∼200sccm 유량으로 식각챔버 내루에 유입시키고, 상기 HF는 50∼100sccm의 유량으로 유입시킨다.Then, as illustrated in FIG. 1B, a photoresist film is coated, exposed and developed on the resultant to form a
한편, 상기 식각챔버 내부에서의 반응을 알아보면, 상기 감광막 패턴(20)을 마스크로 하고 상기 기판(1) 전면에 공급되는 CH3OH 및 HF의 혼합가스는 상기 셀영역의 실리콘 산화막(7)과 반응하여 이를 제거시킨다. On the other hand, when the reaction inside the etching chamber is examined, the mixed gas of CH3OH and HF supplied to the entire surface of the
상기 CH3OH 및 HF의 혼합가스와 실리콘산화막(7) 간의 반응은 하기 (Ⅰ)식과 같다. 20∼9:1BOE 등의 습식액에서 상대적으로 식각비가 낮고 측면 식각이 작은 HF가스를 사용하여 실리콘산화막(7)을 식각할 경우, 하부의 기판(1), 버퍼산화막(3), 제 2실리콘 질화막(5) 및 실리콘산화막(7)의 계면에서 발생할 수 있는 막간의 스트레스(stress)에 의해 질화막 스페이서에 마이크로 크랙 및 리프팅을 억제할 수 있다. The reaction between the mixed gas of CH3OH and HF and the silicon oxide film 7 is represented by the following formula (I). When the silicon oxide film 7 is etched using a HF gas having a relatively low etch ratio and a small side etch in a wet liquid such as 20 to 9: 1 BOE, the
4HF + CH3OH + SiO2 →SiF4 + 2H2O + CH3OH ‥‥‥‥‥‥(Ⅰ)4HF + CH3OH + SiO2 → SiF4 + 2H2O + CH3OH ‥‥‥‥‥‥‥ (Ⅰ)
이어, 도 1c에 도시된 바와 같이, 상기 셀영역의 실리콘 산화막(7)이 제거된 기판(1)을 식각챔버로부터 언로딩(unloading)시킨 다음, 페리영역의 감광막패턴(20) 에슁공정을 진행한다. 이때, 상기 페리영역의 감광막패턴(20) 에슁공정은, 감광막패턴(20)을 포함한 기판(1)에 마이크로파를 공급한 상태에서 산소(O2)가스와 CF4가스를 공급시켜 상기 페리영역의 감광막패턴(20)을 에슁처리한다.Subsequently, as shown in FIG. 1C, the
그런 다음, 상기 페리영역의 감광막패턴(20)의 에슁공정이 완료된 기판 위에 제 3실리콘 질화막(미도시)을 증착하여 셀영역의 제 2실리콘 질화막(5)의 두께를 높일 수도 있다. Thereafter, a third silicon nitride film (not shown) may be deposited on the substrate on which the etching process of the
이 후, 도 1d에 도시된 바와 같이, 상기 결과물 전면에 갭필용산화막(10)을 형성한 후, 상기 셀영역의 갭필용산화막(10)의 일부를 선택적으로 식각하여 워드라인(G)들 사이의 기판(1)을 노출시키는 도전플러그용 콘택(11)을 형성한다. After that, as shown in FIG. 1D, a gap
본 발명에서는 기존의 공정에서 처럼 플라즈마 알.에프 파워를 사용하지 않고 마이크로파를 인가한 상태에서 O2가스와 함께 CF4가스를 사용하고, 감광막패턴에 대한 에슁비를 수평한 방향과 수직한 방향에서 1;1로 진행함으로써, 게이트라인 사이에 잔류된 감광막까지도 제거할 수 있다. In the present invention, CF4 gas is used together with O2 gas in the state where microwave is applied without using plasma R.F power as in the conventional process, and the ratio of the ratio for the photosensitive film pattern is 1 in the horizontal and vertical direction; By proceeding to 1, even the photosensitive film remaining between the gate lines can be removed.
한편, 본 발명에서는 식각가스로서 CH4 , O2가스를 공급하면서 파워를 500Wm으로, 압력을 500mTorr로 유지시켜 감광막패턴 에슁공정을 진행함으로써, 게이트라인 사이의 골에 해당되는 부분에 잔류된 감광막까지도 제거할 수 있다. 또한, 감광막에 대한 측면 에슁비과 수직한 에슁비를 1;1로 형성시켜, 게이트전극 사이에 잔류된 감광막을 제거하기 위한 에싱타겟을 기존에 비해 감소시키고, 이에따라 페리 지역에 잔류된 감광막 두께를 기존보다 증가시켜 이 후의 습식액에 의한 손상을 방지한다. On the other hand, in the present invention, by supplying CH4, O2 gas as an etching gas while maintaining the power to 500Wm, pressure to 500mTorr to proceed the photoresist pattern etching process, even the photoresist remaining in the portion corresponding to the valley between the gate line can be removed. Can be. In addition, by forming the ratio of the vertical to the side of the photoresist perpendicular to the ratio of 1 to 1, reducing the ashing target for removing the photoresist remaining between the gate electrode compared with the conventional, thereby reducing the thickness of the photoresist remaining in the ferry region Further increase to prevent damage by subsequent wet liquid.
이상에서와 같이, 본 발명은 마이크로파를 인가한 상태에서 CH4 , O2가스를 공급시켜 감광막패턴을 에슁하고, 상기 감광막패턴에 대한 에슁비를 수평한 방향과 수직한 방향에서 1:1수준으로 하여 에슁타겟을 기존보다 감소시켜 게이트라인 사이에 잔류된 감광막까지도 제거함으로써, 페리지역에 남는 감광막의 두께를 기존보다 증가시킬 수있어 이후의 습식식각 공정에 의한 손상을 방지한다. 따라서, 감광막 리프팅이나 손상을 방지할 수 있는 이점이 있다.As described above, according to the present invention, CH4 and O2 gas are supplied in the state of applying microwaves to etch the photoresist pattern, and the etch ratio with respect to the photoresist pattern is 1: 1 in the direction perpendicular to the horizontal direction. By reducing the target and removing the photoresist remaining between the gate lines, the thickness of the photoresist remaining in the ferry area can be increased than before, thereby preventing damage by the subsequent wet etching process. Therefore, there is an advantage that can prevent the photosensitive film lifting or damage.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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