KR100458085B1 - Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic - Google Patents
Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic Download PDFInfo
- Publication number
- KR100458085B1 KR100458085B1 KR1019970029021A KR19970029021A KR100458085B1 KR 100458085 B1 KR100458085 B1 KR 100458085B1 KR 1019970029021 A KR1019970029021 A KR 1019970029021A KR 19970029021 A KR19970029021 A KR 19970029021A KR 100458085 B1 KR100458085 B1 KR 100458085B1
- Authority
- KR
- South Korea
- Prior art keywords
- gas
- semiconductor device
- flow rate
- photoresist
- chf
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000005012 migration Effects 0.000 title abstract description 5
- 238000013508 migration Methods 0.000 title abstract description 5
- 239000007789 gas Substances 0.000 claims abstract description 40
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 5
- 239000012495 reaction gas Substances 0.000 claims abstract description 4
- 239000000654 additive Substances 0.000 claims abstract description 3
- 230000000996 additive effect Effects 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 제조 분야에 관한 것으로, 특히 반도체 장치 제조시 산화막 또는 산화막/질화막 이중막 식각 공정에 관한 것이다.TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to an oxide film or an oxide / nitride double layer etching process in manufacturing a semiconductor device.
반도체 장치의 고집적화에 따라 리쏘그라피(lithography) 공정은 한계 해상도를 높이기 위하여 DUV(Deep Ultra Violet) 광원을 사용하게 되었다.With the higher integration of semiconductor devices, lithography processes have used deep ultra violet (DUV) light sources to increase the marginal resolution.
종래의 DUV 리쏘그라피 공정에서는 DUV용 포토레지스트(photoresist)를 사용하게 되는데, DUV 용 포토레지스트를 사용한 포토레지스트 패턴을 형성하고, C2F6 등의 CxFy 가스를 주 식각 가스로 사용하여 콘택홀 형성할 때, 도 1에 도시된 바와 같이 콘택홀 측벽에 찰흔(striation) 현상이 발생한다. 미설명 도면 부호 10은 콘택홀에 의해 노출된 실리콘 기판을 나타낸 것이며, 11은 층간절연막을 나타낸 것이다.In the conventional DUV lithography process, a photoresist for DUV is used. A photoresist pattern using a photoresist for DUV is formed, and C x F y gas such as C 2 F 6 is used as a main etching gas. When forming the contact hole, a scratch phenomenon occurs on the sidewall of the contact hole as shown in FIG. 1.
찰흔 현상은 이전의 i-라인용 포토레지스트를 사용하여 콘택홀을 식각할 때에는 발생하지 않았던 DUV 공정에서만 발생하는 현상이다. Scratching occurs only in DUV processes that did not occur when etching contact holes using photoresist for i-line.
그런데 이러한 찰흔 현상은 후속 공정인 접착층/확산방지막인 Ti/TiN 증착시에 찰흔에 의한 굴곡속에 잘 매립되지 않아 누설 전류 발생의 원인이 되고, 전자 이동(electromigration) 특성, 스트레스 이동(stress migration) 특성 등을 열화시킴으로서 반도체 장치의 신뢰도(reliability)를 저하시키는 문제점이 있었다.However, these scratches are not buried in the bends due to the scratches during the deposition of Ti / TiN, which is an adhesive layer / diffusion prevention film, which causes leakage currents, and also causes electromigration and stress migration. There is a problem of lowering the reliability of the semiconductor device by deteriorating the back.
본 발명은 DUV용 포토레지스트를 식각장벽으로하여 층간절연막을 식각할 때 패턴 측벽에서 발생하는 찰흔 현상을 방지하는 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which prevents scratches occurring on the sidewalls of a pattern when an interlayer insulating layer is etched using a DUV photoresist as an etch barrier.
상기 목적을 달성하기 위한 본 발명의 일 측면에 따르면, 반도체 기판 상에 형성된 소정의 하부층 상부에 층간절연막을 형성하는 제1 단계; 전체구조 상부에 DUV용 포토레지스트를 도포하고 소정의 포토레지스트 패턴을 형성하는 제2 단계; 및 상기 포토레지스트 패턴을 식각 장벽으로 하여 상기 층간절연막을 식각하되, CHF3 가스 및 CO 가스를 주 반응 가스로 하고, CxFy 가스 및 Ar 가스를 첨가 가스로 사용하는 플라즈마 식각 방식으로 식각하는 제3 단계를 포함하는 반도체 장치 제조 방법이 제공된다.According to an aspect of the present invention for achieving the above object, a first step of forming an interlayer insulating film on a predetermined lower layer formed on a semiconductor substrate; A second step of applying a photoresist for DUV on the entire structure and forming a predetermined photoresist pattern; And etching the interlayer dielectric layer using the photoresist pattern as an etch barrier, using a plasma etching method using CHF 3 gas and CO gas as a main reaction gas, and using C x F y gas and Ar gas as additive gases. A semiconductor device manufacturing method comprising a third step is provided.
이하, 첨부된 도면을 참조하여 본 발명을 상술한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 일실시예에 따른 콘택홀 식각 공정 단면도를 나타낸 것이다.2 is a cross-sectional view of a contact hole etching process according to an exemplary embodiment of the present invention.
도 2는 소정의 하부층 형성을 마친 실리콘 기판(20) 상에 형성된 산화막으로 구성된 층간절연막(21)을 형성하고, 그 상부에 DUV용 포토레지스트를 도포한 후 콘택홀 형성을 위한 포토레지스트 패턴(22)을 형성한 다음, 이를 식각 장벽으로하여 하부의 층간절연막(21)을 선택적 식각함으로서 콘택홀을 형성한 단면을 나타낸 것이다. FIG. 2 shows an
여기서 콘택홀 식각은 CHF3 가스 및 CO 가스를 주 반응 가스로 하는 플라즈마 방식을 사용하는데, 자세한 공정 조건을 살펴보면 다음과 같다.Here, the contact hole etching uses a plasma method using CHF 3 gas and CO gas as the main reaction gas, and detailed process conditions are as follows.
CHF3/CO 가스 유량비(flow rate)는 0.8~1.2 정도로 유지하며, CHF3 가스량은 30~100 sccm, CO 가스량은 30~100 sccm, 전체 기체량은 60~200 sccm 정도로 유지한다. 또한 챔버의 소오스 전력(soure power)은 2000~2800 W, 바이어스 전력(bias power)은 1000~1800 W 범위로 사용하며, 실리콘 루프(silicon roof)의 온도는 240~280 ℃, 월(wall) 온도는 200~220 ℃, 음전극(cathode)의 온도는 -10~10 ℃로 유지하며, 챔버 압력은 3~10 mTorr 범위에서 조절한다.CHF 3 / CO gas flow rate is maintained at about 0.8 ~ 1.2, CHF 3 gas amount of 30 ~ 100 sccm, CO gas amount of 30 ~ 100 sccm, total gas volume of about 60 ~ 200 sccm. In addition, the source power (soure power) of the chamber (2000 ~ 2800 W, the bias power (bias power) is used in the range of 1000 ~ 1800 W, silicon roof temperature is 240 ~ 280 ℃, wall temperature 200 ~ 220 ℃, the temperature of the cathode (cathode) is maintained at -10 ~ 10 ℃, the chamber pressure is adjusted in the range of 3 ~ 10 mTorr.
에스펙트 비(aspect ratio)가 큰 콘택홀을 식각할 경우에는 CHF3/CO 가스 유량비를 0.8∼1,0 sccm으로 감소시켜 식각한다. CHF3/CO 가스 유량비가 감소되면 포토레지스트에 대한 식가 선택비가 감소하는데, CxFy 가스 및 Ar 가스를 더 첨가하여 식각함으로서 실리콘 기판(20) 및 포토레지스트 패턴(22)과의 식각 선택비를 크게 유지할 수 있다. 이때 CxFy 가스의 유량은 10∼30 sccm, Ar 가스의 유량은 10∼50 sccm으로 조절한다.When etching a contact hole having a large aspect ratio, the CHF 3 / CO gas flow rate ratio is reduced to 0.8-1,0 sccm to be etched. When the CHF 3 / CO gas flow rate ratio decreases, the etch selectivity for the photoresist decreases, and the etch selectivity with the
도 3은 본 발명의 다른 실시예에 따른 콘택홀 식각 공정 단면도를 나타낸 것으로, 층간절연막을 질화막(31) 및 산화막(32)로 형성한 경우의 콘택홀 식각 공정을 도시한 것이다. 3 is a cross-sectional view of a contact hole etching process according to another embodiment of the present invention, and illustrates a contact hole etching process when the interlayer insulating layer is formed of the
미설명 도면 부호 30은 실리콘 기판을 나타낸 것이며, 33은 DUV용 포토레지스트를 사용한 포토레지스트 패턴을 나타낸 것이다.Reference numeral 30 denotes a silicon substrate, and 33 denotes a photoresist pattern using a photoresist for DUV.
여기서 콘택홀 식각은 본 발명의 일실시예와 거의 같은 조건으로 공정을 진행하는데, 다만 CHF3 가스 및 CO 가스의 유량은 각각 30~100 sccm으로 일실시예에서와 같이 하고, 다만 CHF3/CO 가스 유량비를 0.6~1.0으로 조절한다. 왜냐하면, CHF3/CO 유량비가 "1.0" 보다 작을 경우에는 질화막(31)의 식각이 거의 일어나지 않기 때문이다.In this case, the contact hole etching process is performed under almost the same conditions as in the embodiment of the present invention, except that the flow rates of CHF 3 gas and CO gas are 30-100 sccm, respectively, as in the embodiment, except that CHF 3 / CO Adjust the gas flow rate to 0.6 to 1.0. This is because the etching of the
상기한 실시예에 나타난 바와 같이 본 발명은 i-라인용 포토레지스트뿐만 아니라, DUV용 포토레지스트를 사용할 때에도 찰흔 현상을 방지할 수 있으며, 특히 DUV용 포토레지스트에 대한 층간절연막의 식각 선택비가 8 이상을 나타내므로 효과적인 콘택홀 공정을 진행할 수 있게 한다.As shown in the above embodiment, the present invention can prevent scratches when using not only an i-line photoresist but also a DUV photoresist, and in particular, the etching selectivity of the interlayer insulating film with respect to the DUV photoresist is 8 or more. It is possible to proceed an effective contact hole process.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기한 바와 같이 본 발명은 DUV용 포토레지스트를 사용한 층간절연막의 식각시 발생하는 찰흔 현상을 방지하는 효과가 있으며, 이로 인하여 누설 전류를 감소시키고, 전자 이동 특성 및 스트레스 이동 특성을 개선함으로서 반도체 장치의 신뢰도를 향상시키는 효과가 있다.As described above, the present invention has an effect of preventing scratches occurring during etching of an interlayer insulating film using a DUV photoresist, thereby reducing leakage current, improving electron transfer characteristics, and stress transfer characteristics. There is an effect of improving the reliability.
도 1은 종래 기술에 따라 형성된 콘택홀 평면도.1 is a plan view of a contact hole formed according to the prior art.
도 2는 본 발명의 일실시예에 따른 콘택홀 식각 공정 단면도.Figure 2 is a cross-sectional view of the contact hole etching process according to an embodiment of the present invention.
도 3은 본 발명의 다른 실시예에 따른 콘택홀 식각 공정 단면도.3 is a cross-sectional view of a contact hole etching process according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
30 : 실리콘 기판30: silicon substrate
31 : 질화막31: nitride film
32 : 산화막32: oxide film
33 : 포토레지스트 패턴33: photoresist pattern
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029021A KR100458085B1 (en) | 1997-06-30 | 1997-06-30 | Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970029021A KR100458085B1 (en) | 1997-06-30 | 1997-06-30 | Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990004861A KR19990004861A (en) | 1999-01-25 |
| KR100458085B1 true KR100458085B1 (en) | 2005-02-23 |
Family
ID=37376871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970029021A KR100458085B1 (en) | 1997-06-30 | 1997-06-30 | Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100458085B1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05247673A (en) * | 1990-10-19 | 1993-09-24 | Tokyo Electron Ltd | Method for etching body to be treated incorporating oxide part and nitride part |
| JPH06132252A (en) * | 1992-10-16 | 1994-05-13 | Toshiba Corp | Dry etching method |
| JPH06208975A (en) * | 1993-01-11 | 1994-07-26 | Toshiba Corp | Etching method |
| KR950021026A (en) * | 1993-12-08 | 1995-07-26 | 김주용 | Phase change mask |
| KR970030387A (en) * | 1995-11-22 | 1997-06-26 | 김광호 | Contact Forming Method of Semiconductor Device |
-
1997
- 1997-06-30 KR KR1019970029021A patent/KR100458085B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05247673A (en) * | 1990-10-19 | 1993-09-24 | Tokyo Electron Ltd | Method for etching body to be treated incorporating oxide part and nitride part |
| JPH06132252A (en) * | 1992-10-16 | 1994-05-13 | Toshiba Corp | Dry etching method |
| JPH06208975A (en) * | 1993-01-11 | 1994-07-26 | Toshiba Corp | Etching method |
| KR950021026A (en) * | 1993-12-08 | 1995-07-26 | 김주용 | Phase change mask |
| KR970030387A (en) * | 1995-11-22 | 1997-06-26 | 김광호 | Contact Forming Method of Semiconductor Device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990004861A (en) | 1999-01-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7183198B2 (en) | Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes | |
| KR100502673B1 (en) | METHOD FOR FORMING Ti LAYER AND BARRIER METAL LAYER OF SEMICONDUCTOR DEVICE | |
| KR100458085B1 (en) | Method for fabricating semiconductor device to reduce leakage current and improve electron migration characteristic and stress migration characteristic | |
| US20050272232A1 (en) | Method for forming gate electrode of semiconductor device | |
| JP3116276B2 (en) | Photosensitive film etching method | |
| GB2320613A (en) | Interconnect fabrication | |
| KR100495909B1 (en) | Method for fabrication of semiconductor device using ArF photo-lithography capable of protecting tapered profile of hardmask | |
| KR20010045401A (en) | Method of forming for semiconductor device | |
| KR101037690B1 (en) | Method for fabricating semiconductor device | |
| US6743726B2 (en) | Method for etching a trench through an anti-reflective coating | |
| KR20000045442A (en) | Fabrication method of contacts for semiconductor device | |
| KR20040077272A (en) | Method of etching silicon nitride film | |
| KR19990011466A (en) | Dry etching method for manufacturing semiconductor device | |
| KR100788587B1 (en) | Method of manufacturing flash memory device | |
| KR20010058959A (en) | Method for manufacturing semiconductor device | |
| KR100548564B1 (en) | method for forming bit line | |
| KR100458081B1 (en) | Method for forming via hole of semiconductor device to improve step coverage of metal layer | |
| KR100256798B1 (en) | Forming method of self-align contact of semiconductor devices | |
| KR100249012B1 (en) | Method for forming contact hole | |
| KR20020040270A (en) | Etching Method of Semiconductor Device for Contact | |
| KR20020001113A (en) | method for manufacturing semiconductor devices | |
| KR20030057720A (en) | Method of forming contact plug for semiconductor device | |
| KR20020048627A (en) | Method for forming polysilicon plug in semiconductor device | |
| KR20050022169A (en) | Method for forming isolation layer of semiconductor device | |
| KR20040006480A (en) | Method for forming gate spacer of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101025 Year of fee payment: 7 |
|
| LAPS | Lapse due to unpaid annual fee |