WO2013018580A1 - 電界効果トランジスタ - Google Patents
電界効果トランジスタ Download PDFInfo
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- WO2013018580A1 WO2013018580A1 PCT/JP2012/068669 JP2012068669W WO2013018580A1 WO 2013018580 A1 WO2013018580 A1 WO 2013018580A1 JP 2012068669 W JP2012068669 W JP 2012068669W WO 2013018580 A1 WO2013018580 A1 WO 2013018580A1
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- 230000005669 field effect Effects 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 239000000203 mixture Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 description 12
- 229910002704 AlGaN Inorganic materials 0.000 description 11
- 239000002131 composite material Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000010030 laminating Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
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- 238000010586 diagram Methods 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000010953 base metal Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to a heterostructure field effect transistor (HFET) used for a power device or the like.
- HFET heterostructure field effect transistor
- FIG. 1 is a side sectional view showing the structure of a conventional HFET 10P shown in Patent Document 1. As shown in FIG.
- a buffer layer 30P made of GaN is stacked on the surface of the base substrate 20P made of sapphire or the like.
- An electron transit layer 40P made of undoped GaN is stacked on the surface of the buffer layer 30P.
- a barrier layer 50P made of undoped AlGaN is stacked on the surface of the electron transit layer 40P.
- a heterostructure is realized by the undoped GaN of the electron transit layer 40P and the undoped AlGaN of the barrier layer 50P.
- a source electrode 900S and a drain electrode 900D are formed on the surface of the barrier layer 50P at a predetermined distance. Between the source electrode 900S and the drain electrode 900D on the surface of the barrier layer 50P, a gate electrode 900G is formed so as to be separated from each of the source electrode 900S and the drain electrode 900D.
- a thin film region 500P thinner than other regions is provided immediately below the gate electrode 900G.
- FIG. 2 is a side sectional view showing the structure of the conventional HFET 10Q shown in Patent Document 2.
- An AlN layer 32Q and a buffer layer 30Q are sequentially stacked on the surface of the base substrate 20Q.
- the buffer layer 30Q is made of GaN and AlGaN.
- a channel layer 60Q made of a p-GaN layer is stacked on the surface of the buffer layer 30Q.
- p-GaN is p-type doped GaN.
- An electron transit layer 40Q made of undoped GaN is stacked on the surface of the channel layer 60Q.
- An n-type doped AlGaN layer 51Q is stacked on the surface of the electron transit layer 40Q.
- a source electrode 900S and a drain electrode 900D are formed on the surface of the n-type doped AlGaN layer 51Q with a predetermined distance therebetween.
- a gate electrode 900G is formed separately from the source electrode 900S and the drain electrode 900D.
- a hole penetrating the n-type doped AlGaN layer 51Q and the electron transit layer 40Q in the stacking direction is formed.
- An insulating layer 70Q is formed on the inner wall surface of the hole and the surface of the electron supply layer 51, and the gate electrode 900G is formed at a height that fills the hole covered with the insulating layer 70Q.
- a recess structure 700Q in which the n-type doped AlGaN layer 51Q and the electron transit layer 40Q are divided is formed immediately below the gate electrode 900G.
- the threshold voltage Vth is determined by the thickness of the thin film region 500P of the barrier layer 50P. Therefore, a desired threshold voltage Vth cannot be obtained unless the thickness of the thin film region 500P can be controlled with high accuracy. However, it is difficult to stably and accurately manufacture an HFET having a desired threshold voltage Vth due to the thickness accuracy of the manufacturing process.
- an HFET having a desired threshold voltage Vth can be manufactured more stably than the HFET 10P of Patent Document 1, but a p-type semiconductor is used for the channel layer, and the on-resistance is large. There is a possibility of becoming.
- an object of the present invention is to provide a heterostructure field effect transistor (HFET) that can stably realize a positive threshold voltage Vth and has low on-resistance.
- HFET heterostructure field effect transistor
- the field effect transistor of the present invention includes a lower barrier layer, a channel layer, an upper barrier layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer.
- the lower barrier layer is made of Al x Ga 1-x N disposed on the substrate.
- the channel layer is made of GaN disposed on the surface of the lower barrier layer opposite to the substrate.
- the upper barrier layer is disposed on the surface of the channel layer opposite to the lower barrier layer.
- the upper barrier layer is made of Al y Ga 1-y N having an Al composition ratio exceeding the Al composition ratio of the lower barrier layer.
- the source electrode and the drain electrode are disposed on the surface of the upper barrier layer opposite to the channel layer.
- the insulating layer is disposed in the region of the upper barrier layer on the surface where the source electrode and the drain electrode are disposed, excluding the region where the source electrode and the drain electrode are disposed.
- the gate electrode is disposed via an insulating layer.
- the field effect transistor of the present invention has a recess structure in which the insulating layer is formed to reach the channel layer through the upper barrier layer in the region immediately below the gate electrode.
- an AlGaN / GaN / AlGaN three-layer structure including an upper barrier layer made of Al y Ga 1-y N, a channel layer made of GaN, and a lower barrier layer made of Al x Ga 1-x N, and an upper portion
- the threshold voltage is higher than 0 V and can be set to 1.0 V (volt) or more by the recess structure directly under the gate electrode made of an insulating layer that penetrates the barrier layer and reaches the channel layer.
- At least a part of GaN constituting the channel layer is n-type doped.
- This configuration can further improve the electrical conductivity when turned on. That is, the drain current at the on time can be increased.
- GaN is likely to be n-type rather than p-type due to the self-compensation effect of the wide gap semiconductor, so that a field effect transistor can be manufactured more easily than the conventional example 2 shown in Patent Document 2.
- the channel layer of the field effect transistor of the present invention is preferably composed of a plurality of GaN layers. This configuration shows a specific configuration example of the channel layer.
- the field effect transistor of the present invention preferably has the following configuration.
- the channel layer includes a first channel layer on the upper barrier layer side and a second channel layer on the lower barrier layer side.
- the n-type doping concentration in the first channel layer is smaller than the n-type doping concentration in the second channel layer.
- the insulating layer is formed in a shape that does not reach the second channel layer.
- the channel layer is formed of the first channel layer and the second channel layer having different n-type doping concentrations.
- the first channel layer is made of undoped GaN.
- the second channel layer is made of n-type doped GaN.
- the insulating layer is formed only up to the first channel layer made of undoped GaN.
- the threshold voltage is substantially constant and stable regardless of the depth of the insulating layer. Therefore, a desired threshold voltage can be accurately and reliably realized without depending on the recess structure formation accuracy of the manufacturing process. That is, a field effect transistor having a desired threshold voltage can be stably manufactured.
- HFET heterostructure field effect transistor
- FIG. 10 It is side surface sectional drawing which shows the structure of the conventional HFET10P shown in patent document 1.
- FIG. It is side surface sectional drawing which shows the structure of the conventional HFET10Q shown in patent document 2.
- FIG. It is side surface sectional drawing which shows the structure of HFET10 which concerns on this embodiment.
- the gate voltage-drain current characteristic of the HFET 10 according to the present embodiment is shown. It is a figure which shows the relationship between the depth of the recess structure 700, and the threshold voltage Vth. It is a figure which shows the change of the threshold voltage Vth and drain current by the change of the thickness D (nGaN) of the 2nd channel layer 62.
- FIG. It is a figure which shows the change of the threshold voltage Vth and drain current by the change of the carrier concentration n (nGaN) of the 2nd channel layer 62.
- FIG. It is sectional drawing which shows typically the structure in each process of the manufacturing process of HFET10 which concerns on this embodiment.
- FIG. 3 is a side sectional view showing the structure of the HFET 10 according to the embodiment of the present invention.
- FIG. 4 shows the gate voltage-drain current characteristics of the HFET 10 according to this embodiment and the conventional HFET (recess structure only).
- the HFET 10 includes a base substrate 20.
- the base substrate 20 is made of Si.
- the thickness of the base substrate 20 may be set as appropriate according to the height of the HFET 10 or the like.
- the lattice relaxation layer 30 is disposed on the upper surface of the base substrate 20.
- the lattice relaxation layer 30 is a layer that relaxes lattice mismatch between the base substrate 20 made of Si and a lower barrier layer 80 made of Al x Ga 1-x N, which will be described later. Any composition is possible.
- the lattice relaxation layer 30 may be appropriately set according to the height of the HFET 10 or the like.
- the lower barrier layer 80 is disposed on the upper surface of the lattice relaxation layer 30.
- the upper surface of the lattice relaxation layer 30 is the surface opposite to the surface on which the base substrate 20 is disposed in the lattice relaxation layer 30.
- the lower barrier layer 80 is made of Al x Ga 1-x N. At this time, the composition ratio of Al and Ga is determined so that x satisfies the condition (0 ⁇ x ⁇ 0.20).
- the thickness of the lower barrier layer 80 is a predetermined value of 500 [nm] or more.
- the channel layer 60 is disposed on the upper surface of the lower barrier layer 80.
- the upper surface of the lower barrier layer 80 is a surface opposite to the surface on which the lattice relaxation layer 30 is provided in the lower barrier layer 80.
- the channel layer 60 has a two-layer structure of a first channel layer 61 and a second channel layer 62.
- the second channel layer 62 contacts the lower barrier layer 80.
- the channel layer 60 is made of GaN.
- the first channel layer 61 is made of undoped GaN that is not doped with other elements
- the second channel layer 62 is made of n-type doping doped with Si.
- the element to be doped is not limited to Si, but may be any element that can form n-type by doping GaN (for example, Ge or O).
- the channel layer is not limited to two layers, and may further include layers having different n-type doping concentrations.
- the thickness of the second channel layer 62 is appropriately determined according to a desired threshold voltage Vth and drain current Id, although the concept of detailed setting will be described later.
- the thickness of the first channel layer 61 is appropriately determined according to the formation accuracy of the recesses provided immediately below the gate electrode 900G when forming the recess structure. Specifically, when the recess for the recess structure is formed, the thickness is greater than the thickness that can include variations in the depth of the recess.
- the upper barrier layer 50 is disposed on the upper surface of the channel layer 60.
- the upper surface of the channel layer 60 is a surface of the channel layer 60 opposite to the surface on which the lower barrier layer 80 is disposed. In other words, it is the surface of the channel layer 60 opposite to the second channel 62 side of the first channel layer 61.
- the upper barrier layer 50 is made of Al y Ga 1-y N. At this time, the composition ratio of Al and Ga is determined so that y satisfies the condition of (0.15 ⁇ y ⁇ 0.30).
- the thickness of the upper barrier layer 50 is a predetermined value of 10 [nm] or more and 30 [nm] or less. However, the Al content of the upper barrier layer 50 is set higher than the Al content of the lower barrier layer 80.
- the drain electrode 900 ⁇ / b> D and the source electrode 900 ⁇ / b> S are formed on the upper surface of the upper barrier layer 50 at a predetermined interval.
- the upper surface of the upper barrier layer 50 is a surface opposite to the surface on which the channel layer 60 is provided in the upper barrier layer 50.
- An insulating layer 70 is formed between the drain electrode 900D and the source electrode 900S on the upper surface of the upper barrier layer 50.
- the insulating layer 70 is made of silicon nitride (SiN), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), or the like.
- the gate electrode 900G is formed at a predetermined position of the insulating layer 70 so as to sink a predetermined amount from the upper surface of the insulating layer 70 and to protrude a predetermined amount from the upper surface.
- the upper surface of the insulating layer 70 is a surface of the insulating layer 70 opposite to the upper barrier layer 50.
- the gate electrode 900G is formed between the drain electrode 900D and the source electrode 900S so as to be separated from the drain electrode 900D and the source electrode 900S.
- the gate electrode 900G is formed by using Ni as a base and laminating an electrode such as Au thereon.
- the drain electrode 900D and the source electrode 900S use Ti or Al as a base metal and Au or the like as an upper layer. It is formed by laminating these electrodes.
- a recess having a shape that penetrates the upper barrier layer 50 and reaches the middle in the height direction of the first channel layer 61 is formed in a predetermined range including directly under the gate electrode 900G. Yes.
- the insulating layer 70 is formed in a shape that extends to this recess.
- a recess structure 700 is realized immediately below the gate electrode 900G.
- the bottom surface of the recess structure 700 (the bottom surface of the recess) may be within a range in the height direction of the first channel layer 61 so as not to reach the second channel layer 62.
- the threshold voltage Vth of the HFET 10 can be made substantially 0 [V], similarly to the characteristic of the conventional configuration of FIG.
- the upper barrier layer 50 made of Al y Ga 1-y N (0.15 ⁇ y ⁇ 0.30) and Al x Ga 1-x N (0 ⁇ x ⁇ 0.20;
- a structure in which the channel layer 60 made of GaN is sandwiched between the lower barrier layer 80 made of x ⁇ y) is used. That is, the upper barrier layer 50 having a relatively high Al composition ratio is disposed on the electrode side of the channel layer 60, and the Al composition ratio is relatively opposite to the upper barrier layer 50 across the channel layer 60.
- a lower lower barrier layer 80 is disposed.
- the threshold voltage Vth can be further increased to a positive value of about several [V]. As a result, an HFET having a positive threshold voltage Vth can be realized more reliably.
- the number of electrons traveling through the channel layer can be increased by n-type doping the second channel layer 62 of the channel layer 60, as compared with undoped or p-type doping.
- the on-resistance can be lowered and the drain current can be increased.
- the channel layer 60 is configured by a laminated body of an undoped first channel layer 61 and an n-type doped second channel layer 62, and the recess structure 700 is formed by the first channel 61.
- the recess structure 700 is formed by the first channel 61.
- FIG. 5 is a diagram showing the relationship between the depth of the recess structure 700 and the threshold voltage Vth.
- the Al concentration of the lower barrier layer 80 is 8%
- the carrier concentration of the second channel layer 62 is 1.0 ⁇ 10 18 [1 / cm 3 ]
- the thickness of the second channel layer 62 is 15 [ nm].
- D (REC) 0 is set when the bottom surface of the recess structure 700 is at the boundary between the first channel layer 61 and the upper barrier layer 50, and D (REC) becomes a positive value as it is shallower. It is set so as to become negative as the depth increases.
- the threshold voltage Vth is constant at approximately 1 [V].
- FIG. 5 shows the characteristics under one condition, the characteristics of the threshold voltage Vth move in parallel in the direction in which the threshold voltage Vth increases or decreases even if each of the above conditions is changed. The inventor has confirmed through experimentation that there is only this. That is, the threshold voltage Vth becomes constant by setting the depth (bottom surface position) of the recess structure 700 within the height range of the first channel layer 61 as in the configuration of the present embodiment.
- the HFET 10 having such a structure can further adjust the threshold voltage Vth and the drain current by adjusting the thickness D (nGaN) of the second channel layer 62 and the carrier concentration n (nGaN). .
- FIG. 6A is a diagram illustrating a change in the threshold voltage Vth due to a change in the thickness D (nGaN) of the second channel layer 62.
- FIG. 6B is a diagram showing a change in drain current due to a change in the thickness D (nGaN) of the second channel layer 62.
- FIG. 6 shows a case where the Al concentration of the lower barrier layer 80 is 8% and the carrier concentration n (nGaN) of the second channel layer 62 is 1.0 ⁇ 10 18 [1 / cm 3 ].
- the threshold voltage Vth can be lowered by increasing the thickness D (nGaN) of the second channel layer 62.
- the threshold voltage Vth is 0.0 [V] because the threshold voltage Vth is approximately 24 [nm] to make the threshold voltage Vth positive. 20 [nm] or less.
- the thickness D (nGaN) may be set to about 15 [nm] to 20 [nm].
- a drain current can also be made high.
- FIG. 7A is a diagram showing changes in the threshold voltage Vth due to changes in the carrier concentration n (nGaN) of the second channel layer 62.
- FIG. 7B is a diagram showing changes in drain current due to changes in the carrier concentration n (nGaN) of the second channel layer 62.
- FIG. 7 shows a case where the Al concentration of the lower barrier layer 80 is 8% and the thickness D (nGaN) of the second channel layer 62 is 15 [nm].
- the carrier concentration n (nGaN) of the second channel layer 62 is increased, the carrier concentration n (nGaN) is 1.0 ⁇ 10 17 [1 / cm 3 ] or less.
- the threshold voltage Vth does not change, the threshold voltage Vth rapidly decreases to 0 [V] or less when the concentration exceeds this concentration.
- the drain current remains low, but when this concentration is exceeded. The drain current rises rapidly.
- nGaN carrier concentration in which the threshold voltage Vth is higher than 0 [V] in a region where the drain current rapidly increases. From this point, it is more preferable to set the carrier concentration to about 1.0 ⁇ 10 18 [1 / cm 3 ].
- the carrier concentration n (nGaN) is kept constant at 1.0 ⁇ 10 18 [1 / cm 3 ] and the thickness D (nGaN) is changed, and the thickness D (nGaN) is changed.
- the thickness D (nGaN) and the carrier concentration n (nGaN) are set to other values. It has been confirmed by the inventor that the above characteristics can be obtained.
- the threshold voltage Vth having a predetermined positive value is obtained.
- the HFET 10 having a low on-resistance can be easily realized.
- the first channel layer 61 is undoped. However, if the carrier concentration is significantly lower than that of the second channel layer 62, the above-described effects can be obtained even if n-type doping is performed. It is.
- FIG. 8 is a cross-sectional view schematically showing the structure in each process of the manufacturing process of the HFET 10 according to the present embodiment.
- the following forming process is performed in the state of a mother wafer in which a predetermined number of HFETs 10 are arranged on the main surface. Then, after all the following processes are completed, the process is divided into the HFETs 10.
- a base substrate 20 made of Si is prepared.
- a buffer layer 30 and a lower barrier layer are formed on one main surface of the base substrate 21 using a metal organic chemical vapor deposition method: MOCVD (Metal Organic Chemical Vapor Deposition) as shown in FIG. 80, the second channel layer 62, the first channel layer 61, and the upper barrier layer 50 are formed by epitaxial growth in this order.
- MOCVD Metal Organic Chemical Vapor Deposition
- the composite semiconductor substrate 810 is formed.
- the thickness of each layer of the composite semiconductor substrate 810 is appropriately set according to the function and specification of each layer as the HFET 10 as described above.
- the buffer layer 30 may be made of GaN, AlN or the like formed at a low temperature.
- an element isolation trench 800 for cutting out each HFET 10 from the mother wafer is formed.
- the depth of the element dividing trench 800 is up to the channel layer 60 in FIG. 8B, but is not limited thereto, and may be set as appropriate according to manufacturing conditions and the like.
- the source electrode 900S and the drain electrode 900D are formed on the surface of the upper barrier layer 50 in the composite semiconductor substrate 810 with a predetermined distance therebetween.
- the source electrode 900S and the drain electrode 900D are formed by laminating Ti or Al as a base metal and laminating Au as an upper layer. Thereby, a composite semiconductor substrate 811 with a source / drain is formed.
- the source / drain composite semiconductor substrate 811 is annealed to lower the contact resistance of the source electrode 900S and the drain electrode 900D.
- a predetermined region between the source electrode 900S formation position of the composite semiconductor substrate 811 with source / drain and the drain electrode 900D, in other words, the gate electrode 900G is formed in a later step.
- Recessed recesses 700 are formed by selectively dry etching the region. At this time, the recess for recess 700 is formed to a depth that penetrates the upper barrier layer 50 and does not reach the second channel layer 62, in other words, a depth such that the bottom surface of the recess is present in the first channel layer 61. Is done.
- an insulating layer 70 is formed on the surface of the upper barrier layer 50 including the region where the recess 710 for recessing is formed in the source / drain composite semiconductor substrate 811.
- the thickness of the insulating layer 70 is appropriately set according to the function and specifications.
- a gate electrode 900G is formed in the formation region of the recess 710 on the surface of the insulating layer 70.
- the gate electrode 900G is formed by laminating Ni as a base metal and laminating Au or the like thereon.
- the HFETs 10 arranged and formed on the mother wafer in this way are divided along the element dividing grooves 800 to be divided into individual pieces of the HFET 10 as shown in FIG. Thereby, a plurality of HFETs 10 are simultaneously formed from one mother wafer.
Abstract
Description
20,20P,20Q:ベース基板、
30,30P,30Q:バッファ層、
32Q:AlN層、
40P,40Q:電子走行層、
50,50P:上部障壁層、
51Q:n型ドープAlGaN層、
60,60Q:チャンネル層
70,70Q:絶縁層、
80:下部障壁層、
500P:薄膜領域、
700,700Q:リセス構造、
800:素子分離用溝、
810:複合半導体基板、
811:ソースドレイン付き複合半導体基板、
900G:ゲート電極、900S:ソース電極、900D:ドレイン電極
Claims (5)
- 基板上に配設されたAlxGa1-xNからなる下部障壁層と、
該下部障壁層の、前記基板と反対側の面に配設されたGaNからなるチャンネル層と、
該チャンネル層の、前記下部障壁層と反対側の面に配設された、前記下部障壁層のAl組成比を超えるAl組成比のAlyGa1-yNからなる上部障壁層と、
該上部障壁層の、前記チャンネル層と反対側の面に配設されたソース電極およびドレイン電極と、
前記ソース電極および前記ドレイン電極の配設面における、前記ソース電極および前記ドレイン電極の配設領域を除く前記上部障壁層の領域に配設された絶縁層と、
前記絶縁層を介して配設されたゲート電極と、を備え、
前記ゲート電極の直下の領域では、前記絶縁層が、前記上部障壁層を貫通して前記チャンネル層に達する位置まで形成されたリセス構造からなる、電界効果トランジスタ。 - 前記チャンネル層を構成するGaNの少なくとも一部は、n型ドーピングされている、請求項1に記載の電界効果トランジスタ。
- 前記チャンネル層は複数のGaN層からなる、請求項1または請求項2に記載の電界効果トランジスタ。
- 前記チャンネル層は、前記上部障壁層側となる第1チャンネル層と、前記下部障壁層側となる第2チャンネル層とからなり、
前記第1チャンネル層におけるn型ドーピング濃度が前記第2チャンネル層におけるn型ドーピング濃度よりも小さくされており、
前記絶縁層は、前記第2チャンネル層に到達しない形状で形成されている、請求項2または請求項3に記載の電界効果トランジスタ。 - 前記第1チャンネル層は、アンドープのGaNからなり、
前記第2チャンネル層は、n型ドーピングのGaNからなる、
請求項4に記載の電界効果トランジスタ。
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