WO2012165196A1 - インバータ駆動装置 - Google Patents
インバータ駆動装置 Download PDFInfo
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- WO2012165196A1 WO2012165196A1 PCT/JP2012/062943 JP2012062943W WO2012165196A1 WO 2012165196 A1 WO2012165196 A1 WO 2012165196A1 JP 2012062943 W JP2012062943 W JP 2012062943W WO 2012165196 A1 WO2012165196 A1 WO 2012165196A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
Definitions
- the present invention relates to an inverter drive device.
- an IGBT is used as a power semiconductor element used in a high voltage inverter of a hybrid vehicle (HEV) or an electric vehicle (EV).
- IGBTs tend to have less short-circuit tolerance than MOSFETs, and short-circuit and overcurrent protection circuits must be designed in consideration of this.
- Patent Document 1 discloses that an overcurrent is suppressed by clamping a gate voltage of an IGBT using a Zener diode when an overcurrent is detected.
- the gate voltage may vibrate by repeating the Zener clamp operation and the Zener clamp release. This phenomenon becomes a factor that increases the voltage surge.
- the gate voltage of the IGBT may oscillate.
- an inverter drive device acquires a voltage on the emitter electrode side of a power semiconductor element, a drive circuit that outputs a gate voltage of the power semiconductor element based on a PWM signal, and the voltage
- a predetermined voltage value exceeds a predetermined first predetermined voltage value a fault signal for stopping the output of the gate voltage is output to the drive circuit after the first predetermined time has elapsed after acquiring the voltage on the emitter electrode side.
- the overcurrent protection circuit and the voltage on the emitter electrode side of the power semiconductor element are acquired, and when the voltage exceeds a predetermined second predetermined voltage value, the second predetermined voltage is acquired after acquiring the voltage on the emitter electrode side.
- a zener clamp protection circuit that clamps the gate voltage signal of the drive circuit after a lapse of time, and the zener clamp protection circuit obtains the voltage on the emitter electrode side After a predetermined period of time, a latch circuit to continue clamp the gate voltage by the Zener clamping protection circuit.
- the safety of the inverter system can be improved.
- FIG. 9 is a timing chart illustrating an example of a voltage waveform when the zener clamp operation is released in a short time in the embodiment of the present invention (FIG. 7).
- FIG. 7 it is a timing chart figure of an example of a voltage waveform when Zener clamp operation is canceled at the time of fault output.
- inverter circuit diagram which can add individually overcurrent detection time and Zener clamp operation time by the embodiment of the present invention.
- It is an inverter circuit diagram which can set an overcurrent detection level and a Zener clamp detection level separately by embodiment of this invention.
- FIG. 1 is a circuit block diagram of a general HEV inverter system.
- the inverter system includes power semiconductor elements 104 to 109 that convert a DC voltage of the battery 100 into an AC voltage, a motor 102, a current sensor 103 that detects a current from the power semiconductor elements 104 to 109, a CPU, and a counter circuit.
- a PWM circuit 101 incorporating an input / output circuit and the like, and gate drive circuits 110 to 115 for driving the power semiconductor elements 104 to 109.
- the Zener clamp circuit is included in the gate drive circuit described above.
- the gate drive circuit is configured for each arm.
- the power semiconductor element is mainly an IGBT.
- the PWM circuit 101 performs a PWM (pulse width modulation) calculation that makes the deviation between the current value output from the power semiconductor elements 104 to 109 detected by the current sensor 103 and the set value zero.
- PWM pulse width modulation
- FIG. 2 is a circuit configuration diagram of a conventional gate driving circuit 110 a for driving the power semiconductor element 104.
- the overcurrent protection circuit 204 of the commonly used gate driving circuit 110a as shown in FIG. 2 reads the voltage of the mirror emitter detection resistor 202 connected to the mirror emitter terminal of the power semiconductor element 104, An overcurrent abnormality of the power semiconductor element 104 is detected, and the operation of the power semiconductor element 104 is stopped.
- the overcurrent protection circuit 204 passes a blanking filter 207 for removing recovery surge noise to the mirror voltage read from the mirror emitter detection resistor 202, and detects a predetermined overcurrent detection set in the overcurrent detection comparator 205.
- a fault signal for stopping the output of the power semiconductor element 104 is output from the fault signal output unit 206.
- 2 includes a control PWM signal that is a control signal for turning on / off PWM control.
- FIG. 8 also shows a control PWM off signal for turning off the PWM control for explanation.
- FIG. 5 shows a timing chart of the overcurrent protection operation in the gate drive circuit 110a shown in FIG.
- the gate voltage, collector voltage, and mirror voltage (collector current) shown on the vertical axis are the voltage values of the power semiconductor element 104.
- Va is the overcurrent detection reference voltage Va illustrated in FIG.
- the power semiconductor is operated during the blanking time Ta of the blanking filter 207. Since the element 104 is not stopped, the short-circuit operation is continued with the control voltage of the drive circuit 200 until the power semiconductor element 104 is stopped due to an overcurrent protection abnormality.
- the blanking time Ta cannot be set freely, so that there is a possibility that a sufficient safe operation margin cannot be secured.
- the zener clamp protection circuit 300 includes a zener diode 301 for clamping the gate voltage of the power semiconductor element 104, a zener clamp MOSFET 302 for energizing the zener diode 301, and a blanking filter 307 for zener clamp detection protection. It consists of. Similar to the overcurrent protection circuit 204, the mirror emitter detection resistor 202 is connected to the gate terminal of the MOSFET 302. When the mirror voltage exceeds the threshold voltage of the MOSFET 302 via the blanking filter 307, the Zener clamp Is a circuit configuration that operates.
- the gate drive circuit 110b of FIG. 3 can perform a Zener clamp operation to clamp the gate voltage of the power semiconductor element 104 and reduce the short circuit energy until the short circuit abnormality is stopped.
- FIG. 6 shows this unstable operation in a timing chart.
- the gate voltage, collector voltage, and mirror voltage (collector current) shown on the vertical axis are the respective voltage values of the power semiconductor element 104.
- the zener clamp on the vertical axis indicates the switching timing of the MOSFET 302.
- Vb represents the detection reference voltage Vb of the Zener clamp detection comparator of the Zener clamp protection circuit 300 shown in FIG.
- Tb represents the blanking time Tb of the blanking filter 307.
- FIG. 4 is a circuit configuration diagram of the gate driving circuit 110 according to the embodiment of the present invention.
- the zener clamp protection circuit 310 in FIG. 4 includes a blanking filter 307 for detecting zener clamp protection for detecting the voltage of the mirror emitter detection resistor 202 and removing the steady-state recovery surge noise in the same manner as the overcurrent protection circuit 204.
- a zener clamp operation is performed.
- the overcurrent protection circuit 204 detects the voltage on the emitter electrode side of the power semiconductor element 104, compares this voltage value with the overcurrent detection reference voltage Va (first predetermined voltage value), and based on the comparison result.
- a fault signal for stopping output of the gate voltage signal to the drive circuit 200 is output from the fault signal output unit 206.
- the Zener clamp protection circuit 310 detects the voltage on the emitter electrode side of the power semiconductor element 104, compares this voltage value with the detection reference voltage Vb (second predetermined voltage value), and drives the drive circuit based on the comparison result. Clamp the 200 gate voltage signal.
- the output of the Zener clamp uses the latch circuit 303 to continue the Zener clamp operation for a certain period regardless of the mirror voltage after the Zener clamp operation, so that the input voltage of the power semiconductor element 104 oscillates. It is possible to eliminate such harmful effects.
- FIG. 7 shows a timing chart of the overcurrent protection circuit 204 and the Zener clamp protection circuit 310 in FIG.
- the blanking time of the blanking filter 207 for detecting overcurrent is Ta
- the detection reference voltage Va of the comparator 205 for detecting overcurrent is Ta
- Tb is the blanking time of the blanking filter 307 for detecting the zener clamp
- the zener clamp is set.
- the detection reference voltage Vb of the detection comparator 305 is used.
- the blanking time Tb for detecting the zener clamp is set as small as possible. However, it is set longer than the width of the recovery noise that occurs during normal operation.
- the zener clamp is set to work. This is to prevent the Zener clamp from operating and limiting the output current of the power semiconductor element 104 when an overcurrent is generated that is not greater than the current when the inverter circuit is short-circuited.
- the time Tzcp for outputting the zener clamp is set longer than the blanking time Ta. This is to prevent the zener clamp from ending and the short-circuit current from increasing again until an overcurrent is detected and stopped after the blanking time has elapsed.
- the zener clamp output time Tzcp is set to about the short-circuit withstand time of the power semiconductor element 104.
- FIG. 8 is a first timing chart showing the output timing of the reset signal of the latch circuit 303.
- the reset signal trigger (latch release signal in FIG. 4) of the latch circuit 303 that generates the Zener clamp time is input in synchronization with the control PWM input to the drive circuit 200 being turned off. In FIG. 8, this synchronization circuit is omitted.
- Such a control avoids a state in which the zener clamp continues to operate when the next control PWM is turned on when the zener clamp output time Tzcp is larger than the minimum OFF width of the PWM input to the drive circuit 200. It is.
- FIG. 9 is a second timing chart showing the output timing of the reset signal of the latch circuit 303.
- the end timing of the output time Tzcp that is, the reset signal trigger of the latch circuit 303 that generates the Zener clamp time is input in synchronization with the timing at which the fault signal output from the fault signal output unit 206 is turned on.
- the end timing of the output time Tzcp may be synchronized with a signal indicating that another inverter circuit abnormality has been detected.
- the drive circuit 200 lowers the gate voltage in a soft shut-off state in which the gate voltage is turned off for a longer time than the time for turning off the gate voltage during normal control (after timing A in FIG. 9). ). In this case, since there is no need for a Zener clamp, the Zener clamp latching operation is terminated.
- FIG. 10 shows a first circuit configuration diagram in the case where the inverter driving apparatus of this embodiment is partially integrated into an IC.
- the Zener diode 301 and the MOSFET 302 generate heat because the Zener clamp current flows for a long time. Therefore, the overcurrent protection circuit 204 and the Zener clamp protection circuit 310 excluding the Zener diode 301 and the MOSFET 302 are integrated into an IC. Further, it is possible to make additional adjustments individually on the outside of the IC circuit using the filter Tb ′ 401 and the filter Ta ′ 402.
- FIG. 11 shows a second circuit configuration diagram in the case where the inverter driving apparatus of this embodiment is partially integrated into an IC.
- the overcurrent detection level and the Zener clamp detection level can be individually adjusted by separately providing the mirror emitter detection resistor 202 and the mirror emitter detection resistor 203. However, the overcurrent detection level is set lower than the Zener clamp detection level.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
Description
図1は、一般的なHEV用インバータシステムの回路ブロック図である。このインバータシステムにはバッテリ100の直流電圧を交流電圧に変換するパワー半導体素子104~109と、モータ102と、前記パワー半導体素子104~109からの電流を検出する電流センサ103と、CPU,カウンタ回路,入出力回路などを内蔵したPWM回路101と、前記パワー半導体素子104~109を駆動するためのゲート駆動回路110~115で構成される。ツェナクランプ回路は前述のゲート駆動回路に含まれる。ここでゲート駆動回路はアーム毎に構成される。なお、本実施形態においては、パワー半導体素子は主にIGBTである。
なお、図2のPWM信号には、PWM制御をオン/オフする制御信号である制御PWM信号も含まれている。また、図8には、説明のためPWM制御をオフするための制御PWMオフ信号が示されている。
このような制御は、ツェナクランプ出力時間Tzcpが、ドライブ回路200に入力されるPWMの最小オフ幅よりも大きい場合に、次の制御PWMオン時にツェナクランプが動作し続けている状態を回避するためである。
インバータ回路の異常状態を検出した場合、ドライブ回路200は、ゲート電圧を通常制御時のゲート電圧をオフする時間よりも長い時間でオフするソフト遮断状態でゲート電圧を下げる(図9のタイミングA以降)。この場合ツェナクランプの必要性が無いことから、ツェナクランプのラッチ動作を終了する。
日本国特許出願2011年第121215号(2011年5月31日出願)
Claims (6)
- パワー半導体素子により構成されるインバータ回路を駆動するインバータ駆動装置であって、
PWM信号に基づいて前記パワー半導体素子のゲート電圧を出力するドライブ回路と、
前記パワー半導体素子のエミッタ電極側の電圧を取得し、当該電圧が予め定められた第1所定電圧値を越えた場合に、前記エミッタ電極側の電圧を取得してから第1所定時間経過後に、前記ドライブ回路に前記ゲート電圧の出力を停止するためのフォルト信号を出力する過電流保護回路と、
前記パワー半導体素子のエミッタ電極側の電圧を取得し、当該電圧が予め定められた第2所定電圧値を越えた場合に、前記エミッタ電極側の電圧を取得してから第2所定時間経過後に、前記ドライブ回路の前記ゲート電圧のクランプを行うツェナクランプ保護回路と、を備え、
前記ツェナクランプ保護回路は、前記エミッタ電極側の電圧を取得した後、前記第1所定時間の期間よりも大きい期間、当該ツェナクランプ保護回路による前記ゲート電圧のクランプを継続させるラッチ回路を有するインバータ駆動装置。 - 請求項1に記載のインバータ駆動装置であって、
前記第2所定電圧値は、前記第1所定電圧値よりも大きく設定されるインバータ駆動装置。 - 請求項1または2に記載のインバータ駆動装置であって、
前記第2所定時間は、前記第1所定時間よりも小さく設定されるインバータ駆動装置。 - 請求項1乃至3のいずれか1項に記載のインバータ駆動装置であって、
前記ラッチ回路は、前記クランプの継続時間を、前記パワー半導体素子の短絡耐量時間よりも長く設定するインバータ駆動装置。 - 請求項1乃至4のいずれか1項に記載のインバータ駆動装置であって、
前記ラッチ回路は、前記ドライブ回路に入力される前記PWM信号のオフ信号と同期して、前記ツェナクランプ保護回路による前記ゲート電圧のクランプの解除を行うインバータ駆動装置。 - 請求項1乃至4のいずれか1項に記載のインバータ駆動装置であって、
前記ラッチ回路は、前記ドライブ回路に入力される前記フォルト信号と同期して、前記ツェナクランプ保護回路による前記ゲート電圧のクランプの解除を行うインバータ駆動装置。
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DE112012002329.3T DE112012002329T5 (de) | 2011-05-31 | 2012-05-21 | Wechselrichter-Ansteuervorrichtung |
US14/119,091 US9065443B2 (en) | 2011-05-31 | 2012-05-21 | Inverter drive device |
CN201280026382.4A CN103582993B (zh) | 2011-05-31 | 2012-05-21 | 逆变器驱动装置 |
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JP2011-121215 | 2011-05-31 | ||
JP2011121215A JP5750311B2 (ja) | 2011-05-31 | 2011-05-31 | インバータ駆動装置 |
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JP (1) | JP5750311B2 (ja) |
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JP2018033280A (ja) * | 2016-08-26 | 2018-03-01 | 株式会社デンソー | 半導体装置 |
WO2019171783A1 (ja) | 2018-03-08 | 2019-09-12 | 株式会社日立製作所 | インバータ装置およびその駆動方法 |
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JP5750311B2 (ja) * | 2011-05-31 | 2015-07-22 | 日立オートモティブシステムズ株式会社 | インバータ駆動装置 |
JP6329944B2 (ja) | 2013-05-10 | 2018-05-23 | 株式会社日立製作所 | 絶縁ゲート型半導体素子の制御装置およびそれを用いた電力変換装置 |
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JP6520102B2 (ja) * | 2014-12-17 | 2019-05-29 | 富士電機株式会社 | 半導体装置および電流制限方法 |
JP6761466B2 (ja) * | 2016-04-26 | 2020-09-23 | 三菱電機株式会社 | 電動機駆動装置および空気調和機 |
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KR102660729B1 (ko) * | 2016-10-28 | 2024-04-26 | 삼성전자주식회사 | 전원 잡음을 검출하는 불휘발성 메모리 장치 및 그것의 동작 방법 |
WO2019021590A1 (ja) * | 2017-07-28 | 2019-01-31 | 三菱電機株式会社 | 電力用半導体素子の駆動回路 |
EP3702793A1 (en) * | 2019-03-01 | 2020-09-02 | Mitsubishi Electric R & D Centre Europe B.V. | A method and a device for monitoring the gate signal of a power semiconductor |
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- 2012-05-21 DE DE112012002329.3T patent/DE112012002329T5/de active Pending
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JP2018033280A (ja) * | 2016-08-26 | 2018-03-01 | 株式会社デンソー | 半導体装置 |
WO2018037898A1 (ja) * | 2016-08-26 | 2018-03-01 | 株式会社デンソー | 半導体装置 |
WO2019171783A1 (ja) | 2018-03-08 | 2019-09-12 | 株式会社日立製作所 | インバータ装置およびその駆動方法 |
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US9065443B2 (en) | 2015-06-23 |
JP5750311B2 (ja) | 2015-07-22 |
JP2012249481A (ja) | 2012-12-13 |
DE112012002329T5 (de) | 2014-03-27 |
CN103582993B (zh) | 2016-05-04 |
US20140085762A1 (en) | 2014-03-27 |
CN103582993A (zh) | 2014-02-12 |
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