WO2012146044A1 - 一种非对称栅mos器件及其制备方法 - Google Patents

一种非对称栅mos器件及其制备方法 Download PDF

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WO2012146044A1
WO2012146044A1 PCT/CN2011/084808 CN2011084808W WO2012146044A1 WO 2012146044 A1 WO2012146044 A1 WO 2012146044A1 CN 2011084808 W CN2011084808 W CN 2011084808W WO 2012146044 A1 WO2012146044 A1 WO 2012146044A1
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metal
gate
mos device
fabricating
layer
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French (fr)
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吴东平
胡成
朱伦
朱志炜
张世理
张卫
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Fudan University
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Fudan University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/0133—Aspects related to lithography, isolation or planarisation of the conductor at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01318—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN
    • H10D64/0132—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN the conductor being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01322—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H10D64/668—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers the layer being a silicide, e.g. TiSi2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the present invention relates to the field of semiconductor process technologies, and in particular, to an asymmetric gate MOS device and a method of fabricating the same. Background technique
  • the ever-decreasing feature size of the device also presents a series of challenges.
  • SCE short channel effect
  • DIBL drain induced barrier effect
  • HCE hot carrier effect
  • Hot Carrier Effect a series of challenges.
  • the prior art primarily addresses these issues through trench engineering. Channel engineering improves the performance of the device by non-uniform doping in the channel, and the resulting channel electric field distribution is continuous.
  • LDD Lightly Doped Drain
  • Pocket and Halo structures In trench engineering, many new trench structure devices have been proposed, such as Lightly Doped Drain (LDD), Pocket and Halo structures.
  • the lightly doped drain structure can effectively absorb the power line at the drain, reduce the electric field at the drain end of the device, and suppress the hot carrier effect.
  • Pocket and Halo devices can locally increase the source barrier by raising the source terminal heavily, and weaken the influence of the leakage end field on the source barrier. 4.
  • the above LDD structure increases the series resistance of the source and drain regions of the device, which reduces the driving current of the device.
  • the threshold voltage of the device increases, and the saturation drive current of the device is also increased. Lower, this affects the speed of the device.
  • an asymmetric gate field effect transistor has been proposed.
  • the so-called asymmetric gate field effect transistor means that the gate structure of the source and drain regions of the transistor are not completely the same, and thus the carrier emission region (source) Zone) and the carrier collection zone (drainage zone) produce electrical and physical asymmetry, which can optimize the overall performance parameters of the transistor, which is particularly important for the optimal design of future very small-sized transistors.
  • the existing method for preparing an asymmetric gate field effect transistor is generally to form a gate oxide layer having a thickness inconsistent at the source end and the drain end of the transistor, and to adjust the electric field distribution of the channel by adjusting the thickness of the gate oxide layer at the source end and the drain end. Thereby improving the overall performance of the transistor.
  • the above method for preparing an asymmetrical gate field effect transistor by forming a gate oxide layer having a thickness inconsistent at the source end and the drain end of the transistor has a certain difficulty in the process, and it is difficult to achieve better control.
  • An object of the present invention is to provide an asymmetric gate MOS device and a method of fabricating the same to improve the performance of a MOS device.
  • the present invention provides an asymmetric gate MOS device, the gate of which is a metal gate, and the work function of the metal gate is different between the source terminal and the drain terminal of the MOS device.
  • the metal gate is a metal semiconductor compound nanowire.
  • the MOS device specifically includes:
  • a gate electrode is formed on the gate oxide layer, and sidewalls are formed on both sides of the gate electrode; and source and drain regions are formed in the semiconductor substrate on both sides of the gate electrode.
  • the metal gate has a length of 2 to 11 nm.
  • the semiconductor substrate is silicon or silicon on the insulating layer
  • the metal semiconductor compound nanowire is a metal silicide nanowire.
  • the semiconductor substrate is a germanium or an insulating layer
  • the metal semiconductor compound nanowires are metal germanide nanowires.
  • the present invention also provides a method for fabricating the above asymmetric gate MOS device, the method comprising the following steps:
  • Source-drain implantation is performed to form source and drain regions in the semiconductor substrate.
  • preparing the gate on the gate oxide layer specifically includes the following steps:
  • the ion used for ion implantation doping the metal semiconductor compound nanowire is any one of P ion, As ion or B ion or a combination thereof.
  • the metal thin film is deposited on sidewalls on both sides of the polycrystalline semiconductor layer by a PVD method.
  • the target portion is separated into an ionic state to generate metal ions, and a first bias is applied to the polycrystalline semiconductor layer.
  • the separating the target portion into an ionic state is achieved by applying a second bias voltage to the target.
  • the first bias voltage is any one of a DC bias voltage, an AC bias voltage, and a pulse bias voltage.
  • the second bias voltage is any one of a DC bias voltage, an AC bias voltage, or a pulse bias voltage.
  • the semiconductor substrate is silicon or silicon on the insulating layer
  • the polycrystalline semiconductor layer is a polysilicon layer
  • the metal semiconductor compound nanowires are metal silicide nanowires.
  • the semiconductor substrate is a germanium or an insulating layer
  • the polycrystalline semiconductor layer is a polysilicon layer
  • the metal semiconductor compound nanowires are metal-deciplex nanowires.
  • the metal semiconductor compound nanowire is formed by reacting a metal with the polycrystalline semiconductor layer, wherein the metal is any one of nickel, cobalt, titanium, and antimony, or nickel, cobalt, titanium, or antimony. Any of them and incorporate platinum.
  • tungsten and/or molybdenum are also incorporated into the metal.
  • a substrate temperature of 0 to 300 ° C is deposited when a metal thin film is deposited on sidewalls on both sides of the polycrystalline semiconductor layer.
  • the annealing temperature is 200 to 900 °C.
  • the asymmetric gate MOS device provided by the present invention has a gate of a metal gate, and a work function of the metal gate is different between a source terminal and a drain terminal of the MOS device, thereby making the overall MOS device Performance parameters are more optimized.
  • the method for preparing an asymmetric gate MOS device performs ion implantation doping on the gate of the MOS device, so that the work function of the gate is at the source end and the drain of the MOS device.
  • the different ends make the overall performance parameters of the MOS device more optimized, and the method is convenient.
  • FIG. 1 is a cross-sectional view of an asymmetric gate MOS device according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for fabricating an asymmetric gate MOS device according to an embodiment of the present invention
  • 3A-3K are cross-sectional views of devices corresponding to respective steps of a method for fabricating an asymmetric gate MOS device according to an embodiment of the present invention. detailed description
  • the core idea of the present invention is to provide an asymmetric gate MOS device whose gate is a metal gate, and the work function of the metal gate is different between the source terminal and the drain terminal of the MOS device, thereby making the overall performance of the MOS device
  • the parameter is more optimized; at the same time, a method for preparing an asymmetric gate MOS device is provided, wherein the work function of the gate is at the source end of the MOS device by ion implantation doping the gate of the MOS device Different from the drain end, the overall performance parameters of the MOS device are more optimized, and the method is convenient.
  • FIG. 1 is a cross-sectional view of an asymmetric gate MOS device according to an embodiment of the present invention.
  • a gate of an asymmetric gate MOS device 100 according to an embodiment of the present invention is a metal gate, and the The work function of the metal gate is different between the source and drain terminals of the MOS device 100.
  • the asymmetric gate MOS device 100 provided by the embodiment of the present invention includes:
  • a gate oxide layer 102 is formed on the semiconductor substrate 101; wherein the gate oxide layer 102 is a high germanium dielectric layer;
  • a gate electrode is formed on the gate oxide layer 102, and sidewalls 104 are formed on both sides of the gate; wherein the gate is a metal gate, and work functions on both sides of the metal gate are different;
  • the metal gate is a metal semiconductor compound nanowire 103;
  • the source and drain regions are formed in the semiconductor substrate 101 on both sides of the gate; specifically, the source region 105 and the drain region 106 formed in the semiconductor substrate 101 formed on both sides of the gate;
  • the metal gate is different in work function between the source region 105 and the drain region 106.
  • the length of the metal gate is 2 to 11 nm, that is, the feature size of the MOS device 100 provided by the embodiment of the present invention is 2 to 11 nm.
  • the semiconductor substrate 101 is silicon or silicon on an insulating layer, and the metal semiconductor compound nanowires 103 are metal silicide nanowires.
  • the semiconductor substrate 101 is a germanium or an insulating layer
  • the metal semiconductor compound nanowires 103 are metal-substituted nanowires.
  • FIG. 2 is a flowchart of a method for fabricating an asymmetric gate MOS device according to an embodiment of the present invention
  • FIG. 3A to FIG. 3K are schematic diagrams of an asymmetric method according to an embodiment of the present invention.
  • the method for fabricating the asymmetric gate MOS device 100 according to the embodiment of the present invention includes the following steps:
  • preparing a gate on the gate oxide layer 102 and performing ion implantation doping on the gate, so that work functions on both sides of the gate are different; wherein the gate is a metal gate;
  • the metal gate is a metal semiconductor compound nanowire 103; specifically, preparing the gate on the gate oxide layer 102 further includes the following steps:
  • a polycrystalline semiconductor layer 110 and an insulating layer 120 are sequentially formed on the gate oxide layer 102, as shown in FIG. 3A;
  • the insulating layer 120 and the polycrystalline semiconductor layer 110 are sequentially etched to remove the insulating layer 120 and the polycrystalline semiconductor layer 110 on both sides, as shown in FIG. 3B;
  • a metal thin film 130 is deposited on sidewalls on both sides of the polycrystalline semiconductor layer 110, as shown in FIG. 3C; metal in the metal thin film 130 is diffused toward the polycrystalline semiconductor layer 110;
  • the metal thin film 130 remaining on the sidewall surface of the polycrystalline semiconductor layer 110 is removed, and as shown in FIG. 3D, after the metal diffuses to the surface of the polycrystalline semiconductor layer 110, the surface of the polycrystalline semiconductor layer 110 is formed. a thin layer of metal semiconductor 140;
  • the ion is any one of P ions, As ions, or B ions, or a combination thereof.
  • the ion implantation doping can be achieved by performing single-sided ion implantation on the metal semiconductor compound nanowire 103, as shown in FIG.
  • 3H that is, ion implantation doping of one side wall of the metal semiconductor compound nanowire 103
  • the ion doping on the two sides of the metal semiconductor compound nanowire 103 is different; or by performing bilateral ion implantation on the metal semiconductor compound nanowire 103, as shown in FIG. 31, that is, the metal semiconductor compound nanowire
  • the sidewalls of both sides of the 103 are doped with ion implantation. In this case, the ion doses of the two sides are different, or the types of ions implanted on both sides are different, so that the ion doping on both sides of the metal semiconductor compound nanowires 103 is different.
  • the pole work function determines the threshold voltage of the device. Therefore, by adjusting the work function of the gate in the source and drain regions to make them different, the source and drain regions are asymmetrical in electrical and physical properties. The overall performance parameters of the transistor are optimized.
  • the metal thin film 130 is deposited on the sidewalls on both sides of the polycrystalline semiconductor layer 110 by a PVD method.
  • the target portion may be selectively separated into an ion state to generate metal ions, and a first bias is applied to the polycrystalline semiconductor layer 110; Separating the target portion into an ion state may be achieved by applying a second bias voltage to the target; and wherein the first bias voltage is any one of a DC bias voltage, an AC bias voltage, or a pulse bias voltage
  • the second bias voltage is any one of a DC bias voltage, an AC bias voltage, or a pulse bias voltage.
  • the target portion is separated into an ionic state to generate metal ions, and a first bias is applied to the polycrystalline semiconductor layer 110 to accelerate the movement of the metal ions toward the sidewall of the polycrystalline semiconductor layer 110. And entering the sidewall of the polycrystalline semiconductor layer 110 such that diffusion to the polycrystalline semiconductor.
  • the sidewalls of the bulk layer 110 have more metal ions and deeper diffusion depth, so that the width of the finally formed metal semiconductor compound nanowires 103 is widened, so that the gate length of the asymmetric gate MOS device 100 provided by the embodiment of the present invention is lengthened.
  • the feature size is increased; therefore, the gate length of the asymmetric gate MOS device 100 provided by the embodiment of the present invention is adjustable. Specifically, the gate length of the asymmetric gate MOS device 100 may be 2 to 11 nm.
  • the separating the target portion into an ion state is achieved by adding a second bias voltage to the target, but the invention is not limited thereto. Any means for ionizing a portion of the target into an ionic state is within the scope of the present invention.
  • the semiconductor substrate 101 is silicon or silicon on the insulating layer
  • the polycrystalline semiconductor layer 110 is a polysilicon layer
  • the metal semiconductor compound nanowires 103 are metal silicide nanowires.
  • the semiconductor substrate 101 is a germanium or an insulating layer
  • the polycrystalline semiconductor layer 110 is a polysilicon layer
  • the metal semiconductor compound nanowires 103 are metal germanide nanowires.
  • the semiconductor substrate 101 may be silicon or silicon on the insulating layer, and the fault or the insulating layer is wrong. However, it should be recognized that the present invention does not
  • the semiconductor substrate 101 can also be other types of semiconductor substrates, such as gallium arsenide and the like.
  • the metal semiconductor compound nanowire 103 is formed by reacting a metal with the polycrystalline semiconductor layer 110, wherein the metal is any one of nickel, cobalt, titanium, and antimony, or nickel, cobalt, titanium, Any of the ruthenium is doped with platinum; platinum is doped because pure nickel silicide has poor stability under high temperature conditions, or film thickness becomes uneven and agglomerates, or nickel oxynitride NiSi with high resistivity is formed.
  • the metal is further doped with tungsten and/or molybdenum; to further control the growth of nickel silicide or platinum-doped nickel silicide and the diffusion of nickel/platinum, and increase the stability of nickel silicide or platinum-doped nickel silicide; Tungsten and/or molybdenum in the metal is similarly explained.
  • the substrate temperature is 0 to 300 ° C. This is because for the metallic nickel, the deposition temperature exceeds 300 ° C.
  • Nickel reacts directly with the polycrystalline semiconductor layer 110 (eg, polysilicon) to form nickel silicide while excess nickel is diffused. Leading to the failure of thickness control; at this particular temperature, nickel diffuses through the sidewalls of the polysilicon to the sidewalls of the polysilicon. This diffusion has self-saturation characteristics: The diffusion of nickel into the sidewalls of the polysilicon occurs only in the thin layer of silicon.
  • the thickness of the thin layer of nickel being related to the temperature of the substrate at the time of deposition, and the higher the temperature, the greater the thickness of the thin layer of nickel, at room temperature, the thin layer
  • the equivalent nickel thickness of nickel is about 2 nanometers.
  • the annealing temperature is 200 to 900 °C.
  • the metal semiconductor compound nanowires 103 provided by the embodiments of the present invention are formed by depositing a metal thin film 130 on the sidewall surfaces on both sides of the polycrystalline semiconductor layer 110, the metal in the metal thin film 130 is directed to the side of the polycrystalline semiconductor layer 110.
  • the surface of the wall is diffused, and after annealing, a metal semiconductor compound nanowire 103 (ie, a metal gate) is formed on a sidewall surface of the polycrystalline semiconductor layer 110 without using a high-resolution photolithography technique to form a metal semiconductor compound nanometer. Line 103, thus greatly saving costs.
  • the present invention provides an asymmetric gate MOS device having a gate as a metal gate, and a work function of the metal gate is different between a source terminal and a drain terminal of the MOS device, thereby making the entire MOS device
  • the performance parameter is further optimized; at the same time, a method for preparing an asymmetric gate MOS device is provided, which performs ion implantation doping on the gate of the MOS device, so that the work function of the gate is in the MOS device
  • the source end and the drain end are different, so that the overall performance parameters of the MOS device are more optimized, and the method is convenient.

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  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

一种非对称栅 MOS器件及其制备方法 技术械
本发明涉及半导体工艺技术领域，尤其涉及一种非对称栅 MOS器件及其制 备方法。 背景技术
自从第一个晶体管发明以来， 经过几十年的飞速发展， 晶体管的横向和纵 向尺寸都迅速缩小。 据国际半导体技术蓝图 （ITRS , International Technology
Roadmap for Semiconductors )在 2004年的预测， 到 2018年晶体管的特征尺寸 将达到 7nm。 尺寸的持续缩小使晶体管的性能（速度） 不断提高， 也使得我们 能够在相同面积的芯片上集成更多的器件， 集成电路的功能越来越强， 同时也 降低了单位功能成本。
然而器件特征尺寸的不断减小也带来了一系列的挑战。 当器件的特征尺寸 进入到深亚 米以后， 器件的短沟道效应（SCE, Short Channel Effect )、 漏致势 垒降氐效应 ( DIBL, Drain Induced Barrier Lower Effect ), 热载流子效应 （HCE, Hot Carrier Effect )等日趋严重， 从而使器件的性能退化。 现有技术主要通过沟 道工程来解决这些问题。 沟道工程是通过沟道内的非均勾掺杂来提高器件的性 能， 所得到的沟道电场分布是连续的。
在沟道工程中， 人们提出了许多新的沟道结构器件， 如轻掺杂漏 （LDD, Lightly Doped Drain )、 Pocket和 Halo结构等。 轻掺杂漏结构可以有效地吸收漏 端的电力线， 降低器件的漏端电场， 抑制热载流子效应。 Pocket和 Halo结构器 件可以通过对源端进行局部重掺杂， 抬高源端势垒， 削弱漏端电场对源端势垒 的影响， 4艮好地抑制器件的阈值电压漂移、 源漏穿通以及器件的 DIBL效应。
但是上述 LDD结构增加了器件源漏区的串联电阻， 会使器件的驱动电流降 低； Pocket结构中， 当 Pocket的注入剂量 /能量增加时， 器件的阈值电压升高， 也使器件的饱和驱动电流降低， 这都影响了器件的工作速度。 为了解决上述问题， 目前提出了一种非对称栅场效应晶体管， 所谓非对称 栅场效应晶体管是指晶体管的源区与漏区的栅结构等不完全相同， 进而使得载 流子发射区 （源区） 与载流子收集区 （漏区）产生电学和物理性能上的不对称 性， 从而可以使得晶体管的整体性能参数更加优化， 对未来极小尺寸晶体管的 优化设计有着特别重要的作用。
现有的制备非对称栅场效应晶体管的方法通常是在晶体管的源端与漏端形 成厚度不一致的栅氧化层， 通过调节源端与漏端的栅氧化层的厚度来调节沟道 的电场分布， 从而提高晶体管的综合性能。
然而， 上述通过在晶体管的源端与漏端形成厚度不一致的栅氧化层来制备 非对称栅场效应晶体管的方法在工艺上具有一定的难度， 艮难实现较好的控制。
因此， 如何方便有效地制备出非对称栅纳米 MOS器件， 已成为目前业界亟 需解决的技术问题。 发明内容
本发明的目的在于提供一种非对称栅 MOS器件及其制备方法，以提高 MOS 器件的性能。
为解决上述问题， 本发明提出一种非对称栅 MOS器件， 所述 MOS器件的 栅极为金属栅， 且所述金属栅的功函数在所述 MOS器件的源端与漏端不同。
可选的， 所述金属栅为金属半导体化合物纳米线。
可选的， 该 MOS器件具体包括：
半导体村底；
栅氧化层， 形成于所述半导体村底上；
栅极， 形成于所述栅氧化层上， 并且所述栅极的两侧形成有侧墙； 以及 源漏区， 形成于所述栅极两侧的所述半导体村底内。
可选的， 所述金属栅的长度为 2~llnm。
可选的， 所述半导体村底为硅或绝缘层上硅， 所述金属半导体化合物纳米 线为金属硅化物纳米线。
可选的， 所述半导体村底为锗或绝缘层上锗， 所述金属半导体化合物纳米 线为金属锗化物纳米线。 同时， 为解决上述问题， 本发明还提出一种上述非对称栅 MOS器件的制备 方法， 该方法包括如下步骤：
提供半导体村底；
在所述半导体村底上制备栅氧化层；
在所述栅氧化层上制备栅极， 并对所述栅极进行离子注入掺杂， 使所述栅 极两侧的功函数不同；
在所述栅极的两侧形成侧墙；
进行源漏注入， 在所述半导体村底内形成源漏区。
可选的， 在所述栅氧化层上制备栅极具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀， 去掉两侧的绝缘层以 及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜， 所述金属薄膜中的金属 向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火， 在所述多晶半导体层的侧壁表面形成金属 半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模， 对所述栅氧化层进行刻蚀； 以及 对所述金属半导体化合物纳米线进行离子注入掺杂， 使所述金属半导体化 合物纳米线两侧的功函数不同。
可选的， 所述对金属半导体化合物纳米线进行离子注入掺杂所采用的离子 为 P离子、 As离子或 B离子中的任一种或其组合。
可选的， 所述对金属半导体化合物纳米线进行离子注入掺杂， 使所述金属 半导体化合物纳米线两侧的功函数不同， 是通过对所述金属半导体化合物纳米 线进行单边离子注入实现的。
可选的， 所述对金属半导体化合物纳米线进行离子注入掺杂， 使所述金属 半导体化合物纳米线两侧的功函数不同， 是通过对所述金属半导体化合物纳米 线进行双边离子注入实现的。 可选的， 所述金属薄膜是通过 PVD法沉积在所述多晶半导体层两侧的侧壁 上的。
可选的， 在所述 PVD法沉积金属薄膜的过程中， 将靶材部分离化成离子状 态， 使其产生金属离子， 并在所述多晶半导体层上加第一偏压。
可选的， 所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压 实现的。
可选的， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 可选的， 所述第二偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 可选的， 所述半导体村底为硅或绝缘层上硅， 所述多晶半导体层为多晶硅 层， 所述金属半导体化合物纳米线为金属硅化物纳米线。
可选的， 所述半导体村底为锗或绝缘层上锗， 所述多晶半导体层为多晶锗 层， 所述金属半导体化合物纳米线为金属错化物纳米线。
可选的， 所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生 成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任 一种并掺入铂。
可选的， 所述金属中还掺入了钨和 /或钼。
可选的， 在所述多晶半导体层两侧的侧壁上沉积金属薄膜时的村底温度为 0~300°C。
可选的， 所述退火的温度为 200~900°C。
与现有技术相比， 本发明提供的非对称栅 MOS器件， 其栅极为金属栅， 且 所述金属栅的功函数在所述 MOS器件的源端与漏端不同， 从而使得 MOS器件 的整体性能参数更加优化。
与现有技术相比，本发明提供的非对称栅 MOS器件的制备方法通过对 MOS 器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述 MOS器件的源端与 漏端不同， 从而使得 MOS器件的整体性能参数更加优化， 该方法筒单方便。 附图说明
图 1为本发明实施例提供的非对称栅 MOS器件的剖面图；
图 2为本发明实施例提供的非对称栅 MOS器件的制备方法的流程图; 图 3A至图 3K为本发明实施例提供的非对称栅 MOS器件的制备方法的各 步骤对应的器件剖面图。 具体实施方式
以下结合附图和具体实施例对本发明提出的非对称栅 MOS器件及其制备方 法作进一步详细说明。 根据下面说明和权利要求书， 本发明的优点和特征将更 清楚。 需说明的是， 附图均采用非常筒化的形式且均使用非精准的比率， 仅用 于方便、 明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于， 提供一种非对称栅 MOS器件， 其栅极为金属栅， 且所述金属栅的功函数在所述 MOS器件的源端与漏端不同， 从而使得 MOS器 件的整体性能参数更加优化；同时，还提供一种非对称栅 MOS器件的制备方法， 该方法通过对 MOS器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述 MOS器件的源端与漏端不同， 从而使得 MOS器件的整体性能参数更加优化， 该方法筒单方便。
请参考图 1 , 图 1为本发明实施例提供的非对称栅 MOS器件的剖面图， 如 图 1所示， 本发明实施例提供的非对称栅 MOS器件 100的栅极为金属栅， 且所 述金属栅的功函数在所述 MOS器件 100的源端与漏端不同。 具体地， 本发明实 施例提供的非对称栅 MOS器件 100包括：
半导体村底 101;
栅氧化层 102, 形成于所述半导体村底 101上； 其中， 所述栅氧化层 102为 高 Κ介质层；
栅极， 形成于所述栅氧化层 102上， 并且所述栅极的两侧形成有侧墙 104; 其中， 所述栅极为金属栅， 所述金属栅两侧的功函数不同； 在本发明的一个具 体实施例中， 所述金属栅为金属半导体化合物纳米线 103; 以及
源漏区， 形成于所述栅极两侧的所述半导体村底 101 内； 具体地， 包括形 成于所述栅极两侧的所述半导体村底 101内的源区 105以及漏区 106;所述金属 栅在所述源区 105与漏区 106的功函数不同。
进一步地， 所述金属栅的长度为 2~llnm, 即本发明实施例提供的 MOS器 件 100的特征尺寸为 2~llnm。 进一步地， 所述半导体村底 101 为硅或绝缘层上硅， 所述金属半导体化合 物纳米线 103为金属硅化物纳米线。
进一步地， 所述半导体村底 101 为锗或绝缘层上锗， 所述金属半导体化合 物纳米线 103为金属错化物纳米线。
请继续参考图 2, 以及图 3A至图 3K, 其中， 图 2为本发明实施例提供的 非对称栅 MOS器件的制备方法的流程图， 图 3A至图 3K为本发明实施例提供 的非对称栅 MOS器件的制备方法的各步骤对应的器件剖面图。 结合图 2, 以及 图 3A至图 3K,本发明实施例提供的非对称栅 MOS器件 100的制备方法包括如 下步骤：
5101、 提供半导体村底 101;
5102、 在所述半导体村底 101 上制备栅氧化层 102; 其中， 所述栅氧化层 102为高 K介质层；
5103、 在所述栅氧化层 102上制备栅极， 并对所述栅极进行离子注入掺杂， 使所述栅极两侧的功函数不同； 其中， 所述栅极为金属栅； 在本发明的一个具 体实施例中， 所述金属栅为金属半导体化合物纳米线 103; 具体地， 在所述栅氧 化层 102上制备栅极又包括以下步骤：
在所述栅氧化层 102上依次形成多晶半导体层 110 以及绝缘层 120, 如图 3A所示；
依次对所述绝缘层 120 以及所述多晶半导体层 110进行刻蚀， 去掉两侧的 绝缘层 120以及多晶半导体层 110, 如图 3B所示；
在所述多晶半导体层 110两侧的侧壁上沉积金属薄膜 130, 如图 3C所示； 所述金属薄膜 130中的金属向所述多晶半导体层 110扩散；
去除所述多晶半导体层 110侧壁表面剩余的金属薄膜 130, 如图 3D所示， 所述金属扩散至所述多晶半导体层 110表面后， 在所述多晶半导体层 110的表 面形成含有金属的半导体薄层 140;
对所述多晶半导体层 110进行退火， 在所述多晶半导体层 110的侧壁表面 形成金属半导体化合物纳米线 103, 如图 3E所示；
去除所述绝缘层 120及所述多晶半导体层 110, 如图 3F所示；
以所述金属半导体化合物纳米线 103为掩模， 对所述栅氧化层 102进行刻 蚀； 刻蚀后的器件剖面图如图 3G所示； 以及
对所述金属半导体化合物纳米线 103 进行离子注入掺杂， 使所述金属半导 体化合物纳米线 103 两侧的功函数不同； 其中， 所述对金属半导体化合物纳米 线 103进行离子注入掺杂所采用的离子为 P离子、 As离子或 B离子中的任一种 或其组合。 并且该离子注入掺杂可通过对所述金属半导体化合物纳米线 103 进 行单边离子注入实现， 如图 3H所示， 即对所述金属半导体化合物纳米线 103的 一边侧壁进行离子注入掺杂， 使得所述金属半导体化合物纳米线 103 两侧的离 子掺杂不同； 也可以通过对所述金属半导体化合物纳米线 103进行双边离子注 入实现， 如图 31所示， 即对所述金属半导体化合物纳米线 103的两边侧壁均进 行离子注入掺杂， 此时可选择两边注入的离子剂量不同， 或者两边注入的离子 种类不同， 使得所述金属半导体化合物纳米线 103两侧的离子掺杂不同。
由于注入的离子会聚集到所述金属半导体化合物纳米线 103 与所述栅氧化 层 102的界面，从而改变所述金属半导体化合物纳米线 103与所述栅氧化层 102 之间的功函数， 而栅极的功函数决定了器件的阈值电压， 因此， 通过调节栅在 源区与漏区的功函数， 使其不同， 进而使得源区与漏区产生电学和物理性能上 的不对称性， 从而可以使得晶体管的整体性能参数更加优化。
5104、 在所述栅极的两侧形成侧墙 104, 如图 3J所示；
5105、 进行源漏注入， 在所述半导体村底 101 内形成源漏区； 具体地， 在 所述栅极两侧的半导体村底 101 内形成源区 106 以及漏区 107, 完成非对称栅 MOS器件 100的制备， 如图 3K所示。
进一步地， 所述金属薄膜 130是通过 PVD法沉积在所述多晶半导体层 110 两侧的侧壁上的。 并且， 在所述 PVD法沉积金属薄膜 130的过程中， 还可以选 择将靶材部分离化成离子状态， 使其产生金属离子， 并在所述多晶半导体层 110 上加第一偏压； 其中， 所述将靶材部分离化成离子状态可通过在所述靶材上加 第二偏压实现； 并且， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任 一种， 所述第二偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
通过将靶材部分离化成离子状态， 使其产生金属离子， 并在所述多晶半导 体层 110上加第一偏压， 使得所述金属离子加速向所述多晶半导体层 110的侧 壁运动， 并进入所述多晶半导体层 110 的侧壁， 从而使得扩散至所述多晶半导 体层 110 的侧壁的金属离子更多， 扩散深度更深， 因而最终形成的金属半导体 化合物纳米线 103的宽度加宽，从而使得本发明实施例提供的非对称栅 MOS器 件 100的栅极长度加长，特征尺寸加大；因此本发明实施例提供的非对称栅 MOS 器件 100的栅极长度是可调的。 具体地， 所述非对称栅 MOS器件 100的栅极长 度可为 2~llnm。
需要说明的是， 在本发明的一个具体实施例中， 所述将靶材部分离化成离 子状态是通过在所述靶材上加第二偏压实现的， 然而本发明并不以此为限， 任 何使得靶材的一部分离化成离子状态的方式都在本发明的保护范围之内。
进一步地， 所述半导体村底 101为硅或绝缘层上硅， 所述多晶半导体层 110 为多晶硅层， 所述金属半导体化合物纳米线 103为金属硅化物纳米线。
进一步地， 所述半导体村底 101为锗或绝缘层上锗， 所述多晶半导体层 110 为多晶锗层， 所述金属半导体化合物纳米线 103为金属锗化物纳米线。
需要说明的是， 在本发明的一个具体实施例中， 所述半导体村底 101 可为 硅或绝缘层上硅、 以及错或绝缘层上错， 然而应该认识到， 本发明并不以此为 限， 所述半导体村底 101还可为其它类型的半导体村底， 如砷化镓等三五族半 导体村底。
进一步地， 所述金属半导体化合物纳米线 103 由金属与所述多晶半导体层 110反应生成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任一种并掺入铂； 掺入铂是因为纯的一硅化镍在高温条件下稳定性差， 或出现薄膜厚度变得不均匀并结块， 或生成电阻率高的二硅化镍 NiSi2, 严重影 响器件的性能， 因此， 为了减慢硅化镍的生长速度以及防止硅化镍薄层遇到高 温时发生结块或形成二硅化镍， 可以在镍中掺入一定比例的铂； 其它金属中掺 铂作类似解释。
进一步地， 所述金属中还掺入了钨和 /或钼； 以进一步控制硅化镍或掺铂硅 化镍的生长和镍 /铂的扩散， 并增加硅化镍或掺铂硅化镍的稳定性； 其它金属中 掺钨和 /或钼作类似解释。
进一步地， 在所述多晶半导体层 110两侧的侧壁上沉积金属薄膜 130时的 村底温度为 0~300°C ; 这是因为对金属镍来说， 沉积温度超过 300°C会造成在超 量的镍扩散的同时镍会和多晶半导体层 110(例如多晶硅）直接反应形成硅化镍， 导致厚度控制的失败； 在该特定温度下， 镍会经多晶硅侧壁表面向多晶硅侧壁 进行扩散， 这种扩散具有自饱和特性： 镍向多晶硅侧壁进行扩散仅在硅的表面 薄层中发生， 形成一定硅 /镍原子比例的薄层镍， 该薄层镍的厚度和淀积时的村 底温度有关， 温度越高， 该薄层镍的厚度也越大， 在室温下， 该薄层镍的等效 镍厚度为 2纳米左右。
进一步地， 所述退火的温度为 200~900°C。
由于本发明实施例提供的金属半导体化合物纳米线 103是通过在多晶半导 体层 110两侧的侧壁表面沉积金属薄膜 130,所述金属薄膜 130中的金属向所述 多晶半导体层 110的侧壁表面扩散， 经过退火后， 在所述多晶半导体层 110的 侧壁表面形成金属半导体化合物纳米线 103 (即金属栅）， 而不需要利用高分辨 率的光刻技术来形成金属半导体化合物纳米线 103, 因而大大节约了成本。
综上所述， 本发明提供了一种非对称栅 MOS器件， 其栅极为金属栅， 且所 述金属栅的功函数在所述 MOS器件的源端与漏端不同， 从而使得 MOS器件的 整体性能参数更加优化； 同时， 还提供了一种非对称栅 MOS器件的制备方法， 该方法通过对 MOS器件的栅极进行离子注入掺杂，使所述栅极的功函数在所述 MOS器件的源端与漏端不同， 从而使得 MOS器件的整体性能参数更加优化， 该方法筒单方便。
显然， 本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明 的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要求及其 等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权 利 要 求 书
1、一种非对称栅 MOS器件，其特征在于，所述 MOS器件的栅极为金属栅， 且所述金属栅的功函数在所述 MOS器件的源端与漏端不同。
2、 如权利要求 1所述的非对称栅 MOS器件， 其特征在于， 所述金属栅为 金属半导体化合物纳米线。
3、 如权利要求 2所述的非对称栅 MOS器件， 其特征在于， 该 MOS器件具 体包括：
半导体村底；
栅氧化层， 形成于所述半导体村底上；
栅极， 形成于所述栅氧化层上， 并且所述栅极的两侧形成有侧墙； 以及 源漏区， 形成于所述栅极两侧的所述半导体村底内。
4、 如权利要求 3所述的非对称栅 MOS器件， 其特征在于， 所述金属栅的 长度为 2~llnm。
5、 如权利要求 4所述的非对称栅 MOS器件， 其特征在于， 所述半导体村 底为硅或绝缘层上硅， 所述金属半导体化合物纳米线为金属硅化物纳米线。
6、 如权利要求 4所述的非对称栅 MOS器件， 其特征在于， 所述半导体村 底为锗或绝缘层上锗， 所述金属半导体化合物纳米线为金属错化物纳米线。
7、 一种如权利要求 3所述的非对称栅 MOS器件的制备方法， 其特征在于， 包括如下步骤：
提供半导体村底；
在所述半导体村底上制备栅氧化层；
在所述栅氧化层上制备栅极， 并对所述栅极进行离子注入掺杂， 使所述栅 极两侧的功函数不同；
在所述栅极的两侧形成侧墙；
进行源漏注入， 在所述半导体村底内形成源漏区。
8、 如权利要求 7所述的非对称栅 MOS器件的制备方法， 其特征在于， 在 所述栅氧化层上制备栅极具体包括如下步骤：
在所述栅氧化层上依次形成多晶半导体层以及绝缘层；
依次对所述绝缘层以及所述多晶半导体层进行刻蚀， 去掉两侧的绝缘层以 及多晶半导体层；
在所述多晶半导体层两侧的侧壁上沉积金属薄膜， 所述金属薄膜中的金属 向所述多晶半导体层扩散；
去除所述多晶半导体层侧壁表面剩余的金属薄膜；
对所述多晶半导体层进行退火， 在所述多晶半导体层的侧壁表面形成金属 半导体化合物纳米线；
去除所述绝缘层及所述多晶半导体层；
以所述金属半导体化合物纳米线为掩模， 对所述栅氧化层进行刻蚀； 以及 对所述金属半导体化合物纳米线进行离子注入掺杂， 使所述金属半导体化 合物纳米线两侧的功函数不同。
9、 如权利要求 8所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述对金属半导体化合物纳米线进行离子注入掺杂所采用的离子为 P离子、 As离 子或 B离子中的任一种或其组合。
10、 如权利要求 9所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述对金属半导体化合物纳米线进行离子注入掺杂， 使所述金属半导体化合物纳 米线两侧的功函数不同， 是通过对所述金属半导体化合物纳米线进行单边离子 注入实现的。
11、 如权利要求 9所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述对金属半导体化合物纳米线进行离子注入掺杂， 使所述金属半导体化合物纳 米线两侧的功函数不同， 是通过对所述金属半导体化合物纳米线进行双边离子 注入实现的。
12、 如权利要求 8所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述金属薄膜是通过 PVD法沉积在所述多晶半导体层两侧的侧壁上的。
13、 如权利要求 12所述的非对称栅 MOS器件的制备方法， 其特征在于， 在所述 PVD法沉积金属薄膜的过程中， 将靶材部分离化成离子状态， 使其产生 金属离子， 并在所述多晶半导体层上加第一偏压。
14、 如权利要求 13所述的非对称栅 MOS器件的制备方法， 其特征在于， 所述将靶材部分离化成离子状态是通过在所述靶材上加第二偏压实现的。
15、 如权利要求 14所述的非对称栅 MOS器件的制备方法， 其特征在于， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
16、 如权利要求 14所述的非对称栅 M0S器件的制备方法， 其特征在于， 所述第二偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
17、 如权利要求 8所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述半导体村底为硅或绝缘层上硅， 所述多晶半导体层为多晶硅层， 所述金属半 导体化合物纳米线为金属硅化物纳米线。
18、 如权利要求 8所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述半导体村底为锗或绝缘层上锗， 所述多晶半导体层为多晶锗层， 所述金属半 导体化合物纳米线为金属错化物纳米线。
19、 如权利要求 17或 18所述的非对称栅 MOS器件的制备方法， 其特征在 于， 所述金属半导体化合物纳米线由金属与所述多晶半导体层反应生成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任一种并掺入 铂。
20、 如权利要求 19所述的非对称栅 MOS器件的制备方法， 其特征在于， 所述金属中还掺入了钨和 /或钼。
21、 如权利要求 8所述的非对称栅 MOS器件的制备方法， 其特征在于， 在 所述多晶半导体层两侧的侧壁上沉积金属薄膜时的村底温度为 0~300°C。
22、 如权利要求 8所述的非对称栅 MOS器件的制备方法， 其特征在于， 所 述退火的温度为 200~900°C。
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