WO2012068928A1 - 一种低功耗复合源结构mos晶体管及其制备方法 - Google Patents

一种低功耗复合源结构mos晶体管及其制备方法 Download PDF

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WO2012068928A1
WO2012068928A1 PCT/CN2011/080779 CN2011080779W WO2012068928A1 WO 2012068928 A1 WO2012068928 A1 WO 2012068928A1 CN 2011080779 W CN2011080779 W CN 2011080779W WO 2012068928 A1 WO2012068928 A1 WO 2012068928A1
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gate
source
mos transistor
source region
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PCT/CN2011/080779
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French (fr)
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黄如
黄芊芊
詹瞻
黄欣
王阳元
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北京大学
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Priority to US13/501,241 priority Critical patent/US8710557B2/en
Priority to DE112011103915.8T priority patent/DE112011103915B4/de
Publication of WO2012068928A1 publication Critical patent/WO2012068928A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact

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  • the invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra-large scale integration (ULSI), and particularly relates to a composite source MOS combining Schottky Barrier and T-gate structure. Transistor and its preparation method. BACKGROUND OF THE INVENTION As the size of metal-oxide-silicon field effect transistors (MOSFETs) continues to shrink, especially as the feature size of devices enters the nanoscale, the negative effects of short channel effects of devices are becoming more apparent.
  • DIBL drain-induced barrier reduction effect
  • the band-band tunneling effect increase the device's off-state leakage current, which increases the power consumption of the integrated circuit with a decrease in the threshold voltage of the device.
  • the subthreshold slope of a conventional MOSFET device cannot be synchronously reduced as the device size is reduced due to the theoretical limitation of KT/q, and the subthreshold leakage current is also continuously increased as the threshold voltage is lowered.
  • the Schottky Barrier MOSFET structure was proposed by Lepselter and Sze. The source and drain are replaced by metal or silicide instead of the conventional doping, and the direct tunneling barrier of the carrier at the source is used to achieve conduction.
  • the Schottky barrier MOSFET greatly reduces the source-drain parasitic resistance of the device, and realizes The source-drain ultra-shallow junction, and its simple process requires a small thermal budget, providing a possible solution for the use of high-k and metal-gate materials.
  • the large off-state leakage current and the small on-state current of the Schottky junction greatly limit the application of the Schottky barrier MOSFET device.
  • the problem of the theoretical threshold of 60mv/de C for the subthreshold slope of MOSFET has been proposed by researchers in recent years. The solution is to use a tunneling field effect transistor (TFET).
  • the TFET is turned on with the gate-band tunneling of the PIN junction of the gate-controlled reverse bias, and the leakage current is very small.
  • TFETs have many excellent features such as low leakage current, low subthreshold slope, low operating voltage, and low power consumption, but due to source junction tunneling probability and tunneling area limitations, TFETs and Schottky barrier MOSFETs are facing The problem of low on-state current.
  • the patent (CN 101719517 A) proposes a Schottky tunneling transistor that solves the source-drain self-alignment problem of a TFET device by using a Schottky junction in the use of source and drain, but it also faces the problem of small on-state current. . Summary of the invention
  • the present invention is directed to a low power composite source structure MOS transistor incorporating a Schottky junction and a band tunneling mechanism and a method of fabricating the same.
  • MOS transistor incorporating a Schottky junction and a band tunneling mechanism and a method of fabricating the same.
  • the structure Under the condition of being compatible with the existing CMOS process and having the same active area as the MOSFET, the structure can significantly improve the on-current of the device and reduce the leakage current and parasitic resistance, showing a good sub-threshold. characteristic.
  • a low power composite source structure MOS transistor comprising: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly doped source region, and a highly doped drain region, in high doping
  • a side of the source region away from the channel direction is connected to a Schottky source region, and one end of the control gate extends to a T-type to the highly doped source region, and the extended gate region is an extension gate, and the original control gate region is a main gate.
  • the active region covered by the extension gate is also a channel region, and the material is a substrate material, and the highly doped source region is formed by high doping of the semiconductor, and is located on both sides of the extension gate along the width direction of the active region,
  • the Schottky source region is formed of a metal or a metal silicide, and a Schottky junction (metal semiconductor junction) is formed at the channel under the Schottky source region and the extension gate.
  • the highly doped drain region is formed by high doping of the semiconductor, and the doping type is opposite to the highly doped source region, on the unstretched side of the control gate.
  • the width of the extended gate must be smaller than the injection width of the active region of the source region to ensure that the source region half surrounds the extended gate to ensure a large tunneling area. And the width of the extension gate must be small enough, so that the built-in potential of the source junction on both sides of the extension gate can deplete the channel region below the extension gate, which can reduce the static leakage current of the device (according to the channel and The difference in the doping concentration of the source region is between 1-2 ⁇ m).
  • the length direction of the extension grid may be arbitrary, depending on the amount of current boost required, but generally does not exceed the edge of the source active area.
  • a margin can be left between the main gate and the highly doped drain region to suppress the bipolar conduction characteristics of the structure, so that the main gate region can lose control to obtain a better subthreshold slope.
  • the method for fabricating the composite source structure MOS transistor combined with the Schottky junction and the ⁇ -type gate includes the following steps:
  • a metal source of the photolithographic source sputtering a layer of metal, forming a metal and semiconductor compound by low temperature annealing, and then removing the unreacted metal to form a Schottky source region;
  • the conventional CMOS process is carried out, including depositing a passivation layer, opening a contact hole, and metallization, etc., to obtain the MOS transistor.
  • the semiconductor substrate material in the step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV binary or ternary compound semiconductors, Silicon on insulator (SOI) or germanium on insulator (GOI).
  • the gate dielectric layer material in the step (2) is selected from the group consisting of silicon dioxide, hafnium oxide, tantalum nitride, and the like.
  • the method of growing the gate dielectric layer in the step (2) is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition, and physical vapor deposition.
  • the gate electrode layer material in the step (3) is selected from the group consisting of doped polysilicon, metallic cobalt, nickel, and other metals or metal silicides.
  • the metal material in the step (6) is selected from the group consisting of Pt, Er, Co, Ni, and other metals which can form a compound by annealing with a substrate semiconductor material.
  • the structure utilizes the T-type gate to more effectively control the surface potential of the channel, so that the conduction band of the channel surface can be reduced or the valence band rises to enhance the source electric field strength, and the band tunneling occurs and the conduction current is generated. , breaking through the limits of the traditional MOSFET subthreshold slope.
  • the structure makes full use of the three sides of the extension grid, and the three sides respectively use the belt tunneling and Schottky junction tunneling mechanism to achieve conduction; by adjusting the length of the extension grid edge, a large tunneling area is realized.
  • the device's turn-on current is greatly improved while improving the subthreshold slope of the device.
  • the introduction of the Schottky source region reduces the parasitic resistance of the device, and by strictly controlling the width of the extended gate, the channel region under the extended gate is depleted, greatly reducing the Schottky junction. Leakage current problem, achieving low leakage current.
  • the process for fabricating the device is fully compatible with conventional MOSFET fabrication processes.
  • the structure device uses a composite source structure that combines a Schottky barrier and a T-gate to improve device performance and a simple preparation method.
  • the same active region size can get higher on current, lower leakage current and steeper subthreshold slope, which is expected in the field of low power consumption. It has been adopted and has high practical value.
  • FIG. 1 is a schematic view showing a process step of growing a gate dielectric layer on a semiconductor substrate and depositing a gate electrode;
  • 2a is a cross-sectional view of the device of the gate electrode formed by photolithography and etching in the direction of the broken line of FIG. 2b, and
  • FIG. 2b is a plan view of the corresponding device;
  • FIG. 3a is a cross-sectional view of the device after the photolithography source doped region and ion implantation to form a highly doped source region, taken along the dashed line direction of FIG. 3b, and FIG. 3b is a corresponding device top view;
  • FIG. 4a is a cross-sectional view of the device after immersing the drain doped region and ion implantation to form a highly doped drain region in the direction of the dashed line in FIG. 4b, and FIG. 4b is a top view of the corresponding device;
  • Figure 5a is a cross-sectional view of the device after photolithographic Schottky source region and sputter metal annealing to form a silicide in the direction of the dashed line in Figure 5b, and Figure 5b is a top view of the corresponding device;
  • Figure 6 is a plan view showing the device of the composite source structure MOS transistor of the present invention.
  • Figure 7a is a cross-sectional view of the transistor of the present invention taken along the line AA' of Figure 6;
  • Figure 7b is a cross-sectional view of the transistor of the present invention taken along line BB' of Figure 6;
  • a specific example of the preparation method of the present invention includes the process steps shown in Figures 1 to 5b:
  • the active region isolation layer is formed on the bulk silicon silicon wafer silicon substrate 1 having a crystal orientation of (100) by using a shallow trench isolation technique.
  • the doping concentration of the substrate is lightly doped; then a gate dielectric layer 2 is thermally grown, the gate dielectric layer is Si0 2 , and the thickness is 1-5 nm; the gate electrode layer 3 is deposited, the gate electrode layer is doped polysilicon layer, and the thickness is It is 150-300nm, as shown in Figure 1.
  • the gate pattern is photolithographically patterned, including the main gate 3a and the extension gate 3b, and the gate electrode layer 3 is etched up to the gate dielectric layer 2, wherein the width of the extension gate is 1-2 ⁇ m, as shown in Figs. 2a and 2b.
  • the energy of ion implantation is 40 keV, and the impurity is BF 2 + , as shown in Figures 3a and 3b.
  • the pattern of the drain doped region is lithographically patterned, and the drain ion implantation is performed by using the photoresist as a mask to form a highly doped drain region 6.
  • the energy of the ion implantation is 50 keV, and the impurity is implanted as As + , as shown in FIG. 4a and 4b. Show; Perform a rapid high temperature annealing to activate the source and drain doping impurities.
  • lithography out the source metal area pattern using the photoresist as a mask (may also be a layer of passivation layer and then photolithography and etching out the metal area pattern area) sputtering a layer of metal layer Ni, low temperature Thermal annealing, forming a metal silicide with silicon as the Schottky source region 7 of the device, as shown in Figures 5a, 5b.
  • CMOS post-process including deposition of a passivation layer, opening contact holes, and metallization, can be performed to obtain the low-power composite source structure MOS transistor.

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Description

一种低功耗复合源结构 MOS晶体管及其制备方法
本申请要求于 2010 年 11 月 25 日提交至中国专利局的中国专利申请 (201010560176.4) 的优先权， 其全部内容通过引用合并于此。 技术领域
本发明属于 CMOS超大集成电路（Ultra-Large Scale Integration, ULSI) 中的场效 应晶体管逻辑器件与电路领域， 具体涉及一种结合肖特基势垒 （Schottky Barrier) 和 T型栅结构的复合源 MOS晶体管及其制备方法。 背景技术 随着金属 -氧化物-硅场效应晶体管 （MOSFET) 的尺寸不断缩小， 尤其是当器件 的特征尺寸进入纳米尺度以后，器件的短沟道效应等的负面影响也愈加明显。漏致势 垒降低效应（DIBL)、 带带隧穿效应使得器件关态漏泄电流不断增大， 伴随着器件阈 值电压降低， 增大了集成电路的功耗。 不仅如此， 传统 MOSFET器件的亚阈值斜率 由于受到 KT/q的理论限制而无法随着器件尺寸的缩小而同步减小， 亚阈值漏泄电流 也在随着阈值电压的降低不断地升高。 为了克服纳米尺度下 MOSFET面临的越来越 多的挑战， 新型器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。 早在 20世纪 60年代末， 由 Lepselter和 Sze就提出了肖特基势垒 MOS场效应晶 体管（Schottky Barrier MOSFET)结构。将源漏利用金属或硅化物来代替传统的掺杂， 利用源端的载流子的直接隧穿势垒来实现导通， 肖特基势垒 MOSFET大大降低了器 件的源漏寄生电阻， 实现了源漏超浅结， 且其简单的工艺要求较小的热预算， 为高 K 和金属栅材料的使用提供了可能的解决办法。然而肖特基结较大的关态泄漏电流和较 小的开态电流大大限制了肖特基势垒 MOSFET器件的应用。 另夕卜， 针对 MOSFET亚 阈值斜率有 60mv/deC的理论极限的问题， 近些年来研究者们提出了一种可能的解决 方案， 就是采用隧穿场效应晶体管 （TFET)。 TFET 利用栅极控制反向偏置的 P-I-N 结的带带隧穿实现导通， 且漏电流非常小。 TFET具有低漏电流、 低亚阈值斜率、 低 工作电压和低功耗等诸多优异特性，但由于受源结隧穿几率和隧穿面积的限制， TFET 和肖特基势垒 MOSFET—样面临着低开态电流的问题。 专利 (CN 101719517 A)提出 了一种肖特基隧穿晶体管，它利用肖特基结在源漏的使用解决了 TFET器件的源漏自 对准问题， 但它同样面临开态电流小的难题。 发明内容
本发明的目的在于一种结合肖特基结和带带隧穿机制的低功耗复合源结构 MOS 晶体管及其制备方法。在与现有的 CMOS工艺相兼容和与 MOSFET有相同的有源区 面积的条件下， 该结构能显著地提升器件的导通电流， 且减小漏泄电流和寄生电阻， 展现较好的亚阈特性。
本发明的技术方案如下：
一种低功耗复合源结构 MOS晶体管， 其特征在于， 包括一个控制栅电极层、 一 个栅介质层、 一个半导体衬底、一个高掺杂源区和一个高掺杂漏区， 在高掺杂源区远 离沟道方向的一侧连接一个肖特基源区，控制栅的一端向高掺杂源区延展成 T型，延 展出来的栅区为延展栅，原控制栅区为主栅，在延展栅覆盖下的有源区同样是沟道区， 材料为衬底材料，所述高掺杂源区由半导体高掺杂形成，位于延展栅的沿有源区宽度 方向的两侧，所述肖特基源区由金属或金属硅化物形成， 且在肖特基源区和延展栅下 的沟道处形成肖特基结 （金属半导体结）。 所述高掺杂漏区由半导体高掺杂形成， 且 掺杂类型与高掺杂源区相反， 位于控制栅未延展的一侧。
所述延展栅的宽度必须小于源区有源区的注入宽度， 以保证源区半包围延展栅， 保证大的隧穿面积。且延展栅的宽度必须小到一定值， 以至于延展栅极两侧源结的内 建势可以耗尽延展栅以下的沟道区，这样可以减小器件静态漏泄电流（根据沟道以及 源区掺杂浓度的不同， 这个值取 1-2μιη之间）。
所述延展栅的长度方向可以任意，视需要电流的提升量而定，但是一般不会超过 源端有源区的边缘。
主栅与高掺杂漏区之间可以留有一定的余量，抑制该结构的双极导通特性，这样 主栅区可以失去控制力， 以得到更好的亚阈值斜率。 上述结合肖特基结和 Τ型栅的复合源结构 MOS晶体管的制备方法， 包括以下步 骤：
( 1 ) 在半导体衬底上通过浅槽隔离定义有源区；
(2) 生长栅介质层；
(3 ) 淀积栅电极层， 接着光刻和刻蚀栅电极层形成主栅和延展栅图形；
(4) 光刻源掺杂区， 以光刻胶及栅为掩膜， 离子注入形成高掺杂源区；
( 5 ) 光刻漏掺杂区， 以光刻胶及栅为掩膜， 离子注入形成高掺杂漏区， 快速高温热 退火激活掺杂杂质；
(6) 光刻源金属区， 溅射一层金属， 经过低温退火形成金属与半导体的化合物， 接 着去除未反应的金属， 形成肖特基源区；
(7) 最后进入常规 CMOS后道工序， 包括淀积钝化层、 开接触孔以及金属化等， 即可制得所述的 MOS晶体管。
上述的制备方法中，所述步骤（1 )中的半导体衬底材料选自 Si、 Ge、 SiGe、 GaAs 或其他 II- VI， III-V和 IV-IV族的二元或三元化合物半导体、 绝缘体上的硅（ SOI)或 绝缘体上的锗 （GOI)。
上述的制备方法中， 所述步骤（2) 中的栅介质层材料选自二氧化硅、 二氧化铪、 氮化铪等。 上述的制备方法中， 所述步骤（2)中的生长栅介质层的方法选自下列方法之一： 常规热氧化、 掺氮热氧化、 化学气相淀积和物理气相淀积。
上述的制备方法中， 所述步骤（3 ) 中的栅电极层材料选自掺杂多晶硅、 金属钴， 镍以及其他金属或金属硅化物。
上述的制备方法中， 所述步骤（6) 中的金属材料选自 Pt、 Er、 Co、 Ni以及其他 可与衬底半导体材料通过退火形成化合物的金属。
本发明的优点和积极效果：
一、该结构利用 T型栅极能更有效地控制沟道表面电势，使得沟道表面能带导带 降低或者价带上升来增强源结电场强度，促使带带隧穿发生并产生导通电流， 突破了 传统 MOSFET亚阈值斜率的极限。
二、该结构充分利用了延展栅的三条边，三边分别利用带带隧穿和肖特基结隧穿 机制实现导通； 通过对延展栅边长度的调控， 实现了大的隧穿面积， 大大提高了器件 导通电流， 同时改善器件亚阈值斜率。
三、肖特基源区的引入降低了器件的寄生电阻，且通过对延展栅宽度的严格控制， 使得延展栅下的沟道区域被耗尽， 大大减小了肖特基结所带来的漏泄电流问题， 实现 低的漏电流。
四、 制作该结构器件的工艺方法与传统的 MOSFET制备工艺保持完全兼容。 简而言之， 该结构器件采用复合源结构， 结合了肖特基势垒和 T型栅， 提高了器 件性能且制备方法简单。 与现有的 MOSFET相比， 在同样的工艺条件， 同样的有源 区尺寸下可以得到更高的导通电流、更低的泄漏电流以及更陡直的亚阈值斜率，有望 在低功耗领域得到采用， 有较高的实用价值。 附图说明
图 1是半导体衬底上生长栅介质层并淀积栅电极的工艺步骤示意图； 图 2a是光刻并刻蚀后形成的栅电极的器件沿图 2b虚线方向的剖面图， 图 2b是 相应的器件俯视图；
图 3a是光刻源掺杂区并离子注入形成高掺杂源区后的器件沿图 3b虚线方向的剖 面图， 图 3b是相应的器件俯视图；
图 4a是光刻漏掺杂区并离子注入形成高掺杂漏区后的器件沿图 4b虚线方向的剖 面图， 图 4b是相应的器件俯视图；
图 5a是光刻肖特基源区并溅射金属退火形成硅化物后的器件沿图 5b虚线方向的 剖面图， 图 5b是相应的器件俯视图；
图 6是本发明的复合源结构 MOS晶体管的器件俯视图；
图 7a是本发明晶体管沿图 6中 AA'方向的剖面图；
图 7b是本发明晶体管沿图 6中 BB'方向的剖面图；
图中：
1 ——半导体衬底 2
Figure imgf000007_0001
3 ——栅电极层 （其中， 3a 主 4 3b 延展栅）
Figure imgf000007_0002
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是， 公布实施例的目的在于帮 助进一步理解本发明，但是本领域的技术人员可以理解： 在不脱离本发明及所附权利 要求的精神和范围内， 各种替换和修改都是可能的。 因此， 本发明不应局限于实施例 所公开的内容， 本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图 1至图 5b所示的工艺步骤：
1、在晶向为（100)的体硅硅片硅衬底 1上采用浅槽隔离技术制作有源区隔离层， 衬底掺杂浓度为轻掺杂;然后热生长一层栅介质层 2，栅介质层为 Si02，厚度为 l-5nm; 淀积栅电极层 3， 栅电极层为掺杂多晶硅层， 厚度为 150-300nm， 如图 1所示。
2、 光刻出栅图形， 包括主栅 3a和延展栅 3b， 刻蚀栅电极层 3直到栅介质层 2， 其中延展栅的宽度为 1-2μιη， 如图 2a、 2b所示。
3、 光刻出源掺杂区图形， 主栅左侧边距源掺杂区右侧边的距离为 0-1μιη， 以光 刻胶 4为掩膜进行源离子注入， 形成高掺杂源区 5， 离子注入的能量为 40keV， 注入 杂质为 BF2 +， 如图 3a、 3b所示。
4、 光刻出漏掺杂区图形， 以光刻胶为掩膜进行漏离子注入， 形成高掺杂漏区 6， 离子注入的能量为 50keV， 注入杂质为 As+， 如图 4a、 4b所示； 进行一次快速高温退 火， 激活源漏掺杂的杂质。
5、 光刻出源金属区图形， 以光刻胶为掩膜 （也可以先生长一层钝化层再进行光 刻并刻蚀出金属区图形区域） 溅射一层金属层 Ni， 经低温热退火， 与硅形成金属硅 化物作为器件的肖特基源区 7， 如图 5a、 5b所示。
最后进入常规 CMOS后道工序， 包括淀积钝化层、 开接触孔以及金属化等， 即 可制得所述的低功耗复合源结构 MOS晶体管。 虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领 域的技术人员，在不脱离本发明技术方案范围情况下， 都可利用上述揭示的方法和技 术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施 例。 因此， 凡是未脱离本发明技术方案的内容， 依据本发明的技术实质对以上实施例 所做的任何简单修改、 等同变化及修饰， 均仍属于本发明技术方案保护的范围内。

Claims

权 利 要 求
1、 一种低功耗复合源结构 MOS晶体管， 包括一个控制栅电极层、 一个栅 介质层、 一个半导体衬底、 一个高掺杂源区和一个高掺杂漏区， 其特征在于， 在 高掺杂源区远离沟道方向的一侧连接一个肖特基源区，控制栅的一端向高掺杂源 区延展成 T型， 延展出来的栅区为延展栅， 原控制栅区为主栅， 在延展栅覆盖下 的有源区同样是沟道区， 材料为衬底材料， 所述肖特基源区和延展栅下的沟道处 形成肖特基结。
2、 如权利要求 1所述的低功耗复合源结构 M0S晶体管， 其特征在于， 所 述延展栅的宽度为 1-2μιη。
3、 一种低功耗复合源结构 MOS晶体管的制备方法， 其包括以下步骤： 1) 在半导体衬底上通过浅槽隔离定义有源区； 2) 生长栅介质层；
3) 淀积栅电极层， 接着光刻和刻蚀栅电极层形成主栅和延展栅图形；
4) 光刻源掺杂区， 以光刻胶及栅为掩膜， 离子注入形成高掺杂源区；
5) 光刻漏掺杂区， 以光刻胶及栅为掩膜， 离子注入形成高掺杂漏区， 快 速高温热退火激活掺杂杂质； 6) 光刻源金属区， 溅射一层金属， 经过低温退火形成金属与半导体的化 合物， 接着去除未反应的金属， 形成肖特基源区；
7) 最后进入常规 CMOS 后道工序， 包括淀积钝化层、 开接触孔以及金 属化等， 即可制得如权利要求 1所述的 MOS晶体管。 4、 如权利要求 3所述的方法， 其特征在于， 所述步骤 1)中的半导体衬底材 料选自 Si、 Ge、 SiGe、 GaAs或其他 II-VI, III-V和 IV-IV族的二元或三元化合 物半导体、 绝缘体上的硅或绝缘体上的锗。
5、 如权利要求 3所述的方法， 其特征在于， 所述步骤 2)中的栅介质层材料 选自二氧化硅、 二氧化铪、 氮化铪等。
6、 如权利要求 3所述的方法， 其特征在于， 所述步骤 2)中的生长栅介质层 的方法选自下列方法之一： 常规热氧化、掺氮热氧化、化学气相淀积和物理气相 淀积。
7、 如权利要求 3所述的方法， 其特征在于， 所述步骤 3)中的栅电极层材料 选自掺杂多晶硅、 金属钴， 镍以及其他金属或金属硅化物。
8、 如权利要求 3所述的方法， 其特征在于， 所述步骤 6)中的金属材料选自 Pt、 Er、 Co、 Ni以及其他可与衬底半导体材料通过退火形成化合物的金属。
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