WO2012140934A1 - 高周波パッケージ - Google Patents

高周波パッケージ Download PDF

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Publication number
WO2012140934A1
WO2012140934A1 PCT/JP2012/052117 JP2012052117W WO2012140934A1 WO 2012140934 A1 WO2012140934 A1 WO 2012140934A1 JP 2012052117 W JP2012052117 W JP 2012052117W WO 2012140934 A1 WO2012140934 A1 WO 2012140934A1
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WIPO (PCT)
Prior art keywords
dielectric substrate
high frequency
dielectric
conductor
ground conductor
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PCT/JP2012/052117
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English (en)
French (fr)
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雄亮 橘川
鈴木　拓也
友幸 海野
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201280017668.6A priority Critical patent/CN103460377B/zh
Priority to JP2013509810A priority patent/JP5693710B2/ja
Priority to US14/111,107 priority patent/US9693492B2/en
Priority to EP12771789.0A priority patent/EP2698819B1/en
Publication of WO2012140934A1 publication Critical patent/WO2012140934A1/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/006—Casings specially adapted for signal processing applications, e.g. CATV, tuner, antennas amplifier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to high frequency packages.
  • the configuration of the conventional high frequency package is mounted on the first dielectric substrate having the signal wiring and the ground conductor on the back surface and the back surface of the first dielectric substrate.
  • a high frequency element, a second dielectric substrate having a signal wiring and a ground conductor on the surface surface layer, and a connecting conductor, the high frequency element is mounted on the back surface layer of the first dielectric substrate, and the high frequency element is a first
  • a connection conductor is connected between the ground conductors of the first and second dielectric substrates so as to surround the high frequency element, which is configured to be sandwiched between the back surface of the dielectric substrate and the surface of the second dielectric substrate. It has a shielded space.
  • the present invention has been made in view of the above, and it is an object of the present invention to obtain a high frequency package in which isolation between terminals is improved.
  • the present invention provides a first dielectric substrate provided with a signal wiring and a ground conductor on the back surface, and a first connection conductor on the back surface of the first dielectric substrate. And a second dielectric substrate provided with a signal wiring and a ground conductor on the surface facing the back surface and the high frequency element, and arranged to surround the high frequency element; A plurality of second connection conductors for connecting the ground conductor on the back surface of the dielectric substrate to the ground conductor on the surface of the second dielectric substrate, and the lower portion of the high frequency element on the surface of the second dielectric substrate And a dielectric space surrounded by the conductor pattern.
  • FIG. 1 is a diagram showing a circuit configuration of a high frequency package according to a first embodiment of the present invention.
  • FIG. 2 is a diagram showing a circuit configuration of a high frequency package according to a second embodiment of the present invention.
  • FIG. 3A is a diagram showing calculation results of isolation between terminals when there is no dielectric space.
  • FIG. 3B is a diagram of calculation results of isolation between terminals when there is a dielectric space according to the first embodiment of the present invention.
  • FIG. 1 is a diagram showing a circuit configuration of a high frequency package 100 according to a first embodiment of the present invention.
  • the high frequency package 100 includes a first dielectric substrate 10 having a signal wiring and a ground conductor on the back surface, a high frequency element 20 mounted on the first dielectric substrate 10 through the connection conductor 40, and a signal wiring on the surface surface.
  • a solder ball 41 which is a connection conductor connecting between the ground conductors 30 of the dielectric substrate 11, is provided.
  • the high frequency device 20 is mounted on the first dielectric substrate 10 via the connection conductor 40.
  • the high frequency device 20 is surrounded by the first dielectric substrate 10 and the second dielectric substrate 11 so that the solder balls 41 surround the high frequency device 20.
  • the ground conductor 30 of the dielectric substrate 11 is connected to each other and has a shielding space.
  • a dielectric space 60 configured by being surrounded by the via 50 which is a conductor and the inner layer pattern 51 is formed. For this reason, the effective dielectric constant in the shielding space is increased by the dielectric constant of the dielectric space 60, and the cavity resonant frequency is shifted to a lower frequency to improve the isolation between the terminals.
  • FIG. 3A shows the calculation result of isolation between terminals when there is no dielectric space
  • FIG. 3B shows the calculation result of isolation between terminals when there is a dielectric space.
  • FIG. 2 is a diagram showing a circuit configuration of the high frequency package 200 according to the second embodiment of the present invention.
  • the high frequency package 200 includes a first dielectric substrate 10 having a signal wiring and a ground conductor on the back surface, a high frequency element 20 mounted on the first dielectric substrate 10 through the connection conductor 40, and a signal wiring on the surface surface.
  • a second dielectric substrate 11, a first dielectric substrate 10 and a second dielectric substrate 11 having a ground conductor 30 and having a cavity 50 surrounded by a via 50 made of a conductor and an inner layer pattern 51.
  • the solder ball 41 which is a connection conductor which connects between the ground conductors 30 of these is provided.
  • the high frequency device 20 is mounted on the first dielectric substrate 10 via the connection conductor 40.
  • the high frequency device 20 is surrounded by the first dielectric substrate 10 and the second dielectric substrate 11 so that the solder balls 41 surround the high frequency device 20.
  • the ground conductor 30 of the dielectric substrate 11 is connected to each other and has a shielding space.
  • a cavity space 70 surrounded by the via 50 which is a conductor and the inner layer pattern 51 is formed.
  • the effective dielectric constant in the shielding space is reduced by the dielectric constant of the cavity space 70, and the cavity resonant frequency shifts to a high frequency, whereby the isolation between the terminals is improved.
  • the present invention is not limited to the above embodiment, and can be variously modified without departing from the scope of the invention at the implementation stage.
  • the above embodiments include inventions of various stages, and various inventions can be extracted by appropriate combinations of a plurality of disclosed configuration requirements.
  • the high frequency package according to the present invention is useful for isolation between terminals, and is particularly suitable when the high frequency element is an active element.
  • first dielectric substrate 11 second dielectric substrate 20 high frequency element 30 ground conductor 40 connection conductor 41 solder ball 50 via 51 inner layer pattern 60 dielectric space 70 cavity space 100, 200 high frequency package

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Signal Processing (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Waveguides (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
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Abstract

　実施の形態の高周波パッケージ１００は、裏面に信号配線と接地導体３０を設けた第１の誘電体基板１０と、第１の誘電体基板の裏面に第１接続導体４０を介して接続された高周波素子２０と、前記裏面と前記高周波素子を挟み込んで対向する表面に信号配線と接地導体３０を設けた第２の誘電体基板１１と、前記高周波素子を囲むように配置され、第１の誘電体基板の裏面の接地導体と第２の誘電体基板の表面の接地導体とを接続する複数の第２接続導体４１とを備える。実施の形態の高周波パッケージ１００は、前記第２の誘電体基板の表面の高周波素子の下部に、導体パターンで囲まれた誘電体空間６０が形成されている。

Description

高周波パッケージ
　本発明は、高周波パッケージに関する。
　従来の高周波パッケージの構成は、例えば特許文献１に開示されるように、裏面表層に信号配線と接地導体を有する第１の誘電体基板と、第１の誘電体基板の裏面表層に実装された高周波素子と、表面表層に信号配線と接地導体を有する第２の誘電体基板と、接続導体で構成され、高周波素子は第１の誘電体基板の裏面表層に実装され、高周波素子を第１の誘電体基板の裏面表層と第２の誘電体基板の表面表層とで挟みこむように構成され、接続導体が高周波素子を囲むように第１および第２の誘電体基板の接地導体間で接続され、遮蔽空間を有している。
国際公開第２０１０／０２６９９０号
　しかしながら、上記従来の技術によれば、高周波素子の１辺のサイズが基本周波数の１／２波長と近い大きさになった場合、空洞共振周波数が基本周波数近傍に発生する。このため、高周波素子がアクティブ素子であった場合、端子間のアイソレーションが確保できず、発振してしまうという問題があった。
　本発明は、上記に鑑みてなされたものであって、端子間のアイソレーションが改善した高周波パッケージを得ることを目的とする。
　上述した課題を解決し、目的を達成するために、本発明は、裏面に信号配線と接地導体を設けた第１の誘電体基板と、第１の誘電体基板の裏面に第１接続導体を介して接続された高周波素子と、前記裏面と前記高周波素子を挟み込んで対向する表面に信号配線と接地導体を設けた第２の誘電体基板と、前記高周波素子を囲むように配置され、第１の誘電体基板の裏面の接地導体と第２の誘電体基板の表面の接地導体とを接続する複数の第２接続導体とを備え、前記第２の誘電体基板の表面の高周波素子の下部に、導体パターンで囲まれた誘電体空間が形成されていることを特徴とする。
　本発明によれば、端子間のアイソレーションが改善した高周波パッケージを得るという効果を奏する。
図１は、本発明の実施の形態１にかかる高周波パッケージの回路構成を示す図である。 図２は、本発明の実施の形態２にかかる高周波パッケージの回路構成を示す図である。 図３－１は、誘電体空間が無い場合の端子間アイソレーションの計算結果を示す図である。 図３－２は、本発明の実施の形態１にかかる誘電体空間が有る場合の端子間アイソレーションの計算結果を示す図である。
　以下に、本発明にかかる高周波パッケージの実施の形態を図面に基づいて詳細に説明する。なお、この実施の形態によりこの発明が限定されるものではない。
実施の形態１．
　図１は、本発明の実施の形態１にかかる高周波パッケージ１００の回路構成を示す図である。高周波パッケージ１００は、裏面表層に信号配線と接地導体を有する第１の誘電体基板１０、接続導体４０を介して第１の誘電体基板１０に実装された高周波素子２０、表面表層に信号配線と接地導体３０を有し、導体からなるビア５０および内層パターン５１で周りを囲まれて構成された誘電体空間６０を有する第２の誘電体基板１１、第１の誘電体基板１０および第２の誘電体基板１１の接地導体３０間を接続する接続導体であるはんだボール４１を備える。
　実施の形態１にかかる高周波パッケージ１００の動作について説明する。高周波素子２０は、接続導体４０を介して第１の誘電体基板１０に実装されている。また、高周波素子２０は第１の誘電体基板１０と第２の誘電体基板１１で挟みこむように囲まれ、さらにはんだボール４１が高周波素子２０を囲むように第１の誘電体基板１０および第２の誘電体基板１１の接地導体３０の間で接続され、遮蔽空間を有している。
　ここで、第２の誘電体基板１１の高周波素子２０の下部には、導体であるビア５０および内層パターン５１で囲まれて構成される誘電体空間６０が構成されている。このため、遮蔽空間内の実効的な誘電率は誘電体空間６０の誘電率分だけ大きくなり、空洞共振周波数は低い周波数にずれることで端子間のアイソレーションが改善することになる。
　図３－１に誘電体空間が無い場合の端子間アイソレーションの計算結果を、図３－２に誘電体空間が有る場合の端子間アイソレーションの計算結果をそれぞれ示す。図３－１および図３－２を比較することで、本実施の形態による誘電体空間の存在により端子間アイソレーションが改善されることがわかる。
実施の形態２．
　図２は、本発明の実施の形態２にかかる高周波パッケージ２００の回路構成を示す図である。高周波パッケージ２００は、裏面表層に信号配線と接地導体を有する第１の誘電体基板１０、接続導体４０を介して第１の誘電体基板１０に実装された高周波素子２０、表面表層に信号配線と接地導体３０を有し、導体からなるビア５０および内層パターン５１で周りを囲まれたキャビティ空間７０を有する第２の誘電体基板１１、第１の誘電体基板１０および第２の誘電体基板１１の接地導体３０間を接続する接続導体であるはんだボール４１を備える。
　実施の形態２にかかる高周波パッケージ２００の動作について説明する。高周波素子２０は、接続導体４０を介して第１の誘電体基板１０に実装されている。また、高周波素子２０は第１の誘電体基板１０と第２の誘電体基板１１で挟みこむように囲まれ、さらにはんだボール４１が高周波素子２０を囲むように第１の誘電体基板１０および第２の誘電体基板１１の接地導体３０の間で接続され、遮蔽空間を有している。
　ここで、第２の誘電体基板１１の高周波素子２０の下部には、導体であるビア５０および内層パターン５１で囲まれたキャビティ空間７０が構成されている。このため、遮蔽空間内の実効的な誘電率はキャビティ空間７０の誘電率分だけ小さくなり、空洞共振周波数が高い周波数にずれることで端子間のアイソレーションが改善することになる。
　更に、本願発明は上記実施の形態に限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で種々に変形することが可能である。また、上記実施の形態には種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組み合わせにより種々の発明が抽出されうる。
　例えば、上記実施の形態１および２それぞれに示される全構成要件からいくつかの構成要件が削除されても、発明が解決しようとする課題の欄で述べた課題が解決でき、発明の効果の欄で述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出されうる。更に、上記実施の形態１および２にわたる構成要件を適宜組み合わせてもよい。
　以上のように、本発明にかかる高周波パッケージは、端子間のアイソレーションに有用であり、特に、高周波素子がアクティブ素子であった場合に適している。
　１０　第１の誘電体基板
　１１　第２の誘電体基板
　２０　高周波素子
　３０　接地導体
　４０　接続導体
　４１　はんだボール
　５０　ビア
　５１　内層パターン
　６０　誘電体空間
　７０　キャビティ空間
　１００、２００　高周波パッケージ

Claims (2)

  1. 　裏面に信号配線と接地導体を設けた第１の誘電体基板と、
    　第１の誘電体基板の裏面に第１接続導体を介して接続された高周波素子と、
    　前記裏面と前記高周波素子を挟み込んで対向する表面に信号配線と接地導体を設けた第２の誘電体基板と、
    　前記高周波素子を囲むように配置され、第１の誘電体基板の裏面の接地導体と第２の誘電体基板の表面の接地導体とを接続する複数の第２接続導体と、
    　を備え、
    　前記第２の誘電体基板の表面の高周波素子の下部に、導体パターンで囲まれた誘電体空間が形成されている
    　ことを特徴とする高周波パッケージ。
  2. 　前記導体パターンで囲まれた誘電体空間は、前記第２の誘電体基板を構成する誘電体が存在しないキャビティ空間
    　であることを特徴とする請求項１に記載の高周波パッケージ。
PCT/JP2012/052117 2011-04-14 2012-01-31 高周波パッケージ WO2012140934A1 (ja)

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US14/111,107 US9693492B2 (en) 2011-04-14 2012-01-31 High-frequency package
EP12771789.0A EP2698819B1 (en) 2011-04-14 2012-01-31 High-frequency package

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JP2015173140A (ja) * 2014-03-11 2015-10-01 三菱電機株式会社 高周波パッケージ
WO2024084556A1 (ja) * 2022-10-18 2024-04-25 三菱電機株式会社 高周波半導体パッケージ

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TWI570854B (zh) 2015-08-10 2017-02-11 頎邦科技股份有限公司 具中空腔室之半導體封裝結構及其下基板及製程
TWI663701B (zh) * 2017-04-28 2019-06-21 矽品精密工業股份有限公司 電子封裝件及其製法

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WO2024084556A1 (ja) * 2022-10-18 2024-04-25 三菱電機株式会社 高周波半導体パッケージ

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EP2698819A4 (en) 2014-10-01
EP2698819B1 (en) 2019-08-14
CN103460377A (zh) 2013-12-18
JP5693710B2 (ja) 2015-04-01
CN103460377B (zh) 2017-09-22
US9693492B2 (en) 2017-06-27
JPWO2012140934A1 (ja) 2014-07-28
US20140085858A1 (en) 2014-03-27
EP2698819A1 (en) 2014-02-19

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