WO2012132654A1 - Élément de conversion photoélectrique à jonction arrière et son procédé de fabrication - Google Patents

Élément de conversion photoélectrique à jonction arrière et son procédé de fabrication Download PDF

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WO2012132654A1
WO2012132654A1 PCT/JP2012/054232 JP2012054232W WO2012132654A1 WO 2012132654 A1 WO2012132654 A1 WO 2012132654A1 JP 2012054232 W JP2012054232 W JP 2012054232W WO 2012132654 A1 WO2012132654 A1 WO 2012132654A1
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semiconductor layer
amorphous semiconductor
opening
layer
photoelectric conversion
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PCT/JP2012/054232
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English (en)
Japanese (ja)
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三島　孝博
仁 坂田
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三洋電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a back junction photoelectric conversion element and a method for manufacturing a back junction photoelectric conversion element, and in particular, a back surface that uses an insulating layer to separately form a p-type region and an n-type region for forming the photoelectric conversion element.
  • the present invention relates to a method for manufacturing a junction type photoelectric conversion element and a back surface junction type photoelectric conversion element.
  • a solar cell is also called a photovoltaic device or a photoelectric conversion element, but is expected as a clean energy source, and various structures are used to improve photoelectric conversion efficiency.
  • Patent Document 1 discloses a configuration in which i-type amorphous silicon and p-type amorphous silicon are stacked on n-type single crystal silicon as a photovoltaic device having a heterojunction.
  • a solar cell is formed across a pair of second semiconductor layers disposed on both sides of the first semiconductor layer and from one of the second semiconductor layers to the first semiconductor layer.
  • the structure provided with the insulating layer and the insulating layer formed ranging over the 1st semiconductor layer from the other 2nd semiconductor layer is disclosed.
  • the transparent electrode layer and the collecting electrode layer are separated into an electrode for the first semiconductor layer and an electrode for the second semiconductor layer by a pair of separation grooves formed on the insulating layer.
  • the solar cell described in Patent Document 2 is provided with an electrode for the first semiconductor layer and an electrode for the second semiconductor layer on the back surface opposite to the light receiving surface.
  • Such a structure is called a back junction type photoelectric conversion element, and since no electrode is arranged on the light receiving surface, a large light receiving area can be obtained and the photoelectric conversion efficiency can be improved.
  • an insulating layer is used to make a p type region and an n type region separately.
  • the electrode opens this insulating layer and is connected to the p-type region or the n-type region.
  • a residue of the insulating layer may remain in the opening process. This hinders the improvement of conversion efficiency.
  • An object of the present invention is to provide a back junction type photoelectric conversion element and a method for manufacturing a back junction type photoelectric conversion element capable of reliably removing the influence of residues at the time of opening an insulating layer and ensuring improvement in conversion efficiency. It is to be.
  • the back junction type photoelectric conversion element includes a first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface, and is disposed on the back surface and connected to the semiconductor substrate.
  • a first conductive type region configured to include an amorphous semiconductor layer having a first conductive type region, and a first conductive type region disposed on the back surface and including an amorphous semiconductor layer having a second conductive type, and a pn junction
  • the method for manufacturing a back junction photoelectric conversion element according to the present invention is a method for manufacturing a back junction photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of the first conductivity type silicon substrate.
  • a method comprising: forming a first conductivity type region including an amorphous semiconductor layer having a first conductivity type on a back surface; and including an amorphous semiconductor layer having a second conductivity type A step of forming a second conductivity type region that forms a pn junction with the first conductivity type region on the back surface, and an amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region.
  • the method includes a step of forming an upper lead portion included as a crystalline semiconductor layer, and a step of forming an electrode layer provided in connection with the upper lead portion.
  • an opening is also provided in the amorphous semiconductor layer therebelow to expose the semiconductor substrate. Then, an amorphous semiconductor layer having the same conductivity type as the opened amorphous semiconductor layer is formed again so as to cover the opening, and is drawn out to the upper portion of the insulating layer while covering the opening. As described above, since the amorphous semiconductor layer is re-formed, even if there is a residue at the opening of the insulating layer, it is surely removed and the influence does not remain.
  • the conductivity type of the semiconductor substrate is described as n-type, but it may be p-type. Further, the order of formation of the amorphous semiconductor layers is n-type first and p-type thereafter, but this may be interchanged.
  • the opening of the insulating layer for the contact is provided at the n-type amorphous semiconductor layer, it may be provided at the p-type amorphous semiconductor layer.
  • an i-type amorphous semiconductor layer is used in addition to the p-type amorphous semiconductor layer and the n-type amorphous semiconductor layer. Therefore, even if an i-type amorphous semiconductor layer is included between pn junctions, it belongs to the pn junction.
  • FIG. 1 is a cross-sectional view of a back contact type photoelectric conversion element 14.
  • the back junction type photoelectric conversion element 14 has a pn junction for performing photoelectric conversion on the back surface opposite to the light receiving surface, and an electrode is provided only on the back surface. Thus, since no electrode is disposed on the light receiving surface, a large light receiving area can be obtained, and the photoelectric conversion efficiency per area is improved.
  • the lower side of the paper is the light-receiving surface side
  • the upper side is the back surface.
  • the back junction type photoelectric conversion element 14 is simply referred to as the photoelectric conversion element 14.
  • the photoelectric conversion element 14 is provided with an n-type region 100 and a p-type region 102 on the back surface of a semiconductor substrate 20 which is an n-type silicon single crystal substrate.
  • the n-type region 100 is connected to the semiconductor substrate 20 and includes an n-type amorphous semiconductor layer 28 having the same conductivity type.
  • the i-type amorphous semiconductor layer 24 is provided between the semiconductor substrate 20 and the n-type amorphous semiconductor layer 28, but the i-type amorphous semiconductor layer 24 is not necessarily an essential component.
  • the p-type region 102 includes a p-type amorphous semiconductor layer 44 and forms a pn junction with the n-type region 100.
  • an i-type amorphous semiconductor layer 42 is provided between the semiconductor substrate 20 and the p-type amorphous semiconductor layer 44, but the i-type amorphous semiconductor layer 42 is not necessarily an essential component. .
  • the n-type region electrode 70 is a plating electrode connected to the n-type amorphous semiconductor layer 28.
  • the electrode 70 has a laminated structure of Sn and Cu.
  • the base electrodes 60 and 62 provided between the n-type region electrode 70 and the n-type amorphous semiconductor layer 28 are seed layers used when the electrode 70 is plated.
  • the base electrodes 60 and 62 have a laminated structure of a transparent electrode layer 60 and a Cu layer 62.
  • the electrode 72 for the p-type region is a plating electrode connected to the p-type amorphous semiconductor layer 44. Similar to the electrode 70, the electrode 72 has a laminated structure of Sn and Cu, and is formed by plating using the base electrodes 60 and 62. Comparing the n-type region electrode 70 and the p-type region electrode 72, the former electrode height is higher than the latter electrode height. This is because the surface area of the former base electrodes 60 and 62 is set smaller than the surface area of the latter base electrodes 60 and 62. That is, when plating is performed using the base electrodes 60 and 62 in common, the plating current density varies depending on the surface area difference, and the smaller surface area grows faster.
  • the electrode 72 for the p-type region is provided directly on the p-type amorphous semiconductor layer 44 via the base electrodes 60 and 62.
  • the electrode 70 for the n-type region is provided with an opening in the insulating layer of the silicon nitride layer 40, and subsequently to the opening, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24. Also provided are openings, and another i-type amorphous semiconductor layer 50 and an n-type amorphous semiconductor layer 52 are formed so as to cover these openings, and this is connected to the portion drawn upward.
  • the photoelectric conversion element 14 is described as described below. Is characterized in that this upper drawing part 53 is provided.
  • the i-type amorphous semiconductor layer 22 and the n-type amorphous semiconductor layer 26 provided on the light receiving surface of the semiconductor substrate 20 are layers having a function as a passivation layer of the semiconductor substrate 20 on which photoelectric conversion is performed.
  • the antireflection layer 38 is an insulating film layer having a function of suppressing reflection on the light receiving surface.
  • FIG. 2 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 14. This procedure will be described with reference to FIGS. 3 to 16 except for S28. S28 will be described later with reference to FIGS. 17 to 21 as a photoelectric conversion element 16 having another structure.
  • a semiconductor substrate 20 which is an n-type silicon single crystal substrate is prepared.
  • the plane direction is preferably (100).
  • the surface serving as the light receiving surface has a texture structure. For example, pyramidal irregularities surrounded by the (111) plane can be provided on the surface by utilizing the plane anisotropy of silicon etching.
  • the semiconductor substrate 20 is entirely cleaned with an appropriate cleaning solution for the next step.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are sequentially deposited on the semiconductor substrate 20 having a clean surface (S10).
  • Deposition is also called deposition and is a process of forming a thin film. This step can be performed using a plasma CVD apparatus.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are both formed on the front surface and the back surface of the semiconductor substrate 20.
  • an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 and an n-type amorphous semiconductor layer 28 are formed on the back surface. Is shown.
  • the silicon nitride layer is deposited (S12). This process is also performed using a plasma CVD apparatus.
  • a typical example of silicon nitride is Si 3 N 4 , but the composition of Si 3 N 4 does not necessarily depend on the manufacturing conditions of the plasma CVD apparatus. Generally, the composition is SiN x .
  • the thickness of the silicon nitride layer 40 is about 10 nm to 500 nm.
  • FIG. 4 shows how the silicon nitride layer 40 is formed on the back surface.
  • An antireflection layer 38 is formed on the surface that becomes the light receiving surface. Since a silicon nitride film can be used as the antireflection layer 38, the same film as the silicon nitride layer 40 on the back surface may be formed on the light receiving surface side at the same time. However, the silicon nitride layer 40 on the back surface is used for subsequent patterning and etching characteristics are important, whereas the antireflection layer 38 has optical characteristics important. Therefore, the back side silicon nitride layer 40 and the antireflection layer 38 are preferably insulating films having different film characteristics. In the following, the description will be made while distinguishing the silicon nitride layer 40 on the back surface and the antireflection layer 38 on the light receiving surface side.
  • the silicon nitride layer 40 on the back surface can be formed by changing the film composition, for example, so that the etching characteristics can be distinguished from those having alkali resistance and those having acid resistance.
  • the n-type amorphous semiconductor layer 28 side can be formed as an acid-resistant film, and an alkali-resistant film can be formed thereon.
  • the silicon nitride layer in contact with the resist film is preferably resistant to alkali.
  • the silicon nitride layer 40 is partially removed (S14).
  • a photolithography technique is used for this processing. That is, a photosensitive resist film is applied to the entire surface of the silicon nitride layer 40, the resist film in a portion where the silicon nitride layer 40 is to be removed is exposed, and the resist film in that portion is removed by development. This process is patterning of the resist film. Then, using the resist film as an etching mask, a portion of the silicon nitride layer 40 without the resist film is removed using an appropriate etching solution. As the etchant, hydrofluoric acid which is a mixture of HF and nitric acid can be used. After the etching, washing with water is performed.
  • FIG. 5 shows the patterned resist film 80 and the remaining silicon nitride layer 40 using the resist film 80 as an etching mask. Thereafter, the resist film 80 is removed. Since the resist film 80 is soluble in alkali, only the resist film 80 can be removed using caustic soda (NaOH) while leaving the silicon nitride layer 40 as it is.
  • CaOH caustic soda
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 thereunder are formed using the silicon nitride layer 40 as an etching mask. It is removed (S16).
  • caustic soda (NaOH) is used by utilizing the fact that the amorphous semiconductor layer dissolves in alkali.
  • the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing.
  • the hydrofluoric acid is used to remove the oxide film formed by SC2.
  • FIG. 6 shows a state in which the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 are left in the shape of the silicon nitride layer 40 and the semiconductor substrate 20 is exposed in other portions. . In this way, opening of the portion of the p-type region 102 is performed.
  • the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are deposited on the entire surface (S18). This step is performed using a plasma CVD apparatus.
  • an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are in contact with the semiconductor substrate 20 which is an n-type silicon single crystal substrate in the opened p-type region 102. Is shown. Note that an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are also deposited on the silicon nitride layer 40.
  • the n-type region 100 includes a p-type amorphous semiconductor layer 44, an i-type amorphous semiconductor layer 42, a silicon nitride layer 40, and an n-type amorphous semiconductor layer from the top. 28, i-type amorphous semiconductor layer 24 is present.
  • an opening process is performed through these, and the surface of the semiconductor substrate 20 which is an n-type silicon single crystal substrate is exposed.
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed (S20).
  • a photolithography technique is used for this processing. That is, a resist film is applied, and the applied resist film is patterned to remove the n-contact portion by exposure and development. A solvent-soluble type having acid resistance and alkali resistance is used for the resist film.
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 can be removed using caustic soda (NaOH). Thereafter, cleaning is performed.
  • FIG. 8 shows a state where the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed from the opening 83 of the resist film 82.
  • the resist film 82 is removed using an appropriate solvent. Then, using the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 as an etching mask, the silicon nitride layer 40 is removed (S22). As the etching solution, hydrofluoric acid is used. Here, the amorphous semiconductor layer utilizes the property that it is not very soluble in hydrofluoric acid. In this step, it is preferable to provide a protective film such as a resist so that the antireflection layer 38 on the light receiving surface side is not etched.
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 corresponding to the opening are removed (S24).
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are used as etching masks, and the caustic soda (NaOH) described in S16 is used as an etchant.
  • the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing.
  • the hydrofluoric acid is used to remove the oxide film formed by SC2.
  • the amorphous semiconductor layer is soluble in alkali, but the etching rate of the p-type amorphous semiconductor is lower than the etching rate of the n-type amorphous semiconductor.
  • the n-type amorphous semiconductor layer 28 can be etched using the p-type amorphous semiconductor layer 44 as an etching mask.
  • silicon nitride formed by plasma CVD can be removed by hydrofluoric acid, in practice, a minute residue remains, and it may take a considerable time to completely remove the residue.
  • silicon nitride formed by a plasma CVD apparatus may not have a stoichiometric composition of Si 3 N 4 but may have an excessively large Si composition such as Si 3.5 N 4. Conceivable.
  • electrical contact between the electrode and the n-type amorphous semiconductor layer 28 is hindered, and the photoelectric conversion efficiency of the photoelectric conversion element 14 is reduced. Become.
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 corresponding to the opening are removed while the opening is formed in the silicon nitride layer 40. Therefore, even if there is a silicon nitride residue on the n-type amorphous semiconductor layer 28, the silicon nitride residue is removed along with the removal of the n-type amorphous semiconductor layer 28. It has no effect on the process.
  • the size of the opening 83 defined by the resist film is set such that the p-type amorphous semiconductor layer 44, the i-type amorphous semiconductor layer 42, the silicon nitride layer 40, and the n-type amorphous semiconductor layer 28.
  • the i-type amorphous semiconductor layer 24 is sequentially opened, and the surface of the semiconductor substrate 20 which is an n-type silicon single crystal substrate is exposed.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are again deposited (S26).
  • the same amorphous semiconductor layer is formed again in the opening 83 from which the i-type amorphous semiconductor layer 24 formed in S10 and the n-type amorphous semiconductor layer 28 are removed.
  • FIG. 10 shows how the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are formed on the entire surface.
  • an unnecessary portion can be removed while leaving a portion necessary for electrode connection of the n-type region 100.
  • a resist film for removing unnecessary portions is formed (S30), unnecessary portions are removed using the resist film as an etching mask (S32), and then the resist film is removed (S34).
  • FIG. 11 shows how the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are formed by patterning the resist film 88 to a required size B.
  • the size B of the necessary portion is set larger than the size A of the opening area of the opening 83 in FIG.
  • the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are connected to the semiconductor substrate 20 through the opening 83 and cover the opening 83 so as to cover the upper portion of the silicon nitride layer 40 that is an insulating layer. Pulled out. This part to be drawn out is the upper drawing part 53.
  • FIG. 12 is a view showing a state where the resist film 88 is removed.
  • the base electrode is a conductive seed layer for forming a plating electrode.
  • a transparent electrode layer called a TCO (Transparent Conductive Oxide) layer is formed over the entire surface, and a Cu layer is formed over the entire surface.
  • TCO Transparent Conductive Oxide
  • the light-transmitting conductive layer indium tin oxide or the like can be used.
  • the thickness of the TCO layer which is a transparent electrode layer, is about 100 nm, and the thickness of the Cu layer is about 100 nm to 1 ⁇ m.
  • This step is processed using a sputtering apparatus.
  • FIG. 13 shows a state in which a laminated structure of the transparent electrode layer 60 and the Cu layer 62 is formed on the entire surface as the base electrodes 60 and 62.
  • a resist film for electrode separation is formed (S42). This is because the n-type region electrode 70 and the p-type region electrode 72 are electrically separated and plated.
  • a resist film is applied, and patterning is performed by exposure and development to form a separation groove at the boundary between the n-type region portion and the p-type region portion.
  • FIG. 14 shows a resist film 84 in which a separation groove 85 is formed.
  • FIG. 15 shows a state in which the base electrodes 60 and 62 at the separation groove 85 are removed by this etching. At this time, it is preferable that the end portion of the upper lead portion 53 is not exposed at the separation groove 85 and is covered with the base electrodes 60 and 62.
  • FIG. 16 shows a state in which the resist film is removed, and the base electrodes 60 and 62 are separated into the n-type region 100 and the p-type region 102 by the separation unit 86.
  • a plating electrode is formed (S48). Specifically, cleaning with sulfuric acid (H 2 SO 4 ), electrolytic plating of Cu using a plating bath and subsequent cleaning, electrolytic plating of Sn using a plating bath, and subsequent cleaning are sequentially performed.
  • the thickness of the Cu plating layer is about 10 ⁇ m to 20 ⁇ m, and the thickness of the Sn plating layer is 1 ⁇ m to 5 ⁇ m. In this way, the photoelectric conversion element 14 having the structure described in FIG. 1 is completed.
  • the resist film 88 is applied on the n-type amorphous semiconductor layer 52 in S30. Since the amorphous semiconductor layer is easily etched by a chemical solution, it is preferable that the amorphous semiconductor layer is not subjected to a wet process as much as possible. Therefore, it is preferable to form an appropriate conductive thin film on the n-type amorphous semiconductor layer 52 and apply a resist film 88 to the conductive thin film.
  • a TCO film is used as the conductive thin film, and the TCO film is deposited on the n-type amorphous semiconductor layer 52. This step is performed using a sputtering apparatus.
  • FIG. 17 is a cross-sectional view of the photoelectric conversion element 16 having a structure to which the process of S28 is added.
  • a laminated structure of an i-type amorphous semiconductor layer 50, an n-type amorphous semiconductor layer 52, and a transparent electrode layer 54 that is a TCO film is shown as the upper lead portion 53.
  • FIG. 18 is a diagram showing a state in which the transparent electrode layer 54 is formed on the entire surface following the step S26 described in FIG.
  • FIG. 19 is a view corresponding to FIG. 11 and, as shown here, the transparent electrode layer 54 is disposed between the resist film 88 and the n-type amorphous semiconductor layer 52.
  • the semiconductor layer 52 can be prevented from being directly exposed to the wet process.
  • FIG. 20 is a diagram corresponding to FIG. 12, and FIG. 21 is a diagram corresponding to FIG. In either case, a laminated structure of an i-type amorphous semiconductor layer 50, an n-type amorphous semiconductor layer 52, and a transparent electrode layer 54 that is a TCO film is shown as the upper lead portion 53. Subsequent steps are the same except that the upper lead portion 53 includes the transparent electrode layer 54, and thus description thereof is omitted.
  • FIG. 22 is a diagram corresponding to FIG. 1.
  • photoelectric is used to extract an electrode from the n-type amorphous semiconductor layer 28 under the silicon nitride layer 40 that is an insulating layer without using the upper lead portion.
  • 3 is a sectional view of a conversion element 12.
  • FIG. The n-type region 100 has the same configuration as that shown in FIG. 1 except that there is no upper lead portion, and thus detailed description thereof is omitted.
  • FIG. 23 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 12 of the comparative example.
  • the removal process of the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 in the n-contact of S24, the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer of S26 It can be seen that the position process and the process of removing unnecessary parts of S30, S32, and S34 are omitted in 52. That is, S10, S12, S14, S16, S18, S20, and S22 in FIG. 23 are exactly the same as S10, S12, S14, S16, S18, S20, and S22 in FIG. Therefore, the different steps will be mainly described.
  • FIG. 24 is a diagram showing the first deposition process of the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28 in S10, and has the same contents as FIG.
  • S12, S14, S16, S18, and S20 the processing for the semiconductor substrate 20 including the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28 is sequentially performed. From FIG. 8, the detailed description is omitted.
  • FIG. 25 is a diagram showing the state of SiN x removal for the n-contact in S22.
  • an opening 83 is provided in the silicon nitride layer 40 that is an insulating layer, but no opening is provided in the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28.
  • FIG. 26 is a diagram illustrating the formation of the base electrodes 60 and 62 in S40, and corresponds to FIG. Compared with FIG. 13, since there is no upper lead portion 53, the base electrodes 60 and 62 are connected to the n-type amorphous semiconductor layer 28.
  • FIG. 27 is a diagram showing the electrode separation resist formation in S42 and corresponds to FIG.
  • FIG. 28 shows the electrode etching in S44, which corresponds to FIG.
  • FIG. 29 is a diagram showing how the resist is removed in S46, and corresponds to FIG. The processing contents of these are the same, except that there is no upper lead portion 53 under the base electrodes 60 and 62.
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 under the silicon nitride layer 40 which is an insulating layer. Even if there is a residue during the opening process of the silicon nitride layer 40, it is removed satisfactorily and does not affect the subsequent steps. Then, the upper lead portion 53 is provided in this opening, and the electrode 70 of the n-type region 100 can be formed.
  • the back junction type photoelectric conversion element and the back junction type photoelectric conversion element manufacturing method according to the present invention can be used for a photovoltaic power generation system or the like.

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Abstract

Dans cet élément de conversion photoélectrique (14), une région de type n (100) contenant une couche semi-conductrice amorphe de type n (28) et une région de type p (102) contenant une couche semi-conductrice amorphe de type p (44) sont formées sur la surface arrière d'un substrat semi-conducteur (20), à savoir un substrat de silicium monocristallin de type n. Dans la région de type n (100), un orifice est formé dans une couche isolante de nitrure de silicium (40), la couche semi-conductrice amorphe de type n (28) et une couche semi-conductrice amorphe de type i (24) sont retirées du dessous de la couche isolante, et tout résidu de nitrure de silicium laissé sur celle-ci est retiré simultanément si tel est le cas. Une partie sortie supérieure (53) contenant une couche semi-conductrice amorphe de type i (50) et une couche semi-conductrice amorphe de type n (52) est ensuite formée dans l'orifice, ce qui crée sur celle-ci une électrode (70).
PCT/JP2012/054232 2011-03-25 2012-02-22 Élément de conversion photoélectrique à jonction arrière et son procédé de fabrication WO2012132654A1 (fr)

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WO2010113750A1 (fr) * 2009-03-30 2010-10-07 三洋電機株式会社 Pile solaire
JP2012028718A (ja) * 2010-07-28 2012-02-09 Sanyo Electric Co Ltd 太陽電池の製造方法
JP2012033666A (ja) * 2010-07-30 2012-02-16 Sanyo Electric Co Ltd 太陽電池の製造方法及び太陽電池
JP2012033810A (ja) * 2010-08-02 2012-02-16 Sanyo Electric Co Ltd 太陽電池の製造方法
JP2012049193A (ja) * 2010-08-24 2012-03-08 Sanyo Electric Co Ltd 太陽電池の製造方法

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WO2010113750A1 (fr) * 2009-03-30 2010-10-07 三洋電機株式会社 Pile solaire
JP2012028718A (ja) * 2010-07-28 2012-02-09 Sanyo Electric Co Ltd 太陽電池の製造方法
JP2012033666A (ja) * 2010-07-30 2012-02-16 Sanyo Electric Co Ltd 太陽電池の製造方法及び太陽電池
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11355654B2 (en) * 2016-04-01 2022-06-07 Sunpower Corporation Tri-layer semiconductor stacks for patterning features on solar cells
US11935972B2 (en) 2016-04-01 2024-03-19 Maxeon Solar Pte. Ltd. Tri-layer semiconductor stacks for patterning features on solar cells

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