WO2012132654A1 - Back-junction photoelectric conversion element and method for manufacturing back-junction photoelectric conversion element - Google Patents

Back-junction photoelectric conversion element and method for manufacturing back-junction photoelectric conversion element Download PDF

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WO2012132654A1
WO2012132654A1 PCT/JP2012/054232 JP2012054232W WO2012132654A1 WO 2012132654 A1 WO2012132654 A1 WO 2012132654A1 JP 2012054232 W JP2012054232 W JP 2012054232W WO 2012132654 A1 WO2012132654 A1 WO 2012132654A1
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semiconductor layer
amorphous semiconductor
opening
layer
photoelectric conversion
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PCT/JP2012/054232
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French (fr)
Japanese (ja)
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三島　孝博
仁 坂田
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三洋電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a back junction photoelectric conversion element and a method for manufacturing a back junction photoelectric conversion element, and in particular, a back surface that uses an insulating layer to separately form a p-type region and an n-type region for forming the photoelectric conversion element.
  • the present invention relates to a method for manufacturing a junction type photoelectric conversion element and a back surface junction type photoelectric conversion element.
  • a solar cell is also called a photovoltaic device or a photoelectric conversion element, but is expected as a clean energy source, and various structures are used to improve photoelectric conversion efficiency.
  • Patent Document 1 discloses a configuration in which i-type amorphous silicon and p-type amorphous silicon are stacked on n-type single crystal silicon as a photovoltaic device having a heterojunction.
  • a solar cell is formed across a pair of second semiconductor layers disposed on both sides of the first semiconductor layer and from one of the second semiconductor layers to the first semiconductor layer.
  • the structure provided with the insulating layer and the insulating layer formed ranging over the 1st semiconductor layer from the other 2nd semiconductor layer is disclosed.
  • the transparent electrode layer and the collecting electrode layer are separated into an electrode for the first semiconductor layer and an electrode for the second semiconductor layer by a pair of separation grooves formed on the insulating layer.
  • the solar cell described in Patent Document 2 is provided with an electrode for the first semiconductor layer and an electrode for the second semiconductor layer on the back surface opposite to the light receiving surface.
  • Such a structure is called a back junction type photoelectric conversion element, and since no electrode is arranged on the light receiving surface, a large light receiving area can be obtained and the photoelectric conversion efficiency can be improved.
  • an insulating layer is used to make a p type region and an n type region separately.
  • the electrode opens this insulating layer and is connected to the p-type region or the n-type region.
  • a residue of the insulating layer may remain in the opening process. This hinders the improvement of conversion efficiency.
  • An object of the present invention is to provide a back junction type photoelectric conversion element and a method for manufacturing a back junction type photoelectric conversion element capable of reliably removing the influence of residues at the time of opening an insulating layer and ensuring improvement in conversion efficiency. It is to be.
  • the back junction type photoelectric conversion element includes a first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface, and is disposed on the back surface and connected to the semiconductor substrate.
  • a first conductive type region configured to include an amorphous semiconductor layer having a first conductive type region, and a first conductive type region disposed on the back surface and including an amorphous semiconductor layer having a second conductive type, and a pn junction
  • the method for manufacturing a back junction photoelectric conversion element according to the present invention is a method for manufacturing a back junction photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of the first conductivity type silicon substrate.
  • a method comprising: forming a first conductivity type region including an amorphous semiconductor layer having a first conductivity type on a back surface; and including an amorphous semiconductor layer having a second conductivity type A step of forming a second conductivity type region that forms a pn junction with the first conductivity type region on the back surface, and an amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region.
  • the method includes a step of forming an upper lead portion included as a crystalline semiconductor layer, and a step of forming an electrode layer provided in connection with the upper lead portion.
  • an opening is also provided in the amorphous semiconductor layer therebelow to expose the semiconductor substrate. Then, an amorphous semiconductor layer having the same conductivity type as the opened amorphous semiconductor layer is formed again so as to cover the opening, and is drawn out to the upper portion of the insulating layer while covering the opening. As described above, since the amorphous semiconductor layer is re-formed, even if there is a residue at the opening of the insulating layer, it is surely removed and the influence does not remain.
  • the conductivity type of the semiconductor substrate is described as n-type, but it may be p-type. Further, the order of formation of the amorphous semiconductor layers is n-type first and p-type thereafter, but this may be interchanged.
  • the opening of the insulating layer for the contact is provided at the n-type amorphous semiconductor layer, it may be provided at the p-type amorphous semiconductor layer.
  • an i-type amorphous semiconductor layer is used in addition to the p-type amorphous semiconductor layer and the n-type amorphous semiconductor layer. Therefore, even if an i-type amorphous semiconductor layer is included between pn junctions, it belongs to the pn junction.
  • FIG. 1 is a cross-sectional view of a back contact type photoelectric conversion element 14.
  • the back junction type photoelectric conversion element 14 has a pn junction for performing photoelectric conversion on the back surface opposite to the light receiving surface, and an electrode is provided only on the back surface. Thus, since no electrode is disposed on the light receiving surface, a large light receiving area can be obtained, and the photoelectric conversion efficiency per area is improved.
  • the lower side of the paper is the light-receiving surface side
  • the upper side is the back surface.
  • the back junction type photoelectric conversion element 14 is simply referred to as the photoelectric conversion element 14.
  • the photoelectric conversion element 14 is provided with an n-type region 100 and a p-type region 102 on the back surface of a semiconductor substrate 20 which is an n-type silicon single crystal substrate.
  • the n-type region 100 is connected to the semiconductor substrate 20 and includes an n-type amorphous semiconductor layer 28 having the same conductivity type.
  • the i-type amorphous semiconductor layer 24 is provided between the semiconductor substrate 20 and the n-type amorphous semiconductor layer 28, but the i-type amorphous semiconductor layer 24 is not necessarily an essential component.
  • the p-type region 102 includes a p-type amorphous semiconductor layer 44 and forms a pn junction with the n-type region 100.
  • an i-type amorphous semiconductor layer 42 is provided between the semiconductor substrate 20 and the p-type amorphous semiconductor layer 44, but the i-type amorphous semiconductor layer 42 is not necessarily an essential component. .
  • the n-type region electrode 70 is a plating electrode connected to the n-type amorphous semiconductor layer 28.
  • the electrode 70 has a laminated structure of Sn and Cu.
  • the base electrodes 60 and 62 provided between the n-type region electrode 70 and the n-type amorphous semiconductor layer 28 are seed layers used when the electrode 70 is plated.
  • the base electrodes 60 and 62 have a laminated structure of a transparent electrode layer 60 and a Cu layer 62.
  • the electrode 72 for the p-type region is a plating electrode connected to the p-type amorphous semiconductor layer 44. Similar to the electrode 70, the electrode 72 has a laminated structure of Sn and Cu, and is formed by plating using the base electrodes 60 and 62. Comparing the n-type region electrode 70 and the p-type region electrode 72, the former electrode height is higher than the latter electrode height. This is because the surface area of the former base electrodes 60 and 62 is set smaller than the surface area of the latter base electrodes 60 and 62. That is, when plating is performed using the base electrodes 60 and 62 in common, the plating current density varies depending on the surface area difference, and the smaller surface area grows faster.
  • the electrode 72 for the p-type region is provided directly on the p-type amorphous semiconductor layer 44 via the base electrodes 60 and 62.
  • the electrode 70 for the n-type region is provided with an opening in the insulating layer of the silicon nitride layer 40, and subsequently to the opening, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24. Also provided are openings, and another i-type amorphous semiconductor layer 50 and an n-type amorphous semiconductor layer 52 are formed so as to cover these openings, and this is connected to the portion drawn upward.
  • the photoelectric conversion element 14 is described as described below. Is characterized in that this upper drawing part 53 is provided.
  • the i-type amorphous semiconductor layer 22 and the n-type amorphous semiconductor layer 26 provided on the light receiving surface of the semiconductor substrate 20 are layers having a function as a passivation layer of the semiconductor substrate 20 on which photoelectric conversion is performed.
  • the antireflection layer 38 is an insulating film layer having a function of suppressing reflection on the light receiving surface.
  • FIG. 2 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 14. This procedure will be described with reference to FIGS. 3 to 16 except for S28. S28 will be described later with reference to FIGS. 17 to 21 as a photoelectric conversion element 16 having another structure.
  • a semiconductor substrate 20 which is an n-type silicon single crystal substrate is prepared.
  • the plane direction is preferably (100).
  • the surface serving as the light receiving surface has a texture structure. For example, pyramidal irregularities surrounded by the (111) plane can be provided on the surface by utilizing the plane anisotropy of silicon etching.
  • the semiconductor substrate 20 is entirely cleaned with an appropriate cleaning solution for the next step.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are sequentially deposited on the semiconductor substrate 20 having a clean surface (S10).
  • Deposition is also called deposition and is a process of forming a thin film. This step can be performed using a plasma CVD apparatus.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are both formed on the front surface and the back surface of the semiconductor substrate 20.
  • an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 and an n-type amorphous semiconductor layer 28 are formed on the back surface. Is shown.
  • the silicon nitride layer is deposited (S12). This process is also performed using a plasma CVD apparatus.
  • a typical example of silicon nitride is Si 3 N 4 , but the composition of Si 3 N 4 does not necessarily depend on the manufacturing conditions of the plasma CVD apparatus. Generally, the composition is SiN x .
  • the thickness of the silicon nitride layer 40 is about 10 nm to 500 nm.
  • FIG. 4 shows how the silicon nitride layer 40 is formed on the back surface.
  • An antireflection layer 38 is formed on the surface that becomes the light receiving surface. Since a silicon nitride film can be used as the antireflection layer 38, the same film as the silicon nitride layer 40 on the back surface may be formed on the light receiving surface side at the same time. However, the silicon nitride layer 40 on the back surface is used for subsequent patterning and etching characteristics are important, whereas the antireflection layer 38 has optical characteristics important. Therefore, the back side silicon nitride layer 40 and the antireflection layer 38 are preferably insulating films having different film characteristics. In the following, the description will be made while distinguishing the silicon nitride layer 40 on the back surface and the antireflection layer 38 on the light receiving surface side.
  • the silicon nitride layer 40 on the back surface can be formed by changing the film composition, for example, so that the etching characteristics can be distinguished from those having alkali resistance and those having acid resistance.
  • the n-type amorphous semiconductor layer 28 side can be formed as an acid-resistant film, and an alkali-resistant film can be formed thereon.
  • the silicon nitride layer in contact with the resist film is preferably resistant to alkali.
  • the silicon nitride layer 40 is partially removed (S14).
  • a photolithography technique is used for this processing. That is, a photosensitive resist film is applied to the entire surface of the silicon nitride layer 40, the resist film in a portion where the silicon nitride layer 40 is to be removed is exposed, and the resist film in that portion is removed by development. This process is patterning of the resist film. Then, using the resist film as an etching mask, a portion of the silicon nitride layer 40 without the resist film is removed using an appropriate etching solution. As the etchant, hydrofluoric acid which is a mixture of HF and nitric acid can be used. After the etching, washing with water is performed.
  • FIG. 5 shows the patterned resist film 80 and the remaining silicon nitride layer 40 using the resist film 80 as an etching mask. Thereafter, the resist film 80 is removed. Since the resist film 80 is soluble in alkali, only the resist film 80 can be removed using caustic soda (NaOH) while leaving the silicon nitride layer 40 as it is.
  • CaOH caustic soda
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 thereunder are formed using the silicon nitride layer 40 as an etching mask. It is removed (S16).
  • caustic soda (NaOH) is used by utilizing the fact that the amorphous semiconductor layer dissolves in alkali.
  • the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing.
  • the hydrofluoric acid is used to remove the oxide film formed by SC2.
  • FIG. 6 shows a state in which the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 are left in the shape of the silicon nitride layer 40 and the semiconductor substrate 20 is exposed in other portions. . In this way, opening of the portion of the p-type region 102 is performed.
  • the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are deposited on the entire surface (S18). This step is performed using a plasma CVD apparatus.
  • an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are in contact with the semiconductor substrate 20 which is an n-type silicon single crystal substrate in the opened p-type region 102. Is shown. Note that an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are also deposited on the silicon nitride layer 40.
  • the n-type region 100 includes a p-type amorphous semiconductor layer 44, an i-type amorphous semiconductor layer 42, a silicon nitride layer 40, and an n-type amorphous semiconductor layer from the top. 28, i-type amorphous semiconductor layer 24 is present.
  • an opening process is performed through these, and the surface of the semiconductor substrate 20 which is an n-type silicon single crystal substrate is exposed.
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed (S20).
  • a photolithography technique is used for this processing. That is, a resist film is applied, and the applied resist film is patterned to remove the n-contact portion by exposure and development. A solvent-soluble type having acid resistance and alkali resistance is used for the resist film.
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 can be removed using caustic soda (NaOH). Thereafter, cleaning is performed.
  • FIG. 8 shows a state where the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed from the opening 83 of the resist film 82.
  • the resist film 82 is removed using an appropriate solvent. Then, using the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 as an etching mask, the silicon nitride layer 40 is removed (S22). As the etching solution, hydrofluoric acid is used. Here, the amorphous semiconductor layer utilizes the property that it is not very soluble in hydrofluoric acid. In this step, it is preferable to provide a protective film such as a resist so that the antireflection layer 38 on the light receiving surface side is not etched.
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 corresponding to the opening are removed (S24).
  • the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are used as etching masks, and the caustic soda (NaOH) described in S16 is used as an etchant.
  • the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing.
  • the hydrofluoric acid is used to remove the oxide film formed by SC2.
  • the amorphous semiconductor layer is soluble in alkali, but the etching rate of the p-type amorphous semiconductor is lower than the etching rate of the n-type amorphous semiconductor.
  • the n-type amorphous semiconductor layer 28 can be etched using the p-type amorphous semiconductor layer 44 as an etching mask.
  • silicon nitride formed by plasma CVD can be removed by hydrofluoric acid, in practice, a minute residue remains, and it may take a considerable time to completely remove the residue.
  • silicon nitride formed by a plasma CVD apparatus may not have a stoichiometric composition of Si 3 N 4 but may have an excessively large Si composition such as Si 3.5 N 4. Conceivable.
  • electrical contact between the electrode and the n-type amorphous semiconductor layer 28 is hindered, and the photoelectric conversion efficiency of the photoelectric conversion element 14 is reduced. Become.
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 corresponding to the opening are removed while the opening is formed in the silicon nitride layer 40. Therefore, even if there is a silicon nitride residue on the n-type amorphous semiconductor layer 28, the silicon nitride residue is removed along with the removal of the n-type amorphous semiconductor layer 28. It has no effect on the process.
  • the size of the opening 83 defined by the resist film is set such that the p-type amorphous semiconductor layer 44, the i-type amorphous semiconductor layer 42, the silicon nitride layer 40, and the n-type amorphous semiconductor layer 28.
  • the i-type amorphous semiconductor layer 24 is sequentially opened, and the surface of the semiconductor substrate 20 which is an n-type silicon single crystal substrate is exposed.
  • the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are again deposited (S26).
  • the same amorphous semiconductor layer is formed again in the opening 83 from which the i-type amorphous semiconductor layer 24 formed in S10 and the n-type amorphous semiconductor layer 28 are removed.
  • FIG. 10 shows how the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are formed on the entire surface.
  • an unnecessary portion can be removed while leaving a portion necessary for electrode connection of the n-type region 100.
  • a resist film for removing unnecessary portions is formed (S30), unnecessary portions are removed using the resist film as an etching mask (S32), and then the resist film is removed (S34).
  • FIG. 11 shows how the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are formed by patterning the resist film 88 to a required size B.
  • the size B of the necessary portion is set larger than the size A of the opening area of the opening 83 in FIG.
  • the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are connected to the semiconductor substrate 20 through the opening 83 and cover the opening 83 so as to cover the upper portion of the silicon nitride layer 40 that is an insulating layer. Pulled out. This part to be drawn out is the upper drawing part 53.
  • FIG. 12 is a view showing a state where the resist film 88 is removed.
  • the base electrode is a conductive seed layer for forming a plating electrode.
  • a transparent electrode layer called a TCO (Transparent Conductive Oxide) layer is formed over the entire surface, and a Cu layer is formed over the entire surface.
  • TCO Transparent Conductive Oxide
  • the light-transmitting conductive layer indium tin oxide or the like can be used.
  • the thickness of the TCO layer which is a transparent electrode layer, is about 100 nm, and the thickness of the Cu layer is about 100 nm to 1 ⁇ m.
  • This step is processed using a sputtering apparatus.
  • FIG. 13 shows a state in which a laminated structure of the transparent electrode layer 60 and the Cu layer 62 is formed on the entire surface as the base electrodes 60 and 62.
  • a resist film for electrode separation is formed (S42). This is because the n-type region electrode 70 and the p-type region electrode 72 are electrically separated and plated.
  • a resist film is applied, and patterning is performed by exposure and development to form a separation groove at the boundary between the n-type region portion and the p-type region portion.
  • FIG. 14 shows a resist film 84 in which a separation groove 85 is formed.
  • FIG. 15 shows a state in which the base electrodes 60 and 62 at the separation groove 85 are removed by this etching. At this time, it is preferable that the end portion of the upper lead portion 53 is not exposed at the separation groove 85 and is covered with the base electrodes 60 and 62.
  • FIG. 16 shows a state in which the resist film is removed, and the base electrodes 60 and 62 are separated into the n-type region 100 and the p-type region 102 by the separation unit 86.
  • a plating electrode is formed (S48). Specifically, cleaning with sulfuric acid (H 2 SO 4 ), electrolytic plating of Cu using a plating bath and subsequent cleaning, electrolytic plating of Sn using a plating bath, and subsequent cleaning are sequentially performed.
  • the thickness of the Cu plating layer is about 10 ⁇ m to 20 ⁇ m, and the thickness of the Sn plating layer is 1 ⁇ m to 5 ⁇ m. In this way, the photoelectric conversion element 14 having the structure described in FIG. 1 is completed.
  • the resist film 88 is applied on the n-type amorphous semiconductor layer 52 in S30. Since the amorphous semiconductor layer is easily etched by a chemical solution, it is preferable that the amorphous semiconductor layer is not subjected to a wet process as much as possible. Therefore, it is preferable to form an appropriate conductive thin film on the n-type amorphous semiconductor layer 52 and apply a resist film 88 to the conductive thin film.
  • a TCO film is used as the conductive thin film, and the TCO film is deposited on the n-type amorphous semiconductor layer 52. This step is performed using a sputtering apparatus.
  • FIG. 17 is a cross-sectional view of the photoelectric conversion element 16 having a structure to which the process of S28 is added.
  • a laminated structure of an i-type amorphous semiconductor layer 50, an n-type amorphous semiconductor layer 52, and a transparent electrode layer 54 that is a TCO film is shown as the upper lead portion 53.
  • FIG. 18 is a diagram showing a state in which the transparent electrode layer 54 is formed on the entire surface following the step S26 described in FIG.
  • FIG. 19 is a view corresponding to FIG. 11 and, as shown here, the transparent electrode layer 54 is disposed between the resist film 88 and the n-type amorphous semiconductor layer 52.
  • the semiconductor layer 52 can be prevented from being directly exposed to the wet process.
  • FIG. 20 is a diagram corresponding to FIG. 12, and FIG. 21 is a diagram corresponding to FIG. In either case, a laminated structure of an i-type amorphous semiconductor layer 50, an n-type amorphous semiconductor layer 52, and a transparent electrode layer 54 that is a TCO film is shown as the upper lead portion 53. Subsequent steps are the same except that the upper lead portion 53 includes the transparent electrode layer 54, and thus description thereof is omitted.
  • FIG. 22 is a diagram corresponding to FIG. 1.
  • photoelectric is used to extract an electrode from the n-type amorphous semiconductor layer 28 under the silicon nitride layer 40 that is an insulating layer without using the upper lead portion.
  • 3 is a sectional view of a conversion element 12.
  • FIG. The n-type region 100 has the same configuration as that shown in FIG. 1 except that there is no upper lead portion, and thus detailed description thereof is omitted.
  • FIG. 23 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 12 of the comparative example.
  • the removal process of the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 in the n-contact of S24, the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer of S26 It can be seen that the position process and the process of removing unnecessary parts of S30, S32, and S34 are omitted in 52. That is, S10, S12, S14, S16, S18, S20, and S22 in FIG. 23 are exactly the same as S10, S12, S14, S16, S18, S20, and S22 in FIG. Therefore, the different steps will be mainly described.
  • FIG. 24 is a diagram showing the first deposition process of the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28 in S10, and has the same contents as FIG.
  • S12, S14, S16, S18, and S20 the processing for the semiconductor substrate 20 including the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28 is sequentially performed. From FIG. 8, the detailed description is omitted.
  • FIG. 25 is a diagram showing the state of SiN x removal for the n-contact in S22.
  • an opening 83 is provided in the silicon nitride layer 40 that is an insulating layer, but no opening is provided in the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28.
  • FIG. 26 is a diagram illustrating the formation of the base electrodes 60 and 62 in S40, and corresponds to FIG. Compared with FIG. 13, since there is no upper lead portion 53, the base electrodes 60 and 62 are connected to the n-type amorphous semiconductor layer 28.
  • FIG. 27 is a diagram showing the electrode separation resist formation in S42 and corresponds to FIG.
  • FIG. 28 shows the electrode etching in S44, which corresponds to FIG.
  • FIG. 29 is a diagram showing how the resist is removed in S46, and corresponds to FIG. The processing contents of these are the same, except that there is no upper lead portion 53 under the base electrodes 60 and 62.
  • the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 under the silicon nitride layer 40 which is an insulating layer. Even if there is a residue during the opening process of the silicon nitride layer 40, it is removed satisfactorily and does not affect the subsequent steps. Then, the upper lead portion 53 is provided in this opening, and the electrode 70 of the n-type region 100 can be formed.
  • the back junction type photoelectric conversion element and the back junction type photoelectric conversion element manufacturing method according to the present invention can be used for a photovoltaic power generation system or the like.

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Abstract

In this photoelectric conversion element (14), an n-type region (100) containing an n-type amorphous semiconductor layer (28) and a p-type region (102) containing a p-type amorphous semiconductor layer (44) are provided on the back surface of a semiconductor substrate (20), namely an n-type single-crystal silicon substrate. In the n-type region (100), an opening is provided in a silicon-nitride insulation layer (40), the n-type amorphous semiconductor layer (28) and an i-type amorphous semiconductor layer (24) are removed from beneath said insulation layer, and any silicon-nitride residue left thereon is removed simultaneously if present. An upper lead-out part (53) containing an i-type amorphous semiconductor layer (50) and an n-type amorphous semiconductor layer (52) is then formed in the opening, and an electrode (70) is provided thereon.

Description

裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法Back junction type photoelectric conversion element and method for manufacturing back junction type photoelectric conversion element
　本発明は、裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法に係り、特に、光電変換素子を形成するｐ型領域とｎ型領域を作り分けるために絶縁層を用いる裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法に関する。 The present invention relates to a back junction photoelectric conversion element and a method for manufacturing a back junction photoelectric conversion element, and in particular, a back surface that uses an insulating layer to separately form a p-type region and an n-type region for forming the photoelectric conversion element. The present invention relates to a method for manufacturing a junction type photoelectric conversion element and a back surface junction type photoelectric conversion element.
　太陽電池は、光起電力装置、あるいは光電変換素子とも呼ばれるが、クリーンなエネルギ源として期待され、光電変換効率を向上させるために、様々な構造が用いられる。 A solar cell is also called a photovoltaic device or a photoelectric conversion element, but is expected as a clean energy source, and various structures are used to improve photoelectric conversion efficiency.
　例えば、特許文献１には、ヘテロ接合を有する光起電力装置として、ｎ型単結晶シリコン上にｉ型非晶質シリコンおよびｐ型非晶質シリコンをそれぞれ積層する構成が開示されている。 For example, Patent Document 1 discloses a configuration in which i-type amorphous silicon and p-type amorphous silicon are stacked on n-type single crystal silicon as a photovoltaic device having a heterojunction.
　また、特許文献２には、太陽電池として、第１半導体層の両隣に配設される一対の第２半導体層と、一方の第２半導体層上から第１半導体層上まで跨って形成される絶縁層と、他方の第２半導体層上から第１半導体層上まで跨って形成される絶縁層を備える構成が開示されている。ここでは、透明電極層と収集電極層は、絶縁層上に形成される一対の分離溝によって、第１半導体層用の電極と第２半導体層用の電極とに分離される。 Further, in Patent Document 2, a solar cell is formed across a pair of second semiconductor layers disposed on both sides of the first semiconductor layer and from one of the second semiconductor layers to the first semiconductor layer. The structure provided with the insulating layer and the insulating layer formed ranging over the 1st semiconductor layer from the other 2nd semiconductor layer is disclosed. Here, the transparent electrode layer and the collecting electrode layer are separated into an electrode for the first semiconductor layer and an electrode for the second semiconductor layer by a pair of separation grooves formed on the insulating layer.
特開平７－１４２７５３号公報Japanese Patent Application Laid-Open No. 7-142753 特開２００９－２００２６７号公報JP 2009-200277 A
　特許文献２に記載される太陽電池は、受光面と反対側の裏面に第１半導体層用の電極と第２半導体層用の電極を設けるものである。このような構造は、裏面接合型の光電変換素子と呼ばれ、受光面に電極が配置されないので、受光面積を広く取れ、光電変換効率を向上させることができる。 The solar cell described in Patent Document 2 is provided with an electrode for the first semiconductor layer and an electrode for the second semiconductor layer on the back surface opposite to the light receiving surface. Such a structure is called a back junction type photoelectric conversion element, and since no electrode is arranged on the light receiving surface, a large light receiving area can be obtained and the photoelectric conversion efficiency can be improved.
　裏面接合型の光電変換素子では、裏面にｐｎ接合を形成するので、ｐ型領域とｎ型領域を作り分けるために絶縁層が用いられる。電極はこの絶縁層を開口してｐ型領域またはｎ型領域と接続される。ところが、絶縁層によっては、開口工程において、絶縁層の残渣が残ってしまうことが生じる。そのためにせっかくの変換効率向上が妨げられる。 In the back junction type photoelectric conversion element, since a pn junction is formed on the back surface, an insulating layer is used to make a p type region and an n type region separately. The electrode opens this insulating layer and is connected to the p-type region or the n-type region. However, depending on the insulating layer, a residue of the insulating layer may remain in the opening process. This hinders the improvement of conversion efficiency.
　本発明の目的は、絶縁層の開口の際の残渣の影響を確実に除去して、変換効率の向上を確保できる裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法を提供することである。 An object of the present invention is to provide a back junction type photoelectric conversion element and a method for manufacturing a back junction type photoelectric conversion element capable of reliably removing the influence of residues at the time of opening an insulating layer and ensuring improvement in conversion efficiency. It is to be.
　本発明に係る裏面接合型の光電変換素子は、受光面と、受光面の反対側の裏面とを有する第１導電型の半導体基板と、裏面に配置され、半導体基板に接続し第１導電型を有する非晶質半導体層を含んで構成される第１導電型領域と、裏面に配置され、第２導電型を有する非晶質半導体層を含んで構成され、第１導電型領域とｐｎ接合を形成する第２導電型領域と、第１導電型領域または第２導電型領域のいずれか一方の領域の非晶質半導体層の上に形成される絶縁層と、絶縁層に設けられる絶縁層開口部と、絶縁層開口部に対応してその下部に設けられる非晶質開口部とを通して、半導体基板に接続し、非晶質開口部と絶縁層開口部を覆って絶縁層の上部に引き出され、絶縁層が設けられる非晶質半導体層と同じ導電型を有する非晶質半導体層を引出非晶質半導体層として含む上部引出部と、上部引出部に接続して設けられる電極層と、を備えることを特徴とする。 The back junction type photoelectric conversion element according to the present invention includes a first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface, and is disposed on the back surface and connected to the semiconductor substrate. A first conductive type region configured to include an amorphous semiconductor layer having a first conductive type region, and a first conductive type region disposed on the back surface and including an amorphous semiconductor layer having a second conductive type, and a pn junction A second conductive type region for forming the insulating layer, an insulating layer formed on the amorphous semiconductor layer in either the first conductive type region or the second conductive type region, and an insulating layer provided on the insulating layer Connected to the semiconductor substrate through the opening and an amorphous opening provided below the opening corresponding to the insulating layer opening, covering the amorphous opening and the insulating layer opening, and leading to the upper part of the insulating layer Amorphous semiconductor having the same conductivity type as the amorphous semiconductor layer provided with the insulating layer To an upper lead-out portion including a layer as lead amorphous semiconductor layer, and an electrode layer provided connected to the upper lead portion, comprising: a.
　また、本発明に係る裏面接合型の光電変換素子の製造方法は、第１導電型のシリコン基板の受光面とは反対側の裏面にｐｎ接合が形成される裏面接合型の光電変換素子の製造方法であって、第１導電型を有する非晶質半導体層を含んで構成される第１導電型領域を裏面に形成する工程と、第２導電型を有する非晶質半導体層を含んで構成され、第１導電型領域とｐｎ接合を形成する第２導電型領域を裏面に形成する工程と、第１導電型領域または第２導電型領域のいずれか一方の領域の非晶質半導体層の上に絶縁層を形成する工程と、絶縁層を開口して絶縁層開口部を形成する工程と、絶縁層開口部に対応してその下部に設けられる非晶質開口部を開口して非晶質開口部を形成する工程と、絶縁層開口部と非晶質開口部とを通して、半導体基板に接続し、非晶質開口部と絶縁層開口部を覆って絶縁層の上部に引き出され、絶縁層が設けられる非晶質半導体層と同じ導電型を有する非晶質半導体層を引出非晶質半導体層として含む上部引出部を形成する工程と、上部引出部に接続して設けられる電極層を形成する工程と、を含むことを特徴とする。 The method for manufacturing a back junction photoelectric conversion element according to the present invention is a method for manufacturing a back junction photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of the first conductivity type silicon substrate. A method comprising: forming a first conductivity type region including an amorphous semiconductor layer having a first conductivity type on a back surface; and including an amorphous semiconductor layer having a second conductivity type A step of forming a second conductivity type region that forms a pn junction with the first conductivity type region on the back surface, and an amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region. Forming an insulating layer thereon, opening the insulating layer to form an insulating layer opening, and opening an amorphous opening provided below the amorphous layer corresponding to the insulating layer opening; Through the step of forming a material opening, the insulating layer opening and the amorphous opening An amorphous semiconductor layer connected to a plate, covering the amorphous opening and the insulating layer opening and drawn to the top of the insulating layer and having the same conductivity type as the amorphous semiconductor layer provided with the insulating layer is not drawn The method includes a step of forming an upper lead portion included as a crystalline semiconductor layer, and a step of forming an electrode layer provided in connection with the upper lead portion.
　上記構成により、裏面接合型の光電変換素子において、絶縁層の開口部形成に引き続いて、その下の非晶質半導体層にも開口部を設け、半導体基板を露出させる。そして、その開口部を覆うように、開口された非晶質半導体層と同じ導電型の非晶質半導体層を再び形成して、開口部を覆いながら絶縁層の上部に引き出す。このように、非晶質半導体層を再形成するので、絶縁層の開口の際の残渣があっても、確実に除去されて、その影響が残らない。 With the above configuration, in the back junction type photoelectric conversion element, following the formation of the opening of the insulating layer, an opening is also provided in the amorphous semiconductor layer therebelow to expose the semiconductor substrate. Then, an amorphous semiconductor layer having the same conductivity type as the opened amorphous semiconductor layer is formed again so as to cover the opening, and is drawn out to the upper portion of the insulating layer while covering the opening. As described above, since the amorphous semiconductor layer is re-formed, even if there is a residue at the opening of the insulating layer, it is surely removed and the influence does not remain.
本発明に係る実施の形態における裏面接合型の光電変換素子の断面図である。It is sectional drawing of the back junction type photoelectric conversion element in embodiment which concerns on this invention. 本発明に係る実施の形態における裏面接合型の光電変換素子の製造方法の手順を示すフローチャートである。It is a flowchart which shows the procedure of the manufacturing method of the back junction type photoelectric conversion element in embodiment which concerns on this invention. 図２のＳ１０の様子を示す図である。It is a figure which shows the mode of S10 of FIG. 図２のＳ１２の様子を示す図である。It is a figure which shows the mode of S12 of FIG. 図２のＳ１４の様子を示す図である。It is a figure which shows the mode of S14 of FIG. 図２のＳ１６の様子を示す図である。It is a figure which shows the mode of S16 of FIG. 図２のＳ１８の様子を示す図である。It is a figure which shows the mode of S18 of FIG. 図２のＳ２０の様子を示す図である。It is a figure which shows the mode of S20 of FIG. 図２のＳ２２，Ｓ２４の様子を示す図である。It is a figure which shows the mode of S22 and S24 of FIG. 図２のＳ２６の様子を示す図である。It is a figure which shows the mode of S26 of FIG. 図２のＳ３０、Ｓ３２の様子を説明する図である。It is a figure explaining the mode of S30 of FIG. 2, and S32. 図２のＳ３４の様子を示す図である。It is a figure which shows the mode of S34 of FIG. 図２のＳ４０の様子を示す図である。It is a figure which shows the mode of S40 of FIG. 図２のＳ４２の様子を示す図である。It is a figure which shows the mode of S42 of FIG. 図２のＳ４４の様子を示す図である。It is a figure which shows the mode of S44 of FIG. 図２のＳ４６の様子を示す図である。It is a figure which shows the mode of S46 of FIG. 本発明に係る実施の形態における裏面接合型の光電変換素子の他の構成を示す断面図である。It is sectional drawing which shows the other structure of the back junction type photoelectric conversion element in embodiment which concerns on this invention. 他の構成において、図２のＳ２８の様子を示す図である。It is a figure which shows the mode of S28 of FIG. 2 in another structure. 他の構成において、図２のＳ３０，３２の様子を示す図である。It is a figure which shows the mode of S30 and 32 of FIG. 2 in another structure. 他の構成において、図２のＳ３４の様子を示す図である。It is a figure which shows the mode of S34 of FIG. 2 in another structure. 他の構成において、図２のＳ４０の様子を示す図である。It is a figure which shows the mode of S40 of FIG. 2 in another structure. 比較例としての裏面接合型の光電変換素子の断面図である。It is sectional drawing of the back junction type photoelectric conversion element as a comparative example. 比較例としての裏面接合型の光電変換素子の製造方法の手順を示すフローチャートである。It is a flowchart which shows the procedure of the manufacturing method of the back junction type photoelectric conversion element as a comparative example. 比較例におけるＳ１０の様子を示す図である。It is a figure which shows the mode of S10 in a comparative example. 比較例におけるＳ２２の様子を示す図である。It is a figure which shows the mode of S22 in a comparative example. 比較例におけるＳ４０の様子を示す図である。It is a figure which shows the mode of S40 in a comparative example. 比較例におけるＳ４２の様子を示す図である。It is a figure which shows the mode of S42 in a comparative example. 比較例におけるＳ４４の様子を示す図である。It is a figure which shows the mode of S44 in a comparative example. 比較例におけるＳ４６の様子を示す図である。It is a figure which shows the mode of S46 in a comparative example.
　以下に図面を用いて本発明に係る実施の形態につき、詳細に説明する。以下では、半導体基板の導電型をｎ型として説明するが、これをｐ型としても構わない。また、非晶質半導体層の形成の順序を、ｎ型を先とし、ｐ型をその後としたが、これを入れ替えても構わない。また、コンタクトのための絶縁層の開口部をｎ型非晶質半導体層のところに設けるものとしたが、これをｐ型非晶質半導体層のところに設けるものとしてもよい。また、以下では、ｐ型非晶質半導体層とｎ型非晶質半導体層の他に、ｉ型非晶質半導体層を用いる。そこで、ｐｎ接合の間にｉ型非晶質半導体層を含まれていても、これはｐｎ接合に属するものである。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the conductivity type of the semiconductor substrate is described as n-type, but it may be p-type. Further, the order of formation of the amorphous semiconductor layers is n-type first and p-type thereafter, but this may be interchanged. In addition, although the opening of the insulating layer for the contact is provided at the n-type amorphous semiconductor layer, it may be provided at the p-type amorphous semiconductor layer. In the following, an i-type amorphous semiconductor layer is used in addition to the p-type amorphous semiconductor layer and the n-type amorphous semiconductor layer. Therefore, even if an i-type amorphous semiconductor layer is included between pn junctions, it belongs to the pn junction.
　以下で説明する材質、膜厚等は、説明のための例示であって、裏面接合型の光電変換素子の仕様に応じ適宜変更が可能である。 The materials, film thicknesses, and the like described below are examples for explanation, and can be appropriately changed according to the specifications of the back junction type photoelectric conversion element.
　以下では、全ての図面において同様の要素には同一の符号を付し、重複する説明を省略する。また、本文中の説明においては、必要に応じそれ以前に述べた符号を用いるものとする。 In the following, similar elements are denoted by the same reference symbols in all drawings, and redundant description is omitted. In the description in the text, the symbols described before are used as necessary.
　図１は、裏面接合型の光電変換素子１４の断面図である。裏面接合型の光電変換素子１４は、その受光面の反対側の裏面に、光電変換を行うｐｎ接合を形成し、電極も裏面にのみ設けるものである。このように、受光面に電極を一切配置しないので、受光面積が広く取れ、面積当たりの光電変換効率が向上する。図１では、紙面の下側が受光面側で、上側が裏面である。なお、以下では、特に断らない限り、裏面接合型の光電変換素子１４のことを、単に光電変換素子１４と呼ぶことにする。 FIG. 1 is a cross-sectional view of a back contact type photoelectric conversion element 14. The back junction type photoelectric conversion element 14 has a pn junction for performing photoelectric conversion on the back surface opposite to the light receiving surface, and an electrode is provided only on the back surface. Thus, since no electrode is disposed on the light receiving surface, a large light receiving area can be obtained, and the photoelectric conversion efficiency per area is improved. In FIG. 1, the lower side of the paper is the light-receiving surface side, and the upper side is the back surface. Hereinafter, unless otherwise specified, the back junction type photoelectric conversion element 14 is simply referred to as the photoelectric conversion element 14.
　光電変換素子１４には、ｎ型のシリコン単結晶基板である半導体基板２０の裏面に、ｎ型領域１００とｐ型領域１０２が設けられる。ｎ型領域１００は、半導体基板２０に接続し、これと同じ導電型であるｎ型非晶質半導体層２８を含んで構成される。図１では、半導体基板２０とｎ型非晶質半導体層２８との間に、ｉ型非晶質半導体層２４が設けられるが、ｉ型非晶質半導体層２４は必ずしも必須の構成要素ではない。ｐ型領域１０２は、ｐ型非晶質半導体層４４を含んで構成され、ｎ型領域１００とｐｎ接合を形成する。図１では、半導体基板２０とｐ型非晶質半導体層４４との間に、ｉ型非晶質半導体層４２が設けられるが、ｉ型非晶質半導体層４２は必ずしも必須の構成要素ではない。 The photoelectric conversion element 14 is provided with an n-type region 100 and a p-type region 102 on the back surface of a semiconductor substrate 20 which is an n-type silicon single crystal substrate. The n-type region 100 is connected to the semiconductor substrate 20 and includes an n-type amorphous semiconductor layer 28 having the same conductivity type. In FIG. 1, the i-type amorphous semiconductor layer 24 is provided between the semiconductor substrate 20 and the n-type amorphous semiconductor layer 28, but the i-type amorphous semiconductor layer 24 is not necessarily an essential component. . The p-type region 102 includes a p-type amorphous semiconductor layer 44 and forms a pn junction with the n-type region 100. In FIG. 1, an i-type amorphous semiconductor layer 42 is provided between the semiconductor substrate 20 and the p-type amorphous semiconductor layer 44, but the i-type amorphous semiconductor layer 42 is not necessarily an essential component. .
　ｎ型領域用の電極７０は、ｎ型非晶質半導体層２８に接続されるめっき電極である。電極７０は、ＳｎとＣｕの積層構造である。ｎ型領域用の電極７０とｎ型非晶質半導体層２８との間に設けられる下地電極６０，６２は、電極７０をめっきする際に用いられるシード層である。下地電極６０，６２は、透明電極層６０とＣｕ層６２の積層構造である。 The n-type region electrode 70 is a plating electrode connected to the n-type amorphous semiconductor layer 28. The electrode 70 has a laminated structure of Sn and Cu. The base electrodes 60 and 62 provided between the n-type region electrode 70 and the n-type amorphous semiconductor layer 28 are seed layers used when the electrode 70 is plated. The base electrodes 60 and 62 have a laminated structure of a transparent electrode layer 60 and a Cu layer 62.
　ｐ型領域用の電極７２は、ｐ型非晶質半導体層４４に接続されるめっき電極である。電極７２は、電極７０と同様に、ＳｎとＣｕの積層構造であり、下地電極６０，６２を用いてめっきによって形成される。ｎ型領域用の電極７０とｐ型領域用の電極７２を比べると、前者の電極高さの方が後者の電極高さよりも高い。これは、前者の下地電極６０，６２の表面積を後者の下地電極６０，６２の表面積よりも小さく設定したためである。すなわち、下地電極６０，６２を共通にしてめっきを行うと、その表面積の差によってめっき電流密度が異なり、小さい表面積の方が速く成長するためである。 The electrode 72 for the p-type region is a plating electrode connected to the p-type amorphous semiconductor layer 44. Similar to the electrode 70, the electrode 72 has a laminated structure of Sn and Cu, and is formed by plating using the base electrodes 60 and 62. Comparing the n-type region electrode 70 and the p-type region electrode 72, the former electrode height is higher than the latter electrode height. This is because the surface area of the former base electrodes 60 and 62 is set smaller than the surface area of the latter base electrodes 60 and 62. That is, when plating is performed using the base electrodes 60 and 62 in common, the plating current density varies depending on the surface area difference, and the smaller surface area grows faster.
　図１に示されるように、ｐ型領域用の電極７２は、下地電極６０，６２を介して、ｐ型非晶質半導体層４４の上に直接的に設けられる。これに対し、ｎ型領域用の電極７０は、窒化シリコン層４０の絶縁層に開口部を設け、その開口部に続けて、ｎ型非晶質半導体層２８とｉ型非晶質半導体層２４にも開口部を設け、それらの開口部を覆うように、別のｉ型非晶質半導体層５０とｎ型非晶質半導体層５２が形成されて、これが上部に引き出された部分に接続される。この窒化シリコン層４０の上に引き出されるｉ型非晶質半導体層５０とｎ型非晶質半導体層５２を上部引出部５３と呼ぶことにすると、以下で説明するように、この光電変換素子１４においては、この上部引出部５３を備えることが特徴である。 As shown in FIG. 1, the electrode 72 for the p-type region is provided directly on the p-type amorphous semiconductor layer 44 via the base electrodes 60 and 62. On the other hand, the electrode 70 for the n-type region is provided with an opening in the insulating layer of the silicon nitride layer 40, and subsequently to the opening, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24. Also provided are openings, and another i-type amorphous semiconductor layer 50 and an n-type amorphous semiconductor layer 52 are formed so as to cover these openings, and this is connected to the portion drawn upward. The When the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 drawn on the silicon nitride layer 40 are referred to as an upper lead portion 53, the photoelectric conversion element 14 is described as described below. Is characterized in that this upper drawing part 53 is provided.
　半導体基板２０の受光面である表面に設けられるｉ型非晶質半導体層２２とｎ型非晶質半導体層２６は、光電変換が行われる半導体基板２０のパッシベーション層としての機能を有する層である。反射防止層３８は、受光面における反射を抑制する機能を有する絶縁膜層である。 The i-type amorphous semiconductor layer 22 and the n-type amorphous semiconductor layer 26 provided on the light receiving surface of the semiconductor substrate 20 are layers having a function as a passivation layer of the semiconductor substrate 20 on which photoelectric conversion is performed. . The antireflection layer 38 is an insulating film layer having a function of suppressing reflection on the light receiving surface.
　図２は、光電変換素子１４の製造手順を示すフローチャートである。この手順のうち、Ｓ２８を除いて、図３から図１６の図を用いて説明する。Ｓ２８に関しては、別の構造の光電変換素子１６として、図１７から図２１を用いて後述する。 FIG. 2 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 14. This procedure will be described with reference to FIGS. 3 to 16 except for S28. S28 will be described later with reference to FIGS. 17 to 21 as a photoelectric conversion element 16 having another structure.
　最初に、ｎ型のシリコン単結晶基板である半導体基板２０が準備される。面方位としては（１００）が好ましい。受光面となる表面には、光入射効率を高めるため、テキスチャ構造とすることが好ましい。例えば、シリコンのエッチングの面異方性を利用して、（１１１）面で囲まれるピラミッド状の凹凸を表面に設けることができる。半導体基板２０は、次の工程のために、全体が適当な洗浄液で清浄にされる。 First, a semiconductor substrate 20 which is an n-type silicon single crystal substrate is prepared. The plane direction is preferably (100). In order to increase the light incident efficiency, it is preferable that the surface serving as the light receiving surface has a texture structure. For example, pyramidal irregularities surrounded by the (111) plane can be provided on the surface by utilizing the plane anisotropy of silicon etching. The semiconductor substrate 20 is entirely cleaned with an appropriate cleaning solution for the next step.
　清浄な表面とされた半導体基板２０について、次に、ｉ型非晶質半導体層と、ｎ型非晶質半導体層が順次デポジションされる（Ｓ１０）。デポジションは、堆積とも呼ばれ、薄膜を形成する工程のことである。この工程は、プラズマＣＶＤ装置を用いて行うことができる。ｉ型非晶質半導体層とｎ型非晶質半導体層は、半導体基板２０の表面と裏面に共に形成される。図３には、表面にｉ型非晶質半導体層２２とｎ型非晶質半導体層２６が形成され、裏面にｉ型非晶質半導体層２４とｎ型非晶質半導体層２８が形成される様子が示されている。 Next, the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are sequentially deposited on the semiconductor substrate 20 having a clean surface (S10). Deposition is also called deposition and is a process of forming a thin film. This step can be performed using a plasma CVD apparatus. The i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are both formed on the front surface and the back surface of the semiconductor substrate 20. In FIG. 3, an i-type amorphous semiconductor layer 22 and an n-type amorphous semiconductor layer 26 are formed on the front surface, and an i-type amorphous semiconductor layer 24 and an n-type amorphous semiconductor layer 28 are formed on the back surface. Is shown.
　次に、窒化シリコン層のデポジションが行われる（Ｓ１２）。この工程もプラズマＣＶＤ装置を用いて行なわれる。窒化シリコンの代表はＳｉ3Ｎ4であるが、プラズマＣＶＤ装置の製造条件によっては必ずしもＳｉ3Ｎ4の組成とならない。一般的にはＳｉＮXの組成となる。窒化シリコン層４０の厚さは、１０ｎｍから５００ｎｍ程度である。 Next, the silicon nitride layer is deposited (S12). This process is also performed using a plasma CVD apparatus. A typical example of silicon nitride is Si 3 N 4 , but the composition of Si 3 N 4 does not necessarily depend on the manufacturing conditions of the plasma CVD apparatus. Generally, the composition is SiN x . The thickness of the silicon nitride layer 40 is about 10 nm to 500 nm.
　図４では、裏面において、窒化シリコン層４０が形成される様子が示される。受光面となる表面には、反射防止層３８が形成される。反射防止層３８としては、窒化シリコン膜を用いることができるので、裏面の窒化シリコン層４０と同じ膜を受光面側にも同時に形成してもよい。しかし、裏面の窒化シリコン層４０は、以後のパターニングのために用いられるものでエッチング特性が重要であるのに対し、反射防止層３８は光学的特性が重要である。そこで、裏面の窒化シリコン層４０と反射防止層３８とは、膜特性が異なる絶縁膜とすることがよい。以下では、裏面の窒化シリコン層４０と受光面側の反射防止層３８とは区別して説明を進める。 FIG. 4 shows how the silicon nitride layer 40 is formed on the back surface. An antireflection layer 38 is formed on the surface that becomes the light receiving surface. Since a silicon nitride film can be used as the antireflection layer 38, the same film as the silicon nitride layer 40 on the back surface may be formed on the light receiving surface side at the same time. However, the silicon nitride layer 40 on the back surface is used for subsequent patterning and etching characteristics are important, whereas the antireflection layer 38 has optical characteristics important. Therefore, the back side silicon nitride layer 40 and the antireflection layer 38 are preferably insulating films having different film characteristics. In the following, the description will be made while distinguishing the silicon nitride layer 40 on the back surface and the antireflection layer 38 on the light receiving surface side.
　なお、裏面の窒化シリコン層４０としては、例えば、膜組成を変えることによって、エッチング特性が耐アルカリ性のものと、耐酸性のものと区別して形成することができる。工程の組み方によっては、ｎ型非晶質半導体層２８側を耐酸性の特性の膜とし、その上に耐アルカリ性の膜とすることができる。例えば、レジスト膜をアルカリで除去するものとするときは、レジスト膜に接する側の窒化シリコン層を耐アルカリ性のものとすることがよい。 The silicon nitride layer 40 on the back surface can be formed by changing the film composition, for example, so that the etching characteristics can be distinguished from those having alkali resistance and those having acid resistance. Depending on how the processes are assembled, the n-type amorphous semiconductor layer 28 side can be formed as an acid-resistant film, and an alkali-resistant film can be formed thereon. For example, when the resist film is to be removed with alkali, the silicon nitride layer in contact with the resist film is preferably resistant to alkali.
　次に、ｐ型領域１０２に相当する部分を開口するため、窒化シリコン層４０を部分的に除去する（Ｓ１４）。この処理にはフォトリソグラフィ技術が用いられる。すなわち、窒化シリコン層４０の全面に感光性レジスト膜を塗布し、窒化シリコン層４０を除去したい部分のレジスト膜を露光して、現像によりその部分のレジスト膜を取り除く。この処理はレジスト膜のパターニングである。そして、レジスト膜をエッチングマスクとして、適当なエッチング液を用いてレジスト膜のない部分の窒化シリコン層４０を除去する。エッチング液としてはＨＦと硝酸の混合液である弗硝酸を用いることができる。エッチングの後は水洗が行われる。 Next, in order to open a portion corresponding to the p-type region 102, the silicon nitride layer 40 is partially removed (S14). A photolithography technique is used for this processing. That is, a photosensitive resist film is applied to the entire surface of the silicon nitride layer 40, the resist film in a portion where the silicon nitride layer 40 is to be removed is exposed, and the resist film in that portion is removed by development. This process is patterning of the resist film. Then, using the resist film as an etching mask, a portion of the silicon nitride layer 40 without the resist film is removed using an appropriate etching solution. As the etchant, hydrofluoric acid which is a mixture of HF and nitric acid can be used. After the etching, washing with water is performed.
　図５には、パターニングされたレジスト膜８０と、このレジスト膜８０をエッチングマスクとして、残された窒化シリコン層４０が示されている。その後、レジスト膜８０は除去される。レジスト膜８０はアルカリに溶けるので、苛性ソーダ（ＮａＯＨ）を用いて、窒化シリコン層４０をそのままとしてレジスト膜８０のみを除去することができる。 FIG. 5 shows the patterned resist film 80 and the remaining silicon nitride layer 40 using the resist film 80 as an etching mask. Thereafter, the resist film 80 is removed. Since the resist film 80 is soluble in alkali, only the resist film 80 can be removed using caustic soda (NaOH) while leaving the silicon nitride layer 40 as it is.
　次に、ｐ型領域１０２に相当する部分の半導体基板２０を露出させるため、窒化シリコン層４０をエッチングマスクとして、その下のｎ型非晶質半導体層２８とｉ型非晶質半導体層２４が除去される（Ｓ１６）。ここでは、非晶質半導体層がアルカリに溶けることを利用し、苛性ソーダ（ＮａＯＨ）が用いられる。具体的には、有機洗浄、苛性ソーダ、塩酸（ＨＣｌ）と過酸化水素（Ｈ2Ｏ2）の混合液であるＳＣ２、弗酸、水洗の順で処理が行われる。弗酸が用いられるのは、ＳＣ２によって酸化膜が形成されるので、それを除去するためである。 Next, in order to expose the portion of the semiconductor substrate 20 corresponding to the p-type region 102, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 thereunder are formed using the silicon nitride layer 40 as an etching mask. It is removed (S16). Here, caustic soda (NaOH) is used by utilizing the fact that the amorphous semiconductor layer dissolves in alkali. Specifically, the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing. The hydrofluoric acid is used to remove the oxide film formed by SC2.
　図６には、窒化シリコン層４０の形状に、ｎ型非晶質半導体層２８とｉ型非晶質半導体層２４が残され、それ以外の部分に半導体基板２０が露出された様子が示される。このようにして、ｐ型領域１０２の部分の開口が行われる。 FIG. 6 shows a state in which the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 are left in the shape of the silicon nitride layer 40 and the semiconductor substrate 20 is exposed in other portions. . In this way, opening of the portion of the p-type region 102 is performed.
　次に、ｉ型非晶質半導体層４２とｐ型非晶質半導体層４４が全面にデポジションされる（Ｓ１８）。この工程は、プラズマＣＶＤ装置を用いて行なわれる。図７には、開口されたｐ型領域１０２の部分において、ｎ型のシリコン単結晶基板である半導体基板２０に接触して、ｉ型非晶質半導体層４２とｐ型非晶質半導体層４４が配置される様子が示される。なお、窒化シリコン層４０の上にも、ｉ型非晶質半導体層４２とｐ型非晶質半導体層４４が堆積する。 Next, the i-type amorphous semiconductor layer 42 and the p-type amorphous semiconductor layer 44 are deposited on the entire surface (S18). This step is performed using a plasma CVD apparatus. In FIG. 7, an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are in contact with the semiconductor substrate 20 which is an n-type silicon single crystal substrate in the opened p-type region 102. Is shown. Note that an i-type amorphous semiconductor layer 42 and a p-type amorphous semiconductor layer 44 are also deposited on the silicon nitride layer 40.
　そして、次に、ｎ型領域１００に電極をコンタクトさせるための開口処理が行われる。コンタクトとは、電気的に導通をとることである。図７に示されるように、ｎ型領域１００には、上の方から、ｐ型非晶質半導体層４４、ｉ型非晶質半導体層４２、窒化シリコン層４０、ｎ型非晶質半導体層２８、ｉ型非晶質半導体層２４が存在している。ここでは、これらを通しての開口処理が行われ、ｎ型のシリコン単結晶基板である半導体基板２０の表面が露出される。 Then, an opening process for bringing the electrode into contact with the n-type region 100 is performed. A contact is an electrical connection. As shown in FIG. 7, the n-type region 100 includes a p-type amorphous semiconductor layer 44, an i-type amorphous semiconductor layer 42, a silicon nitride layer 40, and an n-type amorphous semiconductor layer from the top. 28, i-type amorphous semiconductor layer 24 is present. Here, an opening process is performed through these, and the surface of the semiconductor substrate 20 which is an n-type silicon single crystal substrate is exposed.
　最初に、ｐ型非晶質半導体層４４とｉ型非晶質半導体層４２の除去が行われる（Ｓ２０）。この処理にはフォトリソグラフィ技術が用いられる。すなわち、レジスト膜を塗布し、塗布されたレジスト膜について、ｎコンタクトの部分を露光と現像で除去するパターニングが行われる。レジスト膜には、耐酸性と耐アルカリ性を有する溶剤溶解型が用いられる。これによって、苛性ソーダ（ＮａＯＨ）を用いて、ｐ型非晶質半導体層４４とｉ型非晶質半導体層４２を除去することができる。その後洗浄が行われる。図８には、レジスト膜８２の開口部８３の部分のｐ型非晶質半導体層４４とｉ型非晶質半導体層４２が除去された様子が示される。 First, the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed (S20). A photolithography technique is used for this processing. That is, a resist film is applied, and the applied resist film is patterned to remove the n-contact portion by exposure and development. A solvent-soluble type having acid resistance and alkali resistance is used for the resist film. Thus, the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 can be removed using caustic soda (NaOH). Thereafter, cleaning is performed. FIG. 8 shows a state where the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are removed from the opening 83 of the resist film 82.
　その後、適当な溶剤を用いてレジスト膜８２が除去される。そして、次に、ｐ型非晶質半導体層４４とｉ型非晶質半導体層４２をエッチングマスクとして用い、窒化シリコン層４０の除去（Ｓ２２）が行われる。エッチング液としては、弗酸が用いられる。ここで、非晶質半導体層は弗酸にあまり溶解しない性質を利用している。なお、この工程の際に、受光面側の反射防止層３８がエッチングされないように、レジスト等の保護膜を設けることが好ましい。 Thereafter, the resist film 82 is removed using an appropriate solvent. Then, using the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 as an etching mask, the silicon nitride layer 40 is removed (S22). As the etching solution, hydrofluoric acid is used. Here, the amorphous semiconductor layer utilizes the property that it is not very soluble in hydrofluoric acid. In this step, it is preferable to provide a protective film such as a resist so that the antireflection layer 38 on the light receiving surface side is not etched.
　次に、窒化シリコン層４０に開口部が形成された状態で、その開口部に相当する部分のｎ型非晶質半導体層２８とｉ型非晶質半導体層２４の除去が行われる（Ｓ２４）。ここでは、ｐ型非晶質半導体層４４とｉ型非晶質半導体層４２をエッチングマスクとして用い、エッチング液として、Ｓ１６で説明した苛性ソーダ（ＮａＯＨ）が用いられる。具体的には、有機洗浄、苛性ソーダ、塩酸（ＨＣｌ）と過酸化水素（Ｈ2Ｏ2）の混合液であるＳＣ２、弗酸、水洗の順で処理が行われる。弗酸が用いられるのは、ＳＣ２によって酸化膜が形成されるので、それを除去するためである。 Next, in a state where the opening is formed in the silicon nitride layer 40, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 corresponding to the opening are removed (S24). . Here, the p-type amorphous semiconductor layer 44 and the i-type amorphous semiconductor layer 42 are used as etching masks, and the caustic soda (NaOH) described in S16 is used as an etchant. Specifically, the treatment is performed in the order of organic cleaning, caustic soda, SC2 which is a mixed solution of hydrochloric acid (HCl) and hydrogen peroxide (H 2 O 2 ), hydrofluoric acid, and water washing. The hydrofluoric acid is used to remove the oxide film formed by SC2.
　なお、上記のように、非晶質半導体層はアルカリに溶けるが、ｎ型非晶質半導体のエッチングレートよりもｐ型非晶質半導体のエッチングレートが小さい。これを利用することで、ｐ型非晶質半導体層４４をエッチングマスクとして、ｎ型非晶質半導体層２８をエッチングすることができる。 As described above, the amorphous semiconductor layer is soluble in alkali, but the etching rate of the p-type amorphous semiconductor is lower than the etching rate of the n-type amorphous semiconductor. By utilizing this, the n-type amorphous semiconductor layer 28 can be etched using the p-type amorphous semiconductor layer 44 as an etching mask.
　プラズマＣＶＤで形成した窒化シリコンは、弗酸によって除去できるとされるが、実際には、微小な残渣が残り、それを完全に除去するにはかなりの時間を要することがある。その原因としては、例えば、プラズマＣＶＤ装置で形成した窒化シリコンがＳｉ3Ｎ4の化学量論的な組成ではなく、Ｓｉ3.5Ｎ4のように、Ｓｉ組成が過剰に多い可能性があることが考えられる。このように、窒化シリコン層４０の除去の際に残渣があると、電極とｎ型非晶質半導体層２８との電気的接触が妨げられ、光電変換素子１４の光電変換効率が低下することになる。 Although silicon nitride formed by plasma CVD can be removed by hydrofluoric acid, in practice, a minute residue remains, and it may take a considerable time to completely remove the residue. As the cause, for example, silicon nitride formed by a plasma CVD apparatus may not have a stoichiometric composition of Si 3 N 4 but may have an excessively large Si composition such as Si 3.5 N 4. Conceivable. Thus, if there is a residue when removing the silicon nitride layer 40, electrical contact between the electrode and the n-type amorphous semiconductor layer 28 is hindered, and the photoelectric conversion efficiency of the photoelectric conversion element 14 is reduced. Become.
　Ｓ２４の工程では、窒化シリコン層４０に開口部が形成された状態で、その開口部に相当する部分のｎ型非晶質半導体層２８とｉ型非晶質半導体層２４の除去が行われる。したがって、仮に、ｎ型非晶質半導体層２８の上に窒化シリコンの残渣があったとしても、ｎ型非晶質半導体層２８の除去と共に取り去られてしまうので、窒化シリコンの残渣は、以下の工程になんら影響を及ぼさない。 In the step S24, the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 corresponding to the opening are removed while the opening is formed in the silicon nitride layer 40. Therefore, even if there is a silicon nitride residue on the n-type amorphous semiconductor layer 28, the silicon nitride residue is removed along with the removal of the n-type amorphous semiconductor layer 28. It has no effect on the process.
　図９には、レジスト膜によって規定された開口部８３の大きさに、ｐ型非晶質半導体層４４、ｉ型非晶質半導体層４２、窒化シリコン層４０、ｎ型非晶質半導体層２８、ｉ型非晶質半導体層２４が順に開口され、ｎ型のシリコン単結晶基板である半導体基板２０の表面が露出される様子が示される。 In FIG. 9, the size of the opening 83 defined by the resist film is set such that the p-type amorphous semiconductor layer 44, the i-type amorphous semiconductor layer 42, the silicon nitride layer 40, and the n-type amorphous semiconductor layer 28. , The i-type amorphous semiconductor layer 24 is sequentially opened, and the surface of the semiconductor substrate 20 which is an n-type silicon single crystal substrate is exposed.
　次に、ｉ型非晶質半導体層と、ｎ型非晶質半導体層が、再度、デポジションされる（Ｓ２６）。このデポジションは、Ｓ１０で形成されたｉ型非晶質半導体層２４と、ｎ型非晶質半導体層２８を除去した開口部８３に再度、同じ非晶質半導体層を形成するものである。図１０には、全面にｉ型非晶質半導体層５０とｎ型非晶質半導体層５２が形成される様子が示される。 Next, the i-type amorphous semiconductor layer and the n-type amorphous semiconductor layer are again deposited (S26). In this deposition, the same amorphous semiconductor layer is formed again in the opening 83 from which the i-type amorphous semiconductor layer 24 formed in S10 and the n-type amorphous semiconductor layer 28 are removed. FIG. 10 shows how the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are formed on the entire surface.
　つぎに、この全面に形成されたｉ型非晶質半導体層５０とｎ型非晶質半導体層５２について、ｎ型領域１００の電極接続に必要な部分を残して、不要部分を除去することが行われる。具体的には、不要部分除去用のレジスト膜を形成し（Ｓ３０）、そのレジスト膜をエッチングマスクとして用いて不要部分を除去し（Ｓ３２）、その後にレジスト膜を除去する（Ｓ３４）。 Next, with respect to the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 formed on the entire surface, an unnecessary portion can be removed while leaving a portion necessary for electrode connection of the n-type region 100. Done. Specifically, a resist film for removing unnecessary portions is formed (S30), unnecessary portions are removed using the resist film as an etching mask (S32), and then the resist film is removed (S34).
　不要部分除去用のレジスト膜としては、溶剤溶解型のレジスト膜が用いられる。エッチング液としては、苛性ソーダ（ＮａＯＨ）を用いることができる。図１１には、レジスト膜８８を必要部分の大きさＢにパターニングして、ｉ型非晶質半導体層５０とｎ型非晶質半導体層５２を成形する様子が示されている。必要部分の大きさＢは、図９の開口部８３の開口面積の大きさＡよりも大きく設定される。これによって、ｉ型非晶質半導体層５０とｎ型非晶質半導体層５２が、開口部８３を通して、半導体基板２０に接続し、開口部８３を覆って絶縁層である窒化シリコン層４０の上部に引き出される。この引き出される部分が、上部引出部５３である。 As a resist film for removing unnecessary portions, a solvent-soluble resist film is used. Caustic soda (NaOH) can be used as the etchant. FIG. 11 shows how the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are formed by patterning the resist film 88 to a required size B. The size B of the necessary portion is set larger than the size A of the opening area of the opening 83 in FIG. As a result, the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer 52 are connected to the semiconductor substrate 20 through the opening 83 and cover the opening 83 so as to cover the upper portion of the silicon nitride layer 40 that is an insulating layer. Pulled out. This part to be drawn out is the upper drawing part 53.
　その後、適当な有機溶剤によってレジスト膜８８が除去される。図１２は、レジスト膜８８が除去された状態を示す図である。 Thereafter, the resist film 88 is removed with a suitable organic solvent. FIG. 12 is a view showing a state where the resist film 88 is removed.
　次に、下地電極形成が行われる（Ｓ４０）。下地電極は、めっき電極を形成するための導電性のシード層である。具体的には、ＴＣＯ（Ｔｒａｎｓｐａｒｅｎｔ　Ｃｏｎｄｕｃｔｉｖｅ　Ｏｘｉｄｅ）層と呼ばれる透明電極層を全面に形成し、その上にＣｕ層を全面に形成する。透光性導電層としては、インジウム錫酸化物等を用いることができる。 Next, base electrode formation is performed (S40). The base electrode is a conductive seed layer for forming a plating electrode. Specifically, a transparent electrode layer called a TCO (Transparent Conductive Oxide) layer is formed over the entire surface, and a Cu layer is formed over the entire surface. As the light-transmitting conductive layer, indium tin oxide or the like can be used.
　透明電極層であるＴＣＯ層の厚さは１００ｎｍ程度、Ｃｕ層の厚さは１００ｎｍから１μｍ程度である。この工程は、スパッタ装置を用いて処理される。図１３には、下地電極６０，６２として、透明電極層６０とＣｕ層６２の積層構造が全面に形成される様子が示される。 The thickness of the TCO layer, which is a transparent electrode layer, is about 100 nm, and the thickness of the Cu layer is about 100 nm to 1 μm. This step is processed using a sputtering apparatus. FIG. 13 shows a state in which a laminated structure of the transparent electrode layer 60 and the Cu layer 62 is formed on the entire surface as the base electrodes 60 and 62.
　つぎに、電極分離用のレジスト膜が形成される（Ｓ４２）。これは、ｎ型領域用の電極７０とｐ型領域用の電極７２を電気的に分離してめっきするためである。ここでは、レジスト膜を塗布して、露光、現像によってパターニングを行い、ｎ型領域部分とｐ型領域部分の境界に分離溝を形成する。図１４には、分離溝８５が形成されたレジスト膜８４が示されている。 Next, a resist film for electrode separation is formed (S42). This is because the n-type region electrode 70 and the p-type region electrode 72 are electrically separated and plated. Here, a resist film is applied, and patterning is performed by exposure and development to form a separation groove at the boundary between the n-type region portion and the p-type region portion. FIG. 14 shows a resist film 84 in which a separation groove 85 is formed.
　そして、電極用のレジスト膜を用いて、下地電極のエッチングが行われる（Ｓ４４）。エッチングには、塩化第二鉄と塩酸（ＨＣｌ）が用いられる。図１５には、このエッチングによって、分離溝８５のところの下地電極６０，６２が除去された様子が示される。このときに、分離溝８５のところに、上部引出部５３の端部が露出せずに、下地電極６０，６２で覆われるようにすることが好ましい。 Then, the base electrode is etched using the electrode resist film (S44). For the etching, ferric chloride and hydrochloric acid (HCl) are used. FIG. 15 shows a state in which the base electrodes 60 and 62 at the separation groove 85 are removed by this etching. At this time, it is preferable that the end portion of the upper lead portion 53 is not exposed at the separation groove 85 and is covered with the base electrodes 60 and 62.
　その後、レジスト膜が除去される（Ｓ４６）。レジスト膜除去には、苛性ソーダ（ＮａＯＨ）が用いられる。図１６にはレジスト膜が除去され、下地電極６０，６２が分離部８６によって、ｎ型領域１００用と、ｐ型領域１０２用とに分離された様子が示される。 Thereafter, the resist film is removed (S46). Caustic soda (NaOH) is used for removing the resist film. FIG. 16 shows a state in which the resist film is removed, and the base electrodes 60 and 62 are separated into the n-type region 100 and the p-type region 102 by the separation unit 86.
　次にめっき電極の形成が行われる（Ｓ４８）。具体的には、硫酸（Ｈ2ＳＯ4）による洗浄、めっき浴を用いたＣｕの電解めっきとその後の洗浄、めっき浴を用いたＳｎの電解めっきとその後の洗浄が順次行われる。Ｃｕめっき層の厚さは１０μｍから２０μｍ程度、Ｓｎめっき層の厚さは１μｍから５μｍである。このようにして、図１で説明した構造の光電変換素子１４が完成する。 Next, a plating electrode is formed (S48). Specifically, cleaning with sulfuric acid (H 2 SO 4 ), electrolytic plating of Cu using a plating bath and subsequent cleaning, electrolytic plating of Sn using a plating bath, and subsequent cleaning are sequentially performed. The thickness of the Cu plating layer is about 10 μm to 20 μm, and the thickness of the Sn plating layer is 1 μm to 5 μm. In this way, the photoelectric conversion element 14 having the structure described in FIG. 1 is completed.
　上記製造方法では、Ｓ３０においてレジスト膜８８がｎ型非晶質半導体層５２の上に塗布される。非晶質半導体層は薬液によりエッチングされやすいため、できるだけウェット工程を通さない方が好ましい。そこで、ｎ型非晶質半導体層５２の上に適当な導電性薄膜を形成し、その導電性薄膜にレジスト膜８８を塗布することがよい。図２では、Ｓ２８において、導電性薄膜として、ＴＣＯ膜を用い、ｎ型非晶質半導体層５２の上にＴＣＯ膜をデポジションする。この工程は、スパッタ装置を用いて行なわれる。 In the above manufacturing method, the resist film 88 is applied on the n-type amorphous semiconductor layer 52 in S30. Since the amorphous semiconductor layer is easily etched by a chemical solution, it is preferable that the amorphous semiconductor layer is not subjected to a wet process as much as possible. Therefore, it is preferable to form an appropriate conductive thin film on the n-type amorphous semiconductor layer 52 and apply a resist film 88 to the conductive thin film. In FIG. 2, in S <b> 28, a TCO film is used as the conductive thin film, and the TCO film is deposited on the n-type amorphous semiconductor layer 52. This step is performed using a sputtering apparatus.
　図１７は、Ｓ２８の工程を付加した構造の光電変換素子１６の断面図である。ここでは、上部引出部５３として、ｉ型非晶質半導体層５０とｎ型非晶質半導体層５２とＴＣＯ膜である透明電極層５４との積層構造が示されている。 FIG. 17 is a cross-sectional view of the photoelectric conversion element 16 having a structure to which the process of S28 is added. Here, a laminated structure of an i-type amorphous semiconductor layer 50, an n-type amorphous semiconductor layer 52, and a transparent electrode layer 54 that is a TCO film is shown as the upper lead portion 53.
　図１８は、図１０で説明したＳ２６の工程に引き続いて、全面に透明電極層５４が形成される様子を示す図である。図１９は、図１１に対応する図で、ここに示されるように、レジスト膜８８とｎ型非晶質半導体層５２との間に透明電極層５４が配置されるので、ｎ型非晶質半導体層５２がウェット工程に直接曝されることが防止できる。 FIG. 18 is a diagram showing a state in which the transparent electrode layer 54 is formed on the entire surface following the step S26 described in FIG. FIG. 19 is a view corresponding to FIG. 11 and, as shown here, the transparent electrode layer 54 is disposed between the resist film 88 and the n-type amorphous semiconductor layer 52. The semiconductor layer 52 can be prevented from being directly exposed to the wet process.
　図２０は図１２に対応する図で、図２１は図１３に対応する図である。いずれも、上部引出部５３として、ｉ型非晶質半導体層５０とｎ型非晶質半導体層５２とＴＣＯ膜である透明電極層５４との積層構造が示されている。その後の工程も、上部引出部５３が透明電極層５４を含むことを除けば同様であるので、説明を省略する。 20 is a diagram corresponding to FIG. 12, and FIG. 21 is a diagram corresponding to FIG. In either case, a laminated structure of an i-type amorphous semiconductor layer 50, an n-type amorphous semiconductor layer 52, and a transparent electrode layer 54 that is a TCO film is shown as the upper lead portion 53. Subsequent steps are the same except that the upper lead portion 53 includes the transparent electrode layer 54, and thus description thereof is omitted.
　次に、上部引出部を用いない光電変換素子の構造と製造方法を比較例として説明する。図２２は、図１に対応する図で、ｎ型領域１００において、上部引出部を用いないで、絶縁層である窒化シリコン層４０の下のｎ型非晶質半導体層２８から電極を引き出す光電変換素子１２の断面図である。ｎ型領域１００において上部引出部がないことを除けば図１と同様の構成であるので、詳細な説明を省略する。 Next, the structure and manufacturing method of a photoelectric conversion element that does not use the upper lead portion will be described as a comparative example. FIG. 22 is a diagram corresponding to FIG. 1. In the n-type region 100, photoelectric is used to extract an electrode from the n-type amorphous semiconductor layer 28 under the silicon nitride layer 40 that is an insulating layer without using the upper lead portion. 3 is a sectional view of a conversion element 12. FIG. The n-type region 100 has the same configuration as that shown in FIG. 1 except that there is no upper lead portion, and thus detailed description thereof is omitted.
　図２３は、比較例の光電変換素子１２の製造手順を示すフローチャートである。図２と比較すると、Ｓ２４のｎコンタクトにおけるｎ型非晶質半導体層２８とｉ型非晶質半導体層２４の除去工程、Ｓ２６のｉ型非晶質半導体層５０とｎ型非晶質半導体層５２の再でポジション工程、Ｓ３０，Ｓ３２，Ｓ３４の不要部除去に関する工程が省略されていることが分かる。すなわち、図２３のＳ１０，Ｓ１２，Ｓ１４，Ｓ１６，Ｓ１８，Ｓ２０，Ｓ２２が、図２のＳ１０，Ｓ１２，Ｓ１４，Ｓ１６，Ｓ１８，Ｓ２０，Ｓ２２と全く同じである。そこで、相違する工程を主に説明する。 FIG. 23 is a flowchart showing a manufacturing procedure of the photoelectric conversion element 12 of the comparative example. Compared with FIG. 2, the removal process of the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 in the n-contact of S24, the i-type amorphous semiconductor layer 50 and the n-type amorphous semiconductor layer of S26 It can be seen that the position process and the process of removing unnecessary parts of S30, S32, and S34 are omitted in 52. That is, S10, S12, S14, S16, S18, S20, and S22 in FIG. 23 are exactly the same as S10, S12, S14, S16, S18, S20, and S22 in FIG. Therefore, the different steps will be mainly described.
　図２４は、最初のＳ１０のｉ型非晶質半導体層２４とｎ型非晶質半導体層２８のデポジション工程を示す図で、図３と同じ内容である。以下、Ｓ１２，Ｓ１４，Ｓ１６，Ｓ１８，Ｓ２０は、このｉ型非晶質半導体層２４とｎ型非晶質半導体層２８を含む半導体基板２０についての処理が順次行われるが、これらは、図４から図８と全く同じであるので、詳細な説明を省略する。 FIG. 24 is a diagram showing the first deposition process of the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28 in S10, and has the same contents as FIG. Hereinafter, in S12, S14, S16, S18, and S20, the processing for the semiconductor substrate 20 including the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28 is sequentially performed. From FIG. 8, the detailed description is omitted.
　図２５は、Ｓ２２におけるｎコンタクトのためのＳｉＮX除去の様子を示す図である。ここでは、絶縁層である窒化シリコン層４０に開口部８３が設けられるが、ｉ型非晶質半導体層２４とｎ型非晶質半導体層２８には開口部が設けられない。 FIG. 25 is a diagram showing the state of SiN x removal for the n-contact in S22. Here, an opening 83 is provided in the silicon nitride layer 40 that is an insulating layer, but no opening is provided in the i-type amorphous semiconductor layer 24 and the n-type amorphous semiconductor layer 28.
　図２６は、Ｓ４０の下地電極６０，６２の形成を示す図で、図１３に対応する。図１３と比較すると、上部引出部５３がないので、下地電極６０，６２が、ｎ型非晶質半導体層２８に接続されている。 FIG. 26 is a diagram illustrating the formation of the base electrodes 60 and 62 in S40, and corresponds to FIG. Compared with FIG. 13, since there is no upper lead portion 53, the base electrodes 60 and 62 are connected to the n-type amorphous semiconductor layer 28.
　図２７はＳ４２の電極分離用レジスト形成を示す図で、図１４に対応する。また、図２８はＳ４４の電極エッチングを示す図で、図１５に対応する。また図２９は、Ｓ４６のレジスト除去の様子を示す図で、図１６に対応する。これらは、処理内容は同じであるが、いずれも、下地電極６０，６２の下に上部引出部５３がないことが相違する。 FIG. 27 is a diagram showing the electrode separation resist formation in S42 and corresponds to FIG. FIG. 28 shows the electrode etching in S44, which corresponds to FIG. FIG. 29 is a diagram showing how the resist is removed in S46, and corresponds to FIG. The processing contents of these are the same, except that there is no upper lead portion 53 under the base electrodes 60 and 62.
　このように、ｎ型領域１００の絶縁層開口に引き続いて、絶縁層である窒化シリコン層４０の下のｎ型非晶質半導体層２８とｉ型非晶質半導体層２４を開口することで、窒化シリコン層４０の開口処理の際に、仮に残渣があっても、これを良好に除去し、その後の工程に残渣の影響を与えない。そして、この開口に上部引出部５３を設けて、ｎ型領域１００の電極７０を形成することができる。 Thus, following the opening of the insulating layer in the n-type region 100, by opening the n-type amorphous semiconductor layer 28 and the i-type amorphous semiconductor layer 24 under the silicon nitride layer 40, which is an insulating layer, Even if there is a residue during the opening process of the silicon nitride layer 40, it is removed satisfactorily and does not affect the subsequent steps. Then, the upper lead portion 53 is provided in this opening, and the electrode 70 of the n-type region 100 can be formed.
　本発明に係る裏面接合型の光電変換素子及び裏面接合型の光電変換素子の製造方法は、太陽光発電システム等に利用できる。 The back junction type photoelectric conversion element and the back junction type photoelectric conversion element manufacturing method according to the present invention can be used for a photovoltaic power generation system or the like.
　１０，１２，１４，１６　光電変換素子、２０　半導体基板、２２，２４，５０　ｉ型非晶質半導体層、２６，２８，５２　ｎ型非晶質半導体層、３８　反射防止層、４０　窒化シリコン層、４２，４４　ｐ型非晶質半導体層、５３　上部引出部、５４　透明電極層、６０，６２　下地電極（６０　透明電極層、６２　Ｃｕ層）、７０，７２　電極、８０，８２，８４，８８　レジスト膜、８３　開口部、８５　分離溝、８６　分離部、１００　ｎ型領域、１０２　ｐ型領域。 10, 12, 14, 16 photoelectric conversion element, 20 semiconductor substrate, 22, 24, 50 i-type amorphous semiconductor layer, 26, 28, 52 n-type amorphous semiconductor layer, 38 antireflection layer, 40 silicon nitride layer 42, 44 p-type amorphous semiconductor layer, 53 upper lead portion, 54 transparent electrode layer, 60, 62 base electrode (60 transparent electrode layer, 62 Cu layer), 70, 72 electrode, 80, 82, 84, 88 Resist film, 83 opening, 85 separation groove, 86 separation, 100 n-type region, 102 p-type region.

Claims (5)

  1. 　受光面と、前記受光面の反対側の裏面とを有する第１導電型の半導体基板と、
    　前記裏面に配置され、前記半導体基板に接続し前記第１導電型を有する非晶質半導体層を含んで構成される第１導電型領域と、
    　前記裏面に配置され、第２導電型を有する非晶質半導体層を含んで構成され、前記第１導電型領域とｐｎ接合を形成する第２導電型領域と、
    　前記第１導電型領域または前記第２導電型領域のいずれか一方の領域の非晶質半導体層の上に形成される絶縁層と、
    　前記絶縁層に設けられる絶縁層開口部と、前記絶縁層開口部に対応してその下部に設けられる非晶質開口部とを通して、前記半導体基板に接続し、前記非晶質開口部と前記絶縁層開口部を覆って前記絶縁層の上部に引き出され、前記絶縁層が設けられる前記非晶質半導体層と同じ導電型を有する非晶質半導体層を引出非晶質半導体層として含む上部引出部と、
    　前記上部引出部に接続して設けられる電極層と、
    　を備えることを特徴とする裏面接合型の光電変換素子。     A first conductivity type semiconductor substrate having a light receiving surface and a back surface opposite to the light receiving surface;
    A first conductivity type region disposed on the back surface and connected to the semiconductor substrate and including an amorphous semiconductor layer having the first conductivity type;
    A second conductivity type region disposed on the back surface and including an amorphous semiconductor layer having a second conductivity type, and forming a pn junction with the first conductivity type region;
    An insulating layer formed on an amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region;
    An insulating layer opening provided in the insulating layer and an amorphous opening provided below the insulating layer opening corresponding to the insulating layer opening are connected to the semiconductor substrate, and the amorphous opening and the insulating An upper lead portion that includes an amorphous semiconductor layer that is drawn to the upper portion of the insulating layer so as to cover the layer opening and has the same conductivity type as the amorphous semiconductor layer on which the insulating layer is provided as a lead amorphous semiconductor layer When,
    An electrode layer provided in connection with the upper lead portion;
    A back junction type photoelectric conversion element comprising:
  2. 　請求項１に記載の裏面接合型の光電変換素子において、
    　前記上部引出部は、
    　前記絶縁層の上部に引き出された部分は、前記絶縁層開口部の開口面積よりも広い面積を有することを特徴とする裏面接合型の光電変換素子。     In the back junction type photoelectric conversion element according to claim 1,
    The upper drawer portion is
    The back-junction photoelectric conversion element characterized in that a portion led out above the insulating layer has an area larger than an opening area of the opening of the insulating layer.
  3. 　請求項１に記載の裏面接合型の光電変換素子において、
    　前記上部引出部は、
    　前記引出非晶質半導体層の上に形成される光透過型導電層を含むことを特徴とする裏面接合型の光電変換素子。     In the back junction type photoelectric conversion element according to claim 1,
    The upper drawer portion is
    A back junction type photoelectric conversion element comprising a light transmission type conductive layer formed on the lead amorphous semiconductor layer.
  4. 　第１導電型のシリコン基板の受光面とは反対側の裏面にｐｎ接合が形成される裏面接合型の光電変換素子の製造方法であって、
    　第１導電型を有する非晶質半導体層を含んで構成される第１導電型領域を前記裏面に形成する工程と、
    　第２導電型を有する非晶質半導体層を含んで構成され、前記第１導電型領域とｐｎ接合を形成する第２導電型領域を前記裏面に形成する工程と、
    　前記第１導電型領域または前記第２導電型領域のいずれか一方の領域の非晶質半導体層の上に絶縁層を形成する工程と、
    　前記絶縁層を開口して絶縁層開口部を形成する工程と、
    　前記絶縁層開口部に対応してその下部に設けられる非晶質開口部を開口して非晶質開口部を形成する工程と、
    　前記絶縁層開口部と前記非晶質開口部とを通して、前記半導体基板に接続し、前記非晶質開口部と前記絶縁層開口部を覆って前記絶縁層の上部に引き出され、前記絶縁層が設けられる前記非晶質半導体層と同じ導電型を有する非晶質半導体層を引出非晶質半導体層として含む上部引出部を形成する工程と、
    　前記上部引出部に接続して設けられる電極層を形成する工程と、
    　　を含むことを特徴とする裏面接合型の光電変換素子の製造方法。     A method of manufacturing a back junction type photoelectric conversion element in which a pn junction is formed on the back surface opposite to the light receiving surface of a first conductivity type silicon substrate,
    Forming a first conductivity type region including an amorphous semiconductor layer having a first conductivity type on the back surface;
    Forming a second conductivity type region on the back surface that includes an amorphous semiconductor layer having a second conductivity type and forms a pn junction with the first conductivity type region;
    Forming an insulating layer on the amorphous semiconductor layer in one of the first conductivity type region and the second conductivity type region;
    Opening the insulating layer to form an insulating layer opening;
    Forming an amorphous opening by opening an amorphous opening provided in a lower portion corresponding to the insulating layer opening; and
    The insulating layer opening and the amorphous opening are connected to the semiconductor substrate, and the amorphous opening and the insulating layer opening are covered and drawn to the top of the insulating layer. Forming an upper lead portion including, as the lead amorphous semiconductor layer, an amorphous semiconductor layer having the same conductivity type as the amorphous semiconductor layer provided;
    Forming an electrode layer connected to the upper lead portion; and
    The manufacturing method of the back junction type photoelectric conversion element characterized by including.
  5. 　請求項４に記載の裏面接合型の光電変換素子の製造方法において、
    　前記上部引出部を形成する工程は、
    　前記引出非晶質半導体層とその上に形成される光透過型導電層を含む積層膜を全面に形成する工程と、
    　前記積層膜を所定の前記上部引出部の形状に形成する工程と、
    　を含むことを特徴とする裏面接合型の光電変換素子の製造方法。     In the manufacturing method of the back junction type photoelectric conversion element of Claim 4,
    The step of forming the upper lead portion includes:
    Forming a laminated film including the lead amorphous semiconductor layer and a light-transmitting conductive layer formed thereon, over the entire surface;
    Forming the laminated film in the shape of the predetermined upper lead portion;
    The manufacturing method of the back junction type photoelectric conversion element characterized by including.
PCT/JP2012/054232 2011-03-25 2012-02-22 Back-junction photoelectric conversion element and method for manufacturing back-junction photoelectric conversion element WO2012132654A1 (en)

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