WO2012132613A1 - Method for producing photoelectric conversion element - Google Patents

Method for producing photoelectric conversion element Download PDF

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Publication number
WO2012132613A1
WO2012132613A1 PCT/JP2012/053808 JP2012053808W WO2012132613A1 WO 2012132613 A1 WO2012132613 A1 WO 2012132613A1 JP 2012053808 W JP2012053808 W JP 2012053808W WO 2012132613 A1 WO2012132613 A1 WO 2012132613A1
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Prior art keywords
layer
photoelectric conversion
conversion element
amorphous silicon
semiconductor layer
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PCT/JP2012/053808
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French (fr)
Japanese (ja)
Inventor
大樹 橋口
三島　孝博
正人 重松
良 後藤
豊 桐畑
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三洋電機株式会社
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Publication of WO2012132613A1 publication Critical patent/WO2012132613A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a method for manufacturing a photoelectric conversion element.
  • Patent Document 1 a light-receiving surface and a semiconductor substrate having a back surface opposite to the light-receiving surface, a first semiconductor layer formed on the back surface, formed on the back surface, and disposed on both sides of the first semiconductor layer.
  • a pair of second semiconductor layers, a first insulating layer formed from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers, and a pair of second semiconductor layers A second insulating layer formed over the other second semiconductor layer to the first semiconductor layer, a transparent electrode layer covering the first semiconductor layer and the second semiconductor layer, and a collection formed on the transparent electrode layer
  • a photoelectric conversion element including an electrode layer is disclosed.
  • a method for manufacturing a photoelectric conversion element in which a plurality of stacked portions including a semiconductor layer are stacked on a semiconductor substrate has been devised. Then, after each laminated portion is formed, an etching process for each laminated portion is performed using a mask or a resist for patterning each laminated portion.
  • an etching process for each laminated portion is performed using a mask or a resist for patterning each laminated portion.
  • alignment is performed using alignment marks provided in each stacked portion, but depending on the position where each alignment mark is formed, There is a possibility of adversely affecting the power generation characteristics of the photoelectric conversion element.
  • a first alignment mark is formed on a crystalline semiconductor substrate, and a first amorphous semiconductor layer is formed on the crystalline semiconductor substrate including the first alignment mark.
  • a first pattern forming unit having a first positioning unit for positioning with respect to the first alignment mark is prepared, and the first pattern forming unit is installed on the first amorphous semiconductor layer by performing the positioning.
  • the second alignment mark is formed on the first amorphous semiconductor layer using the first positioning portion, and the second amorphous semiconductor layer is formed on the crystalline semiconductor substrate including the second alignment mark.
  • a second pattern forming portion provided at a position not overlapping the second alignment mark and having a second positioning portion for positioning with respect to the first alignment mark or the second alignment mark. Preparation and positioning are performed to place a second pattern forming portion on the second amorphous semiconductor layer, and a third alignment mark is formed on the second amorphous semiconductor layer using the second positioning portion.
  • the power generation characteristics of the photoelectric conversion element can be improved.
  • it is a back surface side top view of a photoelectric conversion element.
  • it is sectional drawing of a photoelectric conversion element.
  • it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a back surface side top view which shows a mode that the 1st alignment mark is formed in the n-type single crystal silicon substrate.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a top view of a mask.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a figure showing positional relation of the 1st alignment mark and the 2nd alignment mark.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a top view of a mask.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • it is a figure showing the positional relationship of the 1st alignment mark, the 2nd alignment mark, and the 3rd alignment mark.
  • it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element.
  • FIG. 1 is a plan view of the back side of the photoelectric conversion element 10.
  • FIG. 2 is a partial cross-sectional view taken along the line XX of FIG. 1 and shows a cross-sectional view of the photoelectric conversion element 10.
  • the photoelectric conversion element 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, and i.
  • an arrow A shown in FIG. 2 indicates a direction in which light such as sunlight enters the photoelectric conversion element 10.
  • the “light receiving surface” means a surface on which light such as sunlight is mainly incident.
  • the “back surface” means a surface opposite to the light receiving surface.
  • the n-type single crystal silicon substrate 18 is a power generation layer that receives carriers incident from the light receiving surface and generates carriers.
  • the n-type single crystal silicon substrate 18 is used.
  • the present invention is not limited to this, and an n-type or p-type conductive crystal semiconductor substrate can be used.
  • a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are passivation layers formed on the light-receiving surface of the n-type single crystal silicon substrate 18.
  • the i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer formed on the light receiving surface.
  • the i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film.
  • the n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 14 preferably has an n-type dopant concentration of 1 ⁇ 10 21 / cm 3 or more.
  • the amorphous silicon layer includes a microcrystalline semiconductor film.
  • a microcrystalline semiconductor film is a film in which crystal grains are precipitated in an amorphous semiconductor.
  • the average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
  • the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10.
  • the antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14.
  • the antireflection layer 12 is made of a transparent material and has a refractive index that reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. And a film thickness is preferred.
  • the antireflection layer 12 includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like.
  • the i-n stacked unit 21 is formed on the back surface of the n-type single crystal silicon substrate 18 and includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23. It is preferable that the i-n stacked unit 21 be arranged so that a larger amount of current can be collected from the surface of the photoelectric conversion element 10 in the n-side electrode unit 25 described later.
  • the i-n stacked portion 21 preferably has a comb shape in which a plurality of finger portions extend in parallel.
  • the i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22.
  • the i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film.
  • the n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant.
  • the n-type amorphous silicon layer 23 preferably has an n-type dopant concentration of 1 ⁇ 10 21 / cm 3 or more.
  • the insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31.
  • the insulating layer 24 also functions as a protective layer formed on the n-type amorphous silicon layer 23.
  • the insulating layer 24 may be any material having electrical insulating properties, but preferably includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like.
  • the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23, and the insulating layer 24 constitute a first amorphous semiconductor layer formed on the back surface.
  • the n-side electrode portion 25 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10.
  • the n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
  • the transparent conductive layer 26 is formed on the n-type amorphous silicon layer 23.
  • the transparent conductive layer 26 is made of a metal oxide such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), titanium oxide (TiO 2 ), and indium tin oxide (ITO). It is configured to include at least one.
  • the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO).
  • the metal layer 27 is formed on the transparent conductive layer 26.
  • the metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example.
  • the “seed layer” refers to a layer that is a starting point for plating growth.
  • the first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth.
  • the first electrode unit 28 includes, for example, copper (Cu).
  • the second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth.
  • the second electrode unit 29 includes tin (Sn).
  • the i-p stacked portions 31 are formed on the back surface of the n-type single crystal silicon substrate 18 so as to be alternately arranged with the i-n stacked portions 21.
  • the ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33, and more in the plane of the photoelectric conversion element 10 in the p-side electrode portion 35 described later. It is preferable to arrange so that the current can be collected.
  • the ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel.
  • the i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18.
  • the p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32.
  • the i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 constitute a part of the second amorphous semiconductor layer formed on the back surface.
  • the i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film.
  • the p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant.
  • the p-type amorphous silicon layer 33 preferably has a p-type dopant concentration of 1 ⁇ 10 21 / cm 3 or more.
  • the p-side electrode portion 35 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10.
  • the p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
  • the transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33.
  • the material and the like of the transparent conductive layer 36 are the same as those of the transparent conductive layer 26, detailed description thereof is omitted.
  • the metal layer 37 is formed on the transparent conductive layer 36.
  • the material and the like of the metal layer 37 are the same as those of the metal layer 27, detailed description thereof is omitted.
  • the first electrode portion 38 is formed on the metal layer 37 by plating growth.
  • the material and the like of the first electrode portion 38 are the same as those of the first electrode portion 28, detailed description thereof is omitted.
  • the second electrode part 39 is formed on the first electrode part 38 by plating growth.
  • the material and the like of the second electrode portion 39 are the same as those of the second electrode portion 29, detailed description thereof is omitted.
  • FIG. 3 is a flowchart showing a procedure of a method for manufacturing the photoelectric conversion element 10.
  • the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
  • an n-type single crystal silicon substrate 18 is prepared. As shown in FIG. 4 which is a plan view of the back surface side of the n-type single crystal silicon substrate 18, four corners are formed on the back surface of the n-type single crystal silicon substrate 18, respectively. A cross mark groove is formed (S1). The cross marks are formed by the laser marking device as the first alignment marks 41a to 41d. The first alignment marks 41a and 41b formed at one end of the n-type single crystal silicon substrate 18 and the first alignment marks 41c and 41d formed at the other end of the n-type single crystal silicon substrate 18. As shown in FIG. 4, it is formed at an asymmetrical position about the line BB.
  • the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S2).
  • the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
  • a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S3).
  • a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
  • KOH aqueous solution potassium hydroxide aqueous solution
  • an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 are formed on the light-receiving surface of the n-type single crystal silicon substrate 18, and on the back surface of the n-type single crystal silicon substrate 18, An i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed (S4).
  • each of the i-type amorphous silicon layer 16, the n-type amorphous silicon layer 14, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a is formed by, for example, a plasma CVD method or the like. can do.
  • the insulating layer 24a is formed on the n-type amorphous silicon layer 23a, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S5).
  • the insulating layer 24a and the antireflection layer 12 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • a cross-sectional laminated structure as shown in FIG. 5 is obtained.
  • an i-type amorphous silicon layer 22a, an n-type amorphous silicon layer 23a, and an insulating layer 24a are formed on the back surface of the n-type single crystal silicon substrate 18. These layers are, for example, 0 A thin film of about 5 nm to 50 nm. Therefore, even when the film is covered with such a thin film, the first alignment marks 41a to 41d can be visually recognized from above when performing alignment.
  • the mask 45 shown in FIG. 6 is prepared, the positioning portions 47a to 47d and the first alignment marks 41a to 41d are aligned, and the mask 45 is set (S6).
  • the mask 45 includes a pattern portion 46 that is an opening region for forming a predetermined pattern in the i-type amorphous silicon layer 22a, the n-type amorphous silicon layer 23a, and the insulating layer 24a, and a first alignment mark.
  • This is a pattern forming member including positioning portions 47a to 47d which are opening regions for positioning with respect to 41a to 41d.
  • the positioning portions 47a to 47d are formed at positions that do not overlap the first alignment marks 41a to 41d, respectively, when alignment is performed with respect to the first alignment marks 41a to 41d.
  • positioning portions 47a to 47d are regions located diagonally among regions divided by cross marks of first alignment marks 41a to 41d formed on the back surface of n-type single crystal silicon substrate 18.
  • a rectangular pattern is formed.
  • the mask 45 is arranged so that the rectangular patterns of the positioning portions 47a to 47d are located as far apart as possible from the cross marks of the first alignment marks 41a to 41d.
  • an etching paste is applied by a screen printing method, and the insulating layer 24a, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched, whereby the insulating layer 24a, the i-type amorphous silicon layer are etched.
  • Part of 22a and n-type amorphous silicon layer 23a is removed (S7). That is, of the insulating layer 24a, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a, a region for forming the ip stacked portion 31 on the n-type single crystal silicon substrate 18 in a later step. Remove the top part.
  • the insulating layer 24a, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are patterned, and as shown in FIG. 7, the insulating layer 24b, the i-type amorphous silicon layer 22, A cross-sectional laminated structure in which the n-type amorphous silicon layer 23 is formed is obtained.
  • FIG. 8 a diagram corresponding to an enlarged view of a region indicated by a dotted line C in the plan view on the back surface side of FIG. 4
  • the second alignment mark 42a is applied to the etching paste applied through the positioning portion 47a.
  • the second alignment mark 42a is formed at a position so as not to overlap the first alignment mark 41a.
  • the etching paste applied through the positioning portions 47b to 47d forms the second alignment marks 42b to 42d.
  • the second alignment marks 42b to 42d are also formed at positions that do not overlap with the first alignment marks 41b to 41d, respectively.
  • the insulating layer 24 b, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered.
  • An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed (S8).
  • the i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a can be formed by, for example, a plasma CVD method or the like.
  • the mask 48 shown in FIG. 10 is prepared, the positioning portions 50a to 50d and the first alignment marks 41a to 41d or the second alignment marks 42a to 42d are aligned, and the mask 48 is set ( S9).
  • the mask 48 includes a pattern portion 49 that is an opening region for forming a predetermined pattern in the i-type amorphous silicon layer 32a, the p-type amorphous silicon layer 33a, and the insulating layer 24b, and a first alignment mark.
  • This is a pattern forming member including positioning portions 50a to 50d which are opening regions for positioning with respect to 41a to 41d or the second alignment marks 42a to 42d.
  • the positioning portions 50a to 50d perform the first alignment marks 41a to 41d and the second alignment marks 42a to 42d when aligning the first alignment marks 41a to 41d or the second alignment marks 42a to 42d. It is preferable that it is formed at a position where it does not overlap with the other.
  • positioning portions 50a to 50d are formed of regions divided by cross marks of first alignment marks 41a to 41d formed on the back surface of n-type single crystal silicon substrate 18. A rectangular pattern is formed in a region located diagonally.
  • the mask 48 is arranged so that the rectangular patterns of the positioning portions 50a to 50d are located as far apart as possible from the cross marks of the first alignment marks 41a to 41d.
  • an etching paste is applied by a screen printing method, and the insulating layer 24b, the i-type amorphous silicon layer 32a, and the p-type amorphous silicon layer 33a are etched to thereby form the insulating layer 24b, the i-type amorphous silicon.
  • a part of the layer 32a and the p-type amorphous silicon layer 33a is removed (S10).
  • the insulating layer 24b, the i-type amorphous silicon layer 32a, and the p-type amorphous silicon layer 33a are patterned, and as shown in FIG.
  • the third alignment mark 43a is applied to the etching paste applied through the positioning portion 50a.
  • the third alignment mark 43a is formed at a position so as not to overlap the first alignment mark 41a and the second alignment mark 42a.
  • the etching paste applied through the positioning portions 50b to 50d forms the third alignment marks 43b to 43d.
  • the third alignment marks 43b to 43d are also formed at positions that do not overlap the first alignment marks 41b to 41d and the second alignment marks 42b to 42d, respectively.
  • the transparent conductive layer 26a and the metal layer 27a are formed (S11). Specifically, it is formed by a thin film forming method such as a plasma CVD method or a sputtering method.
  • the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the insulating layer 24.
  • Form (S12) the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
  • the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37.
  • the electrode part 39 is formed (S13). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
  • alignment is performed on the first alignment marks 41a to 41d using masks 45 and 48, and patterning processing is performed by applying an etching paste.
  • the second alignment marks 42a to 42d formed on the first and third alignment marks 43a to 43d formed on the second amorphous semiconductor portion are formed at the positions where they overlap each other, a hole penetrating in the stacking direction is formed. Is done. Therefore, the n-type single crystal silicon substrate 18 is exposed in the region where the alignment marks are formed. Therefore, since the passivation layer does not exist in the exposed portion of the n-type single crystal silicon substrate 18, carrier recombination may occur.
  • the second alignment marks 42a to 42d and the third alignment marks 43a to 43d are formed at positions that do not overlap.
  • the n-type single crystal silicon substrate 18 is covered with either the i-type amorphous silicon layer 22 or the i-type amorphous silicon layer 32, the i-type amorphous silicon layer 22 or the i-type amorphous silicon layer 22 is covered.
  • the amorphous silicon layer 32 is passivated. Therefore, recombination of carriers generated in the n-type single crystal silicon substrate 18 is suppressed, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
  • the first alignment marks 41a to 41d are formed in the shape of a cross mark, and therefore, the position where the cross mark intersects can be set as an alignment target. . That is, since a point can be set as an object of alignment, for example, it is possible to perform alignment appropriately as compared with a shape that makes it difficult to set a point as an object of alignment such as a circle. Accordingly, the positioning of the positioning portions 47a to 47d and the positioning portions 50a to 50d can be suitably performed with respect to the first alignment marks 41a to 41d.
  • the first alignment marks 41a and 41b, the second alignment marks 42a and 42b, and the third alignment marks 43a and 43b provided at one end and the other end are provided.
  • the first alignment marks 41c and 41d, the second alignment marks 42c and 42d, and the third alignment marks 43c and 43d are provided at asymmetric positions around the line BB. Thereby, determination of the direction of one side edge part and the other side edge part can be performed easily.
  • the first alignment marks 41a and 41b, the second alignment marks 42a and 42b, the third alignment marks 43a and 43b provided at one end, and the other end are provided.
  • the first alignment marks 41c and 41d, the second alignment marks 42c and 42d, and the third alignment marks 43c and 43d have been described as having an asymmetric positional relationship around the BB line.
  • the shape of the first alignment marks 41a and 41b may be a cross mark
  • the shape of the first alignment marks 41c and 41d may be an x mark.
  • the second alignment marks 42a to 42d and the third alignment marks 43a to 43d are described as being provided at the four corners, respectively. However, as shown in FIG. Only the second alignment marks 42b and 42c may be formed for 42a to 42d, and only the third alignment marks 43a and 43d may be formed for the third alignment marks 43a to 43d. Thereby, the second alignment marks 42b and 42c and the third alignment marks 43a and 43d are arranged on different diagonal lines. That is, since the second alignment marks 42b and 42c and the third alignment marks 43a and 43d are formed at positions where they do not overlap, the n-type single crystal silicon substrate 18 has the i-type amorphous silicon layer 22 or the i-type amorphous silicon. Passivation is performed by either one of the quality silicon layers 32. Therefore, recombination of carriers generated in the n-type single crystal silicon substrate 18 is suppressed, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
  • a mask is used as a pattern forming member for performing an etching process and an etching paste is used as an etching treatment agent.
  • an etching process is performed using a resist as a pattern forming member. It is good also as what performs using an etching liquid as an agent.

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Abstract

This method for producing a photoelectric conversion element forms first alignment marks (41a-41d) on a crystalline semiconductor substrate, forms a first non-crystalline semiconductor layer on the crystalline semiconductor substrate, including on the first alignment marks (41a-41d), forms second alignment marks (42a-42d) on the first non-crystalline semiconductor layer using positioning sections (47a-47d), forms a second non-crystalline semiconductor layer on the crystalline semiconductor substrate including on the second alignment marks (42a-42d), and forms third alignment marks (43a-43d) that are at the second non-crystalline semiconductor layer using positioning sections (50a-50d) and that are provided a position that does not overlap the second alignment marks.

Description

光電変換素子の製造方法Method for manufacturing photoelectric conversion element
　本発明は、光電変換素子の製造方法に関する。 The present invention relates to a method for manufacturing a photoelectric conversion element.
　特許文献１には、受光面と受光面の反対側に裏面を有する半導体基板と、裏面上に形成される第１半導体層と、裏面上に形成され、第１半導体層の両隣に配設される一対の第２半導体層と、一対の第２半導体層のうち一方の第２半導体層上から第１半導体層上まで跨って形成される第１絶縁層と、一対の第２半導体層のうち他方の第２半導体層上から第１半導体層上まで跨って形成される第２絶縁層と、第１半導体層及び第２半導体層を覆う透明電極層と、透明電極層上に形成される収集電極層と、を備える光電変換素子が開示されている。 In Patent Document 1, a light-receiving surface and a semiconductor substrate having a back surface opposite to the light-receiving surface, a first semiconductor layer formed on the back surface, formed on the back surface, and disposed on both sides of the first semiconductor layer. A pair of second semiconductor layers, a first insulating layer formed from one second semiconductor layer to the first semiconductor layer of the pair of second semiconductor layers, and a pair of second semiconductor layers A second insulating layer formed over the other second semiconductor layer to the first semiconductor layer, a transparent electrode layer covering the first semiconductor layer and the second semiconductor layer, and a collection formed on the transparent electrode layer A photoelectric conversion element including an electrode layer is disclosed.
特開２００９－２００２６７号公報JP 2009-200277 A
　半導体基板上に、半導体層を含む複数の積層部が積層される光電変換素子の製造方法が考案されている。そして、当該各積層部がそれぞれ形成された後に、各積層部のパターンニングを行うためのマスクやレジストを用いて、各積層部のエッチング処理が行われる。ここで、当該各マスクやレジストを用いてエッチング処理を行う際に、各積層部に設けられるアライメントマークを用いて位置合わせが行われているが、当該各アライメントマークが形成される位置によっては、光電変換素子の発電特性に悪影響を与える可能性がある。 A method for manufacturing a photoelectric conversion element in which a plurality of stacked portions including a semiconductor layer are stacked on a semiconductor substrate has been devised. Then, after each laminated portion is formed, an etching process for each laminated portion is performed using a mask or a resist for patterning each laminated portion. Here, when performing an etching process using the respective masks and resists, alignment is performed using alignment marks provided in each stacked portion, but depending on the position where each alignment mark is formed, There is a possibility of adversely affecting the power generation characteristics of the photoelectric conversion element.
　本発明に係る光電変換素子の製造方法は、結晶系半導体基板上に第１アライメントマークを形成し、第１アライメントマーク上を含んで結晶系半導体基板上に第１非晶質系半導体層を形成し、第１アライメントマークに対して位置決めするための第１位置決め部を有する第１パターン形成部を準備し、該位置決めを行って第１非晶質系半導体層上に第１パターン形成部を設置し、第１位置決め部を用いて第１非晶質系半導体層に第２アライメントマークを形成し、第２アライメントマーク上を含んで結晶系半導体基板上に第２非晶質系半導体層を形成し、第２アライメントマークと重ならない位置に設けられ、第１アライメントマークまたは第２アライメントマークに対して位置決めするための第２位置決め部を有する第２パターン形成部を準備し、該位置決めを行って第２非晶質系半導体層上に第２パターン形成部を設置し、第２位置決め部を用いて第２非晶質系半導体層に第３アライメントマークを形成する。 In the method for manufacturing a photoelectric conversion element according to the present invention, a first alignment mark is formed on a crystalline semiconductor substrate, and a first amorphous semiconductor layer is formed on the crystalline semiconductor substrate including the first alignment mark. Then, a first pattern forming unit having a first positioning unit for positioning with respect to the first alignment mark is prepared, and the first pattern forming unit is installed on the first amorphous semiconductor layer by performing the positioning. Then, the second alignment mark is formed on the first amorphous semiconductor layer using the first positioning portion, and the second amorphous semiconductor layer is formed on the crystalline semiconductor substrate including the second alignment mark. And a second pattern forming portion provided at a position not overlapping the second alignment mark and having a second positioning portion for positioning with respect to the first alignment mark or the second alignment mark. Preparation and positioning are performed to place a second pattern forming portion on the second amorphous semiconductor layer, and a third alignment mark is formed on the second amorphous semiconductor layer using the second positioning portion. .
　本発明によれば、光電変換素子の発電特性を向上させることができる。 According to the present invention, the power generation characteristics of the photoelectric conversion element can be improved.
本発明に係る実施の形態において、光電変換素子の裏面側平面図である。In embodiment which concerns on this invention, it is a back surface side top view of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の断面図である。In embodiment which concerns on this invention, it is sectional drawing of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を示すフローチャートである。In embodiment concerning this invention, it is a flowchart which shows the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、ｎ型単結晶シリコン基板に第１アライメントマークを形成している様子を示す裏面側平面図である。In embodiment concerning this invention, it is a back surface side top view which shows a mode that the 1st alignment mark is formed in the n-type single crystal silicon substrate. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、マスクの平面図である。In embodiment concerning this invention, it is a top view of a mask. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、第１アライメントマークと第２アライメントマークの位置関係を示す図である。In an embodiment concerning the present invention, it is a figure showing positional relation of the 1st alignment mark and the 2nd alignment mark. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、マスクの平面図である。In embodiment concerning this invention, it is a top view of a mask. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、第１アライメントマークと第２アライメントマークと第３アライメントマークの位置関係を示す図である。In an embodiment concerning the present invention, it is a figure showing the positional relationship of the 1st alignment mark, the 2nd alignment mark, and the 3rd alignment mark. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、光電変換素子の製造方法の手順を説明するための断面図である。In embodiment which concerns on this invention, it is sectional drawing for demonstrating the procedure of the manufacturing method of a photoelectric conversion element. 本発明に係る実施の形態において、第１アライメントマークの変形例を示す図である。In embodiment concerning this invention, it is a figure which shows the modification of a 1st alignment mark. 本発明に係る実施の形態において、第２アライメントマークと第３アライメントマークの位置関係の変形例を示す図である。In embodiment concerning this invention, it is a figure which shows the modification of the positional relationship of a 2nd alignment mark and a 3rd alignment mark.
　以下に図面を用いて、本発明に係る実施の形態を詳細に説明する。以下では、全ての図面において、同様の要素には同一の符号を付し、重複する説明を省略する。本文中の説明においては、必要に応じそれ以前に述べた符号を用いるものとする。 Embodiments according to the present invention will be described below in detail with reference to the drawings. Hereinafter, in all the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. In the description in the text, the symbols described before are used as necessary.
　図１は、光電変換素子１０の裏面側平面図である。図２は、図１のＸ－Ｘ線部分断面図であり、光電変換素子１０の断面図を示している。光電変換素子１０は、反射防止層１２と、ｎ型非晶質シリコン層１４と、ｉ型非晶質シリコン層１６と、ｎ型単結晶シリコン基板１８と、ｉ－ｎ積層部２１と、ｉ－ｐ積層部３１と、絶縁層２４と、ｎ側電極部２５と、ｐ側電極部３５とを備える。ここで、図２に示される矢印Ａは、光電変換素子１０に対して太陽光等の光が入射する方向を示している。なお、「受光面」とは、太陽光等の光が主に入射する面を意味する。また、「裏面」とは、受光面と反対側の面を意味する。 FIG. 1 is a plan view of the back side of the photoelectric conversion element 10. FIG. 2 is a partial cross-sectional view taken along the line XX of FIG. 1 and shows a cross-sectional view of the photoelectric conversion element 10. The photoelectric conversion element 10 includes an antireflection layer 12, an n-type amorphous silicon layer 14, an i-type amorphous silicon layer 16, an n-type single crystal silicon substrate 18, an i-n stacked portion 21, and i. A p-layer portion 31, an insulating layer 24, an n-side electrode portion 25, and a p-side electrode portion 35; Here, an arrow A shown in FIG. 2 indicates a direction in which light such as sunlight enters the photoelectric conversion element 10. The “light receiving surface” means a surface on which light such as sunlight is mainly incident. The “back surface” means a surface opposite to the light receiving surface.
　ｎ型単結晶シリコン基板１８は、受光面から入射された光を受けてキャリアを生成する発電層である。なお、本実施の形態では、ｎ型単結晶シリコン基板１８としたが、これに限定されるものではなく、ｎ型又はｐ型の導電型の結晶系半導体基板とすることができる。例えば、単結晶シリコン基板、多結晶シリコン基板、ガリウム砒素基板（ＧａＡｓ）、インジウム燐基板（ＩｎＰ）等を適用することができる。 The n-type single crystal silicon substrate 18 is a power generation layer that receives carriers incident from the light receiving surface and generates carriers. In this embodiment, the n-type single crystal silicon substrate 18 is used. However, the present invention is not limited to this, and an n-type or p-type conductive crystal semiconductor substrate can be used. For example, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium arsenide substrate (GaAs), an indium phosphorus substrate (InP), or the like can be used.
　ｉ型非晶質シリコン層１６およびｎ型非晶質シリコン層１４は、ｎ型単結晶シリコン基板１８の受光面上に形成されるパッシベーション層である。ｉ型非晶質シリコン層１６及びｎ型非晶質シリコン層１４は、受光面に形成される非晶質系半導体層を構成する。ｉ型非晶質シリコン層１６は、真性な非晶質半導体膜からなる層である。ｎ型非晶質シリコン層１４は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる層である。例えば、ｎ型非晶質シリコン層１４は、ｎ型のドーパントの濃度を１×１０21／ｃｍ3以上とすることが好適である。 The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 are passivation layers formed on the light-receiving surface of the n-type single crystal silicon substrate 18. The i-type amorphous silicon layer 16 and the n-type amorphous silicon layer 14 constitute an amorphous semiconductor layer formed on the light receiving surface. The i-type amorphous silicon layer 16 is a layer made of an intrinsic amorphous semiconductor film. The n-type amorphous silicon layer 14 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. For example, the n-type amorphous silicon layer 14 preferably has an n-type dopant concentration of 1 × 10 21 / cm 3 or more.
　なお、本実施の形態において非晶質シリコン層は、微結晶半導体膜を含む。微結晶半導体膜は、非晶質半導体中に結晶粒が析出している膜である。結晶粒の平均粒径は、これに限定されるものではないが、１ｎｍ以上８０ｎｍ以下程度であると推定されている。 Note that in this embodiment mode, the amorphous silicon layer includes a microcrystalline semiconductor film. A microcrystalline semiconductor film is a film in which crystal grains are precipitated in an amorphous semiconductor. The average grain size of the crystal grains is not limited to this, but is estimated to be about 1 nm to 80 nm.
　反射防止層１２は、ｎ型非晶質シリコン層１４上に形成され、光電変換素子１０の受光面から入射される光の反射を低減させる。また、反射防止層１２は、ｎ型非晶質シリコン層１４の表面を保護する保護層としても機能する。反射防止層１２は、透明な材料で構成され、反射防止層１２によって覆われる層の屈折率との関係で光電変換素子１０の受光面から入射される光の反射を低減させる屈折率を有する材料及び膜厚とすることが好適である。反射防止層１２は、例えば、酸化アルミニウム、窒化アルミニウム、窒化ケイ素及び酸化ケイ素等を含んで構成される。 The antireflection layer 12 is formed on the n-type amorphous silicon layer 14 and reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10. The antireflection layer 12 also functions as a protective layer that protects the surface of the n-type amorphous silicon layer 14. The antireflection layer 12 is made of a transparent material and has a refractive index that reduces reflection of light incident from the light receiving surface of the photoelectric conversion element 10 in relation to the refractive index of the layer covered by the antireflection layer 12. And a film thickness is preferred. The antireflection layer 12 includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like.
　ｉ－ｎ積層部２１は、ｎ型単結晶シリコン基板１８の裏面上に形成され、ｉ型非晶質シリコン層２２と、ｎ型非晶質シリコン層２３と、を備える。ｉ－ｎ積層部２１は、後述するｎ側電極部２５において、光電変換素子１０の面内からより多くの電流が集電できるように配置することが好適である。ｉ－ｎ積層部２１は、例えば、複数のフィンガー部が平行に延びた櫛歯形状とすることが好適である。 The i-n stacked unit 21 is formed on the back surface of the n-type single crystal silicon substrate 18 and includes an i-type amorphous silicon layer 22 and an n-type amorphous silicon layer 23. It is preferable that the i-n stacked unit 21 be arranged so that a larger amount of current can be collected from the surface of the photoelectric conversion element 10 in the n-side electrode unit 25 described later. For example, the i-n stacked portion 21 preferably has a comb shape in which a plurality of finger portions extend in parallel.
　ｉ型非晶質シリコン層２２は、ｎ型単結晶シリコン基板１８の裏面上に形成されるパッシベーション層である。ｎ型非晶質シリコン層２３は、ｉ型非晶質シリコン層２２上に形成される。ｉ型非晶質シリコン層２２は、真性な非晶質半導体膜からなる層である。ｎ型非晶質シリコン層２３は、ｎ型の導電型のドーパントを含む非晶質半導体膜からなる層である。例えば、ｎ型非晶質シリコン層２３は、ｎ型のドーパントの濃度を１×１０21／ｃｍ3以上とすることが好適である。 The i-type amorphous silicon layer 22 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The n-type amorphous silicon layer 23 is formed on the i-type amorphous silicon layer 22. The i-type amorphous silicon layer 22 is a layer made of an intrinsic amorphous semiconductor film. The n-type amorphous silicon layer 23 is a layer made of an amorphous semiconductor film containing an n-type conductive dopant. For example, the n-type amorphous silicon layer 23 preferably has an n-type dopant concentration of 1 × 10 21 / cm 3 or more.
　絶縁層２４は、ｉ－ｎ積層部２１とｉ－ｐ積層部３１とを電気的に絶縁するために形成される。また、絶縁層２４は、ｎ型非晶質シリコン層２３上に形成される保護層としても機能する。絶縁層２４は、電気的な絶縁性を有する材料であればよいが、例えば、酸化アルミニウム、窒化アルミニウム、窒化ケイ素及び酸化ケイ素等を含んで構成することが好適である。なお、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３及び絶縁層２４は、裏面上に形成される第１の非晶質系半導体層を構成する。 The insulating layer 24 is formed to electrically insulate the i-n laminated portion 21 and the ip laminated portion 31. The insulating layer 24 also functions as a protective layer formed on the n-type amorphous silicon layer 23. The insulating layer 24 may be any material having electrical insulating properties, but preferably includes, for example, aluminum oxide, aluminum nitride, silicon nitride, silicon oxide, and the like. The i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23, and the insulating layer 24 constitute a first amorphous semiconductor layer formed on the back surface.
　ｎ側電極部２５は、光電変換素子１０において発電された電気を集電して取り出すために設けられる電極部材である。ｎ側電極部２５は、透明導電層２６と、金属層２７と、第１電極部２８と、第２電極部２９とを備える。 The n-side electrode portion 25 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10. The n-side electrode unit 25 includes a transparent conductive layer 26, a metal layer 27, a first electrode unit 28, and a second electrode unit 29.
　透明導電層２６は、ｎ型非晶質シリコン層２３上に形成される。透明導電層２６は、酸化インジウム（Ｉｎ2Ｏ3）、酸化亜鉛（ＺｎＯ）、酸化錫（ＳｎＯ2）、酸化チタン（ＴｉＯ2）及びインジウム錫酸化物（ＩＴＯ）等の金属酸化物のうちの少なくとも１つを含んで構成される。ここでは、透明導電層２６はインジウム錫酸化物（ＩＴＯ）を用いて形成されているものとして説明する。 The transparent conductive layer 26 is formed on the n-type amorphous silicon layer 23. The transparent conductive layer 26 is made of a metal oxide such as indium oxide (In 2 O 3 ), zinc oxide (ZnO), tin oxide (SnO 2 ), titanium oxide (TiO 2 ), and indium tin oxide (ITO). It is configured to include at least one. Here, the transparent conductive layer 26 is described as being formed using indium tin oxide (ITO).
　金属層２７は、透明導電層２６上に形成される。金属層２７は、例えば、銅（Ｃｕ）等の金属や合金を含んで構成されるシード層である。ここで、「シード層」とは、めっき成長の起点となる層のことをいう。 The metal layer 27 is formed on the transparent conductive layer 26. The metal layer 27 is a seed layer including a metal such as copper (Cu) or an alloy, for example. Here, the “seed layer” refers to a layer that is a starting point for plating growth.
　第１電極部２８は、めっき成長によって金属層２７上に形成される電極である。第１電極部２８は、例えば、銅（Ｃｕ）を含んで構成される。 The first electrode portion 28 is an electrode formed on the metal layer 27 by plating growth. The first electrode unit 28 includes, for example, copper (Cu).
　第２電極部２９は、めっき成長によって第１電極部２８上に形成される電極である。第２電極部２９は、例えば、錫（Ｓｎ）を含んで構成される。 The second electrode part 29 is an electrode formed on the first electrode part 28 by plating growth. For example, the second electrode unit 29 includes tin (Sn).
　ｉ－ｐ積層部３１は、ｎ型単結晶シリコン基板１８の裏面上にｉ－ｎ積層部２１と交互に配置されるように形成される。ｉ－ｐ積層部３１は、ｉ型非晶質シリコン層３２と、ｐ型非晶質シリコン層３３と、を備え、後述するｐ側電極部３５において、光電変換素子１０の面内からより多くの電流が集電できるように配置することが好適である。ｉ－ｐ積層部３１は、例えば、複数のフィンガー部が平行に延伸する櫛歯形状とすることが好適である。 The i-p stacked portions 31 are formed on the back surface of the n-type single crystal silicon substrate 18 so as to be alternately arranged with the i-n stacked portions 21. The ip laminated portion 31 includes an i-type amorphous silicon layer 32 and a p-type amorphous silicon layer 33, and more in the plane of the photoelectric conversion element 10 in the p-side electrode portion 35 described later. It is preferable to arrange so that the current can be collected. The ip laminated portion 31 is preferably, for example, in a comb-teeth shape in which a plurality of finger portions extend in parallel.
　ｉ型非晶質シリコン層３２は、ｎ型単結晶シリコン基板１８の裏面上に形成されるパッシベーション層である。ｐ型非晶質シリコン層３３は、ｉ型非晶質シリコン層３２上に形成される。ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３は、裏面に形成される第２非晶質系半導体層の一部を構成する。ｉ型非晶質シリコン層３２は、真性な非晶質半導体膜からなる層である。ｐ型非晶質シリコン層３３は、ｐ型の導電型のドーパントを含む非晶質半導体膜からなる層である。例えば、ｐ型非晶質シリコン層３３は、ｐ型のドーパントの濃度を１×１０21／ｃｍ3以上とすることが好適である。 The i-type amorphous silicon layer 32 is a passivation layer formed on the back surface of the n-type single crystal silicon substrate 18. The p-type amorphous silicon layer 33 is formed on the i-type amorphous silicon layer 32. The i-type amorphous silicon layer 32 and the p-type amorphous silicon layer 33 constitute a part of the second amorphous semiconductor layer formed on the back surface. The i-type amorphous silicon layer 32 is a layer made of an intrinsic amorphous semiconductor film. The p-type amorphous silicon layer 33 is a layer made of an amorphous semiconductor film containing a p-type conductive dopant. For example, the p-type amorphous silicon layer 33 preferably has a p-type dopant concentration of 1 × 10 21 / cm 3 or more.
　ｐ側電極部３５は、光電変換素子１０において発電された電気を集電して取り出すために設けられる電極部材である。ｐ側電極部３５は、透明導電層３６と、金属層３７と、第１電極部３８と、第２電極部３９とを備える。 The p-side electrode portion 35 is an electrode member provided for collecting and taking out the electricity generated in the photoelectric conversion element 10. The p-side electrode part 35 includes a transparent conductive layer 36, a metal layer 37, a first electrode part 38, and a second electrode part 39.
　透明導電層３６は、ｐ型非晶質シリコン層３３上に形成される。ここで、透明導電層３６の材料等は、透明導電層２６と同じであるため、詳細な説明は省略する。 The transparent conductive layer 36 is formed on the p-type amorphous silicon layer 33. Here, since the material and the like of the transparent conductive layer 36 are the same as those of the transparent conductive layer 26, detailed description thereof is omitted.
　金属層３７は、透明導電層３６上に形成される。ここで、金属層３７の材料等は、金属層２７と同じであるため、詳細な説明は省略する。 The metal layer 37 is formed on the transparent conductive layer 36. Here, since the material and the like of the metal layer 37 are the same as those of the metal layer 27, detailed description thereof is omitted.
　第１電極部３８は、めっき成長によって金属層３７上に形成される。ここで、第１電極部３８の材料等は、第１電極部２８と同じであるため、詳細な説明は省略する。 The first electrode portion 38 is formed on the metal layer 37 by plating growth. Here, since the material and the like of the first electrode portion 38 are the same as those of the first electrode portion 28, detailed description thereof is omitted.
　第２電極部３９は、めっき成長によって第１電極部３８上に形成される。ここで、第２電極部３９の材料等は、第２電極部２９と同じであるため、詳細な説明は省略する。 The second electrode part 39 is formed on the first electrode part 38 by plating growth. Here, since the material and the like of the second electrode portion 39 are the same as those of the second electrode portion 29, detailed description thereof is omitted.
　次に、光電変換素子１０の製造方法の一例を説明する。図３は、光電変換素子１０の製造方法の手順を示すフローチャートである。なお、光電変換素子１０の製造方法は、各工程において示す製造方法に限定されない。各工程において、例えば、スパッタリング法、プラズマＣＶＤ法、スクリーン印刷法或いはめっき法等を適宜用いることができる。 Next, an example of a method for manufacturing the photoelectric conversion element 10 will be described. FIG. 3 is a flowchart showing a procedure of a method for manufacturing the photoelectric conversion element 10. In addition, the manufacturing method of the photoelectric conversion element 10 is not limited to the manufacturing method shown in each process. In each step, for example, a sputtering method, a plasma CVD method, a screen printing method, a plating method, or the like can be used as appropriate.
　まず、ｎ型単結晶シリコン基板１８を用意し、ｎ型単結晶シリコン基板１８の裏面側平面図である図４に示されるように、ｎ型単結晶シリコン基板１８の裏面上において、四隅にそれぞれ十字マークの溝を形成する（Ｓ１）。当該十字マークは、第１アライメントマーク４１ａ～４１ｄとしてレーザーマーキング装置によって形成される。なお、ｎ型単結晶シリコン基板１８の一方側端部に形成される第１アライメントマーク４１ａ，４１ｂと、ｎ型単結晶シリコン基板１８の他方側端部に形成される第１アライメントマーク４１ｃ，４１ｄとは、図４に示されるように、Ｂ－Ｂ線を中心として、非対称の位置に形成されている。 First, an n-type single crystal silicon substrate 18 is prepared. As shown in FIG. 4 which is a plan view of the back surface side of the n-type single crystal silicon substrate 18, four corners are formed on the back surface of the n-type single crystal silicon substrate 18, respectively. A cross mark groove is formed (S1). The cross marks are formed by the laser marking device as the first alignment marks 41a to 41d. The first alignment marks 41a and 41b formed at one end of the n-type single crystal silicon substrate 18 and the first alignment marks 41c and 41d formed at the other end of the n-type single crystal silicon substrate 18. As shown in FIG. 4, it is formed at an asymmetrical position about the line BB.
　そして、ｎ型単結晶シリコン基板１８の受光面及び裏面の洗浄を行う（Ｓ２）。ここで、ｎ型単結晶シリコン基板１８の洗浄は、例えば、ＨＦ水溶液等を用いて行うことができる。 Then, the light receiving surface and the back surface of the n-type single crystal silicon substrate 18 are cleaned (S2). Here, the n-type single crystal silicon substrate 18 can be cleaned using, for example, an HF aqueous solution.
　次に、ｎ型単結晶シリコン基板１８の受光面上にテクスチャ構造を形成する（Ｓ３）。ここで、テクスチャ構造の形成には、水酸化カリウム水溶液（ＫＯＨ水溶液）等のアルカリ性の異方性エッチング液を用いることで、ｎ型単結晶シリコン基板１８の受光面上にピラミッド状の凹凸形状を形成することができる。 Next, a texture structure is formed on the light receiving surface of the n-type single crystal silicon substrate 18 (S3). Here, for the formation of the texture structure, a pyramidal uneven shape is formed on the light-receiving surface of the n-type single crystal silicon substrate 18 by using an alkaline anisotropic etching solution such as a potassium hydroxide aqueous solution (KOH aqueous solution). Can be formed.
　続いて、ｎ型単結晶シリコン基板１８の受光面上に、ｉ型非晶質シリコン層１６とｎ型非晶質シリコン層１４を形成するとともに、ｎ型単結晶シリコン基板１８の裏面上に、ｉ型非晶質シリコン層２２ａとｎ型非晶質シリコン層２３ａを形成する（Ｓ４）。ここで、ｉ型非晶質シリコン層１６、ｎ型非晶質シリコン層１４、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａのそれぞれは、例えば、プラズマＣＶＤ法等により形成することができる。 Subsequently, an i-type amorphous silicon layer 16 and an n-type amorphous silicon layer 14 are formed on the light-receiving surface of the n-type single crystal silicon substrate 18, and on the back surface of the n-type single crystal silicon substrate 18, An i-type amorphous silicon layer 22a and an n-type amorphous silicon layer 23a are formed (S4). Here, each of the i-type amorphous silicon layer 16, the n-type amorphous silicon layer 14, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a is formed by, for example, a plasma CVD method or the like. can do.
　その後、ｎ型非晶質シリコン層２３ａ上に絶縁層２４ａを形成するとともに、ｎ型非晶質シリコン層１４上に反射防止層１２を形成する（Ｓ５）。絶縁層２４ａ及び反射防止層１２は、例えば、スパッタリング法やＣＶＤ法等の薄膜形成法等により形成することができる。Ｓ５の工程後は、図５に示されるような断面積層構造となる。なお、ｎ型単結晶シリコン基板１８の裏面上には、ｉ型非晶質シリコン層２２ａ、ｎ型非晶質シリコン層２３ａ及び絶縁層２４ａが形成されるが、これらの層は、例えば、０．５ｎｍ～５０ｎｍ程度の薄膜である。したがって、このような薄膜によって覆われている状態であっても、位置合わせを行う際に、上方から第１アライメントマーク４１ａ～４１ｄを視認することができる。 Thereafter, the insulating layer 24a is formed on the n-type amorphous silicon layer 23a, and the antireflection layer 12 is formed on the n-type amorphous silicon layer 14 (S5). The insulating layer 24a and the antireflection layer 12 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method. After the step S5, a cross-sectional laminated structure as shown in FIG. 5 is obtained. Note that an i-type amorphous silicon layer 22a, an n-type amorphous silicon layer 23a, and an insulating layer 24a are formed on the back surface of the n-type single crystal silicon substrate 18. These layers are, for example, 0 A thin film of about 5 nm to 50 nm. Therefore, even when the film is covered with such a thin film, the first alignment marks 41a to 41d can be visually recognized from above when performing alignment.
　次に、図６に示されるマスク４５を用意して、位置決め部４７ａ～４７ｄと第１アライメントマーク４１ａ～４１ｄとの位置合わせを行って、マスク４５をセットする（Ｓ６）。ここで、マスク４５は、ｉ型非晶質シリコン層２２ａ、ｎ型非晶質シリコン層２３ａ及び絶縁層２４ａに所定のパターニングを形成するための開口領域であるパターン部４６と、第１アライメントマーク４１ａ～４１ｄに対して位置合わせを行うための開口領域である位置決め部４７ａ～４７ｄとを含むパターン形成部材である。ここで、位置決め部４７ａ～４７ｄは、第１アライメントマーク４１ａ～４１ｄに対して位置合わせを行う際に、それぞれ第１アライメントマーク４１ａ～４１ｄと重ならない位置に形成されていることが好適である。 Next, the mask 45 shown in FIG. 6 is prepared, the positioning portions 47a to 47d and the first alignment marks 41a to 41d are aligned, and the mask 45 is set (S6). Here, the mask 45 includes a pattern portion 46 that is an opening region for forming a predetermined pattern in the i-type amorphous silicon layer 22a, the n-type amorphous silicon layer 23a, and the insulating layer 24a, and a first alignment mark. This is a pattern forming member including positioning portions 47a to 47d which are opening regions for positioning with respect to 41a to 41d. Here, it is preferable that the positioning portions 47a to 47d are formed at positions that do not overlap the first alignment marks 41a to 41d, respectively, when alignment is performed with respect to the first alignment marks 41a to 41d.
　本実施の形態では、位置決め部４７ａ～４７ｄは、ｎ型単結晶シリコン基板１８の裏面に形成された第１アライメントマーク４１ａ～４１ｄの十字マークで分割される領域のうち、対角に位置する領域に矩形パターンを形成する。具体的には、第１アライメントマーク４１ａ～４１ｄの十字マークのそれぞれに対して、位置決め部４７ａ～４７ｄの矩形パターンのそれぞれができるだけ均等に離れて位置するようにマスク４５を配置する。 In the present embodiment, positioning portions 47a to 47d are regions located diagonally among regions divided by cross marks of first alignment marks 41a to 41d formed on the back surface of n-type single crystal silicon substrate 18. A rectangular pattern is formed. Specifically, the mask 45 is arranged so that the rectangular patterns of the positioning portions 47a to 47d are located as far apart as possible from the cross marks of the first alignment marks 41a to 41d.
　そして、スクリーン印刷法によってエッチングペーストを塗布し、絶縁層２４ａ、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａをエッチングすることにより、絶縁層２４ａ、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａの一部分を除去する（Ｓ７）。つまり、絶縁層２４ａ、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａのうち、後工程でｎ型単結晶シリコン基板１８にｉ－ｐ積層部３１を形成させるための領域の上に位置する部分を除去する。これにより、絶縁層２４ａ、ｉ型非晶質シリコン層２２ａ及びｎ型非晶質シリコン層２３ａがパターンニングされて、図７に示されるように絶縁層２４ｂ、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３が形成された断面積層構造となる。また、位置決め部４７ａを通過して塗布されるエッチングペーストが図８（図４の裏面側平面図の点線Ｃの領域の拡大図に対応する図）に示されるように、第２アライメントマーク４２ａを形成する。ここで、第２アライメントマーク４２ａは、第１アライメントマーク４１ａと重ならないような位置に形成されている。なお、図８には示していないが、位置決め部４７ｂ～４７ｄを通過して塗布されるエッチングペーストが第２アライメントマーク４２ｂ～４２ｄを形成する。そして、第２アライメントマーク４２ｂ～４２ｄについても、第１アライメントマーク４１ｂ～４１ｄとそれぞれ重ならないような位置に形成される。 Then, an etching paste is applied by a screen printing method, and the insulating layer 24a, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are etched, whereby the insulating layer 24a, the i-type amorphous silicon layer are etched. Part of 22a and n-type amorphous silicon layer 23a is removed (S7). That is, of the insulating layer 24a, the i-type amorphous silicon layer 22a, and the n-type amorphous silicon layer 23a, a region for forming the ip stacked portion 31 on the n-type single crystal silicon substrate 18 in a later step. Remove the top part. As a result, the insulating layer 24a, the i-type amorphous silicon layer 22a and the n-type amorphous silicon layer 23a are patterned, and as shown in FIG. 7, the insulating layer 24b, the i-type amorphous silicon layer 22, A cross-sectional laminated structure in which the n-type amorphous silicon layer 23 is formed is obtained. Further, as shown in FIG. 8 (a diagram corresponding to an enlarged view of a region indicated by a dotted line C in the plan view on the back surface side of FIG. 4), the second alignment mark 42a is applied to the etching paste applied through the positioning portion 47a. Form. Here, the second alignment mark 42a is formed at a position so as not to overlap the first alignment mark 41a. Although not shown in FIG. 8, the etching paste applied through the positioning portions 47b to 47d forms the second alignment marks 42b to 42d. The second alignment marks 42b to 42d are also formed at positions that do not overlap with the first alignment marks 41b to 41d, respectively.
　続いて、図９に示されるように、絶縁層２４ｂ、ｉ型非晶質シリコン層２２、ｎ型非晶質シリコン層２３及び露出されたｎ型単結晶シリコン基板１８の裏面を覆うように、ｉ型非晶質シリコン層３２ａとｐ型非晶質シリコン層３３ａを形成する（Ｓ８）。ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａは、例えば、プラズマＣＶＤ法等により形成することができる。 Subsequently, as shown in FIG. 9, the insulating layer 24 b, the i-type amorphous silicon layer 22, the n-type amorphous silicon layer 23 and the exposed back surface of the n-type single crystal silicon substrate 18 are covered. An i-type amorphous silicon layer 32a and a p-type amorphous silicon layer 33a are formed (S8). The i-type amorphous silicon layer 32a and the p-type amorphous silicon layer 33a can be formed by, for example, a plasma CVD method or the like.
　次に、図１０に示されるマスク４８を用意して、位置決め部５０ａ～５０ｄと第１アライメントマーク４１ａ～４１ｄ又は第２アライメントマーク４２ａ～４２ｄとの位置合わせを行って、マスク４８をセットする（Ｓ９）。ここで、マスク４８は、ｉ型非晶質シリコン層３２ａ、ｐ型非晶質シリコン層３３ａ及び絶縁層２４ｂに所定のパターニングを形成するための開口領域であるパターン部４９と、第１アライメントマーク４１ａ～４１ｄ又は第２アライメントマーク４２ａ～４２ｄに対して位置合わせを行うための開口領域である位置決め部５０ａ～５０ｄとを含むパターン形成部材である。ここで、位置決め部５０ａ～５０ｄは、第１アライメントマーク４１ａ～４１ｄ又は第２アライメントマーク４２ａ～４２ｄに対して位置合わせを行う際に、第１アライメントマーク４１ａ～４１ｄ及び第２アライメントマーク４２ａ～４２ｄと重ならないような位置に形成されていることが好適である。本実施の形態では、位置決め部５０ａ～５０ｄは、図１０に示すように、ｎ型単結晶シリコン基板１８の裏面に形成された第１アライメントマーク４１ａ～４１ｄの十字マークで分割される領域のうち対角に位置する領域に矩形パターンを形成する。具体的には、第１アライメントマーク４１ａ～４１ｄの十字マークのそれぞれに対して、位置決め部５０ａ～５０ｄの矩形パターンのそれぞれができるだけ均等に離れて位置するようにマスク４８を配置する。 Next, the mask 48 shown in FIG. 10 is prepared, the positioning portions 50a to 50d and the first alignment marks 41a to 41d or the second alignment marks 42a to 42d are aligned, and the mask 48 is set ( S9). Here, the mask 48 includes a pattern portion 49 that is an opening region for forming a predetermined pattern in the i-type amorphous silicon layer 32a, the p-type amorphous silicon layer 33a, and the insulating layer 24b, and a first alignment mark. This is a pattern forming member including positioning portions 50a to 50d which are opening regions for positioning with respect to 41a to 41d or the second alignment marks 42a to 42d. Here, the positioning portions 50a to 50d perform the first alignment marks 41a to 41d and the second alignment marks 42a to 42d when aligning the first alignment marks 41a to 41d or the second alignment marks 42a to 42d. It is preferable that it is formed at a position where it does not overlap with the other. In the present embodiment, as shown in FIG. 10, positioning portions 50a to 50d are formed of regions divided by cross marks of first alignment marks 41a to 41d formed on the back surface of n-type single crystal silicon substrate 18. A rectangular pattern is formed in a region located diagonally. Specifically, the mask 48 is arranged so that the rectangular patterns of the positioning portions 50a to 50d are located as far apart as possible from the cross marks of the first alignment marks 41a to 41d.
　次に、スクリーン印刷法によってエッチングペーストを塗布し、絶縁層２４ｂ、ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａをエッチングすることにより、絶縁層２４ｂ、ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａの一部分を除去する（Ｓ１０）。これにより、絶縁層２４ｂ、ｉ型非晶質シリコン層３２ａ及びｐ型非晶質シリコン層３３ａがパターンニングされて、図１１に示されるように絶縁層２４、ｉ型非晶質シリコン層３２及びｐ型非晶質シリコン層３３が形成された断面積層構造となる。また、位置決め部５０ａを通過して塗布されるエッチングペーストが図１２（図４の裏面側平面図の点線Ｃの領域の拡大図に対応した図）に示されるように、第３アライメントマーク４３ａを形成する。ここで、第３アライメントマーク４３ａは、第１アライメントマーク４１ａ及び第２アライメントマーク４２ａと重ならないような位置に形成されている。なお、図１２には示していないが、位置決め部５０ｂ～５０ｄを通過して塗布されるエッチングペーストが第３アライメントマーク４３ｂ～４３ｄを形成する。そして、第３アライメントマーク４３ｂ～４３ｄについても、第１アライメントマーク４１ｂ～４１ｄ及び第２アライメントマーク４２ｂ～４２ｄとそれぞれ重ならないような位置に形成されている。 Next, an etching paste is applied by a screen printing method, and the insulating layer 24b, the i-type amorphous silicon layer 32a, and the p-type amorphous silicon layer 33a are etched to thereby form the insulating layer 24b, the i-type amorphous silicon. A part of the layer 32a and the p-type amorphous silicon layer 33a is removed (S10). As a result, the insulating layer 24b, the i-type amorphous silicon layer 32a, and the p-type amorphous silicon layer 33a are patterned, and as shown in FIG. 11, the insulating layer 24, the i-type amorphous silicon layer 32, and A cross-sectional laminated structure in which the p-type amorphous silicon layer 33 is formed. Further, as shown in FIG. 12 (a diagram corresponding to an enlarged view of a region indicated by a dotted line C in the rear surface side plan view of FIG. 4), the third alignment mark 43a is applied to the etching paste applied through the positioning portion 50a. Form. Here, the third alignment mark 43a is formed at a position so as not to overlap the first alignment mark 41a and the second alignment mark 42a. Although not shown in FIG. 12, the etching paste applied through the positioning portions 50b to 50d forms the third alignment marks 43b to 43d. The third alignment marks 43b to 43d are also formed at positions that do not overlap the first alignment marks 41b to 41d and the second alignment marks 42b to 42d, respectively.
　そして、透明導電層２６ａ、金属層２７ａを形成する（Ｓ１１）。具体的には、プラズマＣＶＤ法やスパッタリング法等の薄膜形成法により形成する。 Then, the transparent conductive layer 26a and the metal layer 27a are formed (S11). Specifically, it is formed by a thin film forming method such as a plasma CVD method or a sputtering method.
　続いて、図１３に示されるように、透明導電層２６ａ及び金属層２７ａのうち、絶縁層２４の上に位置する部分を分断することにより、透明導電層２６，３６及び金属層２７，３７を形成する（Ｓ１２）。ここで、透明導電層２６ａ及び金属層２７ａは、例えば、リソグラフィー法等によって分断する。 Subsequently, as shown in FIG. 13, the transparent conductive layers 26 and 36 and the metal layers 27 and 37 are separated by dividing a portion of the transparent conductive layer 26 a and the metal layer 27 a located on the insulating layer 24. Form (S12). Here, the transparent conductive layer 26a and the metal layer 27a are divided by, for example, a lithography method.
　その後、図１４に示されるように、電解めっきにより、金属層２７の上に第１電極部２８と第２電極部２９を順次形成し、金属層３７の上に第１電極部３８と第２電極部３９を形成する（Ｓ１３）。これにより、ｎ側電極部２５とｐ側電極部３５とが形成がされる。 After that, as shown in FIG. 14, the first electrode portion 28 and the second electrode portion 29 are sequentially formed on the metal layer 27 by electrolytic plating, and the first electrode portion 38 and the second electrode portion 29 are formed on the metal layer 37. The electrode part 39 is formed (S13). Thereby, the n-side electrode part 25 and the p-side electrode part 35 are formed.
　一般的に、マスク４５，４８を用いて第１アライメントマーク４１ａ～４１ｄに対して位置合わせを行い、エッチングペーストを塗布することによってパターンニング処理を行うと同時に、第１の非晶質系半導体部に形成される第２アライメントマーク４２ａ～４２ｄと、第２の非晶質系半導体部に形成される第３アライメントマーク４３ａ～４３ｄとをそれぞれ重ねる位置に形成すると、積層方向に貫通する孔が形成される。このため、当該各アライメントマークが形成される領域において、ｎ型単結晶シリコン基板１８が露出する状態となる。したがって、ｎ型単結晶シリコン基板１８のうち露出した部分において、パッシベーション層が存在しなくなるため、キャリアの再結合が発生する可能性がある。しかしながら、上記光電変換素子１０の製造方法によれば、少なくとも第２アライメントマーク４２ａ～４２ｄと第３アライメントマーク４３ａ～４３ｄとが重ならない位置に形成されている。これにより、ｎ型単結晶シリコン基板１８は、ｉ型非晶質シリコン層２２又はｉ型非晶質シリコン層３２のいずれかによって覆われているため、ｉ型非晶質シリコン層２２又はｉ型非晶質シリコン層３２によってパッシベーションされることとなる。したがって、ｎ型単結晶シリコン基板１８において生成されたキャリアの再結合が抑制され、光電変換素子１０の発電特性を向上させることができる。 In general, alignment is performed on the first alignment marks 41a to 41d using masks 45 and 48, and patterning processing is performed by applying an etching paste. When the second alignment marks 42a to 42d formed on the first and third alignment marks 43a to 43d formed on the second amorphous semiconductor portion are formed at the positions where they overlap each other, a hole penetrating in the stacking direction is formed. Is done. Therefore, the n-type single crystal silicon substrate 18 is exposed in the region where the alignment marks are formed. Therefore, since the passivation layer does not exist in the exposed portion of the n-type single crystal silicon substrate 18, carrier recombination may occur. However, according to the method for manufacturing the photoelectric conversion element 10, at least the second alignment marks 42a to 42d and the third alignment marks 43a to 43d are formed at positions that do not overlap. Thereby, since the n-type single crystal silicon substrate 18 is covered with either the i-type amorphous silicon layer 22 or the i-type amorphous silicon layer 32, the i-type amorphous silicon layer 22 or the i-type amorphous silicon layer 22 is covered. The amorphous silicon layer 32 is passivated. Therefore, recombination of carriers generated in the n-type single crystal silicon substrate 18 is suppressed, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
　上記光電変換素子１０の製造方法によれば、第１アライメントマーク４１ａ～４１ｄは、十字マークの形状に形成されているため、十字マークの交差している箇所を位置合わせの対象とすることができる。すなわち、点を位置合わせの対象とすることができるため、例えば、丸印等のように点を位置合わせの対象としづらい形状と比べて、好適に位置合わせを行うことができる。したがって、第１アライメントマーク４１ａ～４１ｄに対して、位置決め部４７ａ～４７ｄ及び位置決め部５０ａ～５０ｄの位置合わせを好適に行うことができる。 According to the method for manufacturing the photoelectric conversion element 10, the first alignment marks 41a to 41d are formed in the shape of a cross mark, and therefore, the position where the cross mark intersects can be set as an alignment target. . That is, since a point can be set as an object of alignment, for example, it is possible to perform alignment appropriately as compared with a shape that makes it difficult to set a point as an object of alignment such as a circle. Accordingly, the positioning of the positioning portions 47a to 47d and the positioning portions 50a to 50d can be suitably performed with respect to the first alignment marks 41a to 41d.
　上記光電変換素子１０の製造方法によれば、一方側端部に設けられる第１アライメントマーク４１ａ，４１ｂ、第２アライメントマーク４２ａ，４２ｂ及び第３アライメントマーク４３ａ，４３ｂと、他方側端部に設けられる第１アライメントマーク４１ｃ，４１ｄ、第２アライメントマーク４２ｃ，４２ｄ及び第３アライメントマーク４３ｃ，４３ｄとは、Ｂ－Ｂ線を中心として、非対称の位置に設けられている。これにより、一方側端部と他方側端部の方向の判定を容易に行うことができる。 According to the manufacturing method of the photoelectric conversion element 10, the first alignment marks 41a and 41b, the second alignment marks 42a and 42b, and the third alignment marks 43a and 43b provided at one end and the other end are provided. The first alignment marks 41c and 41d, the second alignment marks 42c and 42d, and the third alignment marks 43c and 43d are provided at asymmetric positions around the line BB. Thereby, determination of the direction of one side edge part and the other side edge part can be performed easily.
　なお、上記光電変換素子１０の製造方法では、一方側端部に設けられる第１アライメントマーク４１ａ，４１ｂ、第２アライメントマーク４２ａ，４２ｂ及び第３アライメントマーク４３ａ，４３ｂと、他方側端部に設けられる第１アライメントマーク４１ｃ，４１ｄ、第２アライメントマーク４２ｃ，４２ｄ及び第３アライメントマーク４３ｃ，４３ｄとは、Ｂ－Ｂ線を中心として、位置関係が非対称であるとして説明したが、形状が非対称であってもよく、また、位置、形状等の組み合わせを非対称としてもよい。例えば、図１５に示されるように、第１アライメントマーク４１ａ，４１ｂの形状を十字マークとし、第１アライメントマーク４１ｃ，４１ｄの形状を×印（×マーク）としてもよい。これにより、一方側端部と他方側端部の方向の判定を容易に行うことができる。 In the method of manufacturing the photoelectric conversion element 10, the first alignment marks 41a and 41b, the second alignment marks 42a and 42b, the third alignment marks 43a and 43b provided at one end, and the other end are provided. The first alignment marks 41c and 41d, the second alignment marks 42c and 42d, and the third alignment marks 43c and 43d have been described as having an asymmetric positional relationship around the BB line. There may be a combination of position, shape, and the like. For example, as shown in FIG. 15, the shape of the first alignment marks 41a and 41b may be a cross mark, and the shape of the first alignment marks 41c and 41d may be an x mark. Thereby, determination of the direction of one side edge part and the other side edge part can be performed easily.
　上記光電変換素子１０の製造方法では、第２アライメントマーク４２ａ～４２ｄ及び第３アライメントマーク４３ａ～４３ｄは、それぞれ四隅に設けられるものとして説明したが、図１６に示されるように、第２アライメントマーク４２ａ～４２ｄについては第２アライメントマーク４２ｂ，４２ｃのみを形成し、第３アライメントマーク４３ａ～４３ｄについては第３アライメントマーク４３ａ，４３ｄのみを形成するものとしてもよい。これにより、第２アライメントマーク４２ｂ，４２ｃと第３アライメントマーク４３ａ，４３ｄとが異なる対角線上に配置されることとなる。すなわち、第２アライメントマーク４２ｂ，４２ｃと第３アライメントマーク４３ａ，４３ｄとが重ならない位置に形成されるため、ｎ型単結晶シリコン基板１８は、ｉ型非晶質シリコン層２２又はｉ型非晶質シリコン層３２のいずれか一方によってパッシベーションされることとなる。したがって、ｎ型単結晶シリコン基板１８において生成されたキャリアの再結合が抑制され、光電変換素子１０の発電特性を向上させることができる。 In the method for manufacturing the photoelectric conversion element 10, the second alignment marks 42a to 42d and the third alignment marks 43a to 43d are described as being provided at the four corners, respectively. However, as shown in FIG. Only the second alignment marks 42b and 42c may be formed for 42a to 42d, and only the third alignment marks 43a and 43d may be formed for the third alignment marks 43a to 43d. Thereby, the second alignment marks 42b and 42c and the third alignment marks 43a and 43d are arranged on different diagonal lines. That is, since the second alignment marks 42b and 42c and the third alignment marks 43a and 43d are formed at positions where they do not overlap, the n-type single crystal silicon substrate 18 has the i-type amorphous silicon layer 22 or the i-type amorphous silicon. Passivation is performed by either one of the quality silicon layers 32. Therefore, recombination of carriers generated in the n-type single crystal silicon substrate 18 is suppressed, and the power generation characteristics of the photoelectric conversion element 10 can be improved.
　上記光電変換素子１０の製造方法では、エッチング処理を行うためのパターン形成部材としてマスクを用い、エッチング処理剤としてエッチングペーストを用いて行うものとして説明したが、パターン形成部材としてレジストを用い、エッチング処理剤としてエッチング液を用いて行うものとしてもよい。 In the manufacturing method of the photoelectric conversion element 10 described above, a mask is used as a pattern forming member for performing an etching process and an etching paste is used as an etching treatment agent. However, an etching process is performed using a resist as a pattern forming member. It is good also as what performs using an etching liquid as an agent.
　１０　光電変換素子、１２　反射防止層、１４　ｎ型非晶質シリコン層、１６　ｉ型非晶質シリコン層、１８　ｎ型単結晶シリコン基板、２１　ｉ－ｎ積層部、２２，２２ａ　ｉ型非晶質シリコン層、２３，２３ａ　ｎ型非晶質シリコン層、２４，２４ａ，２４ｂ　絶縁層、２５　ｎ側電極部、２６，２６ａ，３６　透明導電層、２７，２７ａ，３７　金属層、２８，３８　第１電極部、２９，３９　第２電極部、３１　ｉ－ｐ積層部、３２，３２ａ　ｉ型非晶質シリコン層、３３，３３ａ　ｐ型非晶質シリコン層、３５　ｐ側電極部、４１ａ，４１ｂ，４１ｃ，４１ｄ　第１アライメントマーク、４２ａ，４２ｂ，４２ｃ，４２ｄ　第２アライメントマーク、４３ａ，４３ｂ，４３ｃ，４３ｄ　第３アライメントマーク、４５，４８　マスク、４６，４９　パターン部、４７ａ，４７ｂ，４７ｃ，４７ｄ，５０ａ，５０ｂ，５０ｃ，５０ｄ　位置決め部。 10 photoelectric conversion element, 12 antireflection layer, 14 n-type amorphous silicon layer, 16 i-type amorphous silicon layer, 18 n-type single crystal silicon substrate, 21 in-stacked portion, 22, 22a i-type amorphous Silicon layer, 23, 23a n-type amorphous silicon layer, 24, 24a, 24b insulating layer, 25 n-side electrode part, 26, 26a, 36 transparent conductive layer, 27, 27a, 37 metal layer, 28, 38th 1 electrode part, 29, 39 2nd electrode part, 31 ip laminated part, 32, 32a i type amorphous silicon layer, 33, 33a p type amorphous silicon layer, 35 p side electrode part, 41a, 41b , 41c, 41d, first alignment mark, 42a, 42b, 42c, 42d, second alignment mark, 43a, 43b, 43c, 43d, third alignment mark, 45, 48 m Click, 46 and 49 the pattern portion, 47a, 47b, 47c, 47d, 50a, 50b, 50c, 50d positioning unit.

Claims (5)

  1. 　結晶系半導体基板上に第１アライメントマークを形成し、
    　前記第１アライメントマーク上を含んで前記結晶系半導体基板上に第１非晶質系半導体層を形成し、
    　前記第１アライメントマークに対して位置決めするための第１位置決め部を有する第１パターン形成部を準備し、該位置決めを行って前記第１非晶質系半導体層上に前記第１パターン形成部を設置し、前記第１位置決め部を用いて前記第１非晶質系半導体層に第２アライメントマークを形成し、
    　前記第２アライメントマーク上を含んで前記結晶系半導体基板上に第２非晶質系半導体層を形成し、
    　前記第２アライメントマークと重ならない位置に設けられ、前記第１アライメントマークまたは前記第２アライメントマークに対して位置決めするための第２位置決め部を有する第２パターン形成部を準備し、該位置決めを行って前記第２非晶質系半導体層上に前記第２パターン形成部を設置し、前記第２位置決め部を用いて前記第２非晶質系半導体層に第３アライメントマークを形成する光電変換素子の製造方法。     Forming a first alignment mark on the crystalline semiconductor substrate;
    Forming a first amorphous semiconductor layer on the crystalline semiconductor substrate including the first alignment mark;
    A first pattern forming portion having a first positioning portion for positioning with respect to the first alignment mark is prepared, and the first pattern forming portion is positioned on the first amorphous semiconductor layer by performing the positioning. And forming a second alignment mark on the first amorphous semiconductor layer using the first positioning portion,
    Forming a second amorphous semiconductor layer on the crystalline semiconductor substrate including the second alignment mark;
    A second pattern forming portion is provided which is provided at a position not overlapping with the second alignment mark and has a second positioning portion for positioning with respect to the first alignment mark or the second alignment mark, and performs the positioning. A photoelectric conversion element in which the second pattern forming unit is disposed on the second amorphous semiconductor layer, and a third alignment mark is formed on the second amorphous semiconductor layer using the second positioning unit. Manufacturing method.
  2. 　請求項１に記載の光電変換素子の製造方法において、
    　前記第１位置決め部及び前記第２位置決め部は、それぞれ前記第１パターン形成部及び前記第２パターン形成部に形成される開口部である光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of Claim 1,
    The method for manufacturing a photoelectric conversion element, wherein the first positioning portion and the second positioning portion are openings formed in the first pattern forming portion and the second pattern forming portion, respectively.
  3. 　請求項１または請求項２に記載の光電変換素子の製造方法において、
    　前記第２アライメントマークは、前記第１アライメントマークと重ならない位置に設けられる光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of Claim 1 or Claim 2,
    The method of manufacturing a photoelectric conversion element, wherein the second alignment mark is provided at a position not overlapping with the first alignment mark.
  4. 　請求項１から請求項３のいずれか１に記載の光電変換素子の製造方法において、
    　前記結晶系半導体基板は、第１導電型であり、
    　前記第１非晶質系半導体層は、
    　前記結晶系半導体基板の裏面上に形成されるｉ型の第１非晶質系半導体層と、
    　前記ｉ型の第１非晶質系半導体層上に形成される前記第１導電型の第１非晶質系半導体層と、
    　前記第１導電型の第１非晶質系半導体層上に形成される絶縁層と、
    　を有し、
    　前記第２非晶質系半導体層は、
    　前記結晶系半導体基板の裏面上に形成されるｉ型の第２非晶質系半導体層と、
    　前記ｉ型の第２非晶質系半導体層上に形成される前記第１導電型と逆導電型である第２導電型の第２非晶質系半導体層と、
    　を有する光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of any one of Claims 1-3,
    The crystalline semiconductor substrate is of a first conductivity type,
    The first amorphous semiconductor layer includes
    An i-type first amorphous semiconductor layer formed on the back surface of the crystalline semiconductor substrate;
    The first conductive type first amorphous semiconductor layer formed on the i type first amorphous semiconductor layer;
    An insulating layer formed on the first amorphous semiconductor layer of the first conductivity type;
    Have
    The second amorphous semiconductor layer includes
    An i-type second amorphous semiconductor layer formed on the back surface of the crystalline semiconductor substrate;
    A second conductivity type second amorphous semiconductor layer formed on the i type second amorphous semiconductor layer and having a conductivity type opposite to the first conductivity type;
    The manufacturing method of the photoelectric conversion element which has.
  5. 　請求項４に記載の光電変換素子の製造方法において、
    　前記絶縁層上の第１領域に第１電極部を形成し、前記第２導電型の第２非晶質系半導体層上の領域のうち、前記第１領域と異なる第２領域に第２電極部を形成する光電変換素子の製造方法。     In the manufacturing method of the photoelectric conversion element of Claim 4,
    A first electrode portion is formed in a first region on the insulating layer, and a second electrode is formed in a second region different from the first region among regions on the second conductive type second amorphous semiconductor layer. Manufacturing method of photoelectric conversion element which forms part.
PCT/JP2012/053808 2011-03-25 2012-02-17 Method for producing photoelectric conversion element WO2012132613A1 (en)

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