JP6817764B2 - Solar cell and manufacturing method of solar cell - Google Patents

Description

The present invention relates to a solar cell and a method for manufacturing the solar cell.

Conventionally, the most manufactured and sold solar cells are crystalline silicon solar cells. In crystalline silicon solar cells, metal electrodes are usually provided from the viewpoint of current extraction efficiency. However, when the metal electrode is provided on the light receiving surface of the crystalline silicon battery, it is difficult to obtain the power generation efficiency corresponding to the area of the light receiving surface because the light receiving on the light receiving surface is partially blocked by the opaque metal electrode.

In order to solve this problem, a back contact (back surface electrode) in which p-type and n-type semiconductor layers are formed on the back surface side opposite to the light receiving surface of the crystalline silicon substrate and electrodes are formed on them. Development of type solar cells is underway.
In the back contact type solar cell, an electrode is not formed on the light receiving surface side. Therefore, there is no shielding of sunlight by the electrodes, and high power generation efficiency due to high light receiving efficiency is realized.
However, in a back contact type solar cell, it is necessary to form p-type and n-type semiconductor layers on the back surface side, so how to form the solar cell becomes a problem.

Japanese Unexamined Patent Publication No. 2012-028718

In a typical back contact type solar cell, the laminated electrode layer and the semiconductor layer exist in a state of being separated by a groove. Here, the electrode layer and the semiconductor layer are laminated on the crystalline silicon substrate. Also, the grooves are usually formed by etching.
However, when the present inventors attempted to manufacture a back-contact type solar cell having the above groove according to a conventional method as described in Patent Document 1, for example, the electrode layers separated by the groove It has become clear that there is a problem that a leak path is likely to occur, or that the open circuit voltage of the solar cell is likely to decrease due to damage to the crystalline silicon substrate during solar cell manufacturing.

The present invention has been made in view of the above problems, and is a solar cell having excellent performance by suppressing a leak path between the divided electrode layers and the occurrence of damage on a crystalline silicon substrate, and the solar cell. It is an object of the present invention to provide a method for manufacturing a cell.

The present inventors are solar cells including a crystalline silicon substrate and a semiconductor region, in which the semiconductor region is on the first main surface of the crystalline silicon substrate and is separated into two regions by a separation groove. The electrode layer is on the upper surface side of the semiconductor layer when the semiconductor region includes the semiconductor layer and the electrode layer and the direction from the first main surface to the semiconductor region is upward. In a solar cell, the shortest distance Wt between the electrode layer in one semiconductor region and the electrode layer in the other semiconductor region facing each other across the separation groove is set to the semiconductor layer in one semiconductor region and the semiconductor in the other semiconductor region. We have found that the above problems can be solved by setting the shortest distance to the layer, Wn, to 1.2 times or more and 10 times or less, and have completed the present invention.

That is, the present invention
(I) A solar cell including a crystalline silicon substrate and a semiconductor region.
The semiconductor region is on the first main surface of the crystalline silicon substrate and is electrically isolated by being separated into two regions by a separation groove.
The semiconductor region includes a semiconductor layer and an electrode layer, and includes.
When the direction from the first main surface to the semiconductor region is upward, the electrode layer is on the upper surface side of the semiconductor layer.
The shortest distance Wt between the electrode layer in one semiconductor region and the electrode layer in the other semiconductor region facing each other across the separation groove is the shortest distance between the semiconductor layer in one semiconductor region and the semiconductor layer in the other semiconductor region. The method for manufacturing a solar cell, which is 1.2 times or more and 10 times or less of Wn, and the solar cell according to (ii) and (i).
A groove is formed by etching the electrode layer and the semiconductor layer from the opening of the etching mask on the precursor laminate including the crystalline silicon substrate, the semiconductor region including the semiconductor layer and the electrode layer, and the etching mask which is the outermost layer. Including dividing the semiconductor region by
A method for manufacturing a solar cell, in which an electrode layer is laminated on the upper surface side of a semiconductor layer and an etching mask is laminated on the electrode layer.
I will provide a.

According to the present invention, it is possible to provide a solar cell having excellent performance and a method for manufacturing the solar cell, in which a leak path between the divided electrode layers and the occurrence of damage in a crystalline silicon substrate are suppressed. be able to.

It is a figure which shows typically the cross section of the laminated body formed in the process of manufacturing a back contact type solar cell by a conventional method. It is a figure which shows typically the cross section of the laminated body formed in the process of manufacturing a back contact type solar cell by a conventional method. It is a figure which shows typically the cross section of the back contact type solar cell formed by the conventional method. It is a figure which shows typically a part of the cross section of the back contact type solar cell formed by using the etching mask with the narrow opening width. It is a figure which shows typically a part of the cross section of the back contact type solar cell formed by using the etching mask with a wide opening. It is a figure which shows typically the cross section of a preferable example of the solar cell which concerns on this invention. It is a figure which shows typically the cross section of the precursor laminated body before etching for forming a separation groove. It is a figure which shows typically the cross section of the solar cell which concerns on this invention which separated groove was formed by performing etching with an etching mask.

≪Solar cell≫
As shown in FIG. 6, the solar cell is a solar cell including a crystalline silicon substrate 1 and a semiconductor region 4.
The semiconductor region 4 is located on the first main surface 1a of the crystalline silicon substrate 1 and is electrically isolated by being separated into two regions by a separation groove 9.
The semiconductor region 4 includes a semiconductor layer 5 and an electrode layer 7.
The electrode layer 7 is on the upper surface side of the semiconductor layer 5 when the direction from the first main surface 1a to the semiconductor region 4 is upward.
The shortest distance Wt between the electrode layer 7a of one semiconductor region 4a facing each other across the separation groove 9 and the electrode layer 7b of the other semiconductor region 4b is the semiconductor layer 5 of one semiconductor region 4a and the other semiconductor region. It is 1.2 times or more and 10 times or less the shortest distance Wn with the semiconductor layer 5 of 4b.
The solar cell includes a configuration other than the configuration described above, if necessary, with a configuration other than the above configuration.

First, a typical back-contact type solar cell manufacturing method and the problems clarified by the present inventors regarding the manufacturing method will be described below with reference to FIGS. 1 to 5.

1 to 3 are diagrams schematically showing a cross section of a laminate containing a crystalline silicon substrate at a predetermined stage in a method for manufacturing a back contact type solar cell, perpendicular to the plane direction of the laminate. is there.
FIG. 1 will be described. First, the intrinsic semiconductor layer 2 and the light receiving surface side protective layer 3 are formed on the light receiving surface side (second main surface 1b side) of the crystalline silicon substrate 1. Next, the intrinsic semiconductor layer 6b, the first conductive semiconductor layer 6a, and the insulating layer 8 are laminated in this order on the back surface side (first main surface 1a side). Subsequently, a part of the insulating layer 8 and the first conductive semiconductor layer 6a and the intrinsic semiconductor layer 6b on the back surface side are removed by etching to expose a part of the first main surface 1a of the crystalline silicon substrate 1.

FIG. 2 will be described. In the laminate shown in FIG. 1, the intrinsic semiconductor layer 5b and the second conductive semiconductor layer 5a are formed on substantially the entire surface of the first main surface 1a side including the first conductive semiconductor layer 6a and the insulating layer 8. Next, a part of the second conductive semiconductor layer 5a, the intrinsic semiconductor layer 5b, and the insulating layer 8 is removed by etching to expose the first conductive semiconductor layer 6a.

FIG. 3 will be described. In the laminate shown in FIG. 2, an electrode layer 7 is formed on the first conductive semiconductor layer 6a and the second conductive semiconductor layer 5a, and then the electrode layer 7 overlapping the insulating film 8 is electrodepositioned by a photolithography method. It is divided into a layer 7a and an electrode layer 7b. By forming the second electrode 10a and the second electrode 10b on the divided electrode layers 7a and 7b, respectively, a back contact type solar cell including the structure shown in FIG. 3 is manufactured.

However, as described above, in the back contact type solar cell manufactured by the conventional method as described in Patent Document 1, a leak path between the electrode layers divided by the groove is likely to occur, or when the solar cell is manufactured. There is a problem that the open circuit voltage of the solar cell tends to decrease due to the damage of the crystalline silicon substrate.
The present inventors have speculated that these problems are caused by the causes described below. The causes of these problems will be described with reference to FIGS. 4 and 5.

First, the problem of leak path will be described with reference to FIG.
In FIG. 4, the electrode layer 7 (electrode layer 7a and electrode layer 7b) and the semiconductor layer 5 are separated by forming a groove by etching using an etching mask 11 having an opening width narrow enough to cause a leak path problem. It is a figure which shows typically the state which was done.
When the opening width of the etching mask 11 is narrow, an etching residue of the electrode layer 7 is likely to be generated between the electrode layer 7a and the electrode layer 7b. Therefore, it is considered that a leak path is likely to occur between the electrode layer 7a and the electrode layer 7b due to the etching residue remaining or deposited between the electrode layer 7a and the electrode layer 7b.

Next, the decrease in the open circuit voltage will be described with reference to FIG.
In FIG. 5, the electrode layer 7 (electrode layer 7a and electrode layer 7b) and the semiconductor layer 5 are formed by forming a groove by etching using an etching mask 11 having an opening width wide enough to cause a decrease in release voltage. It is a figure which shows typically the divided state. When the opening width of the etching mask 11 is wide, the surface of the crystalline silicon substrate 1 may be exposed after etching because the position of the opening of the etching mask 11 is slightly deviated from a predetermined position.
In this case, as shown in FIG. 5, the crystalline silicon substrate 1 may be damaged by a base or the like. Then, when the crystalline silicon substrate 1 is damaged, it is considered that the open circuit voltage of the solar cell decreases.

As a result of diligent studies by the present authors based on the problems and their causes regarding the back contact type solar cell manufactured by the conventional method described above, the structure of the solar cell according to the present invention described above was conceived. I came to do it.
In the solar cell according to the present invention having the above-mentioned structure, since the divided electrode layer 7a and the electrode layer 7b have a wide opening width, the generation of a leak path is suppressed, while the divided one is suppressed. Since the opening width between the semiconductor layer and the other semiconductor layer is narrow, the crystalline silicon substrate 1 is less likely to be damaged by etching. Therefore, in the solar cell having the above structure, the leak resistance and the open circuit voltage are high.

Hereinafter, the solar cell according to the present invention will be described with reference to FIG.
FIG. 6 is a diagram schematically showing a cross section perpendicular to the plane direction of the solar cell for an example of a suitable solar cell.

The solar cell shown in FIG. 6 includes a semiconductor region 4 composed of a semiconductor region 4a and a semiconductor region 4b separated by a separation groove 9 on a first main surface 1a of the crystalline silicon substrate 1.
The semiconductor region 4a is composed of an electrode layer 7a and a semiconductor layer 5 in FIG.
The semiconductor layer 5 is usually composed of a second conductive semiconductor layer 5a and an intrinsic semiconductor layer 5b.
Further, the semiconductor region 4b is composed of an electrode layer 7b and a semiconductor layer 5 in FIG.

In the solar cell shown in FIG. 6, the second conductive semiconductor layer 5a and the first conductive semiconductor layer 6a are joined to each other on the intrinsic semiconductor layer 5b and the intrinsic semiconductor layer 6b via the intrinsic semiconductor layer 5b. ing. The intrinsic semiconductor layer 6b is laminated with the first conductive semiconductor layer 6a to form the semiconductor layer 6.
One of the second conductive semiconductor layer 5a and the first conductive semiconductor layer 6a is an n-type semiconductor layer, and the other is a p-type semiconductor layer. Usually, the second conductive semiconductor layer 5a is an n-type semiconductor layer, and the first conductive semiconductor layer 6a is a p-type semiconductor layer.

In the solar cell shown in FIG. 6, an insulating layer 8 is provided on the first conductive semiconductor layer 6a, and the electrode layer 7 and the semiconductor layer 5 are separated by a separation groove 9 on the insulating layer 8.
One of the separated electrode layers 7a is formed so as to cover the second conductive semiconductor layer 5a in a portion other than the separation groove 9. The other electrode layer 7b is formed so as to cover the surface of the semiconductor layer 5 and the surface of the first conductive semiconductor layer 6a in a portion other than the separation groove 9.

The material of the electrode layer 7 (electrode layer 7a and electrode layer 7b) is not particularly limited, but a transparent conductive material is preferable. Transparent conductive materials include indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), metal mesh, and nanocarbon. Examples include materials and conductive polymers. The transparent conductive material is selected from these materials in consideration of electrical characteristics, transparency, ease of patterning, and the like. Of these materials, indium tin oxide (ITO) is more preferred.
When the electrode layer 7 is made of ITO, the ITO may be amorphous ITO or crystalline ITO, and is preferably amorphous ITO.
When amorphous ITO is used, it is easy to form the electrode layer 7 having good contact with the semiconductor layer such as the second conductive semiconductor layer 5a and the first conductive semiconductor layer 6a.
Further, when amorphous ITO is used, the etching rate of the electrode layer 7 when forming the separation groove 9 is high, and it is easy to form the separation groove 9 having a desired shape.

As described above, the shortest distance Wt between the electrode layer 7a of one semiconductor region 4a facing each other across the separation groove 9 and the electrode layer 7b of the other semiconductor region 4b is the semiconductor layer 5 of one semiconductor region 4a. The shortest distance Wn from the semiconductor layer 5 of the other semiconductor region 4b is 1.2 times or more and 10 times or less.
Since Wt and Wn have the above relationship, the Wt is sufficiently wide in the region separating the electrode layer 7a and the electrode layer 7b of the separation groove 9, so that a leak path due to the etching residue of the electrode layer 7 occurs. It is suppressed.
On the other hand, since Wt and Wn have the above relationship, Wn is sufficiently narrow in the region of the separation groove 9 that separates the semiconductor layer 5, and the surface of the crystalline silicon substrate 1 is not easily exposed during the production of the solar cell. As a result, the crystalline silicon substrate 1 is less likely to be damaged, and a decrease in the open circuit voltage of the solar cell can be suppressed.

The measurement of Wt and Wn is performed as follows.
First, the boundary between the electrode layer 7 and the separation groove 9 and the boundary between the semiconductor layer 5 and the separation groove 9 are specified by using the cross-section SEM. When the material of the electrode layer 7 is a material containing In such as ITO and the boundary between the electrode layer 7 and the separation groove 9 is ambiguous, the boundary can be specified by using In detection by EDS (X-ray analysis). it can.
After confirming the boundary, the boundary region is photographed with a 50x or 100x objective lens of the Lasertec confocal microscope H1200, and Wt and Wn (the shortest distance between the end faces of the two separated electrode layers or semiconductor layers) are measured. Each can be measured.

As described above, the value of Wt / Wn is 1.2 or more, preferably 1.4 or more, and more preferably 1.6 or more. Further, the value of Wt / Wn is preferably 10 or less, more preferably 8 or less, and particularly preferably 5 or less, from the viewpoint that the desired laminated structure in the solar cell can be easily controlled.

The value of Wn is not particularly limited as long as it does not interfere with the object of the present invention. Typically, Wn is preferably 10 μm or more, more preferably 20 μm or more, particularly preferably 30 μm or more, and most preferably 50 μm or more. Further, Wn is preferably 80 μm or less, more preferably 70 μm or less, and particularly preferably 60 μm or less.

FIG. 6 shows a cross section of a back contact type solar cell. In the solar cell shown in FIG. 6, the intrinsic semiconductor layer 2 and the light receiving surface side protective layer 3 are laminated in this order on the second main surface 1b.
The intrinsic semiconductor layer 2 is formed for the purpose of surface passivation of the crystalline silicon substrate 1. As the material of the intrinsic semiconductor layer 2, hydrogenated amorphous silicon, silicon nitride, silicon oxide, aluminum oxide and the like are used.

Further, between the electrode layer 7a of one semiconductor region 4a and the electrode layer 7b of the other semiconductor region 4b, a convex portion made of the same material as the electrode layer 7 is formed on the upper surface of the semiconductor layer 5 (FIG. It is also preferable that (not shown) in 6 are scattered in an island shape.
That is, one or more convex portions made of the same material as the electrode layer 7 may be formed on the upper surface of the separated second conductive semiconductor layer 5a exposed in the separation groove 9.
In this case, light is scattered by the convex portion, which is expected to improve the spectral sensitivity current value.

Then, the second electrode 10a is formed on the electrode layer 7a, and the second electrode 10b is formed on the electrode layer 7b. The current generated in the solar cell is taken out by the second electrode 10a and the second electrode 10b.

≪Manufacturing method of solar cells≫
Hereinafter, a suitable manufacturing method for the above-mentioned solar cell will be described.
With respect to the precursor laminate including the above-mentioned crystalline silicon substrate 1, the semiconductor region 4 including the semiconductor layer 5 and the electrode layer 7, and the etching mask 11 which is the outermost layer, the electrode layer 7 and the semiconductor are formed from the opening of the etching mask 11. The semiconductor region 4 is divided by etching the layer 5 to form a separation groove 9.
In the precursor laminate, the electrode layer 7 is laminated on the semiconductor layer 5.
A cross section of the precursor laminate to be etched is shown in FIG.
Then, in the opening width direction of the etching mask 11, the etching proceeds faster in the electrode layer 7 than in the semiconductor layer 5, so that the separation groove 9 satisfying the predetermined conditions described for the solar cell is formed.

FIG. 8 shows a cross section of the solar cell in a state where the separation groove 9 having a desired shape is formed by etching and the etching mask 11 is not peeled off.
When the separation groove 9 having a desired shape is formed, the etching of the electrode layer 7 proceeds not only in the direction from the opening of the etching mask 11 to the insulating layer 8 but also in the width direction of the opening of the etching mask 11. By causing such under-etching, a wide region separating the electrode layer having a width of Wt is formed in the separation groove 9. Here, as described above, Wt is 1.2 times or more and 10 times or less of Wn.
Further, although the etching proceeds faster in the electrode layer 7 than in the semiconductor layer 5, it is preferable that the semiconductor layer 5 is not etched by the etching solution used for etching the electrode layer 7. In this case, the semiconductor layer 5 is etched with an etching solution different from the etching solution used for etching the electrode layer 7.

The etching of the semiconductor layer 5 hardly proceeds in the width direction of the opening of the etching mask 11, but proceeds toward the insulating layer 8 with the same or substantially the same width as the opening width Wr of the etching mask 11. In this way, a region separating the semiconductor layer 5 having a width Wn is formed in the separation groove 9. Here, Wr is equal to or approximately equal to Wn.

Such etching is preferably performed using an etching solution having an etching rate of 5 nm / sec or more for the electrode layer 7. By using such an etching solution, it is easy to form a separation groove having a desired shape in a short time while making a desired difference between Wt and Wn. Further, by using such an etching solution, the electrode layer 7 is likely to remain in an island shape on the upper surface of the electrode layer 7 semiconductor layer 5.
The etching rate of the etching solution with respect to the electrode layer 7 is more preferably 10 nm / sec or more, and particularly preferably 15 nm / sec or more. The etching rate of the etching solution with respect to the electrode layer 7 is preferably 50 nm / sec or less.
On the other hand, the etching of the semiconductor layer 5 is preferably performed using an alkaline etching solution such as an aqueous KOH solution. When an alkaline etching solution is used, it is easy to form a separation groove 9 having a desired shape without increasing Wn excessively.

Examples of the etching solution showing the above etching rate with respect to the electrode layer 7 include an aqueous solution of hydrogen chloride, an aqueous solution of hydrogen halide other than hydrochloric acid, and an aqueous solution of ferric chloride. Of these, an aqueous hydrogen chloride solution (hydrochloric acid) is preferable. The concentration of hydrochloric acid is preferably 5 to 40% by mass, more preferably 7 to 20% by mass, and particularly preferably 8 to 15% by mass.

The etching time is appropriately selected according to the type of the etching solution so that the separation groove 9 in which Wt and Wn are desired values is formed.

As described above, it is preferable to anneal the electrode layer 7 (electrode layer 7a and electrode layer 7b) after forming the separation groove 9. By annealing the electrode layer 7, the crystallinity of the electrode layer 7 is improved, and the contact between the electrode layer 7 and the semiconductor layers such as the second conductive semiconductor layer 5a and the first conductive semiconductor layer 6a is established. Can be improved.
Such curing is remarkable in the electrode layer 7 made of ITO, and more remarkable in the electrode layer 7 made of amorphous ITO.

The annealing conditions are not particularly limited, but are typically 150 to 220 ° C. and 10 to 60 minutes.

Hereinafter, the present invention will be described in more detail based on Examples, but the present invention is not limited to these Examples.

[Comparative Example 1]
An n-type single crystal silicon substrate having an incident plane orientation of (100) and a thickness of 200 μm was used, and the substrate was immersed in a 2 wt% HF aqueous solution for 3 minutes to remove the silicon oxide film on the surface. Then, rinsing with ultrapure water was performed twice. The rinsed substrate was immersed in a 15% by mass isopropyl alcohol aqueous solution containing 5% by mass of KOH kept at 70 ° C. for 15 minutes to etch the surface of the substrate to form a texture on the surface of the substrate. .. Then, rinsing with ultrapure water was performed twice.

When the surface of a single crystal silicon substrate was observed with an atomic force microscope (AFM, manufactured by Pacific Nanotechnology), the surface of the substrate was most etched, and the (111) surface was exposed in a pyramid-shaped texture. Was formed.
The substrate having a texture on the surface thus obtained was used as the crystalline silicon substrate 1.

The crystalline silicon substrate 1 was introduced into the CVD apparatus, and an intrinsic amorphous silicon layer was formed as an intrinsic semiconductor layer 2 on the light receiving surface (second main surface 1b) side with a film thickness of 10 nm.
Next, a silicon nitride layer was formed on the intrinsic semiconductor layer 2 as a light receiving surface side protective layer 3 with a film thickness of 60 nm.

Further, an intrinsic amorphous silicon layer was formed as an intrinsic semiconductor layer 6b on the back surface (first main surface 1a) side with a film thickness of 8 nm. A p-type amorphous silicon layer was formed on the intrinsic semiconductor layer 6b as the first conductive semiconductor layer 6a with a film thickness of 7 nm.
Further, a silicon oxide layer was formed as an insulating layer 8 on the first conductive semiconductor layer 6a with a film thickness of 60 nm.

Next, an etching mask was formed on the insulating layer 8 by a photolithography method using a photoresist, and then a part of the insulating layer 8 was removed using an HF aqueous solution.
After removing a part of the insulating layer 8, the etching mask was peeled off and removed according to a conventional method.
Further, isotropic etching was performed on a part of the first conductive semiconductor layer 6a and the intrinsic semiconductor layer 6b (the surface from which the insulating layer 8 was removed) to expose the first main surface a of the crystalline silicon substrate 1. The substrate obtained through etching has the structure shown in FIG.

After cleaning, the silicon substrate was introduced into the CVD apparatus, and an intrinsic amorphous silicon layer as the intrinsic semiconductor layer 5b was formed on the first main surface a side including the insulating layer 8 with a film thickness of 8 nm.
An n-type amorphous silicon layer was formed as a second conductive type semiconductor layer 5a on the intrinsic semiconductor layer 5b with a film thickness of 12 nm.
An etching mask is formed on the second conductive semiconductor layer 5a thus formed by a photolithography method using a photoresist, and then a part of the second conductive semiconductor layer 5a and the intrinsic semiconductor layer 5b is KOH. It was removed using an aqueous solution.
Subsequently, the insulating layer 8 at the portion exposed by removing the second conductive semiconductor layer 5a and the intrinsic semiconductor layer 5b was removed with an HF aqueous solution to expose a part of the surface of the first conductive semiconductor layer 6a.
After removing a part of the insulating layer 8, the etching mask was peeled off and removed according to a conventional method.
The substrate obtained through etching has the structure shown in FIG.

Further, indium tin oxide (ITO, refractive index: 1.9) is 80 nm as an electrode layer 7 on substantially the entire surface of the first main surface 1a on which the first conductive semiconductor layer 6a and the second conductive semiconductor layer 5a are formed. The film was formed with the thickness of. The film formation of the electrode layer 7 was carried out by using indium tin oxide as a target and applying a power density of 0.5 W / cm ² in an argon atmosphere having a substrate temperature of room temperature and a pressure of 0.2 Pa.

After forming the electrode layer 7, an etching mask 11 was formed on the electrode layer 7 by a photolithography method using a photoresist. The formed etching mask had an opening for forming the separation groove 9, and the opening width of the opening was 50 μm.
Next, the silicon substrate was immersed in a hydrochloric acid aqueous solution having a concentration of 10% by mass for 30 seconds to etch a part of the electrode layer 7. Further, the silicon substrate was immersed in a KOH aqueous solution having a concentration of 3% by mass for 300 seconds to etch a part of the semiconductor layer 5.
By this etching step, the semiconductor region 4 composed of the electrode layer 7 and the semiconductor layer 5 was separated into the semiconductor region 4a and the semiconductor region 4b.
When the cross section of the silicon substrate after etching was observed with an optical microscope, no undercut occurred, and both Wt and Wn were 50 μm, which was the same as the opening width of the etching mask 11.
After etching, the etching mask 11 is peeled off and removed according to a conventional method, and then the second electrode 10a and the second electrode 10b are formed on the separated electrode layer 7a and the electrode layer 7b by screen printing using a silver paste, respectively. Then, the solar cell of Comparative Example 1 was obtained.

For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
The values of the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff of the solar cell of Comparative Example 1 are used as criteria for comparison with the solar cells of Example and Comparative Example 2, respectively. It is shown in Table 1 as 000.

[Comparative Example 2]
A solar cell was obtained in the same manner as in Comparative Example 1 except that the width of the opening of the etching mask 11 was changed from 50 μm to 60 μm.
When the cross section of the silicon substrate after etching was observed with an optical microscope, no undercut occurred, and both Wt and Wn were 60 μm, which was the same as the opening width of the etching mask 11.
For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
When the values of the short-circuit current Isc, open-circuit voltage Voc, curvature factor FF, and conversion efficiency Eff of the solar cell of Comparative Example 1 are 1.000, the short-circuit current Isc, open-circuit voltage Voc, and curvature of the solar cell of Comparative Example 1 The values of the factor FF and the conversion efficiency Eff are shown in Table 1.

[Example 1]
A solar cell was obtained in the same manner as in Comparative Example 1 except that the time for etching the electrode layer 7 was changed from 30 seconds to 150 seconds.
When the cross section of the silicon substrate after etching was observed with an optical microscope, undercut occurred, and Wt was 60 μm and Wn was 50 μm.
For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
When the values of the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff of the solar cell of Comparative Example 1 are 1.000, the short-circuit current Isc, the open circuit voltage Voc, and the curvature of the solar cell of Example 1 The values of the factor FF and the conversion efficiency Eff are shown in Table 1.

[Example 2]
A solar cell was obtained in the same manner as in Comparative Example 1 except that the time for etching the electrode layer 7 was changed from 30 seconds to 300 seconds.
When the cross section of the silicon substrate after etching was observed with an optical microscope, undercut occurred, and Wt was 70 μm and Wn was 50 μm.
For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
When the values of the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff of the solar cell of Comparative Example 1 are 1.000, the short-circuit current Isc, the open circuit voltage Voc, and the curvature of the solar cell of Example 2 The values of the factor FF and the conversion efficiency Eff are shown in Table 1.

[Example 3]
The power density when forming the electrode layer 7 is changed from 0.5 W / cm2 to 3.5 W / cm2 to form the electrode layer 7 made of crystalline ITO, and the etching of the electrode layer 7 is carried out at a concentration of 35% by mass. A solar cell was obtained in the same manner as in Comparative Example 1, except that it was carried out for 300 seconds using the aqueous hydrochloric acid solution of.
When the cross section of the silicon substrate after etching was observed with an optical microscope, undercut occurred, and Wt was 60 μm and Wn was 50 μm.
For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
When the values of the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff of the solar cell of Comparative Example 1 are 1.000, the short-circuit current Isc, the open circuit voltage Voc, and the curvature of the solar cell of Example 3 The values of the factor FF and the conversion efficiency Eff are shown in Table 1.

[Example 4]
Comparative examples other than changing the concentration of the aqueous hydrochloric acid solution used for etching the electrode layer 7 from 10% by mass to 5% by mass and changing the immersion time for etching the electrode layer 7 from 30 seconds to 300 seconds. A solar cell was obtained in the same manner as in 1.
When the cross section of the silicon substrate after etching was observed with an optical microscope, undercut occurred, and Wt was 60 μm and Wn was 50 μm.
For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
When the values of the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff of the solar cell of Comparative Example 1 are 1.000, the short-circuit current Isc, the open circuit voltage Voc, and the curvature of the solar cell of Example 4 The values of the factor FF and the conversion efficiency Eff are shown in Table 1.

[Example 5]
A solar cell was obtained in the same manner as in Example 2 except that the obtained solar cell was annealed under the condition of 170 ° C. for 1 hour.
When the cross section of the silicon substrate after etching was observed with an optical microscope, undercut occurred, and Wt was 70 μm and Wn was 50 μm.
For the obtained solar cell, the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff were determined.
When the values of the short-circuit current Isc, the open circuit voltage Voc, the curvature factor FF, and the conversion efficiency Eff of the solar cell of Comparative Example 1 are 1.000, the short-circuit current Isc, the open circuit voltage Voc, and the curvature of the solar cell of Example 5 The values of the factor FF and the conversion efficiency Eff are shown in Table 1.

Improvement of FF is expected by widening the opening width of the separation groove. However, according to the comparison between Comparative Example 1 and Comparative Example 2, when Wt and Wn are equal, even if the FF is improved by widening the opening, It can be seen that the Voc is impaired.

According to the comparison between Comparative Example 1 and Example 1 and Example 2, when forming a separation groove having a predetermined shape in which Wt / Wn is 1.2 or more, all of Isc, Voc, FF, and Eff are formed. It turns out that is good.
This is because, in Examples 1 and 2, since the Wt is sufficiently wide, the electrode layer 7 is sufficiently etched to reduce the leak path, and since the Wn is sufficiently narrow, damage to the crystalline silicon substrate 1 is unlikely to occur. it is conceivable that.

Comparing Example 1 with Examples 3 and 4, it can be seen that the performance of the solar cells of Example 1 is better than the performance of the solar cells of Examples 3 and 4.
It is considered that this is because the etching rate is low in Examples 3 and 4, so that a leak path due to the etching residue is slightly generated as compared with Example 1.
From the above, it can be seen that the etching rate of the electrode layer 7 is preferably 15 nm / s or more, and that the material of the electrode layer 7 is preferably amorphous ITO having a high etching rate.

The solar cell of Example 5 is an annealed solar cell of Example 2. Therefore, in the solar cell of Example 5, the FF is greatly improved. It is considered that this is because the contact between the electrode layer 7 and the semiconductor layer is improved by annealing the electrode layer 7 made of amorphous ITO.

1 Crystalline silicon substrate 2 Intrinsic semiconductor layer 3 Light receiving surface side protective layer 4 Semiconductor area 5, 6 Semiconductor layer 7 Electrode layer 8 Insulation layer 9 Separation groove 10a, 10b Second electrode 11 Etching mask

Claims (5)

A solar cell including a crystalline silicon substrate and a semiconductor region.
The semiconductor region is on the first main surface of the crystalline silicon substrate, and is electrically isolated by being separated into two regions by a separation groove.
The semiconductor region includes a semiconductor layer and an electrode layer.
When the direction from the first main surface to the semiconductor region is upward, the electrode layer is on the upper surface side of the semiconductor layer.
The shortest distance Wt between the electrode layer in one semiconductor region and the electrode layer in the other semiconductor region facing each other across the separation groove is the semiconductor layer in one semiconductor region and the semiconductor layer in the other semiconductor region. 10 times der less than 1.2 times greater than the shortest distance Wn of is,
The Wn is 10 μm or more and 80 μm or less.
And the electrode layer of said one semiconductor region, be between the electrode layers of the other semiconductor regions, on the upper surface of the semiconductor layer, convex portions made of the same material as the electrode layer you scattered like islands , Solar cell. The solar cell according to claim 1, wherein the electrode layer is made of amorphous ITO. The method for manufacturing a solar cell according to claim 1 or 2 .
With respect to the precursor laminate containing the crystalline silicon substrate, the semiconductor region including the semiconductor layer and the electrode layer, and the etching mask which is the outermost layer, the electrode layer and the semiconductor layer are etched from the opening of the etching mask. The semiconductor region is divided by forming the separation groove.
A method for manufacturing a solar cell, wherein the electrode layer is laminated on the upper surface side of the semiconductor layer, and the etching mask is laminated on the electrode layer. The method according to claim 3 , wherein an etching solution having an etching rate of 5 nm / sec or more for the electrode layer is used in the etching. The method according to claim 4, further comprising annealing the electrode layer after forming the separation groove.

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