WO2018168180A1 - Cellule solaire et son procédé de fabrication - Google Patents

Cellule solaire et son procédé de fabrication Download PDF

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Publication number
WO2018168180A1
WO2018168180A1 PCT/JP2018/001079 JP2018001079W WO2018168180A1 WO 2018168180 A1 WO2018168180 A1 WO 2018168180A1 JP 2018001079 W JP2018001079 W JP 2018001079W WO 2018168180 A1 WO2018168180 A1 WO 2018168180A1
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semiconductor layer
conductive
thin film
region
layer
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PCT/JP2018/001079
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Japanese (ja)
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貴久 藤本
小西　克典
足立　大輔
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株式会社カネカ
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present invention relates to a solar cell and a manufacturing method thereof.
  • the back contact type solar cell includes both a p-type semiconductor layer and an n-type semiconductor layer on the back side of the semiconductor substrate, and includes electrodes on these conductive semiconductor layers. Since the back contact solar cell has an electrode only on the back surface of the semiconductor substrate and no electrode on the light receiving surface, there is no shadowing loss due to the electrode, and high conversion efficiency can be realized. Since the back contact solar cell has both the p-type semiconductor layer and the n-type semiconductor layer on the back side of the semiconductor substrate, it is necessary to pattern the semiconductor layer so that the effective region is wide and no leakage between pn occurs. There is.
  • FIG. 4A to 4J are conceptual diagrams of the manufacturing process on the back side of the back contact solar cell disclosed in Patent Document 1.
  • FIG. 4A the intrinsic semiconductor layer 431 and the first conductive type semiconductor layer 432 are sequentially formed on the back surface (upper side of the drawing) of the semiconductor substrate 1 (FIG. 4A), and the insulating layer 451 is formed on the first conductive type semiconductor layer 432. (FIG. 4B).
  • a part of the insulating layer 451 is removed by etching and patterning is performed (FIG. 4C).
  • the first conductive type semiconductor layer 432 and the intrinsic semiconductor layer 431 exposed thereunder are formed. Is etched and patterned (FIG. 4D).
  • an intrinsic semiconductor layer 441 and a second conductivity type semiconductor layer 442 are formed on the entire back surface (FIG. 4E).
  • the second conductive semiconductor layer 442, the intrinsic semiconductor layer 441, and the insulating layer 451 provided on the patterned first conductive semiconductor layer 432 are etched and patterned to expose the first conductive semiconductor layer 432. .
  • a pattern resist is provided on the second semiconductor layer 442, and the second conductive semiconductor layer 442 and the intrinsic semiconductor layer 441 on the insulating layer 451 are removed by etching (FIG. 4F).
  • the insulating layer 451 is etched with an acid-based etchant such as hydrofluoric acid using the second conductivity type semiconductor layer 442 as a mask (FIG. 4G).
  • the intrinsic semiconductor layer 431 and the first conductivity type semiconductor layer are formed on the semiconductor substrate 1 at the boundary between the formation region of the first conductivity type semiconductor layer 432 and the formation region of the second conductivity type semiconductor layer 442.
  • a boundary region 450 is formed in which 432, an insulating layer 451, an intrinsic semiconductor layer 441, and a second conductivity type semiconductor layer 442 are provided in this order.
  • a conductive thin film 443 made of a conductive oxide or metal is formed on the entire back surface (FIG. 4H).
  • the conductive thin film on or near the boundary region is removed by etching, laser processing, or the like, so that the conductive thin film 443a on the first conductive type semiconductor layer 432 and the conductive thin film 443b on the second conductive type semiconductor layer 442 are obtained.
  • FIG. 4I By forming metal electrodes 435 and 445 on the conductive thin films 443a and 443b, a back contact solar cell is completed (FIG. 4J).
  • the first conductive type semiconductor layer and the second conductive type semiconductor layer overlap with each other, so that the effective power generation amount region. Since an insulating layer is provided between the first conductive semiconductor layer and the second conductive semiconductor layer, leakage between pn can be prevented.
  • the second conductive semiconductor layer 442 is etched on the second conductive semiconductor layer 442 on the first conductive semiconductor layer 432 (FIG. 4F).
  • a resist is provided on the substrate, and the resist is removed after etching. Therefore, the second conductivity type semiconductor layer 442 comes into contact with a chemical solution such as a resist solution or a stripping solution.
  • the insulating layer 451 is etched using an etchant such as hydrofluoric acid with the second conductivity type semiconductor layer 442 as a mask (FIG. 4G)
  • the etchant contacts the second conductivity type semiconductor layer 442.
  • the etchant also contacts the first conductive semiconductor layer 432 exposed by etching the insulating layer 451. As described above, when the semiconductor layer and the insulating layer are patterned, if the semiconductor layer comes into contact with the chemical solution, the semiconductor layer is damaged, and the power generation characteristics of the solar cell deteriorate due to an increase in contact resistance or a decrease in open-circuit voltage. There is.
  • an object of the present invention is to provide a back-contact solar cell that is excellent in carrier recovery efficiency and in which deterioration of characteristics due to patterning or the like is suppressed.
  • the present invention relates to a back contact solar cell in which a first conductivity type region and a second conductivity type region are alternately arranged along a first direction on a first main surface of a semiconductor substrate, and a manufacturing method thereof.
  • a boundary region that is in contact with and separates the first conductivity type region and the second conductivity type region is provided.
  • a first conductive type semiconductor layer, a second conductive type semiconductor layer, a first conductive thin film, a second conductive thin film, and an insulating layer are provided on the first main surface of the semiconductor substrate.
  • the first conductivity type semiconductor layer and the second conductivity type semiconductor layer have different conductivity types, one is p-type and the other is n-type.
  • Each layer on the first main surface of the semiconductor substrate is patterned.
  • the first conductive type semiconductor layer and the first conductive thin film are provided across the entire surface of the first conductive type region and the boundary region.
  • the second conductive type semiconductor layer and the second conductive thin film are provided across the entire surface of the second conductive type region and the boundary region.
  • the insulating layer is provided on the entire boundary region.
  • first conductivity type region a first conductivity type semiconductor layer and a first conductive thin film are provided in this order on a semiconductor substrate.
  • second conductivity type region the second conductivity type semiconductor layer and the second conductive thin film are provided in this order on the semiconductor substrate.
  • the first conductive thin film is preferably provided in the first boundary region in contact with the first conductivity type region and not in the second boundary region in contact with the second conductivity type region.
  • the side surface of the first conductive thin film is covered with the insulating layer at the boundary portion between the first boundary region and the second boundary region.
  • a first conductive type semiconductor layer, a first conductive thin film, and an insulating layer are provided in this order on the semiconductor substrate.
  • a second conductive semiconductor layer and a second conductive thin film may be provided in this order on the insulating layer.
  • the second conductive type semiconductor layer and the second conductive thin film are provided in this order on the insulating layer.
  • the first conductive thin film is not provided between the semiconductor substrate and the insulating layer.
  • the first conductivity type semiconductor layer may or may not be provided between the semiconductor substrate and the insulating layer.
  • a first intrinsic semiconductor layer is provided between the semiconductor substrate and the first conductivity type semiconductor layer.
  • a second intrinsic semiconductor layer is preferably provided between the semiconductor substrate and the second conductivity type semiconductor layer.
  • a pattern layer in which a first conductive type semiconductor layer, a first conductive thin film, and an insulating layer are laminated in this order is formed in the first conductive type region and the boundary region; A second conductive type semiconductor layer and a second conductive thin film are sequentially formed on the region; the insulating layer provided in the first conductive type region can be removed by etching.
  • the second conductive type semiconductor layer and the second conductive thin film are patterned so as to have an opening in the first conductive type region, and the insulating layer is exposed under the opening of the second conductive type semiconductor layer. Therefore, the insulating layer provided in the first conductivity type region can be selectively removed by etching. For example, a second conductive type semiconductor layer and a second conductive thin film are sequentially formed on the entire surface of the substrate, and the second conductive type semiconductor layer and the second conductive thin film provided in the first conductive type region are removed by etching. Thus, an opening is formed in the second conductive type semiconductor layer and the second conductive thin film.
  • the first conductive thin film is not provided at both ends of the pattern layer, and the side surfaces of the first conductive thin film are covered with an insulating layer.
  • the second conductive type semiconductor layer and the second conductive thin film are formed, and the insulating layer exposed under the opening of the second conductive type semiconductor layer is etched to thereby form the first boundary region and the first conductive layer.
  • a solar cell in which the side surface of the first conductive thin film is covered with the insulating layer at the boundary portion between the two boundary regions is obtained.
  • a first conductive thin film having openings at both ends of the pattern layer forming region is formed on the first conductive type semiconductor layer, an insulating layer is formed on the entire surface of the substrate, and then provided in the second conductive type region. By etching away the formed layer, a pattern layer in which the first conductive thin film is not provided at both ends can be formed.
  • the conductive thin film is provided on the first conductivity type semiconductor layer in the boundary region, the carriers that have reached the boundary region can be effectively collected. Further, since the conductive thin film provided on the first conductivity type semiconductor layer in the boundary region is covered with the insulating layer, leakage between pn can be prevented and high conversion characteristics can be realized. Furthermore, since the conductive thin film is provided on each of the first conductive type semiconductor layer and the second conductive type semiconductor layer, contact between the semiconductor layer and a chemical solution such as an etchant in the manufacturing process of the solar cell is prevented. The damage to the semiconductor layer can be reduced and the characteristics of the solar cell can be improved.
  • FIG. 2 is a schematic plan view for explaining the shapes of the first conductivity type region and the second conductivity type region in the back contact solar cell.
  • FIG. 1 is a schematic cross-sectional view of a back contact solar cell according to an embodiment of the present invention, and corresponds to a cross section in the left-right direction (x direction) of FIG.
  • the lower side (second main surface) in FIG. 1 is the light receiving surface of the solar cell, and the upper side (first main surface) is the back surface of the solar cell.
  • the first conductivity type regions 30 and the second conductivity type regions 40 are alternately arranged along the first direction (x direction).
  • the first conductivity type region 30 and the second conductivity type region 40 each extend along a second direction (y direction) orthogonal to the first direction.
  • the first conductivity type region 30 and the second conductivity type region 40 are provided in a comb shape that meshes with each other.
  • the shape of the first conductivity type region 30 and the second conductivity type region 40 does not have to be a comb shape.
  • the first conductivity type region 30 and the second conductivity type region 40 may have a shape that extends in the x direction and connects the comb teeth (so-called bus bar portion). Good.
  • the first conductivity type region 30 is provided with a first conductivity type semiconductor layer 32
  • the second conductivity type region 40 is provided with a second conductivity type semiconductor layer 42.
  • the first conductivity type semiconductor layer 32 and the second conductivity type semiconductor layer 42 have different conductivity types, one is p-type and the other is n-type.
  • a boundary region 50 in contact with both is provided, and the first conductivity type region 30 and the second conductivity type region 40 are separated from each other. .
  • the width of the first conductivity type region 30 and the width of the second conductivity type region 40 are not particularly limited, and may be equal to or different from each other.
  • the width of the first conductivity type region 30 and the width of the second conductivity type region 40 are, for example, about 100 to 1500 ⁇ m.
  • the width of the boundary region 50 is not particularly limited.
  • the width of the boundary region is, for example, about 10 to 500 ⁇ m.
  • the width of the boundary region 50 is preferably as small as possible within a range in which leakage between pn and leakage between the first conductive thin film 33 and the second conductivity type semiconductor layer 42 can be prevented.
  • a first intrinsic semiconductor layer 31 In the back contact solar cell shown in FIG. 1, on the first main surface of the semiconductor substrate 1, a first intrinsic semiconductor layer 31, a first conductive semiconductor layer 32, a first conductive thin film 33, an insulating layer 51, a second An intrinsic semiconductor layer 41, a second conductive type semiconductor layer 42, and a second conductive thin film 43 are provided. Each of these layers is patterned on the first major surface.
  • the first conductivity type is p-type and the second conductivity type is n-type.
  • the solar cell of the present invention may be n-type for the first conductivity type and p-type for the second conductivity type.
  • the p-type semiconductor layer 32 is provided across the p-type region 30 and the boundary region 50.
  • the n-type semiconductor layer 42 is provided across the n-type region 40 and the boundary region 50.
  • an insulating layer 51 is provided between the p-type semiconductor layer 32 and the n-type semiconductor layer 42.
  • the insulating layer 51 is provided on the entire boundary region 50. In other words, the region where the insulating layer 51 is provided is the boundary region 50. In the boundary region 50, the insulating layer 51 prevents leakage between the p-type semiconductor layer 32 and the n-type semiconductor layer 42.
  • the first conductive thin film 33 is provided across the p-type region 30 and the boundary region 50. In the p-type region 30, the first conductive thin film 33 is provided on the p-type semiconductor layer 32, and the first metal electrode 35 is provided thereon.
  • the first conductive thin film 33 is provided on the p-type semiconductor layer 32, and the insulating layer 51 is provided thereon.
  • the solar cell shown in FIG. 4J since no conductive layer is provided on the first conductive type semiconductor layer 432 in the boundary region 450, a recovery loss of carriers reaching this region is likely to occur.
  • the solar cell shown in FIG. 1 can improve the recovery efficiency of the carriers that have reached the boundary region 50.
  • the first conductive thin film 33 is not provided on the p-type semiconductor layer 32, and the p-type semiconductor layer 32 and the insulating layer 51 are in contact with each other. Preferably it is.
  • the side surface of the first conductive thin film 33 is covered with the insulating layer 51 at the boundary portion between the first boundary region 101 and the second boundary region 102. It has been broken.
  • a second conductive thin film 43 is provided on the n-type semiconductor layer 42.
  • the second conductive thin film 43 is provided on the n-type semiconductor layer 42, and the second metal electrode 45 is provided thereon. Similar to the n-type semiconductor layer 42, the second conductive thin film 43 may be provided across the n-type region 40 and the boundary region 50.
  • the second conductive thin film 43 is preferably provided on the entire surface of the n-type semiconductor layer 42.
  • the second metal electrode 45 on the second conductive thin film 43 may protrude from the boundary region 50.
  • the p-type semiconductor layer 32 and the first conductive thin film 33 are formed on the semiconductor substrate 1 in the first boundary region 101.
  • An insulating layer 51, an n-type semiconductor layer 42, and a second conductive thin film 43 are provided in this order; in the second boundary region 102, a p-type semiconductor layer 32, an insulating layer 51, and an n-type semiconductor are formed on the semiconductor substrate 1.
  • a layer 42 and a second conductive thin film 43 are provided in this order.
  • the first intrinsic semiconductor layer 31 is preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32. That is, the first intrinsic semiconductor layer 31 is preferably provided across the p-type region 30 and the boundary region 50.
  • the p-type semiconductor layer 32 may not be provided in the second boundary region 102.
  • the insulating layer 51 is provided on the semiconductor substrate 1 or in contact with the first intrinsic semiconductor layer 31 (see FIGS. 7 and 8).
  • the second intrinsic semiconductor layer 41 is preferably provided between the semiconductor substrate 1 and the n-type semiconductor layer 42.
  • the second intrinsic semiconductor layer 41 may be provided between the insulating layer 51 and the n-type semiconductor layer 42.
  • the second intrinsic semiconductor layer 41 may be provided across the n-type region 40 and the boundary region 50.
  • [Solar cell manufacturing process] 3A to 3I are process conceptual diagrams showing an example of the manufacturing process of the back contact solar cell shown in FIG. Below, with reference to these figures, the process of film-forming and patterning of each layer on the 1st main surface of a solar cell is demonstrated.
  • the semiconductor substrate 1 is prepared.
  • the semiconductor substrate 1 is preferably a crystalline silicon substrate.
  • the crystalline silicon substrate may be either single crystal silicon or polycrystalline silicon.
  • the conductivity type of the crystalline silicon substrate may be either n-type or p-type.
  • the thickness of the semiconductor substrate is, for example, about 100 to 300 ⁇ m.
  • a texture structure is preferably formed on the surface of the second main surface (light receiving surface) of the semiconductor substrate 1.
  • a texture structure may also be formed on the first main surface of the semiconductor substrate. By providing a texture structure on the surface of the semiconductor substrate, surface reflection is reduced, and the amount of light incident on the semiconductor substrate can be increased.
  • a pyramidal texture can be formed by anisotropic etching.
  • a pattern layer forming region 100 provided with a pattern layer 13 and an exposed region 200 where the first main surface of the semiconductor substrate is exposed are formed on the first main surface of the semiconductor substrate 1.
  • the exposed region 200 corresponds to the n-type region (second conductivity type region) 40 of the completed solar cell.
  • the pattern layer 13 has a configuration in which a p-type semiconductor layer 32, a first conductive thin film 33, and an insulating layer 51 are sequentially stacked.
  • a p-type semiconductor layer 32 and an insulating layer 51 are provided on the entire surface of the pattern layer forming region 100.
  • An intrinsic semiconductor layer 31 is preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32.
  • the first conductive thin film 33 is not provided, and the p-type semiconductor layer 32 and the insulating layer 51 are in contact with each other.
  • the pattern layer forming region 100 preferably has a central region 103 where the first conductive thin film 33 is provided and an end region 102 where the first conductive thin film 33 is not provided. In the completed solar cell, this end region 102 corresponds to the second boundary region 102 of the boundary region 50.
  • the insulating layer 51 is provided over the entire pattern layer forming region 100, and the side surface of the first conductive thin film 33 is covered with the insulating layer 51 at the boundary between the central region 103 and the end region 102.
  • the first conductive thin film 33 and the insulating layer 51 are provided on the p-type semiconductor layer 32, and in the end region 102 where the first conductive thin film 33 is not provided, the semiconductor layer An insulating layer 51 is provided in contact with the substrate.
  • the respective layers are formed in a state where the exposed region 200 is shielded by a mask.
  • the first conductive thin film 33 is formed with the end regions 102 at both ends of the pattern layer forming region 100 in addition to the exposed region 200 being shielded by the mask.
  • a pattern layer in which the insulating layer 51 covers the side surface of the first conductive thin film 33 can be formed.
  • the pattern layer 13 is formed by repeatedly performing film formation and etching on the entire surface of the substrate.
  • the film may not be formed in a non-power generation region such as an end portion of the substrate.
  • a p-type semiconductor layer 32 is formed on the entire first main surface of the semiconductor substrate 1.
  • the p-type semiconductor layer 32 is a semiconductor thin film to which a p-type dopant is added, and is preferably a p-type silicon-based layer to which boron is added. From the viewpoint of suppressing impurity diffusion and reducing series resistance, the p-type semiconductor layer 32 is preferably a p-type amorphous silicon-based layer, and a p-type amorphous silicon layer is particularly preferable.
  • the thickness of the p-type semiconductor layer 32 is, for example, about 2 to 50 nm.
  • the intrinsic semiconductor layers 31 and 41 are preferably provided between the semiconductor substrate 1 and the p-type semiconductor layer 32 and between the semiconductor substrate 1 and the n-type semiconductor layer 42.
  • the intrinsic semiconductor layers 31 and 41 are provided on the semiconductor substrate 1, surface passivation of the semiconductor substrate 1 can be effectively performed. Further, by providing the intrinsic semiconductor layers 31 and 41, it is possible to suppress the diffusion of impurities to the semiconductor substrate 1 when forming the conductive semiconductor layers 32 and 42.
  • As the intrinsic semiconductor layer an intrinsic amorphous silicon thin film composed of silicon and hydrogen is preferable. Since the intrinsic semiconductor layers 31 and 41 do not directly contribute to the generation and recovery of photocarriers, the film thickness is set in a range where a passivation effect can be obtained, and is, for example, about 0.1 to 25 nm.
  • a plasma CVD method is preferable as a method for forming the intrinsic semiconductor layer and the conductive semiconductor layer.
  • a silicon-containing gas such as SiH 4 or Si 2 H 6 or a mixed gas of silicon-based gas and H 2 is preferably used for forming a silicon-based semiconductor thin film by the plasma CVD method.
  • B 2 H 6 or PH 3 is preferably used as the dopant gas for forming the p-type or n-type silicon-based thin film.
  • the first conductive thin film 33 is formed on the p-type semiconductor layer 32.
  • the first conductive thin film 33 has a function of collecting optical carriers from the p-type semiconductor layer 32 in the completed solar cell.
  • the first conductive thin film 33 serves to protect the surface of the p-type semiconductor layer 32 from a chemical solution such as an etchant.
  • the second conductive thin film 43 has a function of recovering optical carriers from the n-type semiconductor layer 42 in the completed solar cell, and plays a role of protecting the n-type semiconductor layer 42 from the chemical solution in the manufacturing process of the solar cell. .
  • a metal thin film, a conductive oxide thin film, or the like is preferable.
  • metal oxides such as indium oxide, zinc oxide, tin oxide, and titanium oxide are preferable because they have high durability against chemicals and excellent protection against semiconductor layers.
  • the conductive oxide may be a composite metal oxide.
  • the material of the conductive thin films 33 and 43 is preferably an indium oxide mainly composed of indium oxide because of its excellent conductivity and long-term reliability, and indium tin oxide (ITO) is particularly preferable.
  • the film thickness of the conductive thin films 33 and 43 is, for example, about 10 nm to 200 nm.
  • a method for forming the conductive thin film is not particularly limited, but a dry process such as a physical vapor deposition method such as sputtering or a chemical vapor deposition (MOCVD) method using a reaction between an organometallic compound and oxygen or water is preferable. .
  • a dry process such as a physical vapor deposition method such as sputtering or a chemical vapor deposition (MOCVD) method using a reaction between an organometallic compound and oxygen or water is preferable.
  • the patterning of the first conductive thin film 33 is performed, and an opening 33a is formed as shown in FIG. 3C.
  • the patterning of the first conductive thin film 33 is performed, for example, by photolithography.
  • photolithography a resist film is formed in a portion where the first conductive thin film 33 should remain, and the first conductive thin film 33 exposed under the opening of the resist film is removed by etching.
  • etching a chemical solution that dissolves the first conductive thin film 33 and hardly dissolves the underlying semiconductor layer is used.
  • the first conductive thin film 33 is a conductive oxide such as ITO, an aqueous iron chloride solution, hydrochloric acid, or the like is preferably used as an etchant.
  • patterning may be performed using an etching paste or an etching ink.
  • an etching paste or an etching ink may be applied to a portion where the first conductive thin film 33 is to be removed (a portion where the opening 33a is provided) by screen printing, ink jet printing, or the like.
  • an insulating layer 51 is formed on the patterned first conductive thin film. Since the first conductive thin film 33 is patterned, when an insulating layer is formed on the entire surface of the first main surface, the insulating layer 51 is formed in contact with the p-type semiconductor layer 32 in the opening 33a. The side surface of the thin film 33 is covered with the insulating layer 51.
  • the material of the insulating layer 51 is not particularly limited as long as it has insulating properties and can suppress leakage between the p-type semiconductor layer 32 and the n-type semiconductor layer 42. Since the patterning by etching is easy, the material of the insulating layer 51 is preferably a material mainly composed of a silicon alloy such as silicon oxide, silicon nitride, or silicon oxynitride, and silicon oxide is particularly preferable.
  • the insulating layer 51 is preferably formed by a dry process such as a sputtering method or a plasma CVD method.
  • Each layer provided on the region 200 is removed by etching to expose the semiconductor substrate 1 as shown in FIG. 3E.
  • the insulating layer may be patterned by photolithography using a resist, an etching paste, or the like.
  • an acid-based etchant such as a hydrofluoric acid aqueous solution is preferably used.
  • the first conductive thin film 33, the p-type semiconductor layer 32 exposed between the insulating layers, and the intrinsic semiconductor layer 31 provided thereunder are removed by etching.
  • an aqueous iron chloride solution, hydrochloric acid, or the like is preferably used for etching the conductive thin film.
  • an aqueous solution containing hydrofluoric acid is used, and in particular, a mixed acid of hydrofluoric acid and nitric acid is preferably used.
  • FIG. 3D shows a form in which the opening 33a is formed only in a portion corresponding to the end region 102 of the pattern layer 13, the opening 33a of the first conductive thin film 33 is formed in the exposed region 200 as shown in FIG. May also be formed.
  • the opening 33a of the first conductive thin film 33 is provided in the entire region 200, the first conductive film is formed when each layer provided on the region 200 is removed by etching after the insulating layer 33 is formed. There is no need to perform etching of the thin film 33.
  • the end region 102 of the pattern layer 13 (region where the first conductive thin film 33 is not provided) ) May be patterned so as to be wide.
  • the semiconductor substrate 1 is exposed in the exposed region 200 as shown in FIG. 3E.
  • the surface of the insulating layer 51 or the surface of the semiconductor substrate 1 in the exposed region 200 may be contaminated by the residue or etchant of the film removed by the etching. . Therefore, it is preferable to clean the substrate after forming the pattern layer and before forming the semiconductor layer on the exposed region 200.
  • the cleaning liquid used for cleaning is not particularly limited as long as the surface of the semiconductor substrate can be cleaned. Since the cleaning effect is high, it is preferable to use an aqueous solution containing hydrofluoric acid as the cleaning liquid.
  • the first conductive thin film 33 and the insulating layer 51 are provided on the p-type semiconductor layer 32, damage to the p-type semiconductor layer due to contact with the cleaning liquid is prevented. it can.
  • the conductive layer comes into contact with the cleaning liquid in the cleaning process, metal ions eluted in the cleaning liquid cause contamination of the semiconductor substrate.
  • the conductive material constituting the first conductive thin film does not elute into the cleaning liquid, which is caused by metal ions or the like eluted into the cleaning liquid. The contamination of the semiconductor substrate can be prevented.
  • ⁇ N-type semiconductor layer and second conductive thin film> After the pattern layer 13 is formed and the substrate surface is cleaned as necessary, as shown in FIG. 3H, a patterned n-type semiconductor layer 42 having an opening 42a in the central region 30 of the pattern layer forming region 100 is formed. Then, the second conductive thin film 43 is formed. An intrinsic semiconductor layer 41 is preferably formed between the semiconductor substrate 1 and the n-type semiconductor layer 42. An intrinsic semiconductor layer 41 may be provided between the insulating layer 51 and the n-type semiconductor layer 42.
  • each layer is formed while the p-type region 30 is shielded by a mask; and on the substrate
  • Examples include a method of forming each layer on the entire surface and sequentially patterning by etching or the like.
  • FIGS. 3F to 3H a description will be given of a form in which the patterned n-type semiconductor layer 42 and the second conductive thin film 43 are formed by repeating film formation and etching on the entire surface of the substrate. .
  • an n-type semiconductor layer 42 is formed so as to cover the entire surface of the substrate.
  • the n-type semiconductor layer 42 is a semiconductor thin film layer to which an n-type dopant is added, and is preferably an n-type silicon-based layer to which phosphorus is added. From the viewpoint of suppressing impurity diffusion and reducing series resistance, the n-type semiconductor layer 42 is preferably an n-type amorphous silicon-based layer, and n-type amorphous silicon is particularly preferable.
  • the thickness of the n-type semiconductor layer 42 is, for example, about 2 to 50 nm.
  • the second conductive thin film 43 is formed on the n-type semiconductor layer 42.
  • the material of the second conductive thin film 43 is preferably a metal thin film or a conductive oxide thin film.
  • the second conductive thin film 43, the n-type semiconductor layer 42 and the intrinsic semiconductor layer 41 in the central region 30 of the pattern layer forming region 100 are removed by etching to form an opening 42a as shown in FIG.
  • the insulating layer 51 is exposed.
  • an alkaline aqueous solution containing KOH, NaOH, or the like is preferably used for the etching of the n-type semiconductor layer 42 and the intrinsic semiconductor layer 41.
  • the resist is provided on the second conductive thin film 43. Therefore, the surface of the n-type semiconductor layer 42 does not come into contact with a chemical solution such as a resist solution, a developer solution, or a stripping solution, and damage to the semiconductor layer due to contact with the chemical solution can be prevented.
  • ⁇ Insulating layer patterning> The insulating layer 51 exposed under the opening 42a in the central region 30 of the pattern layer forming region 100 is removed by etching, so that the first conductive thin film 33 is exposed as shown in FIG. 3I.
  • an acid-based etchant such as a hydrofluoric acid aqueous solution is preferably used for etching the insulating layer 51.
  • the region where the insulating layer 51 is removed corresponds to the p-type region 30 of the solar cell, and the region where the insulating layer remains without being removed corresponds to the boundary region 50 of the solar cell.
  • the insulating layer 51 exposed under the opening 42a of the n-type semiconductor layer 42 is removed by etching, the side surfaces of the n-type semiconductor layer 42 and the side surfaces of the insulating layer 51 are aligned.
  • a solar cell in which the n-type semiconductor layer 42 is provided on the entire surface (both the first boundary region 101 and the second boundary region 102) is obtained.
  • the first conductive thin film 33 is exposed. Since the first conductive thin film 33 is provided on the p-type semiconductor layer 42, an etchant used for etching the insulating layer is prevented from contacting the p-type semiconductor layer, and damage to the p-type semiconductor layer is prevented. it can. In the region where the insulating layer is not etched (the region other than the p-type region 30), the second conductive thin film 43 is provided on the n-type semiconductor layer 42. Therefore, the n-type semiconductor layer is brought into contact with the etchant. Damage to 42 can be prevented.
  • the first conductivity for the purpose of carrier recovery from the p-type semiconductor layer and protection from the chemical solution of the p-type semiconductor layer on the p-type semiconductor layer 32 as the first conductivity type semiconductor layer After forming the conductive thin film 33, the insulating layer 51 is formed, and then the n-type semiconductor layer 42 as the second conductivity type semiconductor layer is formed. After forming the second conductive thin film 43 for the purpose of carrier recovery from the n-type semiconductor layer and protection of the n-type semiconductor layer from the chemical solution on the n-type semiconductor layer 42, the second conductive thin film by etching and the n-type semiconductor are formed. Patterning of the layer 42 and the insulating layer 51 is performed. Thus, by providing the first conductive thin film 33 and the second conductive thin film 43 in the first conductive semiconductor layer 32 and the second conductive semiconductor layer 42, respectively, the semiconductor layer caused by contact with the chemical solution Can be prevented, and the characteristics of the solar cell can be improved.
  • the first conductive thin film 33 is not provided in the second boundary region 102 in contact with the second conductivity type region 40, and the side surface of the first conductive thin film 33 is formed by the insulating layer 51. If it is covered, the leakage current from the first conductive thin film 33 to the second conductive type semiconductor layer 42 can be suppressed.
  • the side surface of the first conductivity type semiconductor layer 32 may be covered with an insulating layer 51. If the side surface of the first conductivity type semiconductor layer 32 is covered with the insulating layer 51, the leakage between the first conductivity type semiconductor layer 32 and the second conductivity type semiconductor layer 42 can be further reduced.
  • the side surface of the first intrinsic semiconductor layer 31 is not covered with the insulating layer 51, and the first intrinsic semiconductor layer 31 is provided on the entire boundary region 50.
  • the first intrinsic semiconductor layer 41 or the second intrinsic semiconductor layer 42 is provided on the entire first main surface of the semiconductor substrate 1, the passivation effect of the semiconductor substrate is enhanced, and the first conductivity type semiconductor is provided. Since the side surface of the layer 32 is covered with the insulating layer 51, the leakage between pn can be more reliably reduced.
  • a first metal electrode 35 and a second metal electrode 45 are formed on the first conductive thin film 33 and the second conductive thin film 43, respectively.
  • the formation method of the metal electrodes 35 and 45 is not particularly limited, and may be formed by, for example, a dry process such as sputtering, printing, plating, or the like.
  • the thickness of the metal electrodes 35 and 45 is set to, for example, about 50 nm to 100 ⁇ m.
  • the metal electrodes 35 and 45 may have a laminated structure including a plurality of layers. For example, Cu or the like may be formed by electrolytic plating on a metal layer formed by printing such as Ag paste.
  • the metal may be deposited on the conductive thin films 33 and 43 as a conductive base.
  • a conductive base layer may be provided on the conductive thin films 33 and 34 by printing or the like, and a metal electrode may be formed thereon by plating.
  • the metal grows not only in the thickness direction but also in the width direction. Therefore, the electrode formation region is limited so that a short circuit between the first metal electrode 35 and the second metal electrode 45 does not occur. It is preferable.
  • an insulating layer such as a resist film may be formed on the first conductive thin film 33 and the second conductive thin film 43, and a metal may be deposited on the opening of the insulating layer by plating.
  • the plated metal is deposited on the opening portion of the insulating layer 59.
  • the insulating layer 59 may be provided before or after the formation of the base seed metal layer. After forming the base seed metal layers 35a and 45b on the conductive thin films 33 and 43, an insulating layer 59 is formed on the entire surface of the substrate as shown in FIG. 9A, and the base seed metal layer 35a as shown in FIG. 9B. , 45b may be selectively formed on the seed metal layers 35a, 45a to selectively deposit the plating metals 35b, 45b.
  • the insulating layer 59 is formed during or after the formation.
  • the surface shape of the base seed metal layer is changed, and a crack-like opening 59a can be formed in the insulating layer 59 provided thereon.
  • the seed metal layers 35a and 45a exposed under the openings 59a of the insulating layer 59 serve as starting points for plating, the plated metal layers 35b and 45b are selectively formed in the areas where the base seed metal layers 35a and 45a are printed.
  • Can be formed see, for example, WO2013 / 077038. Due to the unevenness of the seed metal layers 35a and 45a, an opening 59a can be formed in the insulating layer 59 formed thereon (see, for example, WO2011 / 045287).
  • the second main surface which is the light receiving surface, does not directly contribute to power generation and current extraction. Therefore, the configuration on the second main surface is not particularly limited as long as it does not hinder the reception of sunlight.
  • a light-receiving surface intrinsic semiconductor layer 2 a light-receiving surface conductive semiconductor layer 3 and a light-receiving surface protective layer 4 are provided in this order on the second main surface of the semiconductor substrate 1.
  • the light-receiving surface intrinsic semiconductor layer 2 is preferably a silicon-based thin film such as an intrinsic amorphous silicon thin film.
  • a silicon-based thin film such as an intrinsic amorphous silicon thin film.
  • passivation of the substrate surface can be performed effectively. Since the light-receiving surface intrinsic semiconductor layer 2 does not directly contribute to the generation and collection of optical carriers, it is preferable to set the film thickness so as to obtain a passivation effect without preventing light reception.
  • the film thickness of the light-receiving surface intrinsic semiconductor layer 2 is, for example, about 0.1 to 25 nm.
  • the light-receiving surface protective layer 4 is capable of protecting the layers (for example, the light-receiving surface intrinsic semiconductor layer 2 and the light-receiving surface conductive semiconductor layer 3) existing under the light-receiving surface protective layer 4 and has light transmittance.
  • the material is not particularly limited.
  • a material for the light-receiving surface protective layer 4 a material mainly composed of a silicon alloy such as silicon oxide, silicon nitride, or silicon oxynitride is preferable.
  • the film thickness of the light-receiving surface protective layer 4 is not particularly limited, but it is preferable to set the film thickness from the viewpoint of providing an antireflection function and increasing the amount of light taken into the semiconductor substrate 1, and is preferably about 80 nm to 1 ⁇ m.
  • a light-receiving surface conductive semiconductor layer 3 may be formed between the light-receiving surface intrinsic semiconductor layer 2 and the light-receiving surface protective layer 4.
  • the light-receiving surface conductive semiconductor layer 3 preferably has the same conductivity type as the semiconductor substrate 1.
  • an n-type semiconductor layer is preferably formed as the light-receiving surface conductive semiconductor layer 3.
  • the light-receiving surface conductive semiconductor layer 3 is preferably a silicon-based thin film, and more preferably amorphous silicon.
  • the film thickness of the light-receiving surface conductive semiconductor layer 3 is, for example, about 1 to 25 nm.
  • the method for forming the semiconductor layers 2 and 3 and the protective layer 4 on the second main surface of the semiconductor substrate 1 is not particularly limited. A membrane is preferred.
  • the timing at which the semiconductor layers 2 and 3 and the protective layer 4 are formed on the second main surface is not particularly limited. Which is the first of the deposition of each layer on the first major surface and the deposition of each layer on the second major surface? May be done. From the viewpoint of effectively performing passivation of the second main surface of the semiconductor substrate, the light-receiving surface intrinsic semiconductor layer on the second main surface is formed before the first conductive thin film 33 is formed on the first main surface (FIG. 3B). It is preferable to perform film formation of No.2.

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Abstract

L'invention concerne une cellule solaire comprenant une première zone électroconductrice (30) et une seconde zone électroconductrice (40) sur une première surface principale d'un substrat semiconducteur (1), et comprend également une zone frontière (50) qui est en contact avec chacune de la première zone électroconductrice et de la seconde zone électroconductrice et sépare celle-ci. Un premier film mince électroconducteur est disposé à cheval sur la totalité de la surface de la première zone électroconductrice et de la zone frontière. Dans une première zone frontière (101) de la zone frontière qui entre en contact avec la première zone électroconductrice, une première couche semiconductrice électroconductrice (32), un premier film mince électroconducteur (33), et une couche d'isolation (51) sont disposés dans l'ordre indiqué sur le substrat semiconducteur.
PCT/JP2018/001079 2017-03-17 2018-01-16 Cellule solaire et son procédé de fabrication WO2018168180A1 (fr)

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JP2017-053808 2017-03-17

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Cited By (2)

* Cited by examiner, † Cited by third party
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CN116053331A (zh) * 2023-03-31 2023-05-02 福建金石能源有限公司 一种背接触电池及其制作方法和光伏组件
WO2023213125A1 (fr) * 2022-05-05 2023-11-09 西安隆基乐叶光伏科技有限公司 Cellule solaire hbc, procédé de préparation et ensemble cellule

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US20110056545A1 (en) * 2009-09-07 2011-03-10 Kwangsun Ji Solar cell
WO2012132064A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Élément photovoltaïque
JP2013030615A (ja) * 2011-07-28 2013-02-07 Sanyo Electric Co Ltd 太陽電池
US20140034119A1 (en) * 2012-08-02 2014-02-06 Samsung Sdi Co., Ltd. Photoelectric device
WO2014136715A1 (fr) * 2013-03-04 2014-09-12 シャープ株式会社 Élément de conversion photoélectrique
WO2015189878A1 (fr) * 2014-06-13 2015-12-17 国立大学法人福島大学 Cellule solaire et son procédé de fabrication
WO2016158226A1 (fr) * 2015-03-31 2016-10-06 株式会社カネカ Cellule solaire et son procédé de fabrication

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110056545A1 (en) * 2009-09-07 2011-03-10 Kwangsun Ji Solar cell
WO2012132064A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Élément photovoltaïque
JP2013030615A (ja) * 2011-07-28 2013-02-07 Sanyo Electric Co Ltd 太陽電池
US20140034119A1 (en) * 2012-08-02 2014-02-06 Samsung Sdi Co., Ltd. Photoelectric device
WO2014136715A1 (fr) * 2013-03-04 2014-09-12 シャープ株式会社 Élément de conversion photoélectrique
WO2015189878A1 (fr) * 2014-06-13 2015-12-17 国立大学法人福島大学 Cellule solaire et son procédé de fabrication
WO2016158226A1 (fr) * 2015-03-31 2016-10-06 株式会社カネカ Cellule solaire et son procédé de fabrication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023213125A1 (fr) * 2022-05-05 2023-11-09 西安隆基乐叶光伏科技有限公司 Cellule solaire hbc, procédé de préparation et ensemble cellule
CN116053331A (zh) * 2023-03-31 2023-05-02 福建金石能源有限公司 一种背接触电池及其制作方法和光伏组件

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