WO2012026428A1 - Procédé de production de cellule solaire - Google Patents

Procédé de production de cellule solaire Download PDF

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Publication number
WO2012026428A1
WO2012026428A1 PCT/JP2011/068879 JP2011068879W WO2012026428A1 WO 2012026428 A1 WO2012026428 A1 WO 2012026428A1 JP 2011068879 W JP2011068879 W JP 2011068879W WO 2012026428 A1 WO2012026428 A1 WO 2012026428A1
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semiconductor layer
solar cell
layer
amorphous semiconductor
insulating layer
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PCT/JP2011/068879
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English (en)
Japanese (ja)
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泰子 平山
正人 重松
三島　孝博
久保　幸一
井手　大輔
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三洋電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0376—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors
    • H01L31/03762—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including amorphous semiconductors including only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

Definitions

  • the present invention relates to a method for manufacturing a solar cell.
  • Patent Document 1 a so-called back junction type solar cell in which p-type and n-type semiconductor regions are formed on the back side of the solar cell.
  • this back junction solar cell it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, more improved power generation efficiency can be realized.
  • the solar cell can be connected by the wiring material only on the back surface side. For this reason, a wide wiring material can be used. Therefore, the voltage drop by wiring a plurality of solar cells using the wiring material can be suppressed.
  • Patent Document 1 discloses the following manufacturing method as a method for manufacturing a back junction solar cell. That is, first, as shown in FIG. 14, an in-junction 101 made of a laminate of an i-type semiconductor layer 101i and an n-type semiconductor layer 101n and a covering layer 102 are formed on the back surface of an n-type single crystal silicon substrate 100. They are formed in this order. Thereafter, a part of the coating layer 102 is removed by an etching method.
  • a part of the in-junction 101 is removed by an etching method using the coating layer 102 partially etched as a mask.
  • an ip junction 104 made of a stacked body of an i-type semiconductor layer 104i and a p-type semiconductor layer 104p is formed.
  • the coating layer 102 is removed by etching, so that the portion of the in-joint 101 covered with the coating layer 102 is exposed.
  • an n-side electrode is formed on the in-junction 101, and a p-side electrode is formed on the ip junction 104, thereby completing the back junction solar cell.
  • the in junction 101 and the ip junction 104 are arranged without gaps, and a solar cell having improved power generation efficiency can be manufactured. .
  • the present invention has been made in view of the above points, and an object thereof is to provide a method capable of manufacturing a solar cell having improved power generation efficiency.
  • the method for manufacturing a solar cell according to the present invention includes a semiconductor substrate having first and second main surfaces and a first conductive type semiconductor formed on the first main surface and made of a first conductivity type semiconductor.
  • a method of manufacturing a solar cell having a second electrode formed on a second semiconductor layer In the method for manufacturing a solar cell according to the present invention, the first semiconductor layer is formed.
  • An insulating layer is formed over the first semiconductor layer. By removing at least part of the insulating layer, part of the first semiconductor layer is exposed. The exposed portion of the first semiconductor layer from the insulating layer is washed with buffered hydrofluoric acid.
  • a first electrode is formed on the exposed portion of the first semiconductor layer from the insulating layer.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • It is a flowchart showing the manufacturing process of the solar cell in 1st Embodiment.
  • It is schematic-drawing sectional drawing for demonstrating the manufacturing process of a solar cell.
  • It is schematic-drawing sectional drawing for demonstrating the manufacturing process of a solar cell.
  • It is schematic-drawing sectional drawing for demonstrating the manufacturing process of a solar cell.
  • It is schematic-drawing sectional drawing for demonstrating the manufacturing process of a solar cell.
  • It is schematic-drawing sectional drawing for demonstrating the manufacturing process of a solar cell.
  • It is schematic-drawing sectional drawing for demonstrating the manufacturing process of a solar cell.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell described in Patent Document 1.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell described in Patent Document 1.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell described in Patent Document 1.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell described in Patent Document 1.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell described in Patent Document 1.
  • the solar cell 1 is a back junction solar cell.
  • the solar cell 1 may be used as a solar cell module in which a plurality of solar cells 1 are connected by a wiring material. .
  • the solar cell 1 includes a semiconductor substrate 10.
  • the semiconductor substrate 10 has a light receiving surface 10a as a second main surface and a back surface 10b as a first main surface.
  • the semiconductor substrate 10 generates carriers by receiving the light 11 on the light receiving surface 10a.
  • the carriers are holes and electrons that are generated when light is absorbed by the semiconductor substrate 10.
  • the semiconductor substrate 10 is composed of a crystalline semiconductor substrate having n-type or p-type conductivity.
  • Specific examples of the crystalline semiconductor substrate include a crystalline silicon substrate such as a single crystal silicon substrate and a polycrystalline silicon substrate.
  • a crystalline silicon substrate such as a single crystal silicon substrate and a polycrystalline silicon substrate.
  • the semiconductor substrate 10 is formed of an n-type crystalline silicon substrate will be described.
  • an i-type amorphous semiconductor layer 17i made of an intrinsic amorphous semiconductor (hereinafter, the intrinsic semiconductor is referred to as an “i-type semiconductor”) is formed.
  • the i-type amorphous semiconductor layer 17i is specifically formed of i-type amorphous silicon containing hydrogen.
  • the thickness of the i-type amorphous semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the i-type amorphous semiconductor layer 17i can be, for example, about several to 250 inches.
  • amorphous semiconductor includes a microcrystalline semiconductor.
  • a microcrystalline semiconductor refers to a semiconductor in which the average particle diameter of semiconductor crystals precipitated in an amorphous semiconductor is in the range of 1 nm to 50 nm.
  • the n-type amorphous semiconductor layer 17n having the same conductivity type as that of the semiconductor substrate 10 is formed on the i-type amorphous semiconductor layer 17i.
  • the n-type amorphous semiconductor layer 17n is an amorphous semiconductor layer to which an n-type dopant is added and has an n-type conductivity type.
  • the n-type amorphous semiconductor layer 17n is made of n-type amorphous silicon containing hydrogen.
  • the thickness of the n-type amorphous semiconductor layer 17n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 17n can be, for example, about 20 to 500 mm.
  • an insulating layer 16 having both a function as an antireflection film and a function as a protective film is formed on the n-type amorphous semiconductor layer 17n.
  • the insulating layer 16 can be formed of, for example, silicon oxide, silicon nitride, or silicon oxynitride.
  • the thickness of the insulating layer 16 can be appropriately set according to the antireflection characteristics of the antireflection film to be applied.
  • the thickness of the insulating layer 16 can be set to, for example, about 80 nm to 1 ⁇ m.
  • an IN stacked body 12 and an IP stacked body 13 are formed on the back surface 10b of the semiconductor substrate 10. As shown in FIG. 1, each of the IN laminated body 12 and the IP laminated body 13 is formed in a comb-tooth shape. The IN stacked body 12 and the IP stacked body 13 are formed so as to be inserted into each other. For this reason, the IN stacked bodies 12 and the IP stacked bodies 13 are alternately arranged along the direction x perpendicular to the intersecting width direction y on the back surface 10b. The adjacent IN stacked body 12 and the IP stacked body 13 are in contact with each other in the direction x. In other words, in the present embodiment, the entire back surface 10 b is covered with the IN stacked body 12 and the IP stacked body 13.
  • Each of the width W1 (see FIG. 2) of the IN stacked body 12 and the interval W2 between the IN stacked bodies 12 in the direction x can be set to about 100 ⁇ m to 1.5 mm, for example.
  • the width W1 and the interval W2 may be equal to each other or may be different.
  • the IN stacked body 12 includes an i-type amorphous semiconductor layer 12i formed on the back surface 10b and an n-type amorphous semiconductor layer 12n formed on the i-type amorphous semiconductor layer 12i. It is comprised by the laminated body. Similar to the i-type amorphous semiconductor layer 17i, the i-type amorphous semiconductor layer 12i is made of i-type amorphous silicon containing hydrogen.
  • the thickness of the i-type amorphous semiconductor layer 12i is not particularly limited as long as the thickness does not substantially contribute to power generation. The thickness of the i-type amorphous semiconductor layer 12i can be, for example, about several to 250 inches.
  • the n-type amorphous semiconductor layer 12n is doped with an n-type dopant similarly to the n-type amorphous semiconductor layer 17n, and has an n-type conductivity type as with the semiconductor substrate 10.
  • the n-type amorphous semiconductor layer 12n is made of n-type amorphous silicon containing hydrogen.
  • the thickness of the n-type amorphous semiconductor layer 12n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 12n can be, for example, about 20 to 500 mm.
  • the insulating layer 18 is formed on both ends excluding the central portion in the direction x of the IN laminate 12.
  • the central portion in the direction x of the IN stacked body 12 is exposed from the insulating layer 18.
  • the width W3 in the direction x of the insulating layer 18 is not particularly limited, and can be, for example, about 1/3 of the width W1.
  • the interval W4 in the direction x between the insulating layers 18 is not particularly limited, and can be, for example, about 3 of the width W1.
  • the material of the insulating layer 18 is not particularly limited.
  • the insulating layer 18 can be formed of, for example, silicon oxide, silicon nitride, or silicon oxynitride. Especially, it is preferable that the insulating layer 18 is formed of silicon nitride.
  • the insulating layer 18 preferably contains hydrogen.
  • the IP laminate 13 is formed on the portion of the back surface 10b exposed from the IN laminate 12 and the end of the insulating layer 18. For this reason, both ends of the IP stacked body 13 overlap with the IN stacked body 12 in the height direction z with the insulating layer 18 interposed therebetween.
  • the IP stacked body 13 includes an i-type amorphous semiconductor layer 13i formed on the back surface 10b and a p-type amorphous semiconductor layer 13p formed on the i-type amorphous semiconductor layer 13i. It is comprised by the laminated body.
  • the i-type amorphous semiconductor layer 13i is made of i-type amorphous silicon containing hydrogen.
  • the thickness of the i-type amorphous semiconductor layer 13i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the i-type amorphous semiconductor layer 13i can be, for example, about several to 250 inches.
  • the p-type amorphous semiconductor layer 13p is an amorphous semiconductor layer having a p-type conductivity type, to which a p-type dopant is added.
  • the p-type amorphous semiconductor layer 13p is made of p-type amorphous silicon containing hydrogen.
  • the thickness of the p-type amorphous semiconductor layer 13p is not particularly limited. The thickness of the p-type amorphous semiconductor layer 13p can be, for example, about 20 to 500 mm.
  • the i-type amorphous semiconductor layer 13i having a thickness that does not substantially contribute to power generation is provided between the crystalline semiconductor substrate 10 and the p-type amorphous semiconductor layer 13p.
  • Structure is constructed.
  • each of the amorphous semiconductor layers 17, 12, and 13 contains hydrogen.
  • An n-side electrode 14 for collecting electrons is formed on the n-type amorphous semiconductor layer 12n.
  • a p-side electrode 15 that collects holes is formed on the p-type amorphous semiconductor layer 13p.
  • the p-side electrode 15 and the n-side electrode 14 are electrically insulated.
  • the interval W5 between the n-side electrode 14 and the p-side electrode 15 on the insulating layer 18 can be set to about 1/3 of the width W3, for example.
  • each of the IN laminate 12 and the IP laminate 13 is formed in a comb shape.
  • each of the n-side electrode 14 and the p-side electrode 15 is formed in a comb shape including a bus bar and a plurality of fingers.
  • each of the n-side electrode 14 and the p-side electrode 15 is composed of only a plurality of fingers, and may be a so-called bus bar-less electrode that does not have a bus bar.
  • Each of the n-side electrode 14 and the p-side electrode 15 is not particularly limited as long as it can collect carriers.
  • each of the n-side electrode 14 and the p-side electrode 15 is formed by a laminated body of first to fourth conductive layers 19a to 19d.
  • the first conductive layer 19a can be formed of, for example, a translucent conductive oxide (TCO) such as indium oxide. Specifically, in the present embodiment, the first conductive layer 19a is made of ITO. The thickness of the first conductive layer 19a can be about 50 to 100 nm, for example.
  • TCO translucent conductive oxide
  • ITO indium oxide
  • the second to fourth conductive layers 19b to 19d can be formed of a metal or alloy such as Cu, for example. Specifically, in the present embodiment, each of the second and third conductive layers 19b and 19c is formed of Cu.
  • the fourth conductive layer 19d is made of Sn.
  • the thicknesses of the second to fourth conductive layers 19b to 19d can be, for example, about 50 nm to 1 ⁇ m, about 10 ⁇ m to 20 ⁇ m, and about 1 ⁇ m to 5 ⁇ m, respectively.
  • the method for forming the first to fourth conductive layers 19a to 19d is not particularly limited.
  • the first to fourth conductive layers 19a to 19d can be formed by a thin film forming method such as a sputtering method, a CVD method, or a vapor deposition method, or a plating method.
  • the first and second conductive layers 19a and 19b are films formed by a thin film forming method
  • the third and fourth conductive layers 19c and 19d are formed by a plating method. It is a membrane.
  • a semiconductor substrate 10 (see FIGS. 4 and 2) is prepared.
  • step S1 the light receiving surface 10a and the back surface 10b of the semiconductor substrate 10 are cleaned.
  • the semiconductor substrate 10 can be cleaned using, for example, an HF aqueous solution.
  • a texture structure is formed on the light receiving surface 10a of the semiconductor substrate 10.
  • step S2 the i-type amorphous semiconductor layer 17i and the n-type amorphous semiconductor layer 17n are formed on the light receiving surface 10a of the semiconductor substrate 10, and the i-type amorphous semiconductor is formed on the back surface 10b.
  • the formation method of i-type amorphous semiconductor layers 17i and 21 and n-type amorphous semiconductor layers 17n and 22 is not particularly limited.
  • Each of the i-type amorphous semiconductor layers 17i and 21 and the n-type amorphous semiconductor layers 17n and 22 can be formed by, for example, a thin film forming method such as a CVD (Chemical Vapor Deposition) method such as a plasma CVD method. .
  • a thin film forming method such as a CVD (Chemical Vapor Deposition) method such as a plasma CVD method.
  • the insulating layer 16 is formed on the n-type amorphous semiconductor layer 17n, and the insulating layer 23 is formed on the n-type amorphous semiconductor layer 22.
  • the formation method of the insulating layers 16 and 23 is not specifically limited.
  • the insulating layers 16 and 23 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • step S4 the insulating layer 23 is etched to remove a part of the insulating layer 23. Specifically, a portion of the insulating layer 23 located on a region where the p-type semiconductor layer is bonded to the semiconductor substrate 10 in a later step is removed.
  • the insulating layer 23 can be etched using an acidic etching solution such as an HF aqueous solution, for example, when the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride.
  • the insulating layer 16 is made of a material that is not etched by these etchings or a material that has a low etching rate.
  • step S5 using the insulating layer 23 patterned in step S4 as a mask, the i-type amorphous semiconductor layer 21 and the n-type amorphous semiconductor layer 22 are etched using an alkaline etchant. As a result, portions of the i-type amorphous semiconductor layer 21 and the n-type amorphous semiconductor layer 22 other than the portions covered by the insulating layer 23 are removed. As a result, a portion of the back surface 10b where the insulating layer 23 is not located above is exposed, and the i-type amorphous semiconductor layer 12i and the n-type amorphous semiconductor layer 12n (see FIG. 2).
  • the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, although the etching rate of the insulating layer 23 with an acidic etching solution is high, the etching rate of the insulating layer 23 with an alkaline etching solution is low.
  • the semiconductor layers 21 and 22 are made of amorphous silicon. For this reason, the semiconductor layers 21 and 22 have a low etching rate with an acidic etching solution and a high etching rate with an alkaline etching solution.
  • the insulating layer 23 is etched by the acidic etching solution used in step S4, the semiconductor layers 21 and 22 are not substantially etched.
  • the semiconductor layers 21 and 22 are etched by the alkaline etching solution used in step S5, but the insulating layer 23 is not substantially etched. Therefore, in step S4 and step S5, the insulating layer 23 or the semiconductor layers 21 and 22 can be selectively etched.
  • step S6 the i-type amorphous semiconductor layer 24 and the p-type amorphous semiconductor layer 25 are sequentially formed in this order so as to cover the back surface 10b.
  • a method for forming the amorphous semiconductor layers 24 and 25 is not particularly limited.
  • the amorphous semiconductor layers 24 and 25 can be formed by a thin film forming method such as a CVD method, for example.
  • step S7 a part of the portion located on the insulating layer 23 of the amorphous semiconductor layers 24 and 25 is etched. Thereby, the i-type amorphous semiconductor layer 13i and the p-type amorphous semiconductor layer 13p are formed from the amorphous semiconductor layers 24 and 25.
  • an etching agent having an etching rate for the amorphous semiconductor layers 24 and 25 higher than that for the insulating layer 23 is used. For this reason, the amorphous semiconductor layers 24 and 25 are selectively etched out of the insulating layer 23 and the amorphous semiconductor layers 24 and 25.
  • the etching agent used in step S7 is an etching whose etching rate for the amorphous semiconductor layers 24 and 25 is 1.1 times or more, preferably 1.5 times or more, more preferably 2 times or more that of the insulating layer 23. It is preferable that it is an agent. Furthermore, the etching agent used in step S7 is preferably one that etches the amorphous semiconductor layers 24 and 25 but does not substantially etch the insulating layer 23. As a specific example of the etching agent used in step S7, when the amorphous semiconductor layers 24 and 25 are made of silicon and the insulating layer 23 is made of silicon oxide, silicon nitride, or silicon oxynitride, for example, NaOH is used.
  • etching agent used in step S7 does not necessarily need to be a liquid, that is, an etching solution.
  • the etchant used in step S7 may be a gas, for example.
  • the “etching solution” includes a pasty etching paste.
  • step S8 the insulating layer 23 is etched. Specifically, the exposed portion of the insulating layer 23 is buffered with hydrofluoric acid from the amorphous semiconductor layers 13i and 13p including the amorphous semiconductor layers 24 and 25 partially removed by the etching in step S7. While removing by etching, the exposed portion 12n1 of the n-type amorphous semiconductor layer 12n is washed. As described above, in this embodiment, removal of a part of the insulating layer 23 and cleaning of the exposed portion 12n1 of the n-type amorphous semiconductor layer 12n are successively performed by buffered hydrofluoric acid. However, the present invention is not limited to this.
  • the exposed portion may be washed with buffered hydrofluoric acid.
  • examples of the etchant preferably used for removing the insulating layer 23 include an HF aqueous solution.
  • the insulating layer 23 may be removed using an etching gas. At this time, the insulating layer 16 is not etched at all or only slightly etched.
  • “buffered hydrofluoric acid” means an aqueous solution containing HF and NH 4 F.
  • the mixing ratio of HF and NH 4 F is not particularly limited.
  • the mixing ratio of HF and NH 4 F (HF: NH 4 F: water) can be set to, for example, about 8:33:59 to 0.2: 39.8: 60.
  • “buffered hydrofluoric acid” may contain a surfactant.
  • step S9 electrode formation for forming the n-side electrode 14 and the p-side electrode 15 on the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p, respectively.
  • the solar cell 1 can be completed by performing the process.
  • the formation method of the n-side electrode 14 and the p-side electrode 15 can be appropriately selected according to the material of the electrode. Specifically, in the present embodiment, the n-side electrode 14 and the p-side electrode 15 are formed as follows.
  • a conductive layer 26 made of TCO and a conductive layer 27 made of a metal such as Cu or an alloy are formed in this order by a thin film forming method such as a sputtering method.
  • the portions of the conductive layers 26 and 27 located on the insulating layer 18 are divided. Thereby, the first and second conductive layers 19a, 19b are formed from the conductive layers 26, 27.
  • the conductive layers 26 and 27 can be divided by, for example, a photolithography method.
  • the first and second conductive layers 19a and 19b formed on the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p, respectively, are made of Cu by plating.
  • the third conductive layer 19c and the fourth conductive layer 19d made of Sn the n-side electrode 14 and the p-side electrode 15 shown in FIG. 2 can be completed.
  • the exposed portion 12n1 of the n-type amorphous semiconductor layer 12n is washed with buffered hydrofluoric acid.
  • the solar cell 1 which has improved electric power generation efficiency can be manufactured so that it may be backed up also by the following Example. The following reasons can be considered as this reason.
  • the problem that the surface layer of the semiconductor layer is denatured hardly occurs.
  • the component of the insulating layer diffuses into the surface layer of the semiconductor layer, so that a layer having high electrical resistance is formed on the surface layer of the semiconductor layer. It may be formed.
  • the insulating layer is silicon nitride
  • the nitrogen component of the insulating layer may diffuse into the surface layer of the semiconductor layer, which may increase the electrical resistance of the surface layer of the semiconductor layer. Therefore, by treating the surface layer of the semiconductor layer with buffered hydrofluoric acid and cleaning the surface of the semiconductor layer, the electrical resistance between the semiconductor layer and the electrode can be lowered, resulting in improved power generation efficiency. Is considered to be realized.
  • the surface layer of the semiconductor layer is hardly soluble in hydrofluoric acid, and even when the insulating layer is etched with hydrofluoric acid, the surface layer of the semiconductor layer cannot be removed, so that greatly improved power generation efficiency cannot be obtained. Conceivable.
  • buffered hydrofluoric acid when buffered hydrofluoric acid is used, the surface layer of the semiconductor layer that is difficult to dissolve in hydrofluoric acid is easily dissolved in hydrofluoric acid due to NH 4 F contained in the buffered hydrofluoric acid. This surface layer is considered to be removable with buffered hydrofluoric acid.
  • the etching of the insulating layer 23 and the cleaning of the surface of the n-type amorphous semiconductor layer 12n are successively performed with buffered hydrofluoric acid. Therefore, the etching of the insulating layer 23 and the cleaning of the surface of the n-type amorphous semiconductor layer 12n can be performed in a short time with a small number of steps. Therefore, the solar cell 1 can be easily manufactured in a short time.
  • the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p are formed on the back surface 10b, and the electrodes 14 and 15 are provided on the back surface 10b side. There is no need to provide an electrode. Therefore, since the light receiving efficiency can be increased, a further improved power generation efficiency can be realized.
  • both end portions of the p-type amorphous semiconductor layer 13p are formed so as to overlap the n-type amorphous semiconductor layer 12n, and the substantially entire back surface 10b of the semiconductor substrate 10 is not n-type non-layered.
  • the crystalline semiconductor layer 12n and the p-type amorphous semiconductor layer 13p are covered. Therefore, minority carrier recombination hardly occurs, and high photoelectric conversion efficiency can be realized.
  • the insulating layer 18 is formed on the n-type amorphous semiconductor layer 12n out of the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p.
  • the semiconductor layer located under the insulating layer 18 is the n-type amorphous semiconductor layer 12n.
  • the p-side electrode 15 is formed on substantially the entire p-type amorphous semiconductor layer 13p. For this reason, holes that are minority carriers are easily collected by the p-side electrode 15. Therefore, the photoelectric conversion efficiency of the obtained solar cell 1 can be further increased.
  • the semiconductor substrate has a p-type conductivity type, minority carriers become electrons, and thus the first semiconductor layer located under the insulating layer is preferably formed of a p-type semiconductor.
  • the insulating layer 23 is formed of silicon oxide, silicon nitride, or silicon oxynitride. For this reason, the insulating layer 18 formed from the insulating layer 23 has a high gas barrier property. Therefore, the solar cell 1 excellent in weather resistance can be manufactured. From the viewpoint of realizing better weather resistance, the insulating layer 23 is more preferably formed of silicon nitride.
  • the third and fourth conductive layers 19c and 19d are formed by plating. Therefore, for example, the electrodes can be divided easily and in a shorter time than when the first to fourth conductive layers 19a to 19d are all formed and then divided into the n-side electrode 14 and the p-side electrode 15. it can.
  • the n-type amorphous semiconductor layer 12n and the p-type are separated when the first and second conductive layers 19a and 19b are divided.
  • the amorphous semiconductor layer 13p is not easily damaged.
  • the n-type amorphous semiconductor layer 12n and the p-type amorphous semiconductor layer 13p are insulated so that substantially the whole is covered with the insulating layer 18, the n-side electrode 14, and the p-side electrode 15.
  • the layer 18, the n-side electrode 14, and the p-side electrode 15 are formed. Therefore, according to the manufacturing method of the present embodiment, it is possible to manufacture the solar cell 1 that is more excellent in gas barrier properties and weather resistance.
  • FIG. 13 is a schematic cross-sectional view of the solar cell in the second embodiment.
  • a crystalline semiconductor substrate having n-type conductivity is used as the semiconductor substrate 10, and n-type amorphous semiconductor layers 12 n and p are formed on the semiconductor substrate 10.
  • the example in which the type amorphous semiconductor layer 13p is formed has been described. However, the present invention is not limited to this configuration.
  • the n-type dopant is thermally diffused into a part of the n-type crystalline semiconductor substrate 30 on the back surface 30b side, so that the back surface 30b of the crystalline semiconductor substrate 30 is highly doped.
  • the n + -type region 31n may be formed.
  • Example 1 A solar cell substantially similar to the solar cell 1 according to the first embodiment was manufactured by the method described in the first embodiment.
  • the series resistance and conversion efficiency of the manufactured solar cell were measured using a solar simulator manufactured by Wacom. The results are shown in Table 1 below.
  • the mixing ratio of HF and NH 4 F (HF: NH 4 F: water) is 1: 39.2: 59.8 in mass ratio, and HF Buffered hydrofluoric acid having a concentration of 1% by mass was used.
  • SYMBOLS 1 Solar cell 10 ... Semiconductor substrate 10a ... Light-receiving surface 10b ... Back surface 11 ... Light 12 ... IN laminated body 12i ... i-type amorphous semiconductor layer 12n ... n-type amorphous semiconductor layer 12n1 ... Exposed part 13 ... IP laminated body 13i ... i-type amorphous semiconductor layer 13p ... p-type amorphous semiconductor layer 14 ... n-side electrode 15 ... p-side electrode 16 ... insulating layer 17i ... i-type amorphous semiconductor layer 17n ... n-type amorphous semiconductor layer DESCRIPTION OF SYMBOLS 18 ...
  • Insulating layer 19a ... 1st conductive layer 19b ... 2nd conductive layer 19c ... 3rd conductive layer 19d ... 4th conductive layer 21 ... i-type amorphous semiconductor layer 22 ... n-type amorphous semiconductor layer 23 ... Insulating layer 24 ... i-type amorphous semiconductor layer 25 ... p-type amorphous semiconductor layer 26, 27 ... conductive layer 30 ... amorphous semiconductor substrate 30b ... back surface 31n ... n + type region

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

L'invention a pour but de mettre en œuvre un procédé de production de cellule solaire générant de l'électricité avec une efficacité accrue. On forme une première couche semi-conductrice (12n). On forme une couche d'isolation (23) sur la première couche semi-conductrice (12n). On expose une partie de la première couche semi-conductrice (12n) par élimination d'une partie de la couche d'isolation (23). On lave la partie (12n1) de la première couche semi-conductrice (12n) exposée à partir de la couche d'isolation (18) au moyen d'un acide hydrofluorique tamponné. On forme une première électrode (14) sur la partie (12n1) de la première couche semi-conductrice (12n) exposée à partir de la couche d'isolation (18).
PCT/JP2011/068879 2010-08-24 2011-08-22 Procédé de production de cellule solaire WO2012026428A1 (fr)

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EP2693488A1 (fr) * 2011-03-28 2014-02-05 Sanyo Electric Co., Ltd. Dispositif de conversion photoélectrique et son procédé de production
WO2015045242A1 (fr) * 2013-09-25 2015-04-02 パナソニックＩｐマネジメント株式会社 Cellule solaire, module de cellule solaire, et procédé de fabrication de cellule solaire
JP2015065337A (ja) * 2013-09-25 2015-04-09 三洋電機株式会社 太陽電池、太陽電池モジュールおよび太陽電池の製造方法
JP2015065338A (ja) * 2013-09-25 2015-04-09 三洋電機株式会社 太陽電池および太陽電池モジュール

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JPWO2012132835A1 (ja) * 2011-03-25 2014-07-28 三洋電機株式会社 太陽電池
WO2012132655A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Élément de conversion photoélectrique à jonction arrière et son procédé de fabrication
WO2012132654A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Élément de conversion photoélectrique à jonction arrière et son procédé de fabrication
WO2012132838A1 (fr) * 2011-03-25 2012-10-04 三洋電機株式会社 Procédé de production de dispositif de conversion photoélectrique
JPWO2013141232A1 (ja) * 2012-03-23 2015-08-03 パナソニックＩｐマネジメント株式会社 太陽電池及びその製造方法
KR101622090B1 (ko) * 2013-11-08 2016-05-18 엘지전자 주식회사 태양 전지
JP7101264B2 (ja) * 2019-01-18 2022-07-14 株式会社カネカ 太陽電池の製造方法

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