WO2012117825A1 - Cellule solaire et procédé de fabrication d'une cellule solaire - Google Patents

Cellule solaire et procédé de fabrication d'une cellule solaire Download PDF

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WO2012117825A1
WO2012117825A1 PCT/JP2012/052939 JP2012052939W WO2012117825A1 WO 2012117825 A1 WO2012117825 A1 WO 2012117825A1 JP 2012052939 W JP2012052939 W JP 2012052939W WO 2012117825 A1 WO2012117825 A1 WO 2012117825A1
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type
solar cell
semiconductor layer
side electrode
main surface
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Japanese (ja)
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博幸 森
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三洋電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a back junction solar cell and a method for manufacturing a back junction solar cell.
  • Patent Document 1 a so-called back junction type solar cell in which p-type and n-type semiconductor regions are formed on the back side of the solar cell has been proposed.
  • this back junction solar cell it is not necessary to provide an electrode on the light receiving surface side. For this reason, in the back junction solar cell, the light receiving efficiency can be increased. Therefore, higher power generation efficiency can be realized.
  • the present invention has been made in view of such a point, and an object thereof is to provide a solar cell having improved conversion efficiency and reliability with high yield.
  • the solar cell according to the present invention includes a solar cell substrate, an n-side electrode, a p-side electrode, and a semiconductor layer.
  • the solar cell substrate has a first main surface and a second main surface.
  • the first main surface includes an n-type surface and a p-type surface.
  • the n-side electrode is connected to the n-type surface.
  • the p-side electrode is connected to the p-type surface.
  • the semiconductor layer is disposed on the second main surface.
  • the semiconductor layer has a surface layer containing a p-type impurity.
  • a method for manufacturing a solar cell according to the present invention includes a solar cell substrate having a first main surface including an n-type surface and a p-type surface, and a second main surface, and an n-side electrode connected to the n-type surface. And a p-side electrode connected to the p-type surface, and a method for manufacturing a solar cell having a second main surface as a light-receiving surface.
  • the n-type surface, the p-type surface, the n-side electrode, and the p-side electrode are formed in a state where the second main surface of the semiconductor substrate is protected by the semiconductor layer containing the p-type impurity.
  • a solar cell having favorable reliability and photoelectric conversion efficiency can be provided with a good yield.
  • FIG. 1 is a schematic plan view of the solar cell according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • FIG. 3 is a flowchart showing the manufacturing process of the solar cell in the first embodiment.
  • FIG. 4 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 5 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the first embodiment.
  • FIG. 7 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 8 is a schematic cross-sectional view for explaining the manufacturing process of the solar cell in the first embodiment.
  • FIG. 9 is a schematic cross-sectional view of a solar cell according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the second embodiment.
  • FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the second embodiment.
  • FIG. 1 is a schematic plan view of a solar cell 1 according to the first embodiment.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG.
  • the solar cell 1 is a back junction solar cell.
  • the solar cell 1 includes a solar cell substrate 20.
  • the solar cell substrate 20 has a back surface 20a and a light receiving surface 20b.
  • the solar cell substrate 20 generates carriers (electrons and holes) by receiving light on the light receiving surface 20b.
  • the solar cell substrate 20 has a semiconductor substrate 10 having one conductivity type.
  • the semiconductor substrate 10 is configured by a substrate made of an n-type crystal semiconductor.
  • a specific example of the substrate made of an n-type crystal semiconductor is, for example, an n-type single crystal silicon substrate.
  • the semiconductor substrate 10 has first and second main surfaces 10a and 10b.
  • the first main surface 10 a of the semiconductor substrate 10 constitutes the light receiving surface 20 b of the solar cell substrate 20.
  • the light receiving surface 20b formed by the first main surface 10a has a texture structure.
  • the “texture structure” refers to a concavo-convex structure formed to suppress surface reflection and increase the light absorption amount of the photoelectric conversion unit.
  • Specific examples of the texture structure include a pyramidal (quadrangular pyramid or quadrangular frustum-shaped) uneven structure obtained by performing anisotropic etching on the surface of a single crystal silicon substrate having a (100) plane,
  • An example is a concavo-convex structure obtained by subjecting the surface of a crystalline silicon substrate or polycrystalline silicon substrate to isotropic etching by a method such as acid etching or dry etching.
  • An n-type semiconductor layer 12n is disposed on the first region of the second main surface 10b of the semiconductor substrate 10.
  • the n-type semiconductor layer 12n constitutes an n-type front surface 20an that constitutes a part of the back surface 20a.
  • the n-type semiconductor layer 12n is composed of an n-type amorphous semiconductor layer. More specifically, the n-type semiconductor layer 12n is composed of an n-type amorphous silicon layer containing hydrogen.
  • the thickness of the n-type semiconductor layer 12n can be, for example, about 20 to 500 mm.
  • a p-type semiconductor layer 13p is disposed on the second region of the second main surface 10b of the semiconductor substrate 10.
  • the p-type semiconductor layer 13p constitutes a p-type front surface 20ap that constitutes a part of the back surface 20a.
  • the p-type semiconductor layer 13p is composed of a p-type amorphous semiconductor layer. More specifically, the p-type semiconductor layer 13p is composed of a p-type amorphous silicon layer containing hydrogen.
  • the thickness of the p-type semiconductor layer 13p can be about 20 to 500 mm, for example.
  • an i-type semiconductor having a thickness that does not substantially contribute to power generation for example, about several to 250 inches, between each of the n-type semiconductor layer 12n and the p-type semiconductor layer 13p and the second main surface 10b.
  • Layers may be arranged.
  • the i-type semiconductor layer can be made of, for example, i-type amorphous silicon containing hydrogen.
  • a p-type semiconductor layer 13p is disposed on both end portions in the x direction of the n-type semiconductor layer 12n.
  • An insulating layer 18 is disposed between the overlapping portions in the z direction (thickness direction) of the n-type semiconductor layer 12n and the p-type semiconductor layer 13p.
  • the material of the insulating layer 18 is not particularly limited.
  • the insulating layer 18 can be composed of, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. Especially, it is preferable that the insulating layer 18 is comprised by the silicon nitride film.
  • the insulating layer 18 preferably contains hydrogen.
  • the n-side electrode 14 is disposed on the n-type surface 20an constituted by the n-type semiconductor layer 12n.
  • the n-side electrode 14 is electrically connected to the n-type surface 20an.
  • a p-side electrode 15 is disposed on the p-type surface 20ap constituted by the p-type semiconductor layer 13p.
  • the p-side electrode 15 is electrically connected to the p-type surface 20ap.
  • the n-side electrode 14 and the p-side electrode 15 collect electrons and holes, respectively.
  • the n-side electrode 14 and the p-side electrode 15 are electrically separated on the surface of the insulating layer 18.
  • each of the n-side electrode 14 and the p-side electrode 15 has a comb shape, and the n-side electrode 14 and the p-side electrode 15 are interleaved with each other.
  • the present invention is not limited to this configuration.
  • At least one of the n-side electrode and the p-side electrode may be a so-called bus bar-less electrode that does not include the bus bar portion and includes a plurality of finger portions.
  • Each of the n-side electrode 14 and the p-side electrode 15 is, for example, a transparent conductive oxide (TCO), a metal such as Ag, Cu, Sn, Pt, or Au, or one or more of these metals It can be formed of a conductive material such as an alloy containing
  • each of the n-side electrode 14 and the p-side electrode 15 may be configured by a stacked body of a plurality of conductive layers, for example.
  • each of the n-side electrode 14 and the p-side electrode 15 includes a TCO layer formed on the n-type or p-type semiconductor layers 12n and 13p, and at least one metal or alloy formed thereon. It is preferable that it is comprised by the laminated body with a layer.
  • each of the n-side electrode 14 and the p-side electrode 15 is not particularly limited.
  • Each of the n-side electrode 14 and the p-side electrode 15 can be formed by, for example, a thin film forming method such as a sputtering method, a CVD method, or a vapor deposition method, a plating method, or a combination thereof.
  • a semiconductor layer 17 having a surface layer containing a p-type impurity is disposed on the first main surface 10b.
  • the “p-type impurity” refers to a substance that can make a semiconductor layer have a p-type conductivity by being contained in a predetermined amount in the semiconductor layer.
  • Specific examples of p-type impurities include trivalent elements such as boron and aluminum when the semiconductor layer is made of a tetravalent semiconductor material such as silicon.
  • the surface layer containing a p-type impurity may be a p-type conductivity layer or an i-type conductivity layer. That is, the surface layer containing the p-type impurity may contain the p-type impurity to the extent that the p-type is expressed, or may contain the p-type impurity to the extent that the p-type is not expressed.
  • the semiconductor layer 17 is composed of an amorphous semiconductor layer. More specifically, in the present embodiment, the semiconductor layer 17 includes an i-type amorphous semiconductor layer 17i, an n-type amorphous semiconductor layer 17n, and an amorphous semiconductor layer 17p.
  • the i-type amorphous semiconductor layer 17i is disposed on the light receiving surface 20b.
  • the i-type amorphous semiconductor layer 17i can be made of, for example, i-type amorphous silicon containing hydrogen.
  • the thickness of the i-type amorphous semiconductor layer 17i is not particularly limited as long as the thickness does not substantially contribute to power generation.
  • the thickness of the i-type amorphous semiconductor layer 17i can be, for example, about several to 250 inches.
  • the n-type amorphous semiconductor layer 17 n is a semiconductor layer having the same conductivity type as the semiconductor substrate 10.
  • the n-type amorphous semiconductor layer 17n is disposed on the i-type amorphous semiconductor layer 17i.
  • the n-type amorphous semiconductor layer 17n can be composed of, for example, n-type amorphous silicon containing hydrogen.
  • the thickness of the n-type amorphous semiconductor layer 17n is not particularly limited. The thickness of the n-type amorphous semiconductor layer 17n can be, for example, about 20 to 500 mm.
  • An amorphous semiconductor layer 17p is disposed on the n-type amorphous semiconductor layer 17n.
  • the amorphous semiconductor layer 17p contains p-type impurities and constitutes a surface layer containing the p-type impurities.
  • the amorphous semiconductor layer 17p can be made of, for example, amorphous silicon containing p-type impurities and hydrogen.
  • the thickness of the amorphous semiconductor layer 17p is preferably 10 mm or more, and more preferably 20 mm or more.
  • the upper limit of the thickness of the amorphous semiconductor layer 17p is not particularly limited, but is preferably 500 mm, for example. This is because if the thickness of the amorphous semiconductor layer 17p exceeds 500 mm, light absorption by the amorphous semiconductor layer 17p becomes too large, and the photoelectric conversion characteristics may be deteriorated.
  • a protective film 16 is disposed on the semiconductor layer 17.
  • the protective film 16 also has a function as a reflection suppressing film.
  • the protective film 16 can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like. Especially, it is preferable that the protective film 16 is comprised by the silicon nitride film.
  • the thickness of the protective film 16 can be set to, for example, about 80 nm to 1 ⁇ m.
  • the solar cell 1 of the present embodiment can receive light over the entire light receiving surface 20b.
  • FIG. 3 is a flowchart showing the manufacturing process of the solar cell of this embodiment.
  • FIG. 4 is a schematic cross-sectional view for explaining steps S1 and S2.
  • FIG. 5 is a schematic cross-sectional view for explaining step S3.
  • FIG. 6 is a schematic cross-sectional view for explaining step S4.
  • FIG. 7 is a schematic cross-sectional view for explaining step S5.
  • FIG. 8 is a schematic cross-sectional view for explaining step S6.
  • a semiconductor substrate 10 having a first main surface 10a having a texture structure is prepared.
  • the semiconductor layer 17 and the protective film 16 are formed on substantially the entire surface or the entire first main surface 10a of the semiconductor substrate 10 (first forming process).
  • Each of the i-type amorphous semiconductor layer 17i, the n-type amorphous semiconductor layer 17n, the amorphous semiconductor layer 17p, and the protective film 16 is formed by, for example, a CVD (Chemical Vapor Deposition) method typified by a plasma CVD method. It can be formed by a thin film forming method.
  • step S1 which is the first formation process
  • a second formation process for forming the semiconductor layers 12n and 13p, the insulating layer 18, and the electrodes 14 and 15 is performed.
  • Step S2 to Step S7 are performed in the second formation process.
  • an n-type amorphous semiconductor film 21 and an insulating film 22 are formed in this order on substantially the entire surface or the entire second main surface 10b of the semiconductor substrate 10.
  • the n-type amorphous semiconductor layer 21 can be formed, for example, by a thin film forming method such as a CVD (Chemical Vapor Deposition) method typified by a plasma CVD method.
  • the insulating film 22 can be formed by, for example, a thin film forming method such as a sputtering method or a CVD method.
  • step S3 the n-type amorphous semiconductor film 21 and the insulating film 22 are etched.
  • the etchant suitably used for etching the n-type amorphous semiconductor film 21 include a hydrofluoric acid aqueous solution.
  • etching agent that is preferably used for etching the insulating film 22 include, for example, an HF aqueous solution. That is, in step S3, the step of etching the insulating film 22 is preferably an etching step using an alkaline etchant.
  • the “etching agent” includes an etching solution, an etching paste, an etching ink, and the like.
  • a p-type semiconductor film 23 is formed on substantially the entire surface of the second main surface 10b including the surface of the insulating film 22 or on the entire surface.
  • the method for forming the p-type semiconductor film 23 is not particularly limited.
  • the p-type semiconductor film 23 can be formed by a thin film forming method such as a CVD method, for example.
  • step S5 a part of the portion located on the insulating film 22 of the p-type semiconductor layer 23 is removed by etching or the like.
  • the p-type semiconductor layer 13p is formed from the p-type semiconductor film 23.
  • the etchant preferably used for etching the p-type semiconductor film 23 include an alkaline aqueous solution such as a NaOH aqueous solution containing NaOH, a hydrofluoric acid aqueous solution, and the like. That is, the etching process of the p-type semiconductor layer 23 in step S5 is preferably an etching process using an alkaline etchant.
  • step S6 a part of the surface of the n-type semiconductor layer 12n is exposed by removing the exposed portion of the insulating film 22 by etching with an etchant using the p-type semiconductor layer 13p as a mask.
  • the insulating layer 18 is formed from the insulating film 22, and a part of the n-type semiconductor layer 12n is exposed.
  • the etchant preferably used for etching the insulating film 22 include, for example, an HF aqueous solution.
  • step S7 the solar cell 1 is completed by performing an electrode forming step of forming the n-side electrode 14 and the p-side electrode 15 on the n-type semiconductor layer 12n and the p-type semiconductor layer 13p, respectively. Can do.
  • the formation method of the n-side electrode 14 and the p-side electrode 15 can be appropriately selected according to the material of the electrode.
  • the n-side electrode 14 and the p-side electrode 15 are formed by, for example, a thin film forming method such as sputtering, CVD, or vapor deposition, plating, a method of applying a conductive paste, or a method combining these methods. Can do.
  • the n-side electrode 14 and the p-side electrode 15 may be formed, for example, by dividing a conductive film formed so as to cover the n-type semiconductor layer 12n and the p-type semiconductor layer 13p on the insulating layer 18. . In this case, the n-side electrode 14 and the p-side electrode 15 can be formed with a narrow pitch and high shape accuracy.
  • a plurality of layers such as patterned n-type and p-type semiconductor layers must be formed on the back surface.
  • the formation process of the patterned n-type and p-type semiconductor layers and the like usually involves an etching process.
  • an etching process of a semiconductor layer such as an amorphous silicon layer is performed using an alkaline etchant.
  • the reliability of the manufactured solar cell may be lowered, or the initial photoelectric conversion efficiency may be lowered. In addition, this may reduce the manufacturing yield.
  • a silicon nitride film as a protective film may be formed in advance on the light receiving surface, and then an n-side and p-type semiconductor layer may be formed on the back surface.
  • a protective film such as a silicon nitride film without any pinholes.
  • there are some pinholes in the protective film even if the protective film is previously formed on the light receiving surface, it is difficult to reliably suppress damage to the light receiving surface due to the etching agent. Therefore, even when a protective film is formed on the light receiving surface in advance, it is difficult to manufacture a solar cell having favorable reliability and photoelectric conversion efficiency with a good yield.
  • the semiconductor layer 17 having a surface layer containing a p-type impurity is disposed on the light receiving surface 20b.
  • the semiconductor layer having a surface layer containing p-type impurities is denser than a silicon nitride film or the like and has few pinholes.
  • a semiconductor layer having a surface layer containing a p-type impurity has low solubility in an alkaline etchant. Therefore, the solar cell 1 of this embodiment can be manufactured in a state where damage to the light receiving surface 20b is suppressed by forming the semiconductor layer 17 in advance prior to the second forming step. Therefore, in the solar cell 1 of the present embodiment, preferable reliability and photoelectric conversion efficiency can be realized with improved yield.
  • a p-type hydrogenated amorphous silicon layer can be preferably used.
  • a protective film 16 made of a silicon nitride film is further formed on the semiconductor layer 17. For this reason, damage to the light receiving surface 20b due to the etching agent can be more suitably suppressed. Therefore, more preferable reliability and photoelectric conversion efficiency can be realized with an improved yield.
  • the etching agent can be prevented from reaching the semiconductor layer 17 as compared with the case where the protective film is not formed. Therefore, even when a protective film other than the silicon nitride film is formed, preferable reliability and photoelectric conversion efficiency can be realized with improved yield.
  • Such an effect is obtained regardless of the properties of the light receiving surface 20b, but is particularly prominent when the light receiving surface 20b has a texture structure. This is because when the light receiving surface 20b has a texture structure, pinholes are more easily formed in the protective film.
  • FIG. 9 is a schematic cross-sectional view of a solar cell according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the second embodiment.
  • FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in the second embodiment.
  • the present invention is not limited to this configuration.
  • the solar cell substrate 20 is constituted by the semiconductor substrate 10.
  • the semiconductor substrate 10 is provided with an n-type dopant diffusion region 31n and a p-type dopant diffusion region 31p.
  • the n-type dopant diffusion region 31n is provided so as to be exposed to the second main surface 10b constituting the back surface 20a.
  • the n-type dopant diffusion region 31n constitutes the n-type surface 20an.
  • the p-type dopant diffusion region 31p is provided so as to be exposed on the second main surface 10b.
  • the p-type dopant diffusion region 31p constitutes the p-type surface 20ap.
  • the solar cell includes the insulating layer 18 disposed on the back surface 20a. This insulating layer 18 isolates the p-side electrode 15 and the n-side electrode 14.
  • the solar cell of this embodiment can be manufactured, for example, in the following manner.
  • a p-type dopant is diffused from a part of the second main surface 10b of the semiconductor substrate 10, and an n-type dopant is diffused from at least a part of the remaining part.
  • the p-type dopant diffusion region 31p and the n-type dopant diffusion region 31n are formed in the semiconductor substrate 10, and the solar cell substrate 20 is obtained.
  • the semiconductor layer 17 and the protective film 16 are formed.
  • the semiconductor layer 17 and the protective film 16 can be formed in the same manner as in the first embodiment.
  • the semiconductor layer 17 and the protective film 16 may be performed prior to the production of the solar cell substrate 20.
  • an insulating film 22 is formed on the second main surface 10 b of the semiconductor substrate 10.
  • At least a portion of the insulating film 22 located on the p-type dopant diffusion region 31p and the n-type dopant diffusion region 31n is removed by etching, and the p-type dopant diffusion region 31p and The n-type dopant diffusion region 31n is exposed.
  • a solar cell can be completed by forming the n-side electrode 14 and the p-side electrode 15 on the p-type dopant diffusion region 31p and the n-type dopant diffusion region 31n.
  • Example 1 Two samples 1 in which an i-type amorphous silicon layer having a thickness of 5.4 nm and an n-type amorphous silicon layer having a thickness of 8.5 nm were formed in this order on a substrate were produced.
  • the sample 1 was immersed in a 0.4% by mass NaOH aqueous solution at 25 ° C., and the time required until the i-type and n-type amorphous silicon layers disappeared was measured. As a result, the time required until the i-type and n-type amorphous silicon layers disappeared was 5 minutes.
  • the sample 2 was immersed in a 4 mass% NaOH aqueous solution at 50 ° C., and the time required until the i-type and p-type amorphous silicon layers disappeared was measured. As a result, the time required until the i-type and p-type amorphous silicon layers disappeared was 10 minutes.
  • the amorphous silicon layer was used in spite of using an etching solution in which the thicknesses of the p-type and i-type amorphous silicon layers were thinner than those of the experimental example 1 and higher than the experimental example 1. It took a long time to disappear. From this result, it can be seen that p-type amorphous silicon is less likely to be etched by an alkaline etchant than n-type amorphous silicon.
  • the present invention includes various embodiments that are not described here.
  • the example in which the semiconductor layer 17 includes the i-type amorphous semiconductor layer 17i, the n-type amorphous semiconductor layer 17n, and the amorphous semiconductor layer 17p has been described. Not limited to this.
  • the semiconductor layer 17 may be a stacked structure of the i-type amorphous semiconductor layer 17i and the amorphous semiconductor layer 17p, or may be a single layer of the amorphous semiconductor layer 17p.

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  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • General Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Sustainable Energy (AREA)
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Abstract

La présente invention vise à procurer une cellule solaire ayant une efficacité et une fiabilité de conversion améliorées à rendement élevé. La cellule solaire (1) comprend un substrat de cellule solaire (20), une électrode côté n (14), une électrode côté p (15) et une couche semi-conductrice (17). Le substrat de cellule solaire (20) présente une première surface principale (20a) et une seconde surface principale (20b). La première surface principale (20a) contient une surface de type n (20an) et une surface de type p (20ap). L'électrode côté n (14) est connectée à la surface de type n (20an). L'électrode de côté p (15) est connectée à la surface de type p (20ap). La couche semi-conductrice (17) est disposée sur la seconde surface principale (20b). La couche semi-conductrice (17) présente une couche de surface contenant une impureté de type p.
PCT/JP2012/052939 2011-02-28 2012-02-09 Cellule solaire et procédé de fabrication d'une cellule solaire WO2012117825A1 (fr)

Applications Claiming Priority (2)

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JP2011-042124 2011-02-28
JP2011042124A JP2012182167A (ja) 2011-02-28 2011-02-28 太陽電池及び太陽電池の製造方法

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WO2012117825A1 true WO2012117825A1 (fr) 2012-09-07

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JP7101264B2 (ja) * 2019-01-18 2022-07-14 株式会社カネカ 太陽電池の製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11112011A (ja) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd 光起電力素子の製造方法
JP2003298078A (ja) * 2002-03-29 2003-10-17 Ebara Corp 光起電力素子

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11112011A (ja) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd 光起電力素子の製造方法
JP2003298078A (ja) * 2002-03-29 2003-10-17 Ebara Corp 光起電力素子

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