WO2012098635A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2012098635A1 WO2012098635A1 PCT/JP2011/050676 JP2011050676W WO2012098635A1 WO 2012098635 A1 WO2012098635 A1 WO 2012098635A1 JP 2011050676 W JP2011050676 W JP 2011050676W WO 2012098635 A1 WO2012098635 A1 WO 2012098635A1
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Definitions
- the present invention relates to a semiconductor device and a manufacturing method thereof.
- GaN which is a compound semiconductor with a wide band gap
- GaN which is a compound semiconductor with a wide band gap
- the Schottky barrier diode (SBD) is superior to the pn diode in terms of high-speed response and low loss. For this reason, SBD using GaN (GaN-based SBD) is expected as a next-generation low power consumption power device.
- An object of the present invention is to provide a semiconductor device capable of achieving both a low on-voltage and a high off-breakdown voltage and a method for manufacturing the same.
- a semiconductor layer and a Schottky electrode that is in Schottky junction with the semiconductor layer are provided.
- the Schottky electrode includes a metal portion including a metal that is Schottky-bonded to the semiconductor layer, and a nitride portion that is formed around the metal portion and includes the metal nitride, and is Schottky-bonded to the semiconductor layer. And are included.
- a semiconductor device is provided in one embodiment of the power supply device.
- the semiconductor device includes a semiconductor layer and a Schottky electrode that is in Schottky junction with the semiconductor layer.
- the Schottky electrode includes a metal portion including a metal that is Schottky-bonded to the semiconductor layer, and a nitride portion that is formed around the metal portion and includes the metal nitride, and is Schottky-bonded to the semiconductor layer. And are included.
- a metal film that is Schottky-bonded to a semiconductor layer is formed, a peripheral portion of the metal film is nitrided, and a metal part that is Schottky-bonded to the semiconductor layer from the metal film And a nitride portion located around the metal portion and Schottky-bonded to the semiconductor layer.
- the on-voltage can be lowered by the metal part included in the Schottky electrode, and the off-breakdown voltage can be improved by the nitride part.
- FIG. 1A is a plan view showing the structure of the semiconductor device according to the first embodiment.
- 1B is a cross-sectional view taken along the line II in FIG. 1A.
- FIG. 2A is a diagram illustrating a relationship between conduction bands of a metal film and a semiconductor layer.
- FIG. 2B is a diagram illustrating the relationship between the conduction bands of the nitride film and the semiconductor layer.
- FIG. 3A is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment.
- FIG. 3B is a diagram illustrating the relationship between the conduction bands of the nitride film and the semiconductor layer.
- FIG. 4 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment.
- FIG. 5A is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 5B is a cross-sectional view illustrating a method for manufacturing the semiconductor device following FIG. 5A.
- FIG. 5C is a cross-sectional view illustrating a method for manufacturing the semiconductor device following FIG. 5B.
- FIG. 5D is a cross-sectional view illustrating a method for manufacturing the semiconductor device, following FIG. 5C.
- FIG. 5E is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 5D.
- FIG. 5F is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 5E.
- FIG. 5A is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the third embodiment.
- FIG. 5B is a cross-sectional view illustrating a method for manufacturing the semiconductor device following FIG. 5A.
- FIG. 5C is a cross-sectional view illustrating
- FIG. 6A is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the fourth embodiment.
- 6B is a cross-sectional view illustrating a method for manufacturing the semiconductor device, following FIG. 6A.
- 6C is a cross-sectional view illustrating a method for manufacturing the semiconductor device, following FIG. 6B.
- FIG. 7A is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the fifth embodiment.
- FIG. 7B is a cross-sectional view illustrating a method for manufacturing the semiconductor device following FIG. 7A.
- FIG. 7C is a cross-sectional view illustrating a method for manufacturing the semiconductor device, following FIG. 7B.
- FIG. 7D is a cross-sectional view illustrating a method for manufacturing the semiconductor device, following FIG. 7C.
- FIG. 7E is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7D.
- FIG. 7F is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7E.
- FIG. 7G is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7F.
- FIG. 7H is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7G.
- FIG. 7I is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7H.
- FIG. 7J is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7I.
- FIG. 7I is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7I.
- FIG. 7K is a cross-sectional view illustrating a method for manufacturing the semiconductor device, following FIG. 7J.
- FIG. 7L is a cross-sectional view showing a method for manufacturing the semiconductor device, following FIG. 7K.
- FIG. 8A is a diagram showing a layout of electrodes.
- FIG. 8B is a diagram illustrating a wiring layout.
- FIG. 9 is a diagram showing a modification of the layout.
- FIG. 10 is a diagram showing an SBD package including a GaN-based SBD.
- FIG. 11 is a diagram showing a PFC circuit including the SBD package shown in FIG.
- FIG. 12 is a diagram showing a server power supply including the PFC circuit shown in FIG.
- FIG. 1A is a plan view showing the structure of the semiconductor device (Schottky barrier diode) according to the first embodiment
- FIG. 1B is a cross-sectional view taken along the line II in FIG. 1A.
- the Schottky electrode 2 is formed on the semiconductor layer 1 as shown in FIGS. 1A and 1B.
- An ohmic electrode 3 is formed on the back surface of the semiconductor layer 1.
- the Schottky electrode 2 includes a metal film 2 a containing a metal that is in Schottky junction with the semiconductor layer 1 and a nitride film 2 b that is formed around the metal film 2 a and is in Schottky junction with the semiconductor layer 1.
- the nitride film 2b contains a metal nitride contained in the metal film 2a. That is, the nitride film 2b contains a material having a work function lower than that of the material contained in the metal film 2a.
- nitride film 2b can be formed by nitriding the same material as the metal film 2a, for example, it is possible to avoid a decrease in cleanliness as in the case of combining two kinds of metals. Therefore, high reliability can be ensured.
- each ratio of the metal film 2a and the nitride film 2b in the Schottky electrode 2 is not particularly limited, but the area of the metal film 2a is preferably larger than the area of the nitride film 2b in plan view.
- FIG. 3A is a cross-sectional view showing the structure of the semiconductor device (Schottky barrier diode) according to the second embodiment, and shows a cross section taken along line II in FIG. 1A.
- the high resistance region 4 is formed in a portion of the semiconductor layer 1 that is joined to the nitride film 2b.
- the resistance of the high resistance region 4 is higher than the resistance of the portion of the semiconductor layer 1 that joins the metal film 2a.
- Other configurations are the same as those of the first embodiment.
- the spread of the depletion layer when the reverse bias is applied becomes larger. Therefore, as shown in FIG. 3B, even if the Schottky barrier height is about the same as that of the first embodiment, the change of the conduction band in the high resistance region 4 and the semiconductor layer 1 is that of the first embodiment ( It becomes gentler than the broken line in FIG. 3B, and a higher off-breakdown voltage can be obtained.
- FIG. 4 is a sectional view showing the structure of a semiconductor device (Schottky barrier diode) according to the third embodiment.
- an n-type GaN layer 11b is formed on an n-type GaN substrate 11a.
- the GaN substrate 11a is doped with 5 ⁇ 10 17 cm ⁇ 3 of Si as an n-type impurity, for example.
- the GaN layer 11b is doped with 1 ⁇ 10 16 cm ⁇ 3 of Si as an n-type impurity, for example.
- the thickness of the GaN layer 11b is, for example, about 1 ⁇ m.
- a GaN substrate 11 a and a GaN layer 11 b are included in the semiconductor layer 11.
- a passivation film 15 is formed on the GaN layer 11b. In the passivation film 15, an opening 15a for an anode electrode is formed. As the passivation film 15, for example, a silicon nitride film having a thickness of about 400 nm is formed.
- An anode electrode 12 (Schottky electrode) is formed in the opening 15a.
- the anode electrode 12 includes a Ti film 12a that is Schottky-bonded to the GaN layer 11b, and a TiN film 12b that is formed around the Ti film 12a and is Schottky-bonded to the GaN layer 11b.
- the work function of the TiN film 12b is lower than that of the Ti film 12a.
- the thickness of the Ti film 12a and the TiN film 12b is about 1 ⁇ m. The end portion of the TiN film 12b runs over the passivation film 15.
- a cathode electrode 13 (ohmic electrode) is formed on the back surface of the GaN substrate 11a.
- a cathode electrode 13 for example, a laminated film of a Ti film having a thickness of about 10 nm and an Al film having a thickness of about 300 nm is formed.
- a high resistance region 14 is formed at a portion of the GaN layer 11b where the TiN film 12b is joined.
- the resistance of the high resistance region 14 is higher than the resistance of the portion of the GaN layer 11b that joins the Ti film 12a.
- the Schottky barrier height between the TiN film 12b and the semiconductor layer 11 is higher than the Schottky barrier height between the Ti film 12a and the semiconductor layer 11. Therefore, when a forward bias is applied, a current flows between the Ti film 12 a and the semiconductor layer 11 before the TiN film 12 b and the semiconductor layer 11. For this reason, the on-voltage can be reduced. Further, when a reverse bias is applied, a depletion layer spreads from the TiN film 12 b to the semiconductor layer 11 very greatly due to a synergistic effect with the high resistance region 14. For this reason, a sufficient off breakdown voltage can be obtained. That is, according to the third embodiment, both a low on-voltage and a high off-breakdown voltage can be achieved.
- 5A to 5F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the third embodiment in the order of steps.
- an n-type GaN layer 11b is formed on an n-type GaN substrate 11a.
- the GaN layer 11b is epitaxially grown by, for example, a metal-organic chemical vapor deposition (MOCVD) method.
- MOCVD metal-organic chemical vapor deposition
- the cathode electrode 13 is formed on the back surface of the GaN substrate 11a.
- a Ti film is formed on the back surface of the GaN substrate 11a by, for example, vapor deposition, an Al film is formed thereon, and RTA (rapid thermal annealing) at about 700 ° C. is performed.
- RTA rapid thermal annealing
- a passivation film 15 is formed on the GaN layer 11b, and an opening 15a for an anode electrode is formed in the passivation film 15.
- a silicon nitride film is formed by, for example, a CVD method.
- forming the opening 15a for example, dry etching using a fluorine-based gas is performed.
- a Ti film 10 whose edge runs over the passivation film 15 is formed in the opening 15a.
- the Ti film 10 can be formed by, for example, a lift-off method. That is, by forming a resist mask that opens a region where the Ti film 10 is to be formed, depositing the Ti film, and removing the resist mask together with the Ti film thereon, the Ti film 10 can be obtained in a desired region. .
- a region where the TiN film 12b is to be formed and a region where the high resistance region 14 is to be formed for example, a mask 101 which opens the peripheral portion of the Ti film 10 is formed.
- the mask 101 for example, a photoresist mask is formed.
- nitrogen is ion-implanted into the Ti film 10 and the GaN layer 11b.
- this ion implantation it is preferable to employ such a condition that the peak of the implantation depth appears at the interface between the Ti film 10 and the GaN layer 11b or at a position slightly deeper than this interface.
- ion implantations may be performed: ion implantation in which the peak of the implantation depth appears in the Ti film 10 and ion implantation in which the peak of the implantation depth appears in the GaN layer 11b.
- ion implantation conditions can be changed, for example, by adjusting acceleration energy.
- the nitrogen ion implanted portion of the Ti film 10 becomes the TiN film 12b, and the inner portion thereof remains as the Ti film 12a. Further, the resistance of the portion of the GaN layer 11b where nitrogen is ion-implanted increases, and the high resistance region 14 is formed here. Then, if the mask 101 is removed, the structure shown in FIG. 4 is obtained.
- the TiN film 12b is formed by nitriding the Ti film 10, and the remainder of the Ti film 10 is used as the Ti film 12a. Therefore, it is not necessary to form a metal film after the Ti film 10 is formed, and sufficient cleanliness can be obtained if a cleaning process is performed before the Ti film 10 is formed. For this reason, high reliability can also be ensured.
- plasma treatment may be performed instead of ion implantation when the Ti film 10 is nitrided and the high resistance region 14 is formed. That is, a process of exposing a portion exposed from the opening of the mask 101 to N 2 plasma may be performed.
- a Ta film and a TaN film may be used instead of the Ti film and the TiN film.
- the carrier concentration of the GaN substrate 11a and the GaN layer 11b, the thickness of the GaN layer 11b, and the like may be appropriately changed according to characteristics such as an off breakdown voltage and an on resistance required for the Schottky barrier diode.
- the GaN layer 11b a layer in which a plurality of GaN-based semiconductor (for example, GaN and AlGaN) films are stacked may be used.
- FIGS. 6A to 6C are cross-sectional views showing a method of manufacturing a semiconductor device according to the fourth embodiment in the order of steps.
- an n-type GaN layer 21b is formed on an n-type GaN substrate 21a.
- the GaN substrate 21 a and the GaN layer 21 b are included in the semiconductor layer 21.
- the cathode electrode 23 is formed on the back surface of the GaN substrate 21a.
- a passivation film 25 is formed on the GaN layer 21b, and a plurality of openings 25a for anode electrodes are formed in the passivation film 25.
- a Ti film with an edge running over the passivation film 25 is formed in each opening 25a, and nitrogen ion implantation is performed using a mask.
- a Ti film 22a that is Schottky-bonded to the GaN layer 21b and an anode electrode 22 that is formed around the Ti film 22a and includes the TiN film 22b that is Schottky-bonded to the GaN layer 21b are formed.
- a high resistance region 24 having a higher resistance than that of the portion of the GaN layer 21b that joins the Ti film 22a is formed in the portion of the GaN layer 21b that joins the TiN film 22b.
- a polyimide film 26 that exposes the Ti film 22a and the TiN film 22b and covers the passivation film 25 is formed.
- an anode wiring 27 for commonly connecting the anode electrodes 22 is formed on the polyimide film 26.
- the anode wiring 27 for example, an Al film having a thickness of about 2 ⁇ m is formed.
- the cathode electrode 23 may be die-attached to a lead frame with Ag paste or the like, and the anode wiring 27 may be connected to the lead frame via an Al wire or the like.
- the same mounting is possible if the anode wiring connected to the anode electrode 12 is formed.
- a fifth embodiment Next, a fifth embodiment will be described.
- a GaN-based SBD and a GaN-based high electron mobility transistor (HEMT) are formed on the same substrate.
- 7A to 7L are cross-sectional views showing a method of manufacturing the semiconductor device according to the fifth embodiment in the order of steps.
- a buffer layer 42, a non-doped i-GaN layer 43, and an n-type n-AlGaN layer 31 are formed on a substrate 41 by, for example, MOCVD.
- the substrate 41 for example, a semi-insulating SiC substrate, a semi-insulating Si substrate, a sapphire substrate, or the like can be used.
- the buffer layer 42 for example, a GaN layer or an AlGaN layer having a thickness of about 100 nm is formed.
- the thickness of the i-GaN layer 43 is about 2 ⁇ m
- the thickness of the n-AlGaN layer 31 is about 20 nm.
- an element isolation region 44 that defines a region 51 in which a GaN-based HEMT is to be formed and a region 52 in which a GaN-based SBD is to be formed is formed.
- Ar ions may be implanted deeper than the heterojunction interface between the i-GaN layer 43 and the n-AlGaN layer 31. By such ion implantation, the two-dimensional electron gas (2DEG) present in the surface layer portion of the i-GaN layer 43 is divided.
- a passivation film 35 is formed on the n-AlGaN layer 31, and a plurality of openings 35a for the anode electrode, a plurality of openings 35c for the cathode electrode, and a gate electrode are formed in the passivation film 35.
- the plurality of openings 35g, the plurality of openings 35s for the source electrode, and the plurality of openings 35d for the drain electrode are formed.
- As the passivation film 35 a silicon nitride film having a thickness of about 400 nm is formed by, for example, a CVD method. In forming the openings 35a, 35c, 35g, 35s, and 35d, for example, dry etching using a fluorine-based gas is performed.
- the cathode electrode 33 is formed in the opening 35c, the source electrode 45s is formed in the opening 35s, and the drain electrode 45d is formed in the opening 35d.
- the cathode electrode 33, the source electrode 45s, and the drain electrode 45d can be formed by, for example, a lift-off method. That is, a resist mask that opens regions for forming the cathode electrode 33, the source electrode 45s, and the drain electrode 45d is formed, for example, a Ti film having a thickness of about 10 nm and an Al film having a thickness of about 300 nm are deposited. The resist mask is removed together with the Ti film and Al film thereon. Then, RTA at about 700 ° C. is performed. The RTA establishes ohmic contact between the cathode electrode 33, the source electrode 45s, and the drain electrode 45d.
- a gate electrode 45g is formed in the opening 35g.
- the gate electrode 45g can be formed by, for example, a lift-off method. That is, a resist mask that opens a region for forming the gate electrode 45g is formed, for example, a Ni film with a thickness of about 10 nm and an Au film with a thickness of about 200 nm are deposited, and the resist mask is formed with a Ni film and an Au film thereon. Remove with membrane.
- a Ti film 40 whose edge runs over the passivation film 35 is formed in the opening 35a.
- the Ti film 40 can be formed by, for example, a lift-off method. That is, if a resist mask that opens a region for forming the Ti film 40 is formed, the Ti film is deposited, and the resist mask is removed together with the Ti film thereon, the Ti film 40 can be obtained in a desired region. .
- a mask 111 that opens near the periphery of the Ti film 40 is formed.
- the mask 111 for example, a photoresist mask is formed.
- nitrogen is ion-implanted into the Ti film 40 and the n-AlGaN layer 31 as in the third embodiment.
- the nitrogen ion implanted portion of the Ti film 40 becomes the TiN film 32b, and the inner portion remains as the Ti film 32a.
- a Ti film 32 a and a TiN film 32 b are included in the anode electrode 32. Further, the resistance of the portion of the n-AlGaN layer 31 where nitrogen is ion-implanted increases, and a high resistance region 34 is formed here.
- an Au seed layer 46 is formed on the entire surface by sputtering.
- a mask for example, a resist mask
- predetermined openings exposing portions on the anode electrode 32, the cathode electrode 33, the gate electrode 45g, the source electrode 45s, and the drain electrode 45d are formed on the Au seed layer 46.
- an Au film 47 having a thickness of about 10 ⁇ m is formed by plating.
- the mask 112 is removed, and the Au seed layer 46 exposed from the Au film 47 is removed by an ion milling method or the like.
- a drain wiring 48d that commonly connects the drain electrodes 45d is provided to the source electrode 45s.
- the photosensitive polyimide film 36 is formed on the passivation film 35 so as to expose the relay wiring layer 48a and the relay wiring layer 48s and cover the cathode wiring 48c, the gate wiring 48g, and the drain wiring 48d. .
- an anode wiring 37a that commonly connects the relay wiring layers 48a and a source wiring 37s that commonly connects the relay wiring layers 48s are formed.
- an Au seed layer is formed on the entire surface by a sputtering method, a mask that exposes a region where the anode wiring 37a and the source wiring 37s are to be formed, for example, a resist mask is formed, and plating is performed.
- An Au film having a thickness of about 10 ⁇ m is formed by the method. Then, the mask is removed, and the Au seed layer exposed from the Au film is removed by an ion milling method or the like.
- the GaN-based SBD and the GaN-based HEMT are formed on the same substrate.
- the i-GaN layer 43 functions as an electron transit layer
- the n-AlGaN layer 31 functions as an electron supply layer.
- FIG. 8A shows an example of the layout of the anode electrode 32, the cathode electrode 33, the gate electrode 45g, the source electrode 45s, and the drain electrode 45d
- FIG. 8B shows the anode wiring 37a, the cathode wiring 48c, the gate wiring 48g, and the source wiring 37s.
- an example of the layout of the drain wiring 48d is shown.
- the anode wiring 37a and the anode electrode 32 of the GaN-based SBD, the cathode wiring 48c, and the cathode electrode 33 may be laid out in a comb shape.
- each electrode of the GaN-based HEMT may be two-dimensionally arranged like each electrode of the GaN-based SBD in FIG. 8A.
- a through hole may be formed in the substrate, and the GaN-based HEMT drain wiring may be routed to the back surface of the substrate through the through hole.
- the cathode wiring of the GaN-based SBD may be routed to the back surface.
- Al that is less expensive than Au may be used as a wiring material.
- the cathode electrode may be provided on the surface side of the substrate as in the fifth embodiment.
- the sixth embodiment is an apparatus such as a server power supply provided with a GaN-based SBD.
- FIG. 10 is a diagram showing an SBD package including a GaN-based SBD.
- 11 shows a PFC (power factor) including the SBD package shown in FIG. correction) circuit.
- FIG. 12 is a diagram showing a server power supply including the PFC circuit shown in FIG.
- the cathode electrode of the GaN-based SBD 70 is fixed to the package electrode table 81 using a mounting material 82 such as solder.
- a lead 81 a is connected to the package electrode base 81.
- the anode electrode of the GaN-based SBD 70 is connected to another lead 83 by bonding using an Al wire 84. These are sealed with a mold resin 85.
- one terminal of the choke coil 93 and one terminal of the switch element 94 are connected to the lead 83 connected to the anode electrode of the GaN-based SBD 70, and the cathode electrode is connected to the cathode electrode.
- One terminal of the capacitor 95 is connected to the connected lead 81a.
- a capacitor 92 is connected to the other terminal of the choke coil 93.
- the other terminal of the capacitor 92, the other terminal of the switch element 94, and the other terminal of the capacitor 95 are grounded.
- the capacitor 92 is connected to an AC power supply (AC) via a diode bridge 91. Further, a direct current power source (DC) is taken out between both terminals of the capacitor 95.
- AC AC power supply
- DC direct current power source
- the PFC circuit 90 is used by being incorporated in the server power supply 100 or the like.
- a power supply device with higher reliability, for example, a DC-DC converter, an AC-DC converter, or the like.
- another nitride semiconductor layer such as an AlGaN layer may be used instead of the whole or a part of the GaN layer of the Schottky barrier diode.
- the on-voltage can be lowered by the metal part included in the Schottky electrode, and the off-breakdown voltage can be improved by the nitride part.
Abstract
Description
先ず、第1の実施形態について説明する。図1Aは、第1の実施形態に係る半導体装置(ショットキーバリアダイオード)の構造を示す平面図であり、図1Bは、図1A中のI-I線に沿った断面図である。
次に、第2の実施形態について説明する。図3Aは、第2の実施形態に係る半導体装置(ショットキーバリアダイオード)の構造を示す断面図であり、図1A中のI-I線に沿った断面を示している。
次に、第3の実施形態について説明する。図4は、第3の実施形態に係る半導体装置(ショットキーバリアダイオード)の構造を示す断面図である。
次に、第4の実施形態について説明する。第4の実施形態では、複数個のSBDを並列に接続する。図6A~図6Cは、第4の実施形態に係る半導体装置を製造する方法を工程順に示す断面図である。
次に、第5の実施形態について説明する。第5の実施形態では、GaN系SBD及びGaN系高電子移動度トランジスタ(HEMT:high electron mobility transistor)を同一の基板上に形成する。図7A~図7Lは、第5の実施形態に係る半導体装置を製造する方法を工程順に示す断面図である。
次に、第6の実施形態について説明する。第6の実施形態は、GaN系SBDを備えたサーバ電源等の装置である。図10は、GaN系SBDを含むSBDパッケージを示す図である。図11は、図10に示すSBDパッケージを含むPFC(power factor
correction)回路を示す図である。図12は、図11に示すPFC回路を含むサーバ電源を示す図である。
Claims (20)
- 半導体層と、
前記半導体層とショットキー接合したショットキー電極と、
を有し、
前記ショットキー電極は、
前記半導体層とショットキー接合した金属を含む金属部と、
前記金属部の周囲に形成され、前記金属の窒化物を含み、前記半導体層とショットキー接合した窒化物部と、
を有することを特徴とする半導体装置。 - 前記半導体層の前記窒化物部が接合する部分の抵抗は、前記半導体層の前記金属部が接合する部分の抵抗よりも高いことを特徴とする請求項1に記載の半導体装置。
- 前記金属部に含まれる金属は、Ti又はTaであることを特徴とする請求項1に記載の半導体装置。
- 前記半導体層は、窒化物半導体を含むことを特徴とする請求項1に記載の半導体装置。
- 前記半導体層は、
電子走行層と、
前記電子走行層上方に形成された電子供給層と、
を有することを特徴とする請求項1に記載の半導体装置。 - 基板上方に複数個の前記ショットキー電極が設けられており、
複数個の前記ショットキー電極を接続する配線を有することを特徴とする請求項1に記載の半導体装置。 - 半導体装置を有し、
前記半導体装置は、
半導体層と、
前記半導体層とショットキー接合したショットキー電極と、
を有し、
前記ショットキー電極は、
前記半導体層とショットキー接合した金属を含む金属部と、
前記金属部の周囲に形成され、前記金属の窒化物を含み、前記半導体層とショットキー接合した窒化物部と、
を有することを特徴とする電源装置。 - 前記半導体層の前記窒化物部が接合する部分の抵抗は、前記半導体層の前記金属部が接合する部分の抵抗よりも高いことを特徴とする請求項7に記載の電源装置。
- 前記金属部に含まれる金属は、Ti又はTaであることを特徴とする請求項7に記載の電源装置。
- 前記半導体層は、窒化物半導体を含むことを特徴とする請求項7に記載の電源装置。
- 前記半導体層は、
電子走行層と、
前記電子走行層上方に形成された電子供給層と、
を有することを特徴とする請求項7に記載の電源装置。 - 基板上方に複数個の前記ショットキー電極が設けられており、
複数個の前記ショットキー電極を接続する配線を有することを特徴とする請求項7に記載の電源装置。 - 半導体層とショットキー接合した金属膜を形成する工程と、
前記金属膜の周縁部を窒化して、前記金属膜から、前記半導体層とショットキー接合した金属部と、前記金属部の周囲に位置し、前記半導体層とショットキー接合した窒化物部と、を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記金属部と前記窒化物部とを形成する工程は、前記金属膜の周縁部に対する窒素のイオン注入を行う工程又は前記金属膜の周縁部を窒素プラズマに曝す工程を有することを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記半導体層の前記窒化物部が接合する部分の抵抗を、前記半導体層の金属部が接合する部分の抵抗より高める工程を有することを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記半導体層の前記窒化物部が接合する部分の抵抗を高める工程を、前記金属部と前記窒化物部とを形成する工程と並行して行うことを特徴とする請求項15に記載の半導体装置の製造方法。
- 前記金属膜は、Ti又はTaを含むことを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記半導体層は、窒化物半導体を含むことを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記半導体層は、電子走行層と、前記電子走行層上方に形成された電子供給層と、を有することを特徴とする請求項13に記載の半導体装置の製造方法。
- 前記金属膜を形成する工程において、基板上方に複数個の金属膜を形成し、
前記複数個の金属膜から形成した複数個の前記金属部及び窒化物部を接続する配線を形成する工程を有することを特徴とする請求項13に記載の半導体装置の製造方法。
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PCT/JP2011/050676 WO2012098635A1 (ja) | 2011-01-17 | 2011-01-17 | 半導体装置及びその製造方法 |
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Cited By (4)
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JP2014212316A (ja) * | 2013-04-16 | 2014-11-13 | アイメックImec | ショットキーダイオードおよび高電子移動度トランジスタを備えた半導体デバイスの製造方法 |
JP2015073034A (ja) * | 2013-10-03 | 2015-04-16 | 富士通株式会社 | 半導体装置の製造方法 |
US9553152B2 (en) | 2014-01-08 | 2017-01-24 | Fujitsu Limited | Semiconductor device |
JPWO2016185645A1 (ja) * | 2015-05-21 | 2018-03-15 | パナソニック株式会社 | 窒化物半導体装置 |
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DE102014118768A1 (de) * | 2014-12-16 | 2016-06-16 | Infineon Technologies Ag | Halbleiterbauelement mit einem metall-halbleiter-übergang und herstellungsweise dafür |
US10014383B2 (en) * | 2014-12-17 | 2018-07-03 | Infineon Technologies Ag | Method for manufacturing a semiconductor device comprising a metal nitride layer and semiconductor device |
DE102014118874A1 (de) * | 2014-12-17 | 2016-06-23 | Infineon Technologies Austria Ag | Halbleitervorrichtung und Verfahren zum Herstellen einer Halbleitervorrichtung |
US10756084B2 (en) * | 2015-03-26 | 2020-08-25 | Wen-Jang Jiang | Group-III nitride semiconductor device and method for fabricating the same |
US9790085B1 (en) * | 2016-06-16 | 2017-10-17 | Nxp Usa, Inc. | Actively preventing charge induced leakage of semiconductor devices |
FR3086097B1 (fr) * | 2018-09-18 | 2020-12-04 | Commissariat Energie Atomique | Procede de fabrication d'un dispositif electroluminescent |
IT201800011065A1 (it) * | 2018-12-13 | 2020-06-13 | St Microelectronics Srl | Transistore hemt includente una regione di porta perfezionata e relativo procedimento di fabbricazione |
KR102635376B1 (ko) | 2019-01-30 | 2024-02-07 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 수직 확산판을 갖는 커패시터 구조 |
CN111599678B (zh) * | 2020-06-01 | 2023-05-26 | 北京时代全芯存储技术股份有限公司 | 二极管结构的制造方法 |
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