JP2014212316A - ショットキーダイオードおよび高電子移動度トランジスタを備えた半導体デバイスの製造方法 - Google Patents
ショットキーダイオードおよび高電子移動度トランジスタを備えた半導体デバイスの製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract 10
- 239000000463 material Substances 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 29
- 238000000151 deposition Methods 0.000 claims description 28
- 229910002704 AlGaN Inorganic materials 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 5
- 239000002800 charge carrier Substances 0.000 abstract description 2
- 125000005842 heteroatom Chemical group 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000001459 lithography Methods 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
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- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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Abstract
【解決手段】半導体デバイスは、III族−窒化物スタックの上に形成された、ショットキーダイオード(10)および高電子移動度トランジスタ(20)を備える。III族−窒化物スタックは、少なくとも下側および上側のIII族−窒化物層を備え、両者間にヘテロ接合を形成し、その結果、2DEG層(5)が2つの層の下側層に形成される。2DEG層は、ダイオードおよびHEMTの電荷キャリアとして機能する。ドープIII族−窒化物層が、ダイオードのアノードの一部とIII族−窒化物スタックとの間に存在する。前記一部は、ダイオードのショットキー接合とカソードとの間に設置される。追加のドープIII族−窒化物層が、HEMTのゲート電極とIII族−窒化物スタックとの間に存在する。前記III族−窒化物層の厚さは等しくない。
【選択図】図1
Description
・少なくとも下側および上側のIII族−窒化物層。これらの層は、両者間にヘテロ接合を形成し、その結果、2DEG層が2つの層の下側層に形成される。
・下記の構成を備えたダイオード。
‐上側III族−窒化物層とのオーミックコンタクトを形成するカソード。
‐アノード。これは、上側III族−窒化物層とのショットキーバリアコンタクトを形成する第1部分、およびアノードとカソードとの間に配置された第2部分を備える。
‐前記上側III族−窒化物層の上に位置し、アノードとカソードを互いに絶縁する誘電体エリア。
‐アノードの前記第2部分と上側III族−窒化物層との間に位置し、ダイオードの逆バイアス領域における2DEG層をピンチオフするように構成されたドープIII族−窒化物材料の層。
・下記の構成を備えたHEMT。
‐前記上側III族−窒化物層とオーミックコンタクトしているソース電極およびドレイン電極。
‐前記ソース電極と前記ドレイン電極との間に位置するゲート電極。
‐前記上側III族−窒化物層の上に位置し、ソースとゲートとの間およびゲートとドレインとの間にある誘電体エリア。
‐前記ゲート電極と上側III族−窒化物層との間にあるドープIII族−窒化物材料の層。
ダイオードおよびHEMTにおける前記ドープIII族−窒化物材料の層は、異なる厚さを有する。
‐キャリア基板の上にIII族−窒化物スタックを製作するステップ。前記スタックは、少なくとも下側および上側のIII族−窒化物層を備え、両者間にヘテロ接合を形成し、その結果、2DEG層が2つの層の下側層に形成される。
‐誘電体層を前記III族−窒化物スタックの上に堆積するステップ。
‐前記誘電体をパターン化して、ショットキーダイオードのアノード電極およびカソード電極の場所ならびにHEMTのソース電極、ドレイン電極およびゲート電極の場所に対応して、誘電体層を貫通する複数の開口を形成するステップ。前記アノードの場所に対応した開口(以下「アノード開口」と称する)は、前記ダイオードのショットキー接合に対応した第1部分と、前記第1部分に近接した第2部分とを備え、前記第2部分の各開口は、第1部分と、カソード電極に対応した開口のうちの1つとの間に設置される。
‐ドープIII族−窒化物材料からなる第1層を、アノード開口の前記第2部分に製作し、ドープIII族−窒化物材料からなる第2層を、前記HEMTのゲートに対応した開口(以下「ゲート開口」と称する)に製作するステップ。前記第1および第2層(18,26)の厚さは等しくない。
‐前記アノード電極およびカソード電極、ならびにソース電極、ドレイン電極およびゲート電極を製作するステップ。前記アノードの一部が、ドープIII族−窒化物材料からなる前記第1層の上に製作され、ゲート電極が、ドープIII族−窒化物材料からなる前記第2層の上に製作される。
‐ダイオードとHEMTとの間に絶縁(isolation)エリアを製作するステップ。
‐前記ゲート開口をマスクして、ドープIII族−窒化物材料からなる前記第1層を堆積するステップ。
‐アノード開口の前記第2部分の開口をマスクして、ドープIII族−窒化物材料からなる前記第2層を堆積するステップ。
‐前記誘電体層をパターン化する第1のステップにおいて、アノード開口の前記第2部分および前記ゲート開口を形成するステップ。
‐ドープIII族−窒化物材料からなる前記第1層および第2層を、アノード開口の前記第2部分および前記ゲート開口に製作するステップ。
‐第2のパターン化ステップにおいて、ショットキーダイオードのアノードの場所に対応して、開口の前記第1部分を形成するステップ。
‐前記アノード電極および前記ゲート電極を製作するステップ。
‐1つ以上の追加のパターン化ステップにおいて、ショットキーダイオードのカソード電極ならびにHEMTのソース電極およびドレイン電極の場所に対応して、前記開口を形成するステップ。
‐前記カソード電極ならびにソース電極およびドレイン電極を製作するステップ。
‐キャリア基板1の上に、上述のようなIII族−窒化物スタック2/3/4を製作するステップ。こうしたIII族−窒化物スタックの製作は、任意の適切な公知の手法に従って、例えば、有機金属化学気相成長法(MOCVD)によって実施できる。バリア層4は、スタックの上部層である。
‐誘電体層30を前記III族−窒化物スタックの上に堆積するステップ。例えば、Si3N4層が、その場(in-situ)(III族−窒化物スタックの堆積と同じプロセスチャンバー内)で、そして、例えば、III族−窒化物スタックと同じ堆積プロセスによって堆積される。誘電体層は、順番に堆積した複数の層からなるものでもよい。
‐前記誘電体をパターン化して(例えば、1回以上の標準リソグラフィ/エッチング工程により)、ショットキーダイオード10のアノード電極およびカソード電極の場所31〜33ならびにHEMT20のソース電極、ドレイン電極およびゲート電極の場所34/35/36に対応して、誘電体層を貫通する複数の開口31〜36を形成するステップ。ここで、前記アノードに対応した開口は、前記ダイオードのショットキー接合に対応した第1部分31と、前記第1部分に近接し、第1部分31とカソード電極に対応した開口33との間に設置された少なくとも1つの第2部分32とを備える。これらの開口は、好ましくは、1回の標準リソグラフィ/エッチング工程ではなく、本説明で後述するような一連の工程においてパターン化される。
‐p−GaNからなる第1層18を、アノード開口の前記第2部分32に製作し、p−GaNからなる第2層26を、前記HEMTのゲートに対応した開口に製作するステップ。ここで、第1層および第2層の厚さは等しくない。
‐前記電極を、例えば、導電層を堆積し、前記層をパターン化することによって製作するステップ。前記アノード11の一部が、第1p−GaN層18の上に製作され、ゲート電極23は、第2p−GaN層26の上に製作される。再び、全ての電極が単一の工程で製作されず、本説明での更なる好ましい実施形態の場合に説明するように、幾つかの電極を1回以上の標準リソグラフィ/エッチング工程の後に製作し、他の電極を追加のリソグラフィ/エッチング工程の後に製作してもよい。
‐ダイオードとHEMTとの間に絶縁(isolation)エリア25を製作するステップ。これは、例えば、メサエッチング手法によって製作される。
・前記層が、前記他の層または基板の上に直接に、即ち、これと接触して製作または堆積されること。
・前記層が、前記層と前記他の層または基板との間にある1つの中間層または中間層スタックの上に製作されること。
Claims (12)
- ショットキーダイオードおよび高電子移動度トランジスタを備えた半導体デバイスであって、
・少なくとも下側および上側のIII族−窒化物層であって、両者間にヘテロ接合を形成し、その結果、2DEG層が2つの層の下側層に形成される下側および上側のIII族−窒化物層を備え、
・ダイオードは、
‐上側III族−窒化物層とのオーミックコンタクトを形成するカソードと、
‐アノードであって、上側III族−窒化物層とのショットキーバリアコンタクトを形成する第1部分、およびアノードとカソードとの間に配置された第2部分を備えたアノードと、
‐前記上側III族−窒化物層の上に位置し、アノードとカソードを互いに絶縁する誘電体エリアと、
‐アノードの前記第2部分と上側III族−窒化物層との間に位置し、ダイオードの逆バイアス領域における2DEG層をピンチオフするように構成されたドープIII族−窒化物材料の層と、を備え、
・HEMTは、
‐前記上側III族−窒化物層とオーミックコンタクトしているソース電極およびドレイン電極と、
‐前記ソース電極と前記ドレイン電極との間に位置するゲート電極と、
‐前記上側III族−窒化物層の上に位置し、ソースとゲートとの間およびゲートとドレインとの間にある誘電体エリアと、
‐前記ゲート電極と上側III族−窒化物層との間にあるドープIII族−窒化物材料の層と、を備え、
ダイオードおよびHEMTにおける前記ドープIII族−窒化物材料の層は、異なる厚さを有する、デバイス。 - HEMTにおけるドープIII族−窒化物材料の層の厚さは、ショットキーダイオードにおけるドープIII族−窒化物材料の層の厚さより大きい請求項1記載のデバイス。
- 前記ドープIII族−窒化物材料の層は、前記ダイオードおよび前記HEMTにおいて電流の流れ方向に測定した長さを有し、HEMTにおけるドープIII族−窒化物材料の層の長さは、ショットキーダイオードにおけるドープIII族−窒化物材料の層の長さより小さい請求項1または2記載のデバイス。
- アノードの前記第1および第2部分は、誘電体エリアによって分離されている請求項1〜3のいずれかに記載のデバイス。
- アノードの前記第1および第2部分は、直接に隣接している請求項1〜3のいずれかに記載のデバイス。
- 前記下側III族−窒化物層はGaN層であり、前記上側III族−窒化物層はAlGaN層であり、前記ドープIII族−窒化物材料の層は、p−ドープのGaNまたはAlGaNの層である請求項1〜5のいずれかに記載のデバイス。
- ショットキーダイオードおよび高電子移動度トランジスタを備えた半導体デバイスを製造する方法であって、
‐キャリア基板の上にIII族−窒化物スタックを製作するステップであって、前記スタックは、少なくとも下側および上側のIII族−窒化物層を備え、両者間にヘテロ接合を形成し、その結果、2DEG層が2つの層の下側層に形成されるようにしたステップと、
‐誘電体層を前記III族−窒化物スタックの上に堆積するステップと、
‐前記誘電体をパターン化して、ショットキーダイオードのアノード電極およびカソード電極の場所ならびにHEMTのソース電極、ドレイン電極およびゲート電極の場所に対応して、誘電体層を貫通する複数の開口を形成するステップであって、前記アノードの場所に対応した開口(以下「アノード開口」と称する)は、前記ダイオードのショットキー接合に対応した第1部分と、前記第1部分に近接した第2部分とを備え、前記第2部分の各開口は、第1部分と、カソード電極に対応した開口のうちの1つとの間に設置されるようにしたステップと、
‐ドープIII族−窒化物材料からなる第1層を、アノード開口の前記第2部分に製作し、ドープIII族−窒化物材料からなる第2層を、前記HEMTのゲートに対応した開口(以下「ゲート開口」と称する)に製作するステップであって、前記第1および第2層の厚さは等しくないようにしたステップと、
‐前記アノード電極およびカソード電極、ならびにソース電極、ドレイン電極およびゲート電極を製作するステップであって、前記アノードの一部が、ドープIII族−窒化物材料からなる前記第1層の上に製作され、ゲート電極が、ドープIII族−窒化物材料からなる前記第2層の上に製作されるようにしたステップと、
‐ダイオードとHEMTとの間に絶縁エリアを製作するステップと、を含む方法。 - ドープIII族−窒化物材料からなる前記第1層および第2層を製作するステップは、ドープIII族−窒化物材料を、アノード開口の前記第2部分に選択的に堆積することによって実施され、ゲート開口では、前記選択的堆積が単一の堆積工程で生じ、そして、アノード開口の前記第2部分の寸法およびゲート開口の寸法は、得られた第1層の厚さが得られた第2層の厚さと等しくないように選択される請求項7記載の方法。
- アノード開口の第2部分の前記開口および前記ゲート開口は、ある長さを有しており、
前記ゲート開口の長さはアノード開口の前記第2部分の開口の長さより小さく、その結果、前記第2層の厚さは前記第1層の長さより大きい請求項8記載の方法。 - ドープIII族−窒化物材料からなる前記第1層および第2層を製作するステップは、
‐前記ゲート開口をマスクして、ドープIII族−窒化物材料からなる前記第1層を堆積するステップと、
‐アノード開口の前記第2部分の開口をマスクして、ドープIII族−窒化物材料からなる前記第2層を堆積するステップと、によって行われる請求項7記載の方法。 - 誘電体層をIII族−窒化物スタックの上に堆積するステップに続いて、
‐前記誘電体層をパターン化する第1のステップにおいて、アノード開口の前記第2部分および前記ゲート開口を形成するステップと、
‐ドープIII族−窒化物材料からなる前記第1層および第2層を、アノード開口の前記第2部分および前記ゲート開口に製作するステップと、
‐第2のパターン化ステップにおいて、ショットキーダイオードのアノードの場所に対応して、開口の前記第1部分を形成するステップと、
‐前記アノード電極および前記ゲート電極を製作するステップと、
‐1つ以上の追加のパターン化ステップにおいて、ショットキーダイオードのカソード電極ならびにHEMTのソース電極およびドレイン電極の場所に対応して、前記開口を形成するステップと、
‐前記カソード電極ならびにソース電極およびドレイン電極を製作するステップと、が行われる請求項7〜10のいずれかに記載の方法。 - 前記下側III族−窒化物層はGaN層であり、前記上側III族−窒化物層はAlGaN層であり、前記ドープIII族−窒化物材料の層は、p−ドープのGaNまたはAlGaNの層である請求項7〜11のいずれかに記載の方法。
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JP2008078526A (ja) * | 2006-09-25 | 2008-04-03 | New Japan Radio Co Ltd | 窒化物半導体装置及びその製造方法 |
JP2009231395A (ja) * | 2008-03-19 | 2009-10-08 | Sumitomo Chemical Co Ltd | 半導体装置および半導体装置の製造方法 |
JP2011054845A (ja) * | 2009-09-03 | 2011-03-17 | Panasonic Corp | 窒化物半導体装置 |
JP2011205029A (ja) * | 2010-03-26 | 2011-10-13 | Sanken Electric Co Ltd | 半導体装置 |
JP2011228398A (ja) * | 2010-04-16 | 2011-11-10 | Sanken Electric Co Ltd | 半導体装置 |
WO2012098635A1 (ja) * | 2011-01-17 | 2012-07-26 | 富士通株式会社 | 半導体装置及びその製造方法 |
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EP2793255B1 (en) | 2017-12-06 |
US20150214327A1 (en) | 2015-07-30 |
US20140306235A1 (en) | 2014-10-16 |
EP2793255B8 (en) | 2018-01-17 |
US9431511B2 (en) | 2016-08-30 |
EP2793255A1 (en) | 2014-10-22 |
JP6280796B2 (ja) | 2018-02-14 |
US9276082B2 (en) | 2016-03-01 |
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