WO2012096154A1 - 薄膜トランジスタ基板及び製造方法 - Google Patents
薄膜トランジスタ基板及び製造方法 Download PDFInfo
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- WO2012096154A1 WO2012096154A1 PCT/JP2012/000093 JP2012000093W WO2012096154A1 WO 2012096154 A1 WO2012096154 A1 WO 2012096154A1 JP 2012000093 W JP2012000093 W JP 2012000093W WO 2012096154 A1 WO2012096154 A1 WO 2012096154A1
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- film
- transistor substrate
- film transistor
- thin film
- oxide semiconductor
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- 239000000758 substrate Substances 0.000 title claims abstract description 146
- 239000010409 thin film Substances 0.000 title claims abstract description 57
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000010408 film Substances 0.000 claims abstract description 438
- 239000004065 semiconductor Substances 0.000 claims abstract description 115
- 239000011241 protective layer Substances 0.000 claims abstract description 79
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 38
- 239000010410 layer Substances 0.000 claims description 66
- 239000011347 resin Substances 0.000 claims description 53
- 229920005989 resin Polymers 0.000 claims description 53
- 239000004973 liquid crystal related substance Substances 0.000 claims description 48
- 239000011229 interlayer Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 12
- 229910052779 Neodymium Inorganic materials 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 6
- 229910052746 lanthanum Inorganic materials 0.000 claims description 6
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 6
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 abstract description 10
- 230000001681 protective effect Effects 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 16
- 238000002161 passivation Methods 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 15
- 239000003990 capacitor Substances 0.000 description 13
- 229910044991 metal oxide Inorganic materials 0.000 description 11
- 150000004706 metal oxides Chemical class 0.000 description 11
- 238000000059 patterning Methods 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 9
- 239000003566 sealing material Substances 0.000 description 8
- 229910007541 Zn O Inorganic materials 0.000 description 7
- 238000009413 insulation Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
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- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910018125 Al-Si Inorganic materials 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 2
- 229910018507 Al—Ni Inorganic materials 0.000 description 2
- 229910018520 Al—Si Inorganic materials 0.000 description 2
- 239000004988 Nematic liquid crystal Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- IUVCFHHAEHNCFT-INIZCTEOSA-N 2-[(1s)-1-[4-amino-3-(3-fluoro-4-propan-2-yloxyphenyl)pyrazolo[3,4-d]pyrimidin-1-yl]ethyl]-6-fluoro-3-(3-fluorophenyl)chromen-4-one Chemical compound C1=C(F)C(OC(C)C)=CC=C1C(C1=C(N)N=CN=C11)=NN1[C@@H](C)C1=C(C=2C=C(F)C=CC=2)C(=O)C2=CC(F)=CC=C2O1 IUVCFHHAEHNCFT-INIZCTEOSA-N 0.000 description 1
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- 150000002739 metals Chemical class 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
Definitions
- the present invention relates to a thin film transistor substrate having a thin film transistor provided with an oxide semiconductor film, a display device, and a method for manufacturing the thin film transistor substrate.
- an active matrix substrate is a thin film transistor substrate (hereinafter referred to as “TFT substrate”) in which a thin film transistor (hereinafter referred to as “TFT”) is provided as a switching element for each pixel which is the minimum unit of an image. Is widely used.
- TFT substrate a thin film transistor substrate
- TFT thin film transistor
- the TFT substrate is provided with a plurality of TFTs in a matrix on the substrate, and an insulating film is provided so as to cover them, and the surface is flattened. Further, a pixel electrode corresponds to each TFT on the insulating film. And a plurality of structures are formed.
- the liquid crystal display panel has a configuration in which a counter substrate is disposed so as to face the TFT substrate, and a liquid crystal layer is provided between the TFT substrate and the counter substrate.
- an oxide semiconductor film is used instead of a semiconductor layer made of amorphous silicon (a-Si). TFTs using the above have been proposed.
- An oxide semiconductor film is superior to an a-Si semiconductor film in that it has high switching characteristics and a good off-state current value, a high electron mobility, a low-temperature process, and the like. In particular, high switching characteristics and good off-current values enable the TFT to have a compact auxiliary capacitor layout, and low power consumption and high definition are expected due to the high aperture ratio. .
- the semiconductor layer reacts with the source / drain electrodes, and hillocks (unevenness) are formed on the source / drain electrodes.
- hillocks unevenness
- An object of the present invention is to achieve low power consumption and high definition of a TFT substrate including the TFT by obtaining an oxide semiconductor TFT having excellent electrical characteristics.
- the channel protective layer is provided in an island shape so as to cover the channel portion of the oxide semiconductor film, the channel portion of the oxide semiconductor film is exposed to a high temperature and the electrical characteristics deteriorate. Can be suppressed.
- the source electrode and the drain electrode are composed of an aluminum alloy film or a laminated film including the aluminum alloy film, the source electrode and the drain electrode have excellent heat resistance. Therefore, even when heat treatment is performed at a high temperature of about 350 ° C. in a step after the step of forming the source electrode and the drain electrode, hillocks (unevenness) are generated on the surface of the source electrode / drain electrode. There is no possibility that the source electrode and the drain electrode react with each other to deteriorate the electrical characteristics of the oxide semiconductor film. Therefore, for example, after the formation of the interlayer insulating film, an annealing process can be performed at a high temperature of about 350 ° C.
- the TFT has excellent electrical characteristics, it is possible to make the layout of the TFT and the like compact on the TFT substrate, and it is possible to realize low power consumption and high definition as the aperture ratio is improved.
- the channel protective layer preferably has a light shielding property.
- the channel protective layer since the channel protective layer has a light shielding property, it is possible to suppress a change in electrical characteristics when the oxide semiconductor film is irradiated with light.
- the channel protective layer since the channel protective layer is provided in an island shape, a region other than the channel portion in the oxide semiconductor film is not shielded from light. For this reason, it is possible to suppress a decrease in the aperture ratio due to light shielding in a region other than the channel portion.
- the channel protective layer may be formed of a laminate of a plurality of films including a light-sensitive photosensitive resin film, or may be formed of a stack of a plurality of films including a light-shielding metal film. Good.
- the channel protective layer is formed of a laminate of a plurality of films including a light-sensitive photosensitive resin film
- the plurality of films constituting the laminate are an insulating resin film and an oxidation of an upper layer of the insulating resin film.
- the light-shielding photosensitive resin film may be an upper layer of the oxide semiconductor film and the oxide semiconductor film.
- the channel protective layer is formed of a laminate of a plurality of films including a light-sensitive photosensitive resin film
- the plurality of films constituting the laminate are an insulating resin film, an upper layer of the insulating resin film.
- the light-shielding metal film and the photosensitive insulating film on the upper layer of the light-shielding metal film may be used.
- the aluminum alloy film constituting the source electrode and the drain electrode preferably has a heat resistance of 350 ° C. or higher.
- the main component is aluminum, and the subcomponents are silicon (Si), neodymium (Nd), copper (Cu), nickel (Ni), and lanthanum (La).
- the display device of the present invention includes the thin film transistor substrate of the present invention, a counter substrate disposed opposite to the thin film transistor substrate, and a display medium layer provided between the thin film transistor substrate and the counter substrate.
- the display device of the present invention is suitable when the display medium layer is a liquid crystal layer.
- a method of manufacturing a thin film transistor substrate of the present invention includes a substrate, a gate electrode provided on the substrate, a gate insulating film provided on the substrate and covering the gate electrode, provided on the gate insulating film, and opposed to the gate electrode.
- the channel protective layer is provided in an island shape so as to cover the channel portion of the oxide semiconductor film, so that the channel portion of the oxide semiconductor film is prevented from being exposed to a high temperature to deteriorate the electrical characteristics. can do.
- the source electrode and the drain electrode are formed of the aluminum alloy film or the laminated film including the aluminum alloy film, the source electrode and the drain electrode have excellent heat resistance. Therefore, even when heat treatment is performed at a high temperature of about 350 ° C. in a step after the step of forming the source electrode and the drain electrode, hillocks (unevenness) are generated on the surface of the source electrode / drain electrode. There is no possibility that the source electrode and the drain electrode react with each other to deteriorate the electrical characteristics of the oxide semiconductor film. Therefore, for example, after the formation of the interlayer insulating film, an annealing process can be performed at a high temperature of about 350 ° C.
- the TFT has excellent electrical characteristics, it is possible to make the layout of the TFT and the like compact on the TFT substrate, and it is possible to realize low power consumption and high definition as the aperture ratio is improved.
- the channel protective layer is preferably formed of a material having a light shielding property.
- the channel protective layer is formed of a light-shielding material, it is possible to suppress a change in electrical characteristics due to light irradiation on the oxide semiconductor film.
- the channel protective layer is provided in an island shape, a region other than the channel portion in the oxide semiconductor film is not shielded from light. For this reason, it is possible to suppress a decrease in the aperture ratio due to light shielding in a region other than the channel portion.
- the channel protective layer may be formed by laminating a plurality of films including a light-sensitive photosensitive resin film, or forming a plurality of films including a light-shielding metal film. You may form by laminating.
- the channel protective layer is formed by stacking a plurality of films including a light-shielding metal film
- the plurality of films stacked as the channel protective layer are the light shielding properties of the insulating resin film and the upper layer of the insulating resin film. It may be a photosensitive insulating film that is an upper layer of the metal film and the light-shielding metal film.
- the aluminum alloy film constituting the source electrode and the drain electrode preferably has a heat resistance of 350 ° C. or higher.
- the main component is aluminum, and the subcomponents are silicon (Si), neodymium (Nd), copper (Cu), nickel (Ni), and lanthanum (La).
- the channel protective layer is provided in an island shape so as to cover the channel portion of the oxide semiconductor film, the channel portion of the oxide semiconductor film is exposed to a high temperature and the electrical characteristics of the TFT deteriorate. Can be suppressed.
- the source electrode and the drain electrode are composed of an aluminum alloy film or a laminated film including the aluminum alloy film, the source / drain electrodes have excellent heat resistance. Therefore, even when heat treatment is performed at a high temperature of about 350 ° C. in a step after the step of forming the source electrode and the drain electrode, hillocks (unevenness) are generated on the surface of the source electrode / drain electrode.
- the source electrode and the drain electrode react with each other to deteriorate the electrical characteristics of the oxide semiconductor film. Therefore, for example, after the formation of the interlayer insulating film, an annealing process can be performed at a high temperature of about 350 ° C. in order to restore the electrical characteristics of the oxide semiconductor film, and a TFT having excellent electrical characteristics can be obtained. Since the TFT has excellent electrical characteristics, it is possible to make the layout of the TFT and the like compact on the TFT substrate, and it is possible to realize low power consumption and high definition as the aperture ratio is improved.
- FIG. 5 is a sectional view taken along line VV in FIG. 4.
- (A)-(c) is explanatory drawing which shows the manufacturing method of the TFT substrate of Embodiment 1.
- FIG. (A) And (b) is explanatory drawing which shows the manufacturing method of the TFT substrate of Embodiment 1.
- FIG. It is a graph which shows the relationship between a gate voltage and a drain current about TFT concerning Example (A1) and a comparative example (B1).
- Embodiment 1 (Configuration of liquid crystal display device) -TFT substrate-
- FIG. 1 is a plan view of a liquid crystal display device 1 having a TFT substrate 10 including a thin film transistor according to the first embodiment
- FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 3 is an enlarged plan view of the display area D of the TFT substrate 10 including the TFT according to the present embodiment
- FIG. 4 is an enlarged plan view of the TFT in the display area D of the TFT substrate 10
- FIG. FIG. 5 is a cross-sectional view of the TFT taken along line VV in FIG. 4.
- the liquid crystal display device 1 is arranged so that the TFT substrate 10 and the counter substrate 20 face each other, and both are bonded by a sealing material 40 provided on the outer peripheral edge of the substrate.
- a liquid crystal layer 30 is provided as a display medium layer in a region surrounded by the sealing material 40.
- a display region D for displaying an image is formed in the inner portion of the sealing material 40, and a terminal region T is formed in a portion protruding from the counter substrate 20 of the TFT substrate 10.
- the TFT substrate 10 has a plurality of gate signal lines 12GL provided so as to extend in parallel with each other, and extends in parallel with each other in a direction orthogonal to the gate signal lines 12GL.
- a plurality of source signal lines 16SL are provided, and a plurality of TFTs are provided for each intersection of the gate signal lines 12GL and the source signal lines 16SL, that is, for each pixel.
- a plurality of storage capacitor lines 12CsL are provided between the gate signal lines 12GL so as to extend in parallel with each other.
- a gate electrode 12G protruding from the gate signal line 12GL is provided, and the gate electrode 12G is provided above the gate electrode 12G via a gate insulating film 13 provided so as to cover the gate electrode 12G.
- An oxide semiconductor film 14 is provided. Note that a channel portion is formed in the oxide semiconductor film 14 at a position facing the gate electrode 12G. The channel portion is covered with a channel protective layer 15a provided in an island shape on the upper layer.
- a source electrode 16S and a drain electrode 16D are provided in the upper layer of the oxide semiconductor film 14 so as to be separated from each other through a channel portion. Then, a passivation film 17 and a planarizing film 18 are stacked as an interlayer insulating film so as to cover them.
- the gate electrode 12G is made of a known material, such as a Ti film (thickness of about 1 to 10 nm), an Al film (thickness of about 50 to 400 nm), and a Ti film (thickness of about 50 to 300 nm). It is formed of a laminated film.
- the gate insulating film 13 is made of a known material, and is formed of, for example, a SiO 2 film having a thickness of about 20 to 100 nm.
- the oxide semiconductor film 14 is made of, for example, an IGZO (In—Ga—Zn—O) -based metal oxide, and has a thickness of about 20 to 200 nm, for example.
- An IGZO (In—Ga—Zn—O) -based metal oxide has high mobility even if it is amorphous, and thus favorable characteristics for a thin film transistor such as high mobility and low off-state current can be obtained.
- the oxide semiconductor film 14 is formed using an IGZO (In—Ga—Zn—O) -based metal oxide; for example, a metal oxide containing any one of In, Ga, and Zn is used. What is necessary is just to be formed with the thing. Since these metal oxides have high mobility even when they are amorphous, a thin film transistor having a large on-state current can be formed.
- the channel protective layer 15a is formed of an insulating material such as a SiO 2 film, for example.
- the channel protective layer is provided by being patterned into an island shape so as to cover the channel portion so as to correspond to the channel region of the oxide semiconductor film 14. Since the channel protective layer 15 a is provided so as to cover the channel portion of the oxide semiconductor film 14, the channel portion is prevented from being directly heated in the heat treatment step, and the resistance of the channel portion is reduced to reduce the oxide semiconductor film 14. It is suppressed that the electrical characteristics of are deteriorated.
- the channel protective layer 15a has a thickness of about 50 to 400 nm, for example.
- the source electrode 16S and the drain electrode 16D are formed of a laminated film including an Al alloy film.
- the source electrode 16S and the drain electrode 16D are formed of a laminated film of a Ti film, an Al alloy film, and a Ti film.
- the Al alloy film a material having a low specific resistance and a heat resistance of 350 ° C. or more is suitable, the main component is Al, and the subcomponents are silicon (Si), neodymium (Nd), copper (Cu), An alloy that is at least one selected from the group consisting of nickel (Ni) and lanthanum (La) (that is, Al—Si, Al—Nd, Al—Cu, Al—Ni, Al—La) can be mentioned.
- the laminated film constituting the source electrode 16S and the drain electrode 16D can be, for example, a laminated film of a Mo film, an Al alloy film, and a Mo film.
- the source electrode 16S and the drain electrode 16D may be formed of a single layer film of an Al alloy film in addition to a stacked film including an Al alloy film.
- the passivation film 17 is made of a known material, and is formed of, for example, a SiO 2 film having a thickness of about 50 to 500 nm.
- the planarizing film 18 is made of a known material such as a photosensitive resin. Although the passivation film 17 and the planarization film 18 are formed as interlayer insulating films, they may be integrated to form an interlayer insulating film.
- the pixel electrode 19 is made of a known material, and is formed of, for example, an ITO film having a thickness of about 20 to 300 nm.
- the counter substrate 20 is provided with a color filter layer including a light shielding layer and a colored layer on the substrate, a common electrode is provided so as to cover the color filter layer, and an alignment film so as to cover the common electrode. Is provided.
- the liquid crystal layer 30 is made of, for example, a nematic liquid crystal material having electro-optical characteristics.
- liquid crystal display device 1 configured as described above, in each pixel, when a gate signal is sent from the gate driver to the gate electrode 12G via the gate signal line 12GL and the TFT in the display region D is turned on, A source signal is sent from the source driver to the source electrode 16S through the source signal line 16SL, and a predetermined charge is written into the pixel electrode 19 through the oxide semiconductor film 14 and the drain electrode 16D. At this time, a potential difference is generated between each pixel electrode 19 of the TFT substrate 10 and the common electrode of the counter substrate 20, and the liquid crystal layer 30, that is, the liquid crystal capacitance of each pixel, and the storage capacitor connected in parallel to the liquid crystal capacitance. A predetermined voltage is applied to the element. In the liquid crystal display device 1, an image is displayed by adjusting the light transmittance of the liquid crystal layer 30 by changing the alignment state of the liquid crystal layer 30 according to the magnitude of the voltage applied to the liquid crystal layer 30 in each pixel. .
- TFT substrate manufacturing method a manufacturing method of the TFT substrate 10 according to the present embodiment will be described with reference to FIGS.
- a Ti film (thickness of about 1 to 10 nm), an Al film (thickness of about 50 to 400 nm), and a Ti film (thickness of about 50 to 300 nm) are successively formed on the substrate 11 in order.
- the first conductive film is formed, and then patterning is performed so as to form the gate electrode 12G, the gate signal line 12GL, the storage capacitor line 12CsL, the lead line 12c, and the like. Then, as shown in FIG.
- a thickness of 100 to 100 is formed on the upper layer such as the gate electrode 12G, the gate signal line 12GL, the storage capacitor line 12CsL, and the lead line 12c formed after patterning the first conductive film.
- a gate insulating film 13 is formed by laminating a SiN film of about 500 nm and a SiO 2 film of about 20 to 100 nm in thickness.
- an oxide semiconductor film 14 having a thickness of about 20 to 200 nm is formed, and patterning is performed so as to correspond to each region where TFTs are formed, as shown in FIG.
- the oxide semiconductor film 14 may be patterned so as to be provided also in the region of the storage capacitor element.
- a channel protective layer 15a and a gate protective layer 15b are formed by patterning after forming a SiO 2 film having a thickness of about 50 to 400 nm, as shown in FIG. 6C. Then, after forming the channel protective layer 15a and the gate protective layer 15b, for example, annealing is performed under the conditions of 200 to 350 ° C. and 0.5 to 10 hours in an air atmosphere.
- a Ti film (thickness of about 1 to 10 nm), an Al film (thickness of about 50 to 400 nm), and a Ti film (thickness of about 50 to 300 nm) are successively formed in this order to form the second conductive layer.
- the second conductive film is patterned so as to form the source electrode 16S, the drain electrode 16D, and the source signal line 16SL as shown in FIG.
- an SiO 2 film having a thickness of, for example, about 50 to 500 nm is formed as a passivation film 17 on the entire surface of the substrate 11, and then, for example, 200 to 350 ° C. in an air atmosphere. Annealing is performed under conditions of 0.5 to 10 hours.
- a photosensitive resin film is formed as the planarizing film 18. Then, the photosensitive resin film is exposed and developed, further subjected to a decoloring treatment, and then baked under conditions of 200 to 250 ° C. and 0.5 to 5 hours in an air atmosphere, for example.
- thickness to form a third conductive film is an ITO film of about 20 ⁇ 300 nm, then performing patterning in a region covering the contact hole C c of each pixel electrode 19 and the gate source contact portion. Then, after forming the pixel electrode 19 and the like, for example, baking is performed in an air atmosphere at 200 to 250 ° C. and for 0.5 to 5 hours.
- an alignment film (not shown) is formed so as to cover the display region D, and the TFT substrate 10 is completed.
- the TFT substrate 10 is bonded to, for example, a counter substrate 20 that is separately produced by a known method through a sealing material 40, and a liquid crystal layer 30 is provided between both substrates, thereby forming the liquid crystal display device 1. Can do.
- the channel protective layer 15a is provided in an island shape so as to cover the channel portion of the oxide semiconductor film 14, the channel portion of the oxide semiconductor film 14 is exposed to a high temperature and has electrical characteristics. Can be prevented from deteriorating.
- the source electrode 16S and the drain electrode 16D are formed of a laminated film including an aluminum alloy film, the source electrode 16S and the drain electrode 16D have excellent heat resistance. Therefore, even if heat treatment is performed at a high temperature of about 350 ° C. in a step after the step of forming the source electrode 16S and the drain electrode 16D, hillocks (unevenness) are generated on the surfaces of the source electrode 16S and the drain electrode 16D. There is no possibility that the oxide semiconductor film 14 reacts with the source electrode 16S / drain electrode 16D to deteriorate the electrical characteristics of the oxide semiconductor film 14. Therefore, for example, after the passivation film 17 is formed, an annealing process can be performed at a high temperature of about 350 ° C.
- the TFT substrate 10 can be made compact in layout, and lower power consumption and higher definition can be realized as the aperture ratio is improved.
- the TFT substrate 10 of the present embodiment has excellent electrical characteristics and can be charged at high speed with high switching characteristics, so that a high frame rate can be achieved. Therefore, the TFT substrate 10 of this embodiment is suitable for the case of constituting a liquid crystal panel of a 3D display.
- the TFT substrate 10 of the present embodiment since the TFT substrate 10 of the present embodiment has excellent electrical characteristics, high switching characteristics and good off-current, it can be driven at rest, so that low power consumption can be achieved. Therefore, the TFT substrate 10 of the present embodiment is also suitable when constituting a liquid crystal panel of an electronic book.
- the TFT provided corresponding to each pixel in the display area D has been described, but the TFT having the above-described configuration may be provided in the terminal area T. Even when the TFT of this embodiment is provided in the terminal region T, low power consumption and high definition can be realized because the TFT has excellent electrical characteristics. In this case, the area of the frame region can be reduced by increasing the definition of the TFT in the terminal region T. Therefore, this TFT substrate is suitable for constituting a liquid crystal panel of a mobile device.
- Example Measurements for evaluating the electrical characteristics of the TFT (Example) of the configuration of Embodiment 1 shown in FIGS. 4 and 5 and the TFT of the conventional configuration (Comparative Example) shown in FIGS. 17 and 18 were performed.
- An S value (Subthreshold swing value) is used as a parameter that quantitatively indicates the electrical characteristics of the TFT.
- FIG. 8 shows the relationship between the gate voltage and the drain current for the TFTs according to Example (A1) and Comparative Example (B1). From this graph, it can be seen that the TFT according to Example A1 has a smaller S value than the TFT according to Comparative Example B1, and has excellent electrical characteristics.
- FIG. 9 is a graph showing the relationship between the channel length (7 to 54 ⁇ m) and the S value for the TFTs according to the examples (A2 and A3) and the comparative examples (B2 and B3).
- Example A2 is a TFT having a channel width of 9 ⁇ m.
- Example A3 is a TFT having a channel width of 24 ⁇ m.
- Comparative Example B2 is a TFT having a channel width of 5 ⁇ m.
- Comparative Example B3 is a TFT having a channel width of 20 ⁇ m. From this graph, it can be seen that the TFTs of Examples A2 and A3 have a smaller S value than the TFTs of Comparative Examples B2 and B3 and have excellent electrical characteristics regardless of the channel length and channel width.
- Embodiment 2 the liquid crystal display device of Embodiment 2 will be described.
- the liquid crystal display device 1 is disposed so that the TFT substrate 10 and the counter substrate 20 face each other, and are bonded together by a sealing material 40 provided at the outer peripheral edge of the substrate.
- a liquid crystal layer 30 is provided as a display medium layer in a region surrounded by the sealing material 40.
- a display region D for displaying an image is formed in the inner portion of the sealing material 40, and a terminal region T is formed in a portion protruding from the counter substrate 20 of the TFT substrate 10.
- the TFT substrate 10 is formed on the substrate 11 with a conductive film including a gate electrode 12G, a gate signal line 12GL, and the like, a gate insulating film 13, an oxide semiconductor film 14, a channel protective layer 15a and a gate.
- the insulating film including the protective layer 15b, the conductive film including the source electrode 16S, the drain electrode 16D, the source signal line 16SL, the interlayer insulating film including the passivation film 17 and the planarizing film 18, the pixel electrode 19, and the alignment film are stacked. It has a configuration.
- a gate electrode 12G protruding from the gate signal line 12GL is provided, and the gate electrode 12G is provided on an upper layer via a gate insulating film 13 provided so as to cover the gate electrode 12G.
- An oxide semiconductor film 14 is provided. Note that a channel portion is formed in the oxide semiconductor film 14 at a position facing the gate electrode 12G. The channel portion is covered with a channel protective layer 15a provided in an island shape on the upper layer.
- a source electrode 16S and a drain electrode 16D are provided in the upper layer of the oxide semiconductor film 14 so as to be separated from each other through a channel portion. Then, a passivation film 17 and a planarizing film 18 are stacked as an interlayer insulating film so as to cover them.
- the gate electrode 12G is made of a known material, such as a Ti film (thickness of about 1 to 10 nm), an Al film (thickness of about 50 to 400 nm), and a Ti film (thickness of about 50 to 300 nm). It is formed of a laminated film.
- the gate insulating film 13 is made of a known material, and is formed of, for example, a SiO 2 film having a thickness of about 20 to 100 nm.
- the oxide semiconductor film 14 is made of, for example, an IGZO (In—Ga—Zn—O) -based metal oxide, and has a thickness of about 20 to 200 nm, for example.
- An IGZO (In—Ga—Zn—O) -based metal oxide has high mobility even if it is amorphous, and thus favorable characteristics for a thin film transistor such as high mobility and low off-state current can be obtained.
- the oxide semiconductor film 14 is formed using an IGZO (In—Ga—Zn—O) -based metal oxide; for example, a metal oxide containing any one of In, Ga, and Zn is used. What is necessary is just to be formed with the thing. Since these metal oxides have high mobility even when they are amorphous, a thin film transistor having a large on-state current can be formed.
- the channel protective layer 15a is formed of a laminate of a plurality of films.
- the channel protective layer 15a has a configuration in which an insulating resin film 51a, an oxide semiconductor film 52a, and a light-shielding photosensitive resin film 53a are sequentially stacked from the bottom, and has a light-shielding property as a whole.
- the channel protective layer 15 a is provided by being patterned into an island shape so as to cover the channel portion so as to correspond to the channel region of the oxide semiconductor film 14. Since the channel protective layer 15a is provided so as to cover the channel portion of the oxide semiconductor film 14, the channel portion is prevented from being directly heated in the heat treatment step, and the resistance of the channel portion is reduced, and the oxide semiconductor film 14 is reduced. It is suppressed that the electrical characteristics of are deteriorated.
- the insulating resin film 51a is formed of, for example, a SiO 2 film having a thickness of about 10 to 500 nm.
- the oxide semiconductor film 52a is formed of, for example, an IGZO (In—Ga—Zn—O) -based metal oxide film having a thickness of about 10 to 200 nm.
- the light-shielding photosensitive resin film 53a is, for example, a black matrix-forming content-dispersed negative photoresist having a thickness of about 100 to 3000 nm (for example, “CFPR BK” series manufactured by Tokyo Ohka Kogyo Co., Ltd.) or the like. Is formed.
- the source electrode 16S and the drain electrode 16D are formed of a laminated film including an Al alloy film.
- the source electrode 16S and the drain electrode 16D are formed of a laminated film of a Ti film, an Al alloy film, and a Ti film.
- the Al alloy film a material having a low specific resistance and a heat resistance of 350 ° C. or more is suitable, the main component is Al, and the subcomponents are silicon (Si), neodymium (Nd), copper (Cu), An alloy that is at least one selected from the group consisting of nickel (Ni) and lanthanum (La) (that is, Al—Si, Al—Nd, Al—Cu, Al—Ni, Al—La) can be mentioned.
- the laminated film constituting the source electrode 16S and the drain electrode 16D can be, for example, a laminated film of a Mo film, an Al alloy film, and a Mo film.
- the source electrode 16S and the drain electrode 16D may be formed of a single layer film of an Al alloy film in addition to a stacked film including an Al alloy film.
- the passivation film 17 is made of a known material, and is formed of, for example, a SiO 2 film having a thickness of about 50 to 500 nm.
- the planarizing film 18 is made of a known material such as a photosensitive resin. Although the passivation film 17 and the planarization film 18 are formed as interlayer insulating films, they may be integrated to form an interlayer insulating film.
- the pixel electrode 19 is made of a known material, and is formed of, for example, an ITO film having a thickness of about 20 to 300 nm.
- the counter substrate 20 is provided with a color filter layer including a light shielding layer and a colored layer on the substrate, a common electrode is provided so as to cover the color filter layer, and an alignment film so as to cover the common electrode. Is provided.
- the liquid crystal layer 30 is made of, for example, a nematic liquid crystal material having electro-optical characteristics.
- liquid crystal display device 1 configured as described above, in each pixel, when a gate signal is sent from the gate driver to the gate electrode 12G via the gate signal line 12GL and the TFT in the display region D is turned on, A source signal is sent from the source driver to the source electrode 16S through the source signal line 16SL, and a predetermined charge is written into the pixel electrode 19 through the oxide semiconductor film 14 and the drain electrode 16D. At this time, a potential difference is generated between each pixel electrode 19 of the TFT substrate 10 and the common electrode of the counter substrate 20, and the liquid crystal layer 30, that is, the liquid crystal capacitance of each pixel, and the storage capacitor connected in parallel to the liquid crystal capacitance. A predetermined voltage is applied to the element. In the liquid crystal display device 1, an image is displayed by adjusting the light transmittance of the liquid crystal layer 30 by changing the alignment state of the liquid crystal layer 30 according to the magnitude of the voltage applied to the liquid crystal layer 30 in each pixel. .
- TFT substrate manufacturing method a method for manufacturing the TFT substrate 10 according to the present embodiment will be described with reference to FIGS.
- a Ti film (thickness of about 1 to 10 nm), an Al film (thickness of about 50 to 400 nm), and a Ti film (thickness of about 50 to 300 nm) are successively formed on the substrate 11 in order.
- the first conductive film is formed, and then patterning is performed so as to form the gate electrode 12G, the gate signal line 12GL, the storage capacitor line 12CsL, the lead line 12c, and the like. Then, as shown in FIG.
- a thickness of 100 to 100 is formed on the upper layer such as the gate electrode 12G, the gate signal line 12GL, the storage capacitor line 12CsL, and the lead line 12c formed after patterning the first conductive film.
- a gate insulating film 13 is formed by laminating a SiN film of about 500 nm and a SiO 2 film of about 20 to 100 nm in thickness.
- an oxide semiconductor film 14 having a thickness of about 20 to 200 nm is formed, and as shown in FIG. 12B, patterning is performed so as to correspond to each region where a TFT is formed.
- the oxide semiconductor film 14 may be patterned so as to be provided also in the region of the storage capacitor element.
- the light-shielding photosensitive resin film is patterned to form a channel protective layer 15a and a gate protective layer 15b.
- Corresponding light-shielding photosensitive resin films 53a and 53b are formed.
- wet etching is performed shielding photosensitive resin layer 53a, and 53b as a mask, as shown in FIG. 12 (c)
- the oxide semiconductor film 52a of the oxide semiconductor film is etched after forming a 53b, SiO 2
- the film is etched to form insulating resin films 51a and 51b.
- the light-shielding photosensitive resin film 53a is cured by heat treatment so that the light-shielding photosensitive resin films 53a and 53b cover the oxide semiconductor films 52a and 52b. Reflow.
- a Ti film (thickness of about 1 to 10 nm), an Al film (thickness of about 50 to 400 nm), and a Ti film (thickness of about 50 to 300 nm) are successively formed in this order to form the second conductive layer.
- patterning is performed so as to form the source electrode 16S, the drain electrode 16D, and the source signal line 16SL as shown in FIG.
- an SiO 2 film having a thickness of, for example, about 50 to 500 nm is formed as a passivation film 17 on the entire surface of the substrate 11, and then, for example, 200 to 350 ° C. in an air atmosphere. Annealing is performed under conditions of 0.5 to 10 hours.
- a photosensitive resin film is formed as the planarizing film 18. Then, the photosensitive resin film is exposed and developed, further subjected to a decoloring treatment, and then baked under conditions of 200 to 250 ° C. and 0.5 to 5 hours in an air atmosphere, for example.
- thickness to form a third conductive film is an ITO film of about 20 ⁇ 300 nm, then performing patterning in a region covering the contact hole C c of each pixel electrode 19 and the gate source contact portion. Then, after forming the pixel electrode 19 and the like, for example, baking is performed in an air atmosphere at 200 to 250 ° C. and for 0.5 to 5 hours.
- an alignment film (not shown) is formed so as to cover the display region D, and the TFT substrate 10 is completed.
- the TFT substrate 10 is bonded to, for example, a counter substrate 20 that is separately produced by a known method through a sealing material 40, and a liquid crystal layer 30 is provided between both substrates, thereby forming the liquid crystal display device 1. Can do.
- the channel protective layer 15a is provided in an island shape so as to cover the channel portion of the oxide semiconductor film 14, the channel portion of the oxide semiconductor film 14 is exposed to a high temperature and has electrical characteristics. Can be prevented from deteriorating.
- the source electrode 16S and the drain electrode 16D are formed of a laminated film including an aluminum alloy film, the source electrode 16S and the drain electrode 16D have excellent heat resistance. Therefore, even if heat treatment is performed at a high temperature of about 350 ° C. in a step after the step of forming the source electrode 16S and the drain electrode 16D, hillocks (unevenness) are generated on the surfaces of the source electrode 16S and the drain electrode 16D. There is no possibility that the oxide semiconductor film 14 reacts with the source electrode 16S / drain electrode 16D to deteriorate the electrical characteristics of the oxide semiconductor film 14. Therefore, for example, after the passivation film 17 is formed, an annealing process can be performed at a high temperature of about 350 ° C.
- the TFT substrate 10 can be made compact in layout, and lower power consumption and higher definition can be realized as the aperture ratio is improved.
- the TFT substrate 10 of the present embodiment has excellent electrical characteristics and can be charged at high speed with high switching characteristics, so that a high frame rate can be achieved. Therefore, the TFT substrate 10 of this embodiment is suitable for the case of constituting a liquid crystal panel of a 3D display.
- the gate protective film 15b is described as being provided at the intersection of the gate signal line 12GL and the source signal line 16SL, the gate protective film 15b may not be provided.
- the TFT provided corresponding to each pixel in the display area D has been described, but the TFT having the above-described configuration may be provided in the terminal area T. Even when the TFT of this embodiment is provided in the terminal region T, low power consumption and high definition can be realized because the TFT has excellent electrical characteristics. In this case, the area of the frame region can be reduced by increasing the definition of the TFT in the terminal region T. Therefore, this TFT substrate is suitable for constituting a liquid crystal panel of a mobile device.
- the channel protective layer 15a since the channel protective layer 15a has a light shielding property, it is possible to suppress a change in electrical characteristics when the oxide semiconductor film 14 is irradiated with light. Further, since the channel protective layer 15a is provided in an island shape, a region other than the channel portion in the oxide semiconductor film 14 is not shielded from light. For this reason, it is possible to suppress a decrease in the aperture ratio due to light shielding in a region other than the channel portion.
- the channel protective layer 15a is formed of a laminate of a plurality of films.
- the channel protective layer 15a has a configuration in which an insulating resin film 61a, a light-shielding metal film 62a, and a photosensitive insulating film 63a are sequentially stacked from the bottom, and has a light-shielding property as a whole.
- the channel protective layer 15 a is provided by being patterned into an island shape so as to cover the channel portion so as to correspond to the channel region of the oxide semiconductor film 14.
- the channel protective layer 15a is provided so as to cover the channel portion of the oxide semiconductor film 14, the channel portion is prevented from being directly heated in the heat treatment step, and the resistance of the channel portion is reduced, and the oxide semiconductor film 14 is reduced. It is suppressed that the electrical characteristics of are deteriorated.
- the insulating resin film 61a is formed of, for example, a SiO 2 film having a thickness of about 10 to 500 nm.
- the light-shielding metal film 62a is formed of, for example, a metal film such as an Al film, a Mo film, a W film, a Ta film, or a Ti film, or an alloy film containing these metals as a main component, and has a thickness of 40, for example. About 200 nm.
- the photosensitive insulating film 63a is formed of, for example, a heat-resistant transparent sightseeing type protective film having a thickness of about 100 to 3000 nm (for example, “Optomer PC” series manufactured by JSR Corporation).
- the channel protective layer 15a is manufactured by continuously forming a SiO 2 film, a light-shielding metal film, and a photosensitive insulating film, and then patterning the photosensitive insulating film to form the channel protective layer 15a and the gate.
- Photosensitive insulating films 63a and 63b corresponding to the protective layer 15b are formed.
- wet etching is performed using the photosensitive insulating films 63a and 63b as a mask, and as shown in FIG. 16A, the oxide semiconductor film is etched to form the light-shielding metal films 62a and 63b, and then the SiO 2 film is formed.
- Insulating resin films 61a and 61b are formed by etching.
- the channel protective layer 15a thus obtained has a light shielding property as in the TFT of Embodiment 2, it is possible to suppress a change in electrical characteristics due to irradiation of the oxide semiconductor film 14 with light. Can do.
- the present invention is useful for a TFT substrate having a TFT provided with an oxide semiconductor film, a display device, and a method for manufacturing the TFT substrate.
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Abstract
Description
基板上に設けられたゲート電極と、
基板上に設けられ、ゲート電極を覆うゲート絶縁膜と、
ゲート絶縁膜上に設けられ、ゲート電極に対向する位置にチャネル部が形成された酸化物半導体膜と、
酸化物半導体膜上に設けられ、チャネル部を島状に覆うチャネル保護層と、
酸化物半導体膜上に設けられ、チャネル部及びチャネル保護層を介して互いに離間して設けられたソース電極及びドレイン電極と、
ソース電極及びドレイン電極の上層に設けられた層間絶縁膜と、
を備えたものであって、
ソース電極及びドレイン電極は、アルミニウム合金膜、または、アルミニウム合金膜を含む積層膜で構成されていることを特徴とする。
基板の上にゲート電極を形成し、
ゲート電極の上にゲート絶縁膜を形成し、
ゲート絶縁膜の上に酸化物半導体膜を形成し、
酸化物半導体膜のチャネル部を覆うように島状にチャネル保護層を形成し、
酸化物半導体膜及びチャネル保護層の上に、アルミニウム合金膜、または、アルミニウム合金膜を含む積層膜でソース電極及びドレイン電極を形成し、
ソース電極及びドレイン電極の上に層間絶縁膜を形成し、
その後、上記層間絶縁膜を200~350℃でアニールすることを特徴とする。
(液晶表示装置の構成)
-TFT基板-
図1は、本実施形態1にかかる薄膜トランジスタを備えるTFT基板10を有する液晶表示装置1の平面図であり、図2は、図1のII-II線における断面図である。また、図3は、本実施形態にかかるTFTを備えるTFT基板10の表示領域Dを拡大した平面図であり、図4はTFT基板10の表示領域DのTFTの拡大平面図、及び図5は図4のV-V線におけるTFTの断面図である。
対向基板20は、図示しないが、基板上に遮光層及び着色層を備えたカラーフィルタ層が設けられ、カラーフィルタ層を覆うように共通電極が設けられ、さらに、共通電極を覆うように配向膜が設けられている。
液晶層30は、例えば、電気光学特性を有するネマチックの液晶材料などにより構成されている。
上記構成の液晶表示装置1では、各画素において、ゲートドライバからゲート信号がゲート信号線12GLを介してゲート電極12Gに送られて、表示領域DのTFTがオン状態になったときに、TFTにおいて、ソースドライバからソース信号がソース信号線16SLを介してソース電極16Sに送られて、酸化物半導体膜14及びドレイン電極16Dを介して、画素電極19に所定の電荷が書き込まれる。この際、TFT基板10の各画素電極19と対向基板20の共通電極との間において電位差が生じ、液晶層30、すなわち、各画素の液晶容量、及びその液晶容量に並列に接続された保持容量素子に所定の電圧が印加される。そして、液晶表示装置1では、各画素において、液晶層30に印加する電圧の大きさによって液晶層30の配向状態を変えることにより、液晶層30の光透過率を調整して画像が表示される。
以下、本実施形態にかかるTFT基板10の製造方法について図6及び7を用いて説明する。
まず、基板11上に、例えば、Ti膜(厚さが1~10nm程度)、Al膜(厚さが50~400nm程度)、及びTi膜(厚さが50~300nm程度)を順に連続成膜して第1導電膜を形成し、その後、ゲート電極12G、ゲート信号線12GL、保持容量線12CsL、引き出し線12c等を形成するように、パターンニングを行う。そして、図6(a)に示すように、第1導電膜をパターンニングした後形成されたゲート電極12G、ゲート信号線12GL、保持容量線12CsL、引き出し線12c等の上層に、厚さ100~500nm程度のSiN膜及び厚さ20~100nm程度のSiO2膜を積層してゲート絶縁膜13を成膜する。
続いて、例えば厚さ20~200nm程度の酸化物半導体膜14を成膜し、図6(b)に示すように、TFTを形成する領域のそれぞれに対応するようにパターンニングを行う。
次に、例えば厚さが50~400nm程度のSiO2膜を成膜した後パターンニングすることにより、図6(c)に示すように、チャネル保護層15a及びゲート保護層15bを形成する。そして、チャネル保護層15a及びゲート保護層15bを形成後、例えば、大気雰囲気下で200~350℃及び0.5~10時間の条件でアニール処理を行う。
次いで、例えば、Ti膜(厚さが1~10nm程度)、Al膜(厚さが50~400nm程度)、及びTi膜(厚さが50~300nm程度)を順に連続成膜して第2導電膜を形成し、その後、図7(a)に示すように、ソース電極16S、ドレイン電極16D、ソース信号線16SLを形成するように、第2導電膜のパターンニングを行う。
続いて、図7(b)に示すように、基板11全面に、パッシベーション膜17として例えば厚さが50~500nm程度のSiO2膜を成膜した後、例えば、大気雰囲気下で200~350℃及び0.5~10時間の条件でアニール処理を行う。
次に、保持容量素子の領域に、平坦化膜18の表面からドレイン電極16Dに達するコンタクトホールCCsを形成すると共に、ゲートソースコンタクト部において、ソース信号線16SL及び引き出し線12cが表面に露出するコンタクトホールCcを形成する。
上記の構成によれば、酸化物半導体膜14のチャネル部を覆うように島状にチャネル保護層15aが設けられているので、酸化物半導体膜14のチャネル部が高温に曝されて電気的特性が劣化するのを抑制することができる。
図4及び5に示す実施形態1の構成のTFT(実施例)と、図17及び18に示す従来の構成のTFT(比較例)について、各々の電気的特性を評価するための測定を行った。TFTの電気的特性を定量的に示すパラメーターとしては、S値(サブスレッショルドスイング(Subthreshold swing)値)が用いられる。S値は、しきい値電圧以下の領域での、ゲート電圧に対するドレイン電流の変化率のことであり、TFTのId-Vg特性の傾き(S=ΔId/ΔVg)を計測して求めることができる。
次に、実施形態2の液晶表示装置について説明する。
液晶表示装置1は、実施形態1と同様、TFT基板10と対向基板20とが互いに対向するように配置され、基板外周縁部に設けられたシール材40により両者が接着されている。そして、シール材40に囲まれた領域に、表示媒体層として液晶層30が設けられている。
対向基板20は、図示しないが、基板上に遮光層及び着色層を備えたカラーフィルタ層が設けられ、カラーフィルタ層を覆うように共通電極が設けられ、さらに、共通電極を覆うように配向膜が設けられている。
液晶層30は、例えば、電気光学特性を有するネマチックの液晶材料などにより構成されている。
上記構成の液晶表示装置1では、各画素において、ゲートドライバからゲート信号がゲート信号線12GLを介してゲート電極12Gに送られて、表示領域DのTFTがオン状態になったときに、TFTにおいて、ソースドライバからソース信号がソース信号線16SLを介してソース電極16Sに送られて、酸化物半導体膜14及びドレイン電極16Dを介して、画素電極19に所定の電荷が書き込まれる。この際、TFT基板10の各画素電極19と対向基板20の共通電極との間において電位差が生じ、液晶層30、すなわち、各画素の液晶容量、及びその液晶容量に並列に接続された保持容量素子に所定の電圧が印加される。そして、液晶表示装置1では、各画素において、液晶層30に印加する電圧の大きさによって液晶層30の配向状態を変えることにより、液晶層30の光透過率を調整して画像が表示される。
以下、本実施形態にかかるTFT基板10の製造方法について図12~13を用いて説明する。
まず、基板11上に、例えば、Ti膜(厚さが1~10nm程度)、Al膜(厚さが50~400nm程度)、及びTi膜(厚さが50~300nm程度)を順に連続成膜して第1導電膜を形成し、その後、ゲート電極12G、ゲート信号線12GL、保持容量線12CsL、引き出し線12c等を形成するように、パターンニングを行う。そして、図6(a)に示すように、第1導電膜をパターンニングした後形成されたゲート電極12G、ゲート信号線12GL、保持容量線12CsL、引き出し線12c等の上層に、厚さ100~500nm程度のSiN膜及び厚さ20~100nm程度のSiO2膜を積層してゲート絶縁膜13を成膜する。
続いて、例えば厚さ20~200nm程度の酸化物半導体膜14を成膜し、図12(b)に示すように、TFTを形成する領域のそれぞれに対応するようにパターンニングを行う。
次に、SiO2膜、酸化物半導体膜、及び遮光性感光性樹脂膜を連続して成膜したのち、遮光性感光性樹脂膜をパターンニングして、チャネル保護層15a及びゲート保護層15bに対応する遮光性感光性樹脂膜53a、53bを形成する。そして、遮光性感光性樹脂膜53a,53bをマスクとしてウェットエッチングを行い、図12(c)に示すように、酸化物半導体膜をエッチングして酸化物半導体膜52a,53bを形成後、SiO2膜をエッチングして絶縁性樹脂膜51a,51bを形成する。そして、図13(a)に示すように、熱処理を行って遮光性感光性樹脂膜53aを硬化させることにより、遮光性感光性樹脂膜53a、53bが酸化物半導体膜52a、52bを覆うようにリフローさせる。
次いで、例えば、Ti膜(厚さが1~10nm程度)、Al膜(厚さが50~400nm程度)、及びTi膜(厚さが50~300nm程度)を順に連続成膜して第2導電膜を形成し、その後、図13(b)に示すように、ソース電極16S、ドレイン電極16D、ソース信号線16SLを形成するようにパターンニングを行う。
続いて、図13(b)に示すように、基板11全面に、パッシベーション膜17として例えば厚さが50~500nm程度のSiO2膜を成膜した後、例えば、大気雰囲気下で200~350℃及び0.5~10時間の条件でアニール処理を行う。
次に、保持容量素子の領域に、平坦化膜18の表面からドレイン電極16Dに達するコンタクトホールCCsを形成すると共に、ゲートソースコンタクト部において、ソース信号線16SL及び引き出し線12cが表面に露出するコンタクトホールCcを形成する。
上記の構成によれば、酸化物半導体膜14のチャネル部を覆うように島状にチャネル保護層15aが設けられているので、酸化物半導体膜14のチャネル部が高温に曝されて電気的特性が劣化するのを抑制することができる。
上記説明した実施形態2のTFT基板では、チャネル保護層15aが絶縁性樹脂膜51a、酸化物半導体膜52a、及び遮光性感光性樹脂膜53aからなる積層体で形成されてチャネル保護層が遮光性を有するとして説明したが、チャネル保護層15aがその他の構成を有することにより遮光性を有するものであってもよい。以下、チャネル保護層15aの構成が実施形態2と異なる場合の変形実施例について説明する。
チャネル保護層15aは、複数の膜の積層体で形成されている。チャネル保護層15aは、絶縁性樹脂膜61a、遮光性金属膜62a、及び感光性絶縁膜63aが下から順に積層された構成を有し、全体として遮光性を有する。チャネル保護層15aは、酸化物半導体膜14のチャネル領域に対応するようにチャネル部を覆って島状にパターンニングされて設けられている。チャネル保護層15aが酸化物半導体膜14のチャネル部を覆うように設けられているので、チャネル部が熱処理工程において直接加熱されるのが抑制され、チャネル部が低抵抗化して酸化物半導体膜14の電気的特性が劣化するのが抑制される。
10 TFT基板
11 基板
12G ゲート電極
13 ゲート絶縁膜
14 酸化物半導体膜
15a チャネル保護層
16S ソース電極
16D ドレイン電極
17 パッシベーション膜(層間絶縁膜)
18 平坦化膜(層間絶縁膜)
51a 絶縁性樹脂膜
52a 酸化物半導体膜
53a 遮光性感光性樹脂膜
61a 絶縁性樹脂膜
62a 遮光性金属膜
63a 感光性絶縁膜
Claims (18)
- 基板と、
上記基板上に設けられたゲート電極と、
上記基板上に設けられ、上記ゲート電極を覆うゲート絶縁膜と、
上記ゲート絶縁膜上に設けられ、上記ゲート電極に対向する位置にチャネル部が形成された酸化物半導体膜と、
上記酸化物半導体膜上に設けられ、上記チャネル部を島状に覆うチャネル保護層と、
上記酸化物半導体膜上に設けられ、上記チャネル部及びチャネル保護層を介して互いに離間して設けられたソース電極及びドレイン電極と、
上記ソース電極及びドレイン電極の上層に設けられた層間絶縁膜と、
を備えた薄膜トランジスタ基板であって、
上記ソース電極及びドレイン電極は、アルミニウム合金膜、または、アルミニウム合金膜を含む積層膜で構成されていることを特徴とする薄膜トランジスタ基板。 - 請求項1に記載された薄膜トランジスタ基板において、
上記チャネル保護層は、遮光性を有することを特徴とする薄膜トランジスタ基板。 - 請求項2に記載された薄膜トランジスタ基板において、
上記チャネル保護層は、遮光性を有する感光性樹脂膜を含む複数の膜の積層体で形成されていることを特徴とする薄膜トランジスタ基板。 - 請求項3に記載された薄膜トランジスタ基板において、
上記積層体を構成する複数の膜は、絶縁性樹脂膜、該絶縁性樹脂膜の上層の酸化物半導体膜、及び該酸化物半導体膜の上層の上記遮光性感光性樹脂膜であることを特徴とする薄膜トランジスタ基板。 - 請求項2に記載された薄膜トランジスタ基板において、
上記チャネル保護層は、遮光性を有する金属膜を含む複数の膜の積層体で形成されていることを特徴とする薄膜トランジスタ基板。 - 請求項5に記載された薄膜トランジスタ基板において、
上記積層体を構成する複数の膜は、絶縁性樹脂膜、該絶縁性樹脂膜の上層の上記遮光性金属膜、及び該遮光性金属膜の上層の感光性絶縁膜であることを特徴とする薄膜トランジスタ基板。 - 請求項1~6のいずれか1項に記載された薄膜トランジスタ基板において、
上記ソース電極及びドレイン電極を構成するアルミニウム合金膜は、350℃以上の耐熱性を有することを特徴とする薄膜トランジスタ基板。 - 請求項7に記載された薄膜トランジスタ基板において、
上記アルミニウム合金膜は、主成分がアルミニウムであって、副成分がケイ素(Si)、ネオジム(Nd)、銅(Cu)、ニッケル(Ni)及びランタン(La)からなる群より選ばれる少なくとも1種である合金からなることを特徴とする薄膜トランジスタ基板。 - 請求項1~8のいずれか1項に記載された薄膜トランジスタ基板と、該薄膜トランジスタ基板に対向して配置された対向基板と、該薄膜トランジスタ基板と該対向基板との間に設けられた表示媒体層と、を備えたことを特徴とする表示装置。
- 請求項9に記載された表示装置において、
上記表示媒体層が液晶層であることを特徴とする表示装置。 - 基板と、該基板上に設けられたゲート電極と、該基板上に設けられ、該ゲート電極を覆うゲート絶縁膜と、該ゲート絶縁膜上に設けられ、該ゲート電極に対向する位置にチャネル部が形成された酸化物半導体膜と、該酸化物半導体膜上に設けられ、該チャネル部を島状に覆うチャネル保護層と、該酸化物半導体膜上に設けられ、該チャネル部及びチャネル保護層を介して互いに離間して設けられたソース電極及びドレイン電極と、該ソース電極及びドレイン電極の上層に設けられた層間絶縁膜と、を備えた薄膜トランジスタ基板の製造方法であって、
基板の上にゲート電極を形成し、
上記ゲート電極の上にゲート絶縁膜を形成し、
上記ゲート絶縁膜の上に酸化物半導体膜を形成し、
上記酸化物半導体膜のチャネル部を覆うように島状にチャネル保護層を形成し、
上記酸化物半導体膜及び上記チャネル保護層の上に、アルミニウム合金膜、または、アルミニウム合金膜を含む積層膜でソース電極及びドレイン電極を形成し、
上記ソース電極及びドレイン電極の上に層間絶縁膜を形成し、
その後、上記層間絶縁膜を200~350℃でアニールすることを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項11に記載された薄膜トランジスタ基板の製造方法において、
上記チャネル保護層を、遮光性を有する材料で形成することを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項12に記載された薄膜トランジスタ基板の製造方法において、
上記チャネル保護層を、遮光性を有する感光性樹脂膜を含む複数の膜を積層して形成することを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項13に記載された薄膜トランジスタ基板の製造方法において、
上記チャネル保護層として積層する複数の膜は、絶縁性樹脂膜、該絶縁性樹脂膜の上層の酸化物半導体膜、及び該酸化物半導体膜の上層の上記遮光性感光性樹脂膜であることを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項12に記載された薄膜トランジスタ基板の製造方法において、
上記チャネル保護層を、遮光性を有する金属膜を含む複数の膜を積層して形成することを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項15に記載された薄膜トランジスタ基板の製造方法において、
上記チャネル保護層として積層する複数の膜は、絶縁性樹脂膜、該絶縁性樹脂膜の上層の上記遮光性金属膜、及び該遮光性金属膜の上層の感光性絶縁膜であることを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項11~16のいずれか1項に記載された薄膜トランジスタ基板の製造方法において、
上記ソース電極及びドレイン電極を構成するアルミニウム合金膜は、350℃以上の耐熱性を有することを特徴とする薄膜トランジスタ基板の製造方法。 - 請求項17に記載された薄膜トランジスタ基板の製造方法において、
上記アルミニウム合金膜は、主成分がアルミニウムであって、副成分がケイ素(Si)、ネオジム(Nd)、銅(Cu)、ニッケル(Ni)及びランタン(La)からなる群より選ばれる少なくとも1種である合金からなることを特徴とする薄膜トランジスタ基板の製造方法。
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Cited By (4)
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CN103337497A (zh) * | 2013-06-28 | 2013-10-02 | 北京京东方光电科技有限公司 | 一种阵列基板及其制造方法、显示装置 |
KR20150065220A (ko) * | 2013-12-04 | 2015-06-15 | 엘지디스플레이 주식회사 | 어레이기판 |
JP2015153902A (ja) * | 2014-02-14 | 2015-08-24 | 凸版印刷株式会社 | 薄膜トランジスタ装置及びその製造方法 |
JP2020532117A (ja) * | 2017-09-14 | 2020-11-05 | 深▲セン▼市▲華▼星光▲電▼半▲導▼体▲顕▼示技▲術▼有限公司 | Tftデバイス及び液晶表示パネルの静電気保護回路 |
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US20150179801A1 (en) * | 2013-12-25 | 2015-06-25 | Shenzhen China Star Optoelectronics Technology Co. Ltd. | Thin film transistor and method for manufacturing the same |
CN104377247B (zh) * | 2014-11-24 | 2017-12-08 | 深圳市华星光电技术有限公司 | 薄膜晶体管、显示装置及薄膜晶体管的制造方法 |
CN108701719A (zh) * | 2016-02-22 | 2018-10-23 | 夏普株式会社 | 半导体装置和半导体装置的制造方法 |
KR101897345B1 (ko) * | 2016-09-21 | 2018-09-10 | 고려대학교 산학협력단 | 박막 트랜지스터 |
KR20200024382A (ko) | 2018-08-27 | 2020-03-09 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 제조 방법 |
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- 2012-01-10 KR KR1020137019645A patent/KR101604895B1/ko active IP Right Grant
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JP2020532117A (ja) * | 2017-09-14 | 2020-11-05 | 深▲セン▼市▲華▼星光▲電▼半▲導▼体▲顕▼示技▲術▼有限公司 | Tftデバイス及び液晶表示パネルの静電気保護回路 |
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Also Published As
Publication number | Publication date |
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US9171940B2 (en) | 2015-10-27 |
JPWO2012096154A1 (ja) | 2014-06-09 |
CN103314446B (zh) | 2016-04-20 |
KR20140003506A (ko) | 2014-01-09 |
KR101604895B1 (ko) | 2016-03-18 |
JP5357342B2 (ja) | 2013-12-04 |
US20130292682A1 (en) | 2013-11-07 |
CN103314446A (zh) | 2013-09-18 |
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