WO2012070151A1 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 146
- 238000000034 method Methods 0.000 title claims description 22
- 230000001681 protective effect Effects 0.000 claims abstract description 84
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 29
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 6
- 229910002704 AlGaN Inorganic materials 0.000 claims description 5
- 239000011203 carbon fibre reinforced carbon Substances 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 description 39
- 239000002245 particle Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 238000000926 separation method Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 8
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 8
- 229910002804 graphite Inorganic materials 0.000 description 7
- 239000010439 graphite Substances 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 5
- 238000012546 transfer Methods 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 4
- 238000010891 electric arc Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000006911 nucleation Effects 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000001771 vacuum deposition Methods 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- -1 carbon ions Chemical class 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005001 rutherford backscattering spectroscopy Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
- Some field effect transistors have a structure in which an AlGaN / GaN heterojunction is used and a GaN layer is used as an electron transit layer.
- GaN has a wide band gap and is a material having a high breakdown voltage strength and a large saturation electron velocity, so that a semiconductor device capable of realizing a large current, high withstand voltage, and low on-resistance operation is formed. Promising as a material. Therefore, power saving exceeding the limit of silicon power devices is possible, and semiconductor devices using GaN-based materials are being studied as high-efficiency switching elements in the next generation.
- an insulating film is usually formed on the entire surface of the field effect transistor or the like for passivation or the like after forming a gate electrode or a drain electrode.
- an insulating film is formed as a protective film for passivation or the like. In some cases, a sufficient breakdown voltage cannot be obtained.
- a semiconductor device such as a transistor in which an insulating film is formed between a gate electrode and a semiconductor layer
- a semiconductor device and a semiconductor capable of obtaining a sufficient withstand voltage even when the insulating film is formed as a protective film.
- the first semiconductor layer formed on the substrate, the second semiconductor layer formed on the first semiconductor layer, and the first semiconductor layer A source electrode and a drain electrode formed in contact with the second semiconductor layer, an opening formed in the first semiconductor layer, and formed above the second semiconductor layer and on an inner surface of the opening.
- the first semiconductor layer formed on the substrate, the second semiconductor layer formed on the first semiconductor layer, and the first semiconductor layer A source electrode and a drain electrode formed on the semiconductor layer or in contact with the second semiconductor layer; an insulating film formed above the second semiconductor layer; and a gate electrode formed on the insulating film; And a protective film formed on the insulating film, wherein the protective film includes an amorphous film containing carbon as a main component.
- a step of stacking and forming a first semiconductor layer and a second semiconductor layer on a substrate, the first semiconductor layer, or the second semiconductor Forming a source electrode and a drain electrode in contact with the layer; forming an opening in the second semiconductor layer; and forming an insulating film above the second semiconductor layer and on an inner surface of the opening
- a step of forming a gate electrode in the opening through the insulating film, and a step of forming a protective film including an amorphous film mainly composed of carbon on the exposed insulating film It is characterized by that.
- a step of stacking and forming a first semiconductor layer and a second semiconductor layer on a substrate, the first semiconductor layer, or the second semiconductor A step of forming a source electrode and a drain electrode in contact with the layer; a step of forming an insulating film above the second semiconductor layer; a step of forming a gate electrode on a portion of the insulating film; Forming a protective film including an amorphous film containing carbon as a main component on the insulating film.
- the insulating film is formed as a protective film. Sufficient breakdown voltage can be obtained.
- a transistor having an insulating film formed between a gate electrode and a semiconductor layer and having an insulating film as a protective film will be described.
- a transistor having this structure is called a HEMT (High Electron Mobility Transistor), and an electron transit layer 512, an electron supply layer 513, and a cap layer 514 are stacked on a substrate 511 by epitaxial growth. Is formed.
- a two-dimensional electron gas (2DEG) 512a is formed on the electron transit layer 512 closer to the electron supply layer 513.
- the source electrode 515 and the drain electrode 516 are formed in an opening formed by removing the cap layer 514 and the electron supply layer 513, and are connected to the electron transit layer 512.
- the gate electrode 518 is formed through an insulating film 517 in an opening formed by removing a part of the cap layer 514 and the electron supply layer 513. Note that the insulating film 517 is also formed on the cap layer 514, and a protective film 519 is formed on the insulating film 517.
- the substrate 511 is a SiC substrate, a sapphire (Al 2 O 3 ) substrate or the like, the electron transit layer 512 is formed of i-GaN, and the electron supply layer 513 is formed of n-AlGaN, and the cap
- the layer 514 is made of n-GaN.
- the source electrode 515, the drain electrode 516, and the gate electrode 518 are formed of a metal material, and the insulating film 517 is formed by forming an aluminum oxide (Al 2 O 3 ) film by plasma ALD (Atomic Layer Deposition). Is formed.
- the protective film 519 is formed of a silicon nitride (SiN) film. However, from the viewpoint of improving throughput or the like, generally, when the protective film 519 is formed, plasma CVD (at a high film formation rate) Chemical Vapor Deposition) is often used.
- a transistor having a structure in which such a protective film 519 is formed tends to have a significantly lower breakdown voltage than a transistor having a structure in which the protective film 519 is not formed. That is, when the protective film 519 is formed, the withstand voltage of the transistor is lowered and the characteristics are deteriorated.
- a silicon nitride film that is a protective film 519 is formed by plasma CVD, but an aluminum oxide film that is an insulating film 517 is reduced by a reduction action of hydrogen generated as a reaction byproduct generated from a film forming gas. A metal-rich layer is formed at the interface. As a result, it is considered that the withstand voltage decreases.
- the protective film 519 is formed by plasma CVD, when the protective film 519 is formed, the surface of the insulating film 517 is damaged by plasma, and defects such as oxygen are generated. As a result, it is considered that the withstand voltage decreases.
- the semiconductor device in this embodiment is a transistor called HEMT, and an electron transit layer 12, an electron supply layer 13, and a cap layer 14 are formed by being epitaxially grown on a substrate 11 made of a semiconductor or the like.
- the source electrode 15 and the drain electrode 16 are connected to the electron transit layer 12, and the gate electrode 18 is formed in the opening formed by removing a part of the cap layer 14 and the electron supply layer 13. It is formed via an insulating film 17.
- the insulating film 17 is also formed on the cap layer 14, and the first insulating protective film 21, the amorphous carbon film 22, and the second insulating protective film 23 are formed on the insulating film 17 as the protective film 20. Is formed.
- the substrate 11 As the substrate 11, a SiC substrate, a sapphire (Al 2 O 3 ) substrate or the like is used.
- the electron transit layer 12 serving as the first semiconductor layer is formed of i-GaN
- the electron supply layer 13 serving as the second semiconductor layer is formed of n-AlGaN
- the cap serving as the third semiconductor layer.
- the layer 14 is made of n-GaN.
- a two-dimensional electron gas (2DEG) 12a is formed on the side of the electron transit layer 12 closer to the electron supply layer 13.
- the source electrode 15, the drain electrode 16, and the gate electrode 18 are made of a metal material
- the insulating film 17 is formed by forming an aluminum oxide (Al 2 O 3 ) film by plasma ALD (Atomic Layer Deposition). Is formed.
- the first insulating protective film 21 is formed of an aluminum oxide film
- the second insulating protective film 23 is formed of a silicon nitride (SiN) film.
- the amorphous carbon film 22 is an amorphous film containing carbon as a main component, and is also called DLC (Diamond-Like-Carbon).
- the amorphous carbon film 22 is a high-density insulating film excellent in hydrogen barrier properties, has high insulating properties, and has high surface smoothness.
- the hydrogen content in the film is suppressed as much as possible, and it is preferably diamond-like.
- the film density is high and sp3 is large in carbon-carbon bonds.
- the amorphous carbon film containing hydrogen that can be formed by CVD has the highest density of about 2.6 g / cm 3 , and the diamond density is 3.56 g / cm 3 . is there. Accordingly, the amorphous carbon film 22, 2.7 g / cm 3 or more, preferably 3.56 g / cm 3 or less.
- the film density is calculated based on the result obtained by Rutherford backscattering method and the film thickness obtained by cross-sectional length measurement using TEM (Transmission Electron Microscope). Is done.
- the carbon-carbon bonds in carbon include sp2 and sp3, and graphite (graphite) is formed by sp2 bonds, and diamond is formed by sp3 bonds.
- the carbon-carbon bond is preferably sp2 ⁇ sp3.
- Such an amorphous carbon film can be formed by an FCA (Filtered Cathodic Arc) method which is an arc vapor deposition method to be described later.
- the amorphous carbon film formed by the FCA method had a film density of 3.2 g / cm 3 .
- the film thickness of the amorphous carbon film to be formed is preferably 1 nm or more and 30 nm or less.
- a film thickness of at least several atomic layers or more is required. Therefore, the entire surface cannot be covered with a film thickness of 1 nm or less.
- the amorphous carbon film has a large stress, if the film thickness is increased, the film peels off due to the stress.
- the amorphous carbon film 22 even when a silicon nitride (SiN) film is formed by plasma CVD as the second insulating protective film 23, plasma damage to the insulating film 17 is caused. There is no influence.
- a gas containing a hydrogen component is not used, so that the aluminum oxide film on the surface of the insulating film 17 is not reduced by hydrogen or the like, and the surface of the insulating film 17 A metal rich layer is not formed. For these reasons, the withstand voltage can be increased.
- a nucleation layer (not shown) is formed on a substrate 11, and semiconductor layers such as an electron transit layer 12, an electron supply layer 13, and a cap layer 14 are formed by MOVPE (Metal -Organic Vapor Phase Epitaxy) etc. to form by epitaxial growth.
- MOVPE Metal -Organic Vapor Phase Epitaxy
- the substrate 11 is a substrate such as SiC or sapphire (Al 2 O 3 ), and a nucleation layer (not shown) formed on the substrate 11 is, for example, a non-doped i-AlN having a thickness of 0.1 ⁇ m. It is formed by.
- the electron transit layer 12 is made of non-doped i-GaN having a thickness of 3.0 ⁇ m, and the electron supply layer 13 is made of n-Al 0.25 Ga 0.75 N having a thickness of 20 nm.
- the cap layer 14 is made of n-GaN having a thickness of 5 nm.
- the semiconductor layer may be formed by crystal growth of the semiconductor layer by MBE (Molecular Beam Epitaxy) in addition to MOVPE.
- the source electrode 15 and the drain electrode 16 are formed. Specifically, a photoresist is applied on the cap layer 14, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having openings in regions where the source electrode 15 and the drain electrode 16 are formed. Form. Thereafter, the cap layer 14 and the electron supply layer 13 in the region where the resist pattern is not formed are removed by dry etching such as RIE using chlorine gas, and etching is performed until the surface of the electron transit layer 12 is exposed. The dry etching performed at this time is performed by introducing about 30 sccm of chlorine gas as an etching gas into the chamber, setting the pressure in the chamber to about 2 Pa, and applying RF power of 20 W.
- dry etching such as RIE using chlorine gas
- a metal film made of a Ta / Al laminated film or the like is formed by vacuum deposition or the like, and then the metal film in the region where the resist pattern is formed is removed together with the resist pattern by lift-off to thereby form the source electrode 15 and the drain.
- the electrode 16 is formed.
- a heat treatment is performed at a temperature of 550 ° C. to make ohmic contact.
- an opening 31 is formed. Specifically, a photoresist is applied on the cap layer 14, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the opening 31 is formed. Thereafter, a gas containing chlorine is introduced using the resist pattern as a mask and dry etching is performed by RIE or the like to remove a part of the cap layer 14 and the electron supply layer 13 in the region where the resist pattern is not formed. . Thereby, the opening part 31 is formed. After this, the resist pattern is removed.
- an insulating film 17 is formed inside the opening 31 and on the cap layer 14.
- the insulating film 17 is formed by depositing 5 to 100 nm of aluminum oxide, tantalum oxide, hafnium oxide, or the like by a film forming method such as ALD. Specifically, in this embodiment mode, aluminum oxide is formed to a thickness of 20 nm by ALD or the like.
- the gate electrode 18 is formed. Specifically, a lower layer resist (not shown) (for example, trade name PMGI: manufactured by US Microchem) and an upper layer resist (not illustrated) (for example, trade name PFI32-A8: manufactured by Sumitomo Chemical Co., Ltd.) are formed on the insulating film 17. Each is formed by coating by a spin coat method or the like. Thereafter, exposure and development by an exposure apparatus are performed to form an opening having a diameter of about 0.8 ⁇ m in a region including a portion where the opening 31 is formed in the upper resist. Next, using the upper layer resist as a mask, the lower layer resist is wet etched with an alkaline developer.
- a lower layer resist for example, trade name PMGI: manufactured by US Microchem
- an upper layer resist for example, trade name PFI32-A8: manufactured by Sumitomo Chemical Co., Ltd.
- a metal film (Ni: film thickness of about 10 nm / Au: film thickness of about 300 nm) is formed on the entire surface by vacuum deposition, and lift-off is performed using a heated organic solvent, whereby both the lower layer resist and the upper layer resist are formed. Then, the metal film formed on the upper resist is removed. Thereby, the gate electrode 18 made of Ni / Au is formed in the opening 31 via the insulating film 17.
- the protective film 20 is formed by laminating the first insulating protective film 21, the amorphous carbon film 22, and the second insulating protective film 23 on the insulating film 17.
- the first insulating protective film 21 is formed by forming an aluminum oxide film having a thickness of 50 nm by an ALD method.
- the amorphous carbon film 22 is formed by the FCA method using a graphite target as a raw material so as to have a film thickness of about 10 nm under the conditions of an arc current of 70 A and an arc voltage of 26 V.
- a silicon nitride film having a thickness of about 350 nm is formed by plasma CVD using SiH 4 , N 2 , and NH 3 as source gases under the condition of RF power of 60 W. To form.
- FIG. 5 shows the withstand voltage of a transistor which is a semiconductor device in this embodiment and the withstand voltage of a transistor in which a laminated film of an aluminum oxide film and a silicon nitride film is formed as a protective film for comparison.
- a transistor in which a laminated film of an aluminum oxide film and a silicon nitride film was formed as a protective film device breakdown occurred when a voltage of about 150 V was applied between the source electrode and the drain electrode.
- element breakdown did not occur even when a voltage of 400 V or higher was applied between the source electrode and the drain electrode. Thereby, the withstand voltage can be improved in the semiconductor device in this embodiment.
- FIG. 6 shows the structure of an FCA film forming apparatus used in the FCA method.
- the FCA film forming apparatus includes a plasma generation unit 110, a plasma separation unit 120, a particle trap unit 130, a plasma transfer unit 140, and a film formation chamber 150.
- the plasma generation unit 110, the plasma separation unit 120, and the particle trap unit 130 are all formed in a cylindrical shape and are connected in this order.
- the plasma transfer unit 140 is also formed in a cylindrical shape, with one end connected to the plasma separation unit 120 substantially perpendicularly and the other end connected to the film forming chamber 150.
- a stage 152 for installing a substrate 151 or the like to be formed is provided inside the film formation chamber 150.
- An insulating plate 111 is provided at the lower end of the casing of the plasma generating unit 110, and graphite serving as a target (cathode) 112 is installed on the insulating plate 111.
- a cathode coil 114 is provided on the outer periphery of the lower end of the casing of the plasma generator 110, and an anode 113 is provided on the inner wall surface of the casing.
- a predetermined current is supplied to the cathode coil 114 from another power source (not shown) to generate a magnetic field for stabilizing the arc discharge.
- carbon forming the graphite target 112 is evaporated and supplied as ions of the film forming material into the plasma.
- An insulating ring 121 is provided at a boundary portion between the plasma generating unit 110 and the plasma separating unit 120, and the casing of the plasma generating unit 110 and the casing of the plasma separating unit 120 are electrically separated by the insulating ring 121.
- Guide coils 122a and 122b for generating a magnetic field for moving the plasma generated in the plasma generation unit 110 in a predetermined direction while converging the plasma generated in the plasma generation unit 110 to the center of the case are provided on the outer periphery of the plasma separation unit 120.
- an oblique magnetic field generating coil 123 that generates a magnetic field that bends the plasma traveling direction substantially perpendicularly is provided in the vicinity of the connection portion between the plasma separation unit 120 and the plasma transfer unit 140.
- the particles generated in the plasma generation unit 110 go straight into the particle trap unit 130 without being affected by the magnetic field in the plasma separation unit 120.
- a reflection plate 131 that reflects particles in the horizontal direction and a particle capture unit 132 that captures particles reflected by the reflection plate 131 are provided at the upper end of the particle trap unit 130.
- a plurality of fins 133 are arranged obliquely with respect to the inside of the housing. The particles that have entered the particle capturing unit 132 are reflected many times by these fins 133, lose kinetic energy, and finally adhere to and be captured by the fin 133 or the housing wall surface of the particle capturing unit 132.
- the plasma separated from the particles in the plasma separation unit 120 enters the plasma transfer unit 140.
- the plasma transfer unit 140 is divided into a negative voltage application unit 142 and a communication unit 146.
- An insulating ring 141 is provided between the negative voltage application unit 142 and the plasma separation unit 120 and between the negative voltage application unit 142 and the communication unit 146. Thereby, the plasma separation unit 120 and the negative voltage application unit 142 are electrically separated, and the communication unit 146 and the negative voltage application unit 142 are electrically separated.
- the negative voltage application unit 142 is further divided into an inlet part 143 on the plasma separation part 120 side, an outlet part 145 on the connecting part 146 side, and an intermediate part 144 between the inlet part 143 and the outlet part 145.
- An outer periphery of the inlet 143 is provided with a magnetic field 143a for generating a magnetic field for moving the plasma toward the film forming chamber 150 while converging the plasma.
- a plurality of fins 143 b that capture particles that have entered the inlet portion 143 are installed obliquely with respect to the inner surface of the housing inside the inlet portion 143.
- Apertures 144a and 144b having openings parasitic on the plasma flow path are provided on the inlet 143 side and the outlet 145 side of the intermediate part 144.
- a guide coil 144c that generates a magnetic field for bending the plasma traveling direction is provided on the outer periphery of the intermediate portion 144.
- the connecting portion 146 is formed so that the diameter gradually increases from the negative voltage applying portion 142 side toward the film forming chamber 150.
- a plurality of fins 146a are also provided inside the connecting portion 146, and plasma is converged on the outer periphery of the boundary portion between the connecting portion 146 and the film forming chamber 150 to move toward the film forming chamber 150 side.
- the guide coil 146b is provided.
- the plasma generator 110 generates a plasma containing carbon ions by performing an arc discharge, and the plasma is applied to the substrate 151 while removing components that become particles by the oblique magnetic field generating coil 123 and the like. And so on. Thereby, an amorphous carbon film can be formed on the substrate 151 or the like.
- the semiconductor device in this embodiment has a structure in which an amorphous carbon film 221 and an insulating protective film 222 are formed as a protective film 220 on the insulating film 17.
- an electron transit layer 12, an electron supply layer 13, and a cap layer 14 are laminated on a substrate 11 made of a semiconductor or the like by epitaxial growth.
- the source electrode 15 and the drain electrode 16 are connected to the electron transit layer 12, and the gate electrode 18 is formed in the opening formed by removing a part of the cap layer 14 and the electron supply layer 13. It is formed via an insulating film 17.
- the insulating film 17 is also formed on the cap layer 14, and an amorphous carbon film 221 and an insulating protective film 222 are formed on the insulating film 17 as the protective film 220.
- the insulating protective film 222 is formed of a silicon nitride (SiN) film formed by plasma CVD or the like.
- the amorphous carbon film 221 is the same as the amorphous carbon film 22 in the first embodiment, and is an amorphous film mainly containing carbon.
- the semiconductor device manufacturing method in the present embodiment is the same as that in FIGS. 3A to 4B in the semiconductor device manufacturing method in the first embodiment.
- an amorphous carbon film 221 and an insulating protective film 222 are formed on the insulating film 17.
- the amorphous carbon film 221 is formed by an FCA method using a graphite target as a raw material and an amorphous carbon film having a film thickness of about 10 nm under the conditions of an arc current of 70 A and an arc voltage of 26 V.
- the insulating protective film 222 is formed by forming a silicon nitride film having a thickness of about 350 nm under the condition of RF power of 60 W using SiH 4 , N 2 , and NH 3 as a source gas by plasma CVD. .
- the influence of plasma damage on the insulating film 17 is small when the amorphous carbon film 221 is formed. Further, since a gas containing a hydrogen component or the like is not used in the film formation, the aluminum oxide film on the surface of the insulating film 17 is not reduced by hydrogen or the like, and a metal-rich layer is formed on the surface of the insulating film 17. Is not formed. For these reasons, the withstand voltage can be increased. In addition, if the function as the protective film can be obtained only by the amorphous carbon film, the protective film has a structure in which only the amorphous carbon film 221 is formed without forming the insulating protective film 222. Also good.
- FIG. 1 The structure of the semiconductor device in this embodiment is shown in FIG.
- an electron transit layer 312, an electron supply layer 313, and a cap layer 314 are stacked by epitaxial growth on a substrate 311 made of a semiconductor or the like.
- the source electrode 315 and the drain electrode 316 are formed to be connected to the electron transit layer 312, an insulating film 317 is formed on the cap layer 314, and a gate electrode 318 is further formed on the insulating film 317. Is formed.
- a first insulating protective film 321, an amorphous carbon film 322, and a second insulating protective film 323 are formed as the protective film 320 on the exposed insulating film 317.
- a SiC substrate, a sapphire (Al 2 O 3 ) substrate, or the like is used as the substrate 311.
- the electron transit layer 332 serving as the first semiconductor layer is formed of i-GaN
- the electron supply layer 313 serving as the second semiconductor layer is formed of n-AlGaN
- the cap serving as the third semiconductor layer.
- the layer 314 is made of n-GaN.
- a two-dimensional electron gas (2DEG) 312a is formed on the side of the electron transit layer 312 close to the electron supply layer 313.
- the source electrode 315, the drain electrode 316, and the gate electrode 318 are formed of a metal material, and the insulating film 17 is formed by forming an aluminum oxide (Al 2 O 3 ) film by plasma ALD.
- the first insulating protective film 321 is formed of an aluminum oxide film
- the second insulating protective film 323 is formed of a silicon nitride (SiN) film.
- the amorphous carbon film 322 is the same as the amorphous carbon film 22 in the first embodiment.
- a nucleation layer (not shown) is formed on a substrate 311, and semiconductor layers such as an electron transit layer 312, an electron supply layer 313, and a cap layer 314 are formed by MOVPE or the like. It is formed by epitaxial growth.
- the substrate 311 is a substrate such as SiC or sapphire (Al 2 O 3 ), and a nucleation layer (not shown) formed on the substrate 311 is, for example, a non-doped i-AlN having a thickness of 0.1 ⁇ m. It is formed by.
- the electron transit layer 312 is made of non-doped i-GaN having a thickness of 3.0 ⁇ m, and the electron supply layer 313 is made of n-Al 0.25 Ga 0.75 N having a thickness of 20 nm.
- the cap layer 314 is made of n-GaN having a thickness of 5 nm.
- a source electrode 315 and a drain electrode 316 are formed. Specifically, by applying a photoresist on the cap layer 314 and performing exposure and development with an exposure apparatus, a resist pattern (not shown) having openings in regions where the source electrode 315 and the drain electrode 316 are formed is formed. Form. Thereafter, the cap layer 314 and the electron supply layer 313 in the region where the resist pattern is not formed are removed by dry etching such as RIE using chlorine gas, and etching is performed until the surface of the electron transit layer 312 is exposed.
- dry etching such as RIE using chlorine gas
- a metal film made of a Ta / Al laminated film or the like is formed by vacuum deposition or the like, and then the metal film in the region where the resist pattern is formed is removed together with the resist pattern by lift-off to thereby form the source electrode 315 and the drain.
- An electrode 316 is formed.
- a heat treatment is performed at a temperature of 550 ° C. to make ohmic contact.
- an insulating film 317 is formed on the cap layer 314.
- the insulating film 317 is formed by depositing aluminum oxide, tantalum oxide, hafnium oxide, or the like with a thickness of 5 to 100 nm by a deposition method such as ALD. Specifically, in this embodiment mode, aluminum oxide is formed to a thickness of 20 nm by ALD or the like.
- a gate electrode 318 is formed. Specifically, a photoresist is applied on the insulating film 317, and exposure and development are performed by an exposure apparatus, thereby forming a resist pattern (not shown) having an opening in a region where the gate electrode 318 is formed. Thereafter, a metal film (Ni: film thickness of about 10 nm / Au: film thickness of about 300 nm) is formed on the entire surface by vacuum deposition, and then immersed in an organic solvent or the like to resist the metal film formed on the resist pattern. It is removed by lift-off along with the pattern. Thereby, a gate electrode 318 made of Ni / Au is formed on the insulating film 317.
- a protective film 320 is formed by laminating a first insulating protective film 321, an amorphous carbon film 322, and a second insulating protective film 323 on the insulating film 317.
- the first insulating protective film 321 is formed by depositing an aluminum oxide film having a thickness of 50 nm by an ALD method.
- the amorphous carbon film 322 is formed by an FCA method using a graphite target as a raw material and an amorphous carbon film having a thickness of about 10 nm under the conditions of an arc current of 70 A and an arc voltage of 26 V.
- a silicon nitride film having a thickness of about 350 nm is formed by plasma CVD using SiH 4 , N 2 , and NH 3 as source gases under the condition of RF power of 60 W. To form.
- Electron travel layer (first semiconductor layer) 12a 2DEG 13 Electron supply layer (second semiconductor layer) 14 Cap layer (third semiconductor layer) 15 Source electrode 16 Drain electrode 17 Insulating film 18 Gate electrode 20 Protective film 21 First insulating protective film 22 Amorphous carbon film 23 Second insulating protective film
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Abstract
Description
最初に、ゲート電極と半導体層との間に絶縁膜を形成した構造のトランジスタにおいて、保護膜として絶縁膜を形成した構造のトランジスタについて説明する。図1に示されるように、この構造のトランジスタは、HEMT(High Electron Mobility Transistor)と呼ばれるものであり、基板511上に、電子走行層512、電子供給層513、キャップ層514がエピタキシャル成長により積層して形成されている。尚、この構造により、電子走行層512において電子供給層513に近い側に2次元電子ガス(2DEG:2 dimensional electron gas)512aが形成される。また、ソース電極515及びドレイン電極516は、キャップ層514及び電子供給層513を除去することにより形成された開口部内に形成されており、電子走行層512と接続されている。ゲート電極518は、キャップ層514及び電子供給層513の一部を除去することにより形成された開口部内に絶縁膜517を介して形成されている。尚、絶縁膜517はキャップ層514上にも形成されており、絶縁膜517の上には、保護膜519が形成されている。
次に、本実施の形態における半導体装置について説明する。本実施の形態における半導体装置の構造を図2に示す。本実施の形態における半導体装置は、HEMTと呼ばれるトランジスタであり、半導体等からなる基板11上に、電子走行層12、電子供給層13、キャップ層14がエピタキシャル成長により積層して形成されている。また、ソース電極15及びドレイン電極16は電子走行層12と接続されて形成されており、ゲート電極18は、キャップ層14及び電子供給層13の一部を除去することにより形成された開口部内に絶縁膜17を介して形成されている。尚、絶縁膜17はキャップ層14上にも形成されており、絶縁膜17の上には、保護膜20として、第1の絶縁保護膜21、アモルファスカーボン膜22及び第2の絶縁保護膜23が形成されている。
次に、図3及び図4に基づき本実施の形態における半導体装置の製造方法について説明する。
次に、アモルファスカーボン膜を成膜するためのFCA法について説明する。図6に、FCA法に用いられるFCA成膜装置の構造を示す。このFCA成膜装置は、プラズマ発生部110、プラズマ分離部120、パーティクルトラップ部130、プラズマ移送部140、成膜チャンバー150を有している。プラズマ発生部110、プラズマ分離部120及びパーティクルトラップ部130は、いずれも筒状に形成されており、この順で連結されている。プラズマ移送部140も筒状に形成されており、一方の端部はプラズマ分離部120に略垂直に接続されており、他方の端部は、成膜チャンバー150に接続されている。成膜チャンバー150の内部には、成膜対象となる基板等151を設置するためのステージ152が設けられている。
次に、第2の実施の形態について説明する。本実施の形態における半導体装置は、絶縁膜17上に保護膜220としてアモルファスカーボン膜221及び絶縁保護膜222を形成した構造のものである。
次に、第3の本実施の形態における半導体装置について説明する。本実施の形態における半導体装置の構造を図8に示す。本実施の形態における半導体装置は、半導体等からなる基板311上に、電子走行層312、電子供給層313、キャップ層314がエピタキシャル成長により積層して形成されている。また、ソース電極315及びドレイン電極316は電子走行層312と接続されて形成されており、キャップ層314上には絶縁膜317が形成されており、更に、絶縁膜317上にはゲート電極318が形成されている。また、露出している絶縁膜317の上には、保護膜320として、第1の絶縁保護膜321、アモルファスカーボン膜322及び第2の絶縁保護膜323が形成されている。
また、ソース電極315、ドレイン電極316及びゲート電極318は金属材料により形成されており、絶縁膜17は、プラズマALDにより酸化アルミニウム(Al2O3)膜を成膜することにより形成されている。また、第1の絶縁保護膜321は、酸化アルミニウム膜により形成されており、第2の絶縁保護膜323は、窒化シリコン(SiN)膜により形成されている。アモルファスカーボン膜322は、第1の実施の形態におけるアモルファスカーボン膜22と同様のものが用いられている。
次に、図9及び図10に基づき本実施の形態における半導体装置の製造方法について説明する。
12 電子走行層(第1の半導体層)
12a 2DEG
13 電子供給層(第2の半導体層)
14 キャップ層(第3の半導体層)
15 ソース電極
16 ドレイン電極
17 絶縁膜
18 ゲート電極
20 保護膜
21 第1の絶縁保護膜
22 アモルファスカーボン膜
23 第2の絶縁保護膜
Claims (20)
- 基板上に形成された第1の半導体層と、
前記第1の半導体層上に形成された第2の半導体層と、
前記第1の半導体層にまたは前記第2の半導体層に接して形成されたソース電極及びドレイン電極と、
前記第1の半導体層に形成された開口部と、
前記第2の半導体層の上方及び前記開口部の内部表面に形成された絶縁膜と、
前記絶縁膜を介し前記開口部内に形成されたゲート電極と、
前記絶縁膜上に形成された保護膜と、
を有し、
前記保護膜は、炭素を主成分とするアモルファス膜を含むものであることを特徴とする半導体装置。 - 基板上に形成された第1の半導体層と、
前記第1の半導体層上に形成された第2の半導体層と、
前記第1の半導体層にまたは前記第2の半導体層に接して形成されたソース電極及びドレイン電極と、
前記第2の半導体層の上方に形成された絶縁膜と、
前記絶縁膜上に形成されたゲート電極と、
前記絶縁膜上に形成された保護膜と、
を有し、
前記保護膜は、炭素を主成分とするアモルファス膜を含むものであることを特徴とする半導体装置。 - 前記保護膜は、炭素を主成分とするアモルファス膜と絶縁保護膜により形成されているものであり、
前記炭素を主成分とするアモルファス膜は、前記絶縁膜上に形成されるものであり、
前記絶縁保護膜は、前記炭素を主成分とするアモルファス膜上に形成されるものであることを特徴とする請求項1または2に記載の半導体装置。 - 前記絶縁保護膜は、窒化シリコンを含むものであることを特徴とする請求項3に記載の半導体装置。
- 前記保護膜は、第1の絶縁保護膜と炭素を主成分とするアモルファス膜と第2の絶縁保護膜により形成されているものであり、
前記第1の絶縁保護膜は、前記絶縁膜上に形成されるものであり、
前記炭素を主成分とするアモルファス膜は、前記第1の絶縁保護膜上に形成されるものであって、
前記第2の絶縁保護膜は、前記炭素を主成分とするアモルファス膜上に形成されるものであることを特徴とする請求項1または2に記載の半導体装置。 - 前記第2の絶縁保護膜は、窒化シリコンを含むものであることを特徴とする請求項5に記載の半導体装置。
- 前記第1の絶縁保護膜は、前記絶縁膜と同じ材料により形成されているものであることを特徴とする請求項5または6に記載の半導体装置。
- 前記炭素を主成分とするアモルファス膜は、膜厚が、1nm以上、30nm以下であることを特徴とする請求項1から7のいずれかに記載の半導体装置。
- 前記炭素を主成分とするアモルファス膜における炭素間結合の比率は、sp2≦sp3であることを特徴とする請求項1から8のいずれかに記載の半導体装置。
- 前記炭素を主成分とするアモルファス膜における膜密度は、2.7g/cm3以上、3.56g/cm3以下であることを特徴とする請求項1から9のいずれかに記載の半導体装置。
- 前記絶縁膜は、酸化アルミニウムにより形成されているものであることを特徴とする請求項1から10のいずれかに記載の半導体装置。
- 前記第1の半導体層は、GaNを含むものであることを特徴とする請求項1から11のいずれかに記載の半導体装置。
- 前記第2の半導体層は、AlGaNを含むものであることを特徴とする請求項1から12のいずれかに記載の半導体装置。
- 前記第2の半導体層と前記絶縁層との間には、第3の半導体層が設けられており、
前記第3の半導体層は、n-GaNを含むものであることを特徴とする請求項1から13のいずれかに記載の半導体装置。 - 前記半導体装置は、HEMTであることを特徴とする請求項1から14に記載の半導体装置。
- 基板上に第1の半導体層と、第2の半導体層を積層形成する工程と、
前記第1の半導体層にまたは前記第2の半導体層に接してソース電極及びドレイン電極を形成する工程と、
前記第2の半導体層に開口部を形成する工程と、
前記第2の半導体層の上方及び前記開口部の内部表面に絶縁膜を形成する工程と、
前記絶縁膜を介し前記開口部内にゲート電極を形成する工程と、
露出している前記絶縁膜上に炭素を主成分とするアモルファス膜を含む保護膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 基板上に第1の半導体層と、第2の半導体層を積層形成する工程と、
前記第1の半導体層にまたは前記第2の半導体層に接してソース電極及びドレイン電極を形成する工程と、
前記第2の半導体層の上方に絶縁膜を形成する工程と、
前記絶縁膜上の一部にゲート電極を形成する工程と、
露出している前記絶縁膜上に炭素を主成分とするアモルファス膜を含む保護膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 前記保護膜を形成する工程は、
前記絶縁膜上に前記炭素を主成分とするアモルファス膜を形成する工程と、
前記炭素を主成分とするアモルファス膜上に絶縁保護膜を形成する工程と、
を有することを特徴とする請求項16または17に記載の半導体装置の製造方法。 - 前記保護膜を形成する工程は、
前記絶縁膜上に第1の絶縁保護膜を形成する工程と、
前記第1の絶縁保護膜上に前記炭素を主成分とするアモルファス膜を形成する工程と、
前記炭素を主成分とするアモルファス膜上に第2の絶縁保護膜を形成する工程と、
を有することを特徴とする請求項16または17に記載の半導体装置の製造方法。 - 前記炭素を主成分とするアモルファス膜は、アーク蒸着法により形成されるものであることを特徴とする請求項16から19のいずれかに記載の半導体装置の製造方法。
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JP2017034245A (ja) * | 2015-07-28 | 2017-02-09 | ラム リサーチ コーポレーションLam Research Corporation | 感受性材料上にハロゲン化物含有ald膜を統合する方法 |
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JP6659283B2 (ja) | 2015-09-14 | 2020-03-04 | 株式会社東芝 | 半導体装置 |
ITUB20155862A1 (it) * | 2015-11-24 | 2017-05-24 | St Microelectronics Srl | Transistore di tipo normalmente spento con ridotta resistenza in stato acceso e relativo metodo di fabbricazione |
JP7055533B2 (ja) * | 2018-07-23 | 2022-04-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP7167694B2 (ja) * | 2018-12-20 | 2022-11-09 | 富士通株式会社 | 化合物半導体装置の製造方法 |
KR102451638B1 (ko) | 2020-06-12 | 2022-10-06 | 충남대학교산학협력단 | 고유전막 및 이를 포함하는 반도체 또는 커패시터 소자 |
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