Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
  • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
  • H03M1/0872—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by disabling changes in the output during the transitions, e.g. by holding or latching
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/1205—Multiplexed conversion systems
  • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
  • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/1205—Multiplexed conversion systems
  • H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
  • H03M1/1225—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages using time-division multiplexing
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
  • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
  • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/34—Analogue value compared with reference values
  • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
  • H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal

Definitions

• the invention relates generally to amplifiers and, more particularly, to residue amplifiers.
• reference numeral 100 generally designates a conventional analog-to-digital converter (ADC) 100.
• ADC 100 generally comprises several stages 102-1 to 102-N, an ADC 106 (which is typically a flash ADC), and a digital output circuit 104.
• the stages 102-1 to 102-N are generally coupled in series with one another in a sequence, where the first stage 102-1 receives the analog input signal and where each of the subsequent stages 102-2 to 102-N receives a residue signal from the previous stage 102-1 to 102-(N-1), respectively.
• ADC 106 is coupled to the last stage 102-N (receiving its residue signal).
• stages 102-1 to 102-N and ADC 106 are able to resolve a portion of the analog input signal, which is provided to digital output circuit 104.
• Digital output circuit 104 can then perform error correction or other digital processing to generate the digital output signal DOUT.
• Stage 102 generally comprises a track-and-hold (T/H) circuit 108 (i.e., T/H amplifier), ADC 110, digital-to- analog converter (DAC) 112, adder 114, and a residue amplifier 116.
• T/H track-and-hold
• the T/H circuit 110 enters a track phase T during the logic high state of the clock signal CLK and a hold phase H during the logic low state of the clock signal CLK.
• the T/H circuit samples its analog input signal SIN (which may be the analog input signal AIN or the residue signal from the previous stage).
• the sampled signal is provided to ADC 110 and adder 114.
• the ADC 110 resolves a portion of the signal SIN, providing the resolved bits to digital output circuit 104 and DAC 112.
• DAC 112 converts the resolved bits to an analog signal which is provided to adder 114.
• Adder 114 determines the difference between the sampled signal and the analog signal from DAC, which is amplified by amplifier 1 16 and output as a residue signal ROUT.
• the residue amplifiers 116 for each stage 102-1 to 102-N are operating at less than 50% duty cycle, which consumes an excess amount of power. Therefore, it is desirable to have a reside amplifier that consumes less power.
• An example embodiment of the invention accordingly, provides an apparatus.
• the apparatus comprises an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal; a first multiplexer that is coupled to the first input terminal of the amplifier; a second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
• the pulse generator further comprises: a logic circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch; and a delay circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch.
• the logic circuit further comprises a XOR gate.
• the amplifier further comprises: a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the first multiplexer; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the second multiplexer, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor; a first current source that is coupled to the second passive electrode of the first transistor; a second current source that is coupled to the second passive electrode of the second transistor; a first bias transistor that is coupled between the first currents source and the first output terminal; and a second bias transistor that is coupled between the second current source and the second output terminal.
• the first and second transistors are NPN transistors.
• an apparatus comprises data converter circuitry; a first multiplexer that is coupled to the data converter circuitry; a second multiplexer that is coupled to the data converter circuitry; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
• the data converter circuitry further comprises: a first track-and-hold (T/H) circuit; a second T/H circuit; a first analog-to-digital converter (ADC) that is coupled to the first T/H circuit; a second ADC that is coupled to the second T/H circuit; a first digital-to-analog converter (DAC) that is coupled to the first ADC; a second DAC that is coupled to the second ADC; a first adder that is coupled to the first DAC, the first T/H circuit, and the first multiplexer, wherein the first adder determines the difference between the outputs of the first T/H circuit and the first DAC; and a second adder that is coupled to the second DAC, the second T/H circuit, and the second multiplexer, wherein the second adder determines the difference between the outputs of the second T/H circuit and the second DAC.
• T/H track-and-hold
• ADC analog-to-digital converter
• DAC digital-to-analog converter
• an apparatus comprising a plurality of stages that are coupled in series with one another in a sequence, wherein each stage receives an analog input signal or a residue signal from the previous stage, and wherein each stage includes: data converter circuitry; a first multiplexer that is coupled to the data converter circuitry; a second multiplexer that is coupled to the data converter circuitry; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein
• FIGS. 1A and IB are circuit diagrams for an example of a conventional ADC
• FIG. 1C is a timing diagram for the ADC of FIGS. 1A and IB;
• FIGS. 2A and 2B are circuit diagrams for an example of an ADC in accordance with an example embodiment of the invention.
• FIG. 2C is a circuit diagram of an example of a residue amplifier of FIG. 2B.
• FIG. 2 A illustrates an example ADC 200 in accordance with principles of the invention.
• ADC 200 has the same general functionality as ADC 100. However, a difference exists in the pipeline; namely, stages 102-1 to 102-N have been replaced by stages 202-1 to 202- N.
• stages 202-1 to 203-N (hereinafter 202) can be seen in greater detail.
• T/H circuit 203-1 and 203-2 are coupled to receive an analog input signal IN (which is either the analog input signal AIN or a residue signal from the previous stage). Since these T/H circuits 203-1 and 203-2 are arranged in parallel with one another, T/H circuits 203-1 and 203-2 can be timed so as to sample on generally non-overlapping logic stages or phases of a clock signal. T/H circuits 203-1 and 203-2 are respectively coupled to ADC 204-1 and 204-2, and ADCs 204-1 and 204-2, DACs 206-1 and 206-2, adders 208-1 and 208-2, and residue amplifier 210 can then perform analog processing to resolve sampled signals for digital output circuit 104 and to generate a residue signal ROUT.
• ADC 204-1 and 204-2 ADCs 204-1 and 204-2
• DACs 206-1 and 206-2 adders 208-1 and 208-2
• residue amplifier 210 can then perform analog processing to resolve sampled signals for digital output circuit 104 and to generate a residue signal R
• each of the data converter circuits (which respectively include ADCs 204-1 or 204-2, DAC 206-1 or 206-2, and adder 208-1 or 208-2) benefit from the use of a single amplifier.
• a reason is that duty cycle of an amplifier (for each data converter circuit) would be less than 50%, which would consume an excessive amount of power. Therefore, amplifier 210 can be time multiplexed by controller 214 to process signals from each of the data converter circuits or data paths.
• residue amplifier 210 can be seen in greater detail.
• a folded cascode differential amplifier (which generally comprises NPN transistors Ql through Q4 and current sources 222, 224, 226, and 228) that is biased by a bias voltage BIAS is employed. Coupled to the input terminals of this amplifier are multiplexers 216-1 and 216-2. The switching between differential input signals INP1/INM1 and INP2/INM2 (which are provided by adders 208-1 and 208-2, respectively) are controlled through the select signal SELECT (which is provided by the controller 214). Additionally, multiplexers (not shown) that are coupled to the output terminals of this amplifier (so as to receive output signals OUTP and OUTM) to direct the correct input and output signals to the amplifier at the correct instants in time for processing.
• the amplifier which generally comprises NPN transistors Ql through Q4 and current sources 222, 224, 226, and 228, exhibits erratic behavior at the switching instant. This erratic behavior is referred to as a glitch, and if not addressed, the glitch can consume significant amounts of the amplifier's available settling time or even lead to the amplifier output or interior nodes operating at voltages outside their desired ranges. In other words, this glitch can degrade performance.
• a reset mechanism is provided at the output terminals of the amplifier.
• the resent mechanism generally comprises a switch Q5 that is coupled between the output terminals of the amplifier and controlled by a pulse generator (which generally comprises an XOR gate and a delay circuit).

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• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Analogue/Digital Conversion (AREA)
• Amplifiers (AREA)

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Citations (4)

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• 2010
  • 2010-09-13 US US12/880,311 patent/US8248290B2/en active Active
• 2011
  • 2011-09-13 JP JP2013529266A patent/JP2013538535A/ja active Pending
  • 2011-09-13 CN CN201180043704.1A patent/CN103098369B/zh active Active
  • 2011-09-13 WO PCT/US2011/051411 patent/WO2012037133A1/en not_active Ceased
• 2012
  • 2012-07-20 US US13/554,972 patent/US20130021188A1/en not_active Abandoned

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