US20130021188A1 - Multiplexed amplifier with reduced glitching - Google Patents
Multiplexed amplifier with reduced glitching Download PDFInfo
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- US20130021188A1 US20130021188A1 US13/554,972 US201213554972A US2013021188A1 US 20130021188 A1 US20130021188 A1 US 20130021188A1 US 201213554972 A US201213554972 A US 201213554972A US 2013021188 A1 US2013021188 A1 US 2013021188A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
- H03M1/0872—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by disabling changes in the output during the transitions, e.g. by holding or latching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
- H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
- H03M1/1225—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages using time-division multiplexing
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
Definitions
- the invention relates generally to amplifiers and, more particularly, to residue amplifiers.
- reference numeral 100 generally designates a conventional analog-to-digital converter (ADC) 100 .
- ADC 100 generally comprises several stages 102 - 1 to 102 -N, an ADC 106 (which is typically a flash ADC), and a digital output circuit 104 .
- the stages 102 - 1 to 102 -N are generally coupled in series with one another in a sequence, where the first stage 102 - 1 receives the analog input signal and where each of the subsequent stages 102 - 2 to 102 -N receives a residue signal from the previous stage 102 - 1 to 102 -(N- 1 ), respectively.
- ADC 106 is coupled to the last stage 102 -N (receiving its residue signal).
- stages 102 - 1 to 102 -N and ADC 106 are able to resolve a portion of the analog input signal, which is provided to digital output circuit 104 .
- Digital output circuit 104 can then perform error correction or other digital processing to generate the digital output signal DOUT.
- Stage 102 generally comprises a track-and-hold (T/H) circuit 108 (i.e., T/H amplifier), ADC 110 , digital-to-analog converter (DAC) 112 , adder 114 , and a residue amplifier 116 .
- T/H track-and-hold
- the T/H circuit 110 enters a track phase T during the logic high state of the clock signal CLK and a hold phase H during the logic low state of the clock signal CLK.
- the T/H circuit samples its analog input signal SIN (which may be the analog input signal AIN or the residue signal from the previous stage).
- SIN analog input signal
- the hold phase H the sampled signal is provided to ADC 110 and adder 114 .
- the ADC 110 resolves a portion of the signal SIN, providing the resolved bits to digital output circuit 104 and DAC 112 .
- DAC 112 converts the resolved bits to an analog signal which is provided to adder 114 .
- Adder 114 determines the difference between the sampled signal and the analog signal from DAC, which is amplified by amplifier 116 and output as a residue signal ROUT.
- ADC 100 There are some drawbacks to ADC 100 .
- the residue amplifiers 116 for each stage 102 - 1 to 102 -N are operating at less than 50% duty cycle, which consumes an excess amount of power. Therefore, it is desirable to have a reside amplifier that consumes less power.
- a preferred embodiment of the present invention accordingly, provides an apparatus.
- the apparatus comprises an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal; a first multiplexer that is coupled to the first input terminal of the amplifier; a second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
- the pulse generator further comprises: a logic circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch; and a delay circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch.
- the logic circuit further comprises a XOR gate.
- the amplifier further comprises: a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the first multiplexer; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the second multiplexer, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor; a first current source that is coupled to the second passive electrode of the first transistor; a second current source that is coupled to the second passive electrode of the second transistor; a first bias transistor that is coupled between the first currents source and the first output terminal; and a second bias transistor that is coupled between the second current source and the second output terminal.
- the first and second transistors are NPN transistors.
- an apparatus comprises data converter circuitry; a first multiplexer that is coupled to the data converter circuitry; a second multiplexer that is coupled to the data converter circuitry; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
- the data converter circuitry further comprises: a first track-and-hold (T/H) circuit; a second T/H circuit; a first analog-to-digital converter (ADC) that is coupled to the first T/H circuit; a second ADC that is coupled to the second T/H circuit; a first digital-to-analog converter (DAC) that is coupled to the first ADC; a second DAC that is coupled to the second ADC; a first adder that is coupled to the first DAC, the first T/H circuit, and the first multiplexer, wherein the first adder determines the difference between the outputs of the first T/H circuit and the first DAC; and a second adder that is coupled to the second DAC, the second T/H circuit, and the second multiplexer, wherein the second adder determines the difference between the outputs of the second T/H circuit and the second DAC.
- T/H track-and-hold
- ADC analog-to-digital converter
- DAC digital-to-analog converter
- an apparatus comprising a plurality of stages that are coupled in series with one another in a sequence, wherein each stage receives an analog input signal or a residue signal from the previous stage, and wherein each stage includes: data converter circuitry; a first multiplexer that is coupled to the data converter circuitry; a second multiplexer that is coupled to the data converter circuitry; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller
- FIGS. 1A and 1B are circuit diagrams for an example of a conventional ADC
- FIG. 1C is a timing diagram for the ADC of FIGS. 1A and 1B ;
- FIGS. 2A and 2B are circuit diagrams for an example of an ADC in accordance with a preferred embodiment of the present invention.
- FIG. 2C is a circuit diagram of an example of a residue amplifier of FIG. 2B .
- FIG. 2A an example of an ADC 200 in accordance with a preferred embodiment of the present invention can be seen.
- ADC 200 has the same general functionality as ADC 100 . However, a difference exists in the pipeline; namely, stages 102 - 1 to 102 -N have been replaced by stages 202 - 1 to 202 -N.
- stages 202 - 1 to 203 -N (hereinafter 202 ) can be seen in greater detail.
- T/H circuit 203 - 1 and 203 - 2 are coupled to receive an analog input signal IN (which is either the analog input signal AIN or a residue signal from the previous stage). Since these T/H circuits 203 - 1 and 203 - 2 are arranged in parallel with one another, T/H circuits 203 - 1 and 203 - 2 can be timed so as to sample on generally non-overlapping logic stages or phases of a clock signal.
- T/H circuits 203 - 1 and 203 - 2 are respectively coupled to ADC 204 - 1 and 204 - 2 , and ADCs 204 - 1 and 204 - 2 , DACs 206 - 1 and 206 - 2 , adders 208 - 1 and 208 - 2 , and residue amplifier 210 can then perform analog processing to resolve sampled signals for digital output circuit 104 and to generate a residue signal ROUT.
- each of the data converter circuits (which respectively include ADCs 204 - 1 or 204 - 2 , DAC 206 - 1 or 206 - 2 , and adder 208 - 1 or 208 - 2 ) benefit from the use of a single amplifier.
- a reason is that duty cycle of an amplifier (for each data converter circuit) would be less than 50%, which would consume an excessive amount of power. Therefore, amplifier 210 can be time multiplexed by controller 214 to process signals from each of the data converter circuits or data paths.
- residue amplifier 210 can be seen in greater detail.
- a folded cascode differential amplifier (which generally comprises NPN transistors Q 1 through Q 4 and current sources 222 , 224 , 226 , and 228 ) that is biased by a bias voltage BIAS is employed. Coupled to the input terminals of this amplifier are multiplexers 216 - 1 and 216 - 2 . The switching between differential input signals INP 1 /INM 1 and INP 2 /INM 2 (which are provided by adders 208 - 1 and 208 - 2 , respectively) are controlled through the select signal SELECT (which is provided by the controller 214 ). Additionally, multiplexers (not shown) that are coupled to the output terminals of this amplifier (so as to receive output signals OUTP and OUTM) to direct the correct input and output signals to the amplifier at the correct instants in time for processing.
- the amplifier (which generally comprises NPN transistors Q 1 through Q 4 and current sources 222 , 224 , 226 , and 228 ) exhibits erratic behavior at the switching instant. This erratic behavior is referred to as a glitch, and if not addressed, the glitch can consume significant amounts of the amplifier's available settling time or even lead to the amplifier output or interior nodes operating at voltages outside their desired ranges. In other words, this glitch can degrade performance. To combat this problem, a reset mechanism is provided at the output terminals of the amplifier.
- the resent mechanism generally comprises a switch Q 5 that is coupled between the output terminals of the amplifier and controlled by a pulse generator (which generally comprises an XOR gate and a delay circuit).
- a pulse generator which generally comprises an XOR gate and a delay circuit.
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Abstract
In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.
Description
- This application is a continuation of U.S. patent application Ser. No. 12/857,674, filed Aug. 17, 2010, which is hereby incorporated by reference for all purposes.
- The invention relates generally to amplifiers and, more particularly, to residue amplifiers.
- Referring to
FIG. 1A of the drawings,reference numeral 100 generally designates a conventional analog-to-digital converter (ADC) 100.ADC 100 generally comprises several stages 102-1 to 102-N, an ADC 106 (which is typically a flash ADC), and adigital output circuit 104. The stages 102-1 to 102-N are generally coupled in series with one another in a sequence, where the first stage 102-1 receives the analog input signal and where each of the subsequent stages 102-2 to 102-N receives a residue signal from the previous stage 102-1 to 102-(N-1), respectively.ADC 106 is coupled to the last stage 102-N (receiving its residue signal). Based on its input signal (either a residue signal or the analog input signal), stages 102-1 to 102-N andADC 106 are able to resolve a portion of the analog input signal, which is provided todigital output circuit 104.Digital output circuit 104 can then perform error correction or other digital processing to generate the digital output signal DOUT. - Turning now to
FIGS. 1B and 1C , stages 102-1 to 102-N can be seen in greater detail (which are referred to hereinafter asstage 102 for the sake of simplicity).Stage 102 generally comprises a track-and-hold (T/H) circuit 108 (i.e., T/H amplifier),ADC 110, digital-to-analog converter (DAC) 112,adder 114, and aresidue amplifier 116. In operation, the T/H circuit 110 enters a track phase T during the logic high state of the clock signal CLK and a hold phase H during the logic low state of the clock signal CLK. During the track phase T, the T/H circuit samples its analog input signal SIN (which may be the analog input signal AIN or the residue signal from the previous stage). During the hold phase H, the sampled signal is provided toADC 110 and adder 114. The ADC 110 resolves a portion of the signal SIN, providing the resolved bits todigital output circuit 104 andDAC 112.DAC 112 converts the resolved bits to an analog signal which is provided to adder 114.Adder 114 determines the difference between the sampled signal and the analog signal from DAC, which is amplified byamplifier 116 and output as a residue signal ROUT. - There are some drawbacks to ADC 100. In particular, the
residue amplifiers 116 for each stage 102-1 to 102-N are operating at less than 50% duty cycle, which consumes an excess amount of power. Therefore, it is desirable to have a reside amplifier that consumes less power. - Some examples of other conventions circuits are: U.S. Pat. No. 3,877,023; U.S. Pat. No. 5,180,932; U.S. Pat. No. 6,218,887; and U.S. Pat. No. 6,489,845.
- A preferred embodiment of the present invention, accordingly, provides an apparatus. The apparatus comprises an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal; a first multiplexer that is coupled to the first input terminal of the amplifier; a second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
- In accordance with a preferred embodiment of the present invention, the pulse generator further comprises: a logic circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch; and a delay circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch.
- In accordance with a preferred embodiment of the present invention, the logic circuit further comprises a XOR gate.
- In accordance with a preferred embodiment of the present invention, the amplifier further comprises: a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the first multiplexer; a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the second multiplexer, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor; a first current source that is coupled to the second passive electrode of the first transistor; a second current source that is coupled to the second passive electrode of the second transistor; a first bias transistor that is coupled between the first currents source and the first output terminal; and a second bias transistor that is coupled between the second current source and the second output terminal.
- In accordance with a preferred embodiment of the present invention, the first and second transistors are NPN transistors.
- In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises data converter circuitry; a first multiplexer that is coupled to the data converter circuitry; a second multiplexer that is coupled to the data converter circuitry; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
- In accordance with a preferred embodiment of the present invention, the data converter circuitry further comprises: a first track-and-hold (T/H) circuit; a second T/H circuit; a first analog-to-digital converter (ADC) that is coupled to the first T/H circuit; a second ADC that is coupled to the second T/H circuit; a first digital-to-analog converter (DAC) that is coupled to the first ADC; a second DAC that is coupled to the second ADC; a first adder that is coupled to the first DAC, the first T/H circuit, and the first multiplexer, wherein the first adder determines the difference between the outputs of the first T/H circuit and the first DAC; and a second adder that is coupled to the second DAC, the second T/H circuit, and the second multiplexer, wherein the second adder determines the difference between the outputs of the second T/H circuit and the second DAC.
- In accordance with a preferred embodiment of the present invention, an apparatus is provided. The apparatus comprises a plurality of stages that are coupled in series with one another in a sequence, wherein each stage receives an analog input signal or a residue signal from the previous stage, and wherein each stage includes: data converter circuitry; a first multiplexer that is coupled to the data converter circuitry; a second multiplexer that is coupled to the data converter circuitry; an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier; a switch that is coupled between the first and second output terminals of the amplifier; a pulse generator that is coupled to the switch so as to control the switch; and a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched; an ADC that is coupled to the last stage of the sequence; and a digital output circuit that is coupled to the ADC and the data converter circuit for each stage.
- The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and the specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
- For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIGS. 1A and 1B are circuit diagrams for an example of a conventional ADC; -
FIG. 1C is a timing diagram for the ADC ofFIGS. 1A and 1B ; -
FIGS. 2A and 2B are circuit diagrams for an example of an ADC in accordance with a preferred embodiment of the present invention; and -
FIG. 2C is a circuit diagram of an example of a residue amplifier ofFIG. 2B . - Refer now to the drawings wherein depicted elements are, for the sake of clarity, not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views.
- Turning to
FIG. 2A , an example of anADC 200 in accordance with a preferred embodiment of the present invention can be seen.ADC 200 has the same general functionality asADC 100. However, a difference exists in the pipeline; namely, stages 102-1 to 102-N have been replaced by stages 202-1 to 202-N. - Looking to
FIG. 2B , stages 202-1 to 203-N (hereinafter 202) can be seen in greater detail. In operation, T/H circuit 203-1 and 203-2 are coupled to receive an analog input signal IN (which is either the analog input signal AIN or a residue signal from the previous stage). Since these T/H circuits 203-1 and 203-2 are arranged in parallel with one another, T/H circuits 203-1 and 203-2 can be timed so as to sample on generally non-overlapping logic stages or phases of a clock signal. T/H circuits 203-1 and 203-2 are respectively coupled to ADC 204-1 and 204-2, and ADCs 204-1 and 204-2, DACs 206-1 and 206-2, adders 208-1 and 208-2, andresidue amplifier 210 can then perform analog processing to resolve sampled signals fordigital output circuit 104 and to generate a residue signal ROUT. - Here, each of the data converter circuits (which respectively include ADCs 204-1 or 204-2, DAC 206-1 or 206-2, and adder 208-1 or 208-2) benefit from the use of a single amplifier. A reason is that duty cycle of an amplifier (for each data converter circuit) would be less than 50%, which would consume an excessive amount of power. Therefore,
amplifier 210 can be time multiplexed bycontroller 214 to process signals from each of the data converter circuits or data paths. - Turning to
FIG. 2C ,residue amplifier 210 can be seen in greater detail. In this example, a folded cascode differential amplifier (which generally comprises NPN transistors Q1 through Q4 andcurrent sources - When multiplexers 216-1 and 216-2 are switched, however, the amplifier (which generally comprises NPN transistors Q1 through Q4 and
current sources - Having thus described the present invention by reference to certain of its preferred embodiments, it is noted that the embodiments disclosed are illustrative rather than limiting in nature and that a wide range of variations, modifications, changes, and substitutions are contemplated in the foregoing disclosure and, in some instances, some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.
Claims (17)
1. An apparatus comprising:
an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal;
a first multiplexer that is coupled to the first input terminal of the amplifier;
a second multiplexer that is coupled to the second input terminal of the amplifier;
a switch that is coupled between the first and second output terminals of the amplifier;
a pulse generator that is coupled to the switch so as to control the switch; and
a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
2. The apparatus of claim 1 , wherein the pulse generator further comprises:
a logic circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch; and
a delay circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch.
3. The apparatus of claim 2 , wherein the logic circuit further comprises a XOR gate.
4. The apparatus of claim 3 , wherein the amplifier further comprises:
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the first multiplexer;
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the second multiplexer, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor;
a first current source that is coupled to the second passive electrode of the first transistor;
a second current source that is coupled to the second passive electrode of the second transistor;
a first bias transistor that is coupled between the first currents source and the first output terminal; and
a second bias transistor that is coupled between the second current source and the second output terminal.
5. The apparatus of claim 4 , wherein the first and second transistors are NPN transistors.
6. An apparatus comprising:
data converter circuitry;
a first multiplexer that is coupled to the data converter circuitry;
a second multiplexer that is coupled to the data converter circuitry;
an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier;
a switch that is coupled between the first and second output terminals of the amplifier;
a pulse generator that is coupled to the switch so as to control the switch; and
a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched.
7. The apparatus of claim 6 , wherein the pulse generator further comprises:
a logic circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch; and
a delay circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch.
8. The apparatus of claim 7 , wherein the logic circuit further comprises a XOR gate.
9. The apparatus of claim 8 , wherein the amplifier further comprises:
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the first multiplexer;
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the second multiplexer, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor;
a first current source that is coupled to the second passive electrode of the first transistor;
a second current source that is coupled to the second passive electrode of the second transistor;
a first bias transistor that is coupled between the first currents source and the first output terminal; and
a second bias transistor that is coupled between the second current source and the second output terminal.
10. The apparatus of claim 9 , wherein the first and second transistors are NPN transistors.
11. The apparatus of claim 8 , wherein the data converter circuitry further comprises:
a first track-and-hold (T/H) circuit;
a second T/H circuit;
a first analog-to-digital converter (ADC) that is coupled to the first T/H circuit;
a second ADC that is coupled to the second T/H circuit;
a first digital-to-analog converter (DAC) that is coupled to the first ADC;
a second DAC that is coupled to the second ADC;
a first adder that is coupled to the first DAC, the first T/H circuit, and the first multiplexer, wherein the first adder determines the difference between the outputs of the first T/H circuit and the first DAC; and
a second adder that is coupled to the second DAC, the second T/H circuit, and the second multiplexer, wherein the second adder determines the difference between the outputs of the second T/H circuit and the second DAC.
12. An apparatus comprising:
a plurality of stages that are coupled in series with one another in a sequence, wherein each stage receives an analog input signal or a residue signal from the previous stage, and wherein each stage includes:
data converter circuitry;
a first multiplexer that is coupled to the data converter circuitry;
a second multiplexer that is coupled to the data converter circuitry;
an amplifier having a first input terminal, a second input terminal, a first output terminal, and a second input terminal, wherein the first multiplexer that is coupled to the first input terminal of the amplifier, and wherein the second multiplexer that is coupled to the second input terminal of the amplifier;
a switch that is coupled between the first and second output terminals of the amplifier;
a pulse generator that is coupled to the switch so as to control the switch; and
a controller that is coupled to the first multiplexer, the second multiplexer, and pulse generator, wherein the controller provides a select signal to each of the first and second multiplexers, and wherein the controller activates the pulse generator when the first and second multiplexers are switched;
an ADC that is coupled to the last stage of the sequence; and
a digital output circuit that is coupled to the ADC and the data converter circuit for each stage.
13. The apparatus of claim 12 , wherein the pulse generator further comprises:
a logic circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch; and
a delay circuit that is coupled to the controller so as to receive the select signal and that is coupled to the switch.
14. The apparatus of claim 13 , wherein the logic circuit further comprises a XOR gate.
15. The apparatus of claim 14 , wherein the amplifier further comprises:
a first transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the first transistor is coupled to the first multiplexer;
a second transistor having a first passive electrode, a second passive electrode, and a control electrode, wherein the control electrode of the second transistor is coupled to the second multiplexer, and wherein the first passive electrode of the second transistor is coupled to the first passive electrode of the first transistor;
a first current source that is coupled to the second passive electrode of the first transistor;
a second current source that is coupled to the second passive electrode of the second transistor;
a first bias transistor that is coupled between the first currents source and the first output terminal; and
a second bias transistor that is coupled between the second current source and the second output terminal.
16. The apparatus of claim 15 , wherein the first and second transistors are NPN transistors.
17. The apparatus of claim 14 , wherein the data converter circuitry further comprises:
a first track-and-hold (T/H) circuit;
a second T/H circuit;
a first analog-to-digital converter (ADC) that is coupled to the first T/H circuit;
a second ADC that is coupled to the second T/H circuit;
a first digital-to-analog converter (DAC) that is coupled to the first ADC;
a second DAC that is coupled to the second ADC;
a first adder that is coupled to the first DAC, the first T/H circuit, and the first multiplexer, wherein the first adder determines the difference between the outputs of the first T/H circuit and the first DAC; and
a second adder that is coupled to the second DAC, the second T/H circuit, and the second multiplexer, wherein the second adder determines the difference between the outputs of the second T/H circuit and the second DAC.
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US13/554,972 US20130021188A1 (en) | 2010-09-13 | 2012-07-20 | Multiplexed amplifier with reduced glitching |
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US12/880,311 US8248290B2 (en) | 2010-09-13 | 2010-09-13 | Multiplexed amplifier with reduced glitching |
US13/554,972 US20130021188A1 (en) | 2010-09-13 | 2012-07-20 | Multiplexed amplifier with reduced glitching |
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US12/880,311 Continuation US8248290B2 (en) | 2010-09-13 | 2010-09-13 | Multiplexed amplifier with reduced glitching |
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US12/880,311 Active 2030-12-22 US8248290B2 (en) | 2010-09-13 | 2010-09-13 | Multiplexed amplifier with reduced glitching |
US13/554,972 Abandoned US20130021188A1 (en) | 2010-09-13 | 2012-07-20 | Multiplexed amplifier with reduced glitching |
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US (2) | US8248290B2 (en) |
JP (1) | JP2013538535A (en) |
CN (1) | CN103098369B (en) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130161492A1 (en) * | 2011-12-26 | 2013-06-27 | Korea Advanced Institute Of Science And Technology | Switching circuit, charge sense amplifier including switching circuit, and photon counting device including switching circuit |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8248290B2 (en) * | 2010-09-13 | 2012-08-21 | Texas Instruments Incorporated | Multiplexed amplifier with reduced glitching |
US9311867B2 (en) | 2012-11-13 | 2016-04-12 | Apple Inc. | Devices and methods for reducing power consumption of a demultiplexer |
US9065470B2 (en) | 2012-12-19 | 2015-06-23 | Intel Corporation | Low power analog to digital converter |
US8872685B2 (en) * | 2013-03-15 | 2014-10-28 | Qualcomm Incorporated | Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs |
EP3174210B1 (en) * | 2015-11-24 | 2022-05-18 | Nxp B.V. | A data processor |
US9755595B1 (en) | 2016-04-15 | 2017-09-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Settling time reduction for low noise amplifier |
CN112532250A (en) * | 2019-09-19 | 2021-03-19 | 亚德诺半导体国际无限责任公司 | Modular analog signal multiplexer for differential signals |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8248290B2 (en) * | 2010-09-13 | 2012-08-21 | Texas Instruments Incorporated | Multiplexed amplifier with reduced glitching |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3877023A (en) | 1973-05-21 | 1975-04-08 | Texas Instruments Inc | Antiglitch digital to analog converter system |
US5180932A (en) | 1990-03-15 | 1993-01-19 | Bengel David W | Current mode multiplexed sample and hold circuit |
JPH06164339A (en) * | 1992-11-17 | 1994-06-10 | Nippondenso Co Ltd | Digitally controlled delay device and digitally controlled oscillator |
JPH088458B2 (en) * | 1993-07-13 | 1996-01-29 | 日本電気株式会社 | Operational amplifier circuit |
US5530444A (en) | 1995-01-05 | 1996-06-25 | Analog Devices, Inc. | Differential amplifiers which can form a residue amplifier in sub-ranging A/D converters |
US6218887B1 (en) | 1996-09-13 | 2001-04-17 | Lockheed Martin Corporation | Method of and apparatus for multiplexing multiple input signals |
US5867053A (en) | 1997-03-21 | 1999-02-02 | Motorola Inc. | Multiplexed output circuit and method of operation thereof |
JP3816240B2 (en) * | 1998-06-19 | 2006-08-30 | 旭化成マイクロシステム株式会社 | Pipeline type A / D converter |
US6323791B1 (en) * | 1999-10-13 | 2001-11-27 | Analog Devices, Inc. | Control systems and methods for reducing residue signal offset in subranging analog-to-digital converters |
US6489845B1 (en) | 2000-04-04 | 2002-12-03 | Goodrich Corporation | Multiplexing amplifier |
US7868665B2 (en) * | 2002-03-05 | 2011-01-11 | Nova R&D, Inc. | Integrated circuit and sensor for imaging |
US6583747B1 (en) * | 2002-05-24 | 2003-06-24 | Broadcom Corporation | Subranging analog to digital converter with multi-phase clock timing |
US6573853B1 (en) * | 2002-05-24 | 2003-06-03 | Broadcom Corporation | High speed analog to digital converter |
JP3918777B2 (en) * | 2003-05-15 | 2007-05-23 | 富士電機デバイステクノロジー株式会社 | Pulse width modulation circuit |
JP4529007B2 (en) * | 2004-09-02 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
JP4821333B2 (en) * | 2006-01-23 | 2011-11-24 | セイコーエプソン株式会社 | Pipeline A / D converter |
US8094056B2 (en) * | 2006-02-02 | 2012-01-10 | Clariphy Communications, Inc. | Analog-to-digital converter |
TWI333335B (en) * | 2006-12-18 | 2010-11-11 | Ind Tech Res Inst | Analog to digital converting system |
JP4925192B2 (en) * | 2007-03-16 | 2012-04-25 | ルネサスエレクトロニクス株式会社 | Pipeline type A / D converter and semiconductor integrated circuit incorporating the same |
JP4854695B2 (en) * | 2008-03-14 | 2012-01-18 | オンセミコンダクター・トレーディング・リミテッド | Differential comparator and pipeline A / D converter |
US7990185B2 (en) * | 2008-05-12 | 2011-08-02 | Menara Networks | Analog finite impulse response filter |
JP4977115B2 (en) * | 2008-12-02 | 2012-07-18 | 旭化成エレクトロニクス株式会社 | Pipeline type A / D converter |
-
2010
- 2010-09-13 US US12/880,311 patent/US8248290B2/en active Active
-
2011
- 2011-09-13 WO PCT/US2011/051411 patent/WO2012037133A1/en active Application Filing
- 2011-09-13 CN CN201180043704.1A patent/CN103098369B/en active Active
- 2011-09-13 JP JP2013529266A patent/JP2013538535A/en active Pending
-
2012
- 2012-07-20 US US13/554,972 patent/US20130021188A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8248290B2 (en) * | 2010-09-13 | 2012-08-21 | Texas Instruments Incorporated | Multiplexed amplifier with reduced glitching |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130161492A1 (en) * | 2011-12-26 | 2013-06-27 | Korea Advanced Institute Of Science And Technology | Switching circuit, charge sense amplifier including switching circuit, and photon counting device including switching circuit |
US8957361B2 (en) * | 2011-12-26 | 2015-02-17 | Samsung Electronics Co., Ltd. | Switching circuit, charge sense amplifier including switching circuit, and photon counting device including switching circuit |
Also Published As
Publication number | Publication date |
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US20120062402A1 (en) | 2012-03-15 |
JP2013538535A (en) | 2013-10-10 |
WO2012037133A1 (en) | 2012-03-22 |
US8248290B2 (en) | 2012-08-21 |
CN103098369B (en) | 2016-01-06 |
CN103098369A (en) | 2013-05-08 |
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